QuadSPImTb.v 2.6 KB

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  1. `timescale 1ns / 1ps
  2. module QuadSPImTb ();
  3. parameter CLK_PERIOD = 8.13; // Clock period in ns
  4. //================================================================================
  5. // REG/WIRE
  6. //================================================================================
  7. reg rst;
  8. reg clk;
  9. localparam [31:0] startData = 32'h01010101;
  10. // localparam [31:0] startData = 32'h0A0B0C0D;
  11. reg [31:0] data;
  12. reg [31:0] dataS;
  13. wire [1:0] widthSel = 2'h3;
  14. wire clockPol = 1'b0;
  15. wire clockPhase = 1'b0;
  16. wire endianSel = 1'b0;
  17. wire lag = 1'b0;
  18. wire lead = 1'b0;
  19. wire [5:0] stopDelay = 6'h1;
  20. wire selSt = 1'b0;
  21. wire val;
  22. wire valS;
  23. reg [31:0] tbCnt;
  24. wire start = (tbCnt>=100);
  25. wire fifoEmpty = (tbCnt >= 500);
  26. //================================================================================
  27. // ASSIGNMENTS
  28. //================================================================================
  29. //================================================================================
  30. // CODING
  31. //================================================================================
  32. always #(CLK_PERIOD/2) clk = ~clk;
  33. initial begin
  34. clk = 0;
  35. rst = 0;
  36. #40
  37. rst = 1;
  38. #100
  39. rst = 0;
  40. end
  41. always @(posedge clk) begin
  42. if (rst) begin
  43. tbCnt <= 0;
  44. end else begin
  45. tbCnt <= tbCnt+1;
  46. end
  47. end
  48. always @(posedge clk) begin
  49. if (rst) begin
  50. data <= startData;
  51. end else if (val) begin
  52. data <= data+32'h10;
  53. end
  54. end
  55. always @(posedge clk) begin
  56. if (rst) begin
  57. dataS <= 32'h0000000A;
  58. end else if (valS) begin
  59. // end else begin
  60. case(widthSel)
  61. 0: begin
  62. dataS <= dataS+32'h10;
  63. // dataS <= 32'h0000000A;
  64. end
  65. 1: begin
  66. dataS <= dataS+32'h100;
  67. // dataS <= 32'h00000A0A;
  68. end
  69. 2: begin
  70. dataS <= dataS+32'h100;
  71. // dataS <= 32'h000A0A0A;
  72. end
  73. 3: begin
  74. dataS <= dataS+32'h100;
  75. // dataS <= 32'h0A0A0A0A;
  76. end
  77. endcase
  78. end
  79. end
  80. QuadSPIm QuadSPIm
  81. (
  82. .Clk_i(clk),
  83. .Start_i(start),
  84. .Rst_i(rst),
  85. .EmptyFlag_i(fifoEmpty),
  86. .SpiData_i(dataS),
  87. .Sck_o(),
  88. .Ss_o(),
  89. .Mosi0_o(),
  90. .Mosi1_o(),
  91. .Mosi2_o(),
  92. .Mosi3_o(),
  93. .WidthSel_i(widthSel),
  94. .PulsePol_i(clockPol),
  95. .ClockPhase_i(clockPhase),
  96. .EndianSel_i(endianSel),
  97. .Lag_i(lag),
  98. .Lead_i(lead),
  99. .Stop_i(stopDelay),
  100. .SelSt_i(selSt),
  101. .Val_o(val)
  102. );
  103. SPIm Spi
  104. (
  105. .Clk_i (clk),
  106. .Rst_i (rst),
  107. .Start_i (start),
  108. .EmptyFlag_i (fifoEmpty),
  109. .ClockPhase_i (clockPhase),
  110. .SpiData_i (dataS),
  111. .SelSt_i (selSt),
  112. .WidthSel_i (widthSel),
  113. .Lag_i (lag),
  114. .Lead_i (lead),
  115. .EndianSel_i (endianSel),
  116. .Stop_i (stopDelay),
  117. .PulsePol_i (clockPol),
  118. .Mosi0_o (),
  119. .Sck_o (),
  120. .Ss_o (),
  121. .Val_o (valS)
  122. );
  123. endmodule