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- `timescale 1ns / 1ps
- module QuadSPImTb ();
- parameter CLK_PERIOD = 8.13; // Clock period in ns
- //================================================================================
- // REG/WIRE
- //================================================================================
- reg rst;
- reg clk;
- wire [31:0] data = 32'hFAFA_0101;
- wire [1:0] widthSel = 2'h2;
- wire clockPol = 1'b0;
- wire clockPhase = 1'b0;
- wire endianSel = 1'b0;
- wire lag = 1'b0;
- wire leadx = 1'b0;
- wire [5:0] stopDelay = 6'h0;
- wire selSt = 1'b1;
- reg [31:0] tbCnt;
- wire start = (tbCnt>=100);
- //================================================================================
- // ASSIGNMENTS
- //================================================================================
- //================================================================================
- // CODING
- //================================================================================
- always #(CLK_PERIOD/2) clk = ~clk;
- initial begin
- clk = 0;
- rst = 0;
- #40
- rst = 1;
- #100
- rst = 0;
- end
- always @(posedge clk) begin
- if (rst) begin
- tbCnt <= 0;
- end else begin
- tbCnt <= tbCnt+1;
- end
- end
- QuadSPIm QuadSPIm
- (
- .Clk_i(clk),
- .Start_i(start),
- .Rst_i(rst),
- .EmptyFlag_i(1'b0),
- .SpiData_i(data),
- .Sck_o(),
- .Ss_o(),
- .Mosi0_o(),
- .Mosi1_o(),
- .Mosi2_o(),
- .Mosi3_o(),
- .WidthSel_i(widthSel),
- .PulsePol_i(clockPol),
- .ClockPhase_i(clockPhase),
- .EndianSel_i(endianSel),
- .Lag_i(lag),
- .Lead_i(leadx),
- .Stop_i(stopDelay),
- .SelSt_i(selSt),
- .Val_o()
- );
-
- endmodule
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