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S5443_3.xdc

S5443_3.xdc 42 KB
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  1. set_property PACKAGE_PIN C15 [get_ports {SmcAddr_i[0]}]
    2. 

  2. set_property IOSTANDARD LVCMOS33 [get_ports {SmcAddr_i[0]}]
    3. 

  3. set_property PACKAGE_PIN C13 [get_ports {SmcAddr_i[1]}]
    4. 

  4. set_property IOSTANDARD LVCMOS33 [get_ports {SmcAddr_i[1]}]
    5. 

  5. set_property PACKAGE_PIN D15 [get_ports {SmcAddr_i[2]}]
    6. 

  6. set_property IOSTANDARD LVCMOS33 [get_ports {SmcAddr_i[2]}]
    7. 

  7. set_property PACKAGE_PIN C14 [get_ports {SmcAddr_i[3]}]
    8. 

  8. set_property IOSTANDARD LVCMOS33 [get_ports {SmcAddr_i[3]}]
    9. 

  9. set_property PACKAGE_PIN E15 [get_ports {SmcAddr_i[4]}]
    10. 

  10. set_property IOSTANDARD LVCMOS33 [get_ports {SmcAddr_i[4]}]
    11. 

  11. set_property PACKAGE_PIN D13 [get_ports {SmcAddr_i[5]}]
    12. 

  12. set_property IOSTANDARD LVCMOS33 [get_ports {SmcAddr_i[5]}]
    13. 

  13. set_property PACKAGE_PIN F15 [get_ports {SmcAddr_i[6]}]
    14. 

  14. set_property IOSTANDARD LVCMOS33 [get_ports {SmcAddr_i[6]}]
    15. 

  15. set_property PACKAGE_PIN E14 [get_ports {SmcAddr_i[7]}]
    16. 

  16. set_property IOSTANDARD LVCMOS33 [get_ports {SmcAddr_i[7]}]
    17. 

  17. set_property PACKAGE_PIN J15 [get_ports {SmcAddr_i[8]}]
    18. 

  18. set_property IOSTANDARD LVCMOS33 [get_ports {SmcAddr_i[8]}]
    19. 

  19. set_property PACKAGE_PIN F14 [get_ports {SmcAddr_i[9]}]
    20. 

  20. set_property IOSTANDARD LVCMOS33 [get_ports {SmcAddr_i[9]}]
    21. 

  21. set_property PACKAGE_PIN K15 [get_ports {SmcAddr_i[10]}]
    22. 

  22. set_property IOSTANDARD LVCMOS33 [get_ports {SmcAddr_i[10]}]
    23. 

  23. 

  24. 

  25. 

  26. set_property PACKAGE_PIN B15 [get_ports {SmcData_io[0]}]
    27. 

  27. set_property IOSTANDARD LVCMOS33 [get_ports {SmcData_io[0]}]
    28. 

  28. set_property PACKAGE_PIN B14 [get_ports {SmcData_io[1]}]
    29. 

  29. set_property IOSTANDARD LVCMOS33 [get_ports {SmcData_io[1]}]
    30. 

  30. set_property PACKAGE_PIN B11 [get_ports {SmcData_io[2]}]
    31. 

  31. set_property IOSTANDARD LVCMOS33 [get_ports {SmcData_io[2]}]
    32. 

  32. set_property PACKAGE_PIN B12 [get_ports {SmcData_io[3]}]
    33. 

  33. set_property IOSTANDARD LVCMOS33 [get_ports {SmcData_io[3]}]
    34. 

  34. set_property PACKAGE_PIN A12 [get_ports {SmcData_io[4]}]
    35. 

  35. set_property IOSTANDARD LVCMOS33 [get_ports {SmcData_io[4]}]
    36. 

  36. set_property PACKAGE_PIN B9 [get_ports {SmcData_io[5]}]
    37. 

  37. set_property IOSTANDARD LVCMOS33 [get_ports {SmcData_io[5]}]
    38. 

  38. set_property PACKAGE_PIN K14 [get_ports {SmcData_io[6]}]
    39. 

  39. set_property IOSTANDARD LVCMOS33 [get_ports {SmcData_io[6]}]
    40. 

  40. set_property PACKAGE_PIN A11 [get_ports {SmcData_io[7]}]
    41. 

  41. set_property IOSTANDARD LVCMOS33 [get_ports {SmcData_io[7]}]
    42. 

  42. set_property PACKAGE_PIN A6 [get_ports {SmcData_io[8]}]
    43. 

  43. set_property IOSTANDARD LVCMOS33 [get_ports {SmcData_io[8]}]
    44. 

  44. set_property PACKAGE_PIN A13 [get_ports {SmcData_io[9]}]
    45. 

  45. set_property IOSTANDARD LVCMOS33 [get_ports {SmcData_io[9]}]
    46. 

  46. set_property PACKAGE_PIN A10 [get_ports {SmcData_io[10]}]
    47. 

  47. set_property IOSTANDARD LVCMOS33 [get_ports {SmcData_io[10]}]
    48. 

  48. set_property PACKAGE_PIN B6 [get_ports {SmcData_io[11]}]
    49. 

  49. set_property IOSTANDARD LVCMOS33 [get_ports {SmcData_io[11]}]
    50. 

  50. set_property PACKAGE_PIN A5 [get_ports {SmcData_io[12]}]
    51. 

  51. set_property IOSTANDARD LVCMOS33 [get_ports {SmcData_io[12]}]
    52. 

  52. set_property PACKAGE_PIN B10 [get_ports {SmcData_io[13]}]
    53. 

  53. set_property IOSTANDARD LVCMOS33 [get_ports {SmcData_io[13]}]
    54. 

  54. set_property PACKAGE_PIN A8 [get_ports {SmcData_io[14]}]
    55. 

  55. set_property IOSTANDARD LVCMOS33 [get_ports {SmcData_io[14]}]
    56. 

  56. set_property PACKAGE_PIN A14 [get_ports {SmcData_io[15]}]
    57. 

  57. set_property IOSTANDARD LVCMOS33 [get_ports {SmcData_io[15]}]
    58. 

  58. 

  59. set_property PACKAGE_PIN B13 [get_ports SmcAmsN_i]
    60. 

  60. set_property IOSTANDARD LVCMOS33 [get_ports SmcAmsN_i]
    61. 

  61. 

  62. 

  63. set_property PACKAGE_PIN C6 [get_ports Led_o]
    64. 

  64. set_property IOSTANDARD LVCMOS33 [get_ports Led_o]
    65. 

  65. 

  66. set_property PACKAGE_PIN A9 [get_ports SmcAwe_i]
    67. 

  67. set_property IOSTANDARD LVCMOS33 [get_ports SmcAwe_i]
    68. 

  68. 

  69. set_property PACKAGE_PIN C5 [get_ports SmcAre_i]
    70. 

  70. set_property IOSTANDARD LVCMOS33 [get_ports SmcAre_i]
    71. 

  71. 

  72. set_property PACKAGE_PIN C8 [get_ports SmcAoe_i]
    73. 

  73. set_property IOSTANDARD LVCMOS33 [get_ports SmcAoe_i]
    74. 

  74. 

  75. set_property PACKAGE_PIN L15 [get_ports {SmcBe_i[1]}]
    76. 

  76. set_property IOSTANDARD LVCMOS33 [get_ports {SmcBe_i[1]}]
    77. 

  77. set_property PACKAGE_PIN L14 [get_ports {SmcBe_i[0]}]
    78. 

  78. set_property IOSTANDARD LVCMOS33 [get_ports {SmcBe_i[0]}]
    79. 

  79. 

  80. 

  81. set_property PACKAGE_PIN N11 [get_ports {Ld_i[1]}]
    82. 

  82. set_property IOSTANDARD LVCMOS33 [get_ports {Ld_i[1]}]
    83. 

  83. 

  84. set_property PACKAGE_PIN N9 [get_ports {Ld_i[2]}]
    85. 

  85. set_property IOSTANDARD LVCMOS33 [get_ports {Ld_i[2]}]
    86. 

  86. 

  87. set_property PACKAGE_PIN N13 [get_ports {Ld_i[3]}]
    88. 

  88. set_property IOSTANDARD LVCMOS33 [get_ports {Ld_i[3]}]
    89. 

  89. 

  90. set_property PACKAGE_PIN P15 [get_ports {Ld_i[4]}]
    91. 

  91. set_property IOSTANDARD LVCMOS33 [get_ports {Ld_i[4]}]
    92. 

  92. 

  93. set_property PACKAGE_PIN N12 [get_ports {Ld_i[5]}]
    94. 

  94. set_property IOSTANDARD LVCMOS33 [get_ports {Ld_i[5]}]
    95. 

  95. 

  96. set_property PACKAGE_PIN M8 [get_ports {Ld_i[6]}]
    97. 

  97. set_property IOSTANDARD LVCMOS33 [get_ports {Ld_i[6]}]
    98. 

  98. 

  99. set_property PACKAGE_PIN M13 [get_ports {Ld_i[0]}]
    100. 

  100. set_property IOSTANDARD LVCMOS33 [get_ports {Ld_i[0]}]
    101. 

  101. 

  102. #==========================================================================
    103. 

  103. #	SPI INTERFACES
    104. 

  104. 

  105. #SPI0
    106. 

  106. set_property PACKAGE_PIN K1 [get_ports {Sck_o[0]}]
    107. 

  107. set_property IOSTANDARD LVCMOS33 [get_ports {Sck_o[0]}]
    108. 

  108. 

  109. set_property PACKAGE_PIN H1 [get_ports {Ss_o[0]}]
    110. 

  110. set_property IOSTANDARD LVCMOS33 [get_ports {Ss_o[0]}]
    111. 

  111. 

  112. set_property PACKAGE_PIN K2 [get_ports {SsFlash_o[0]}]
    113. 

  113. set_property IOSTANDARD LVCMOS33 [get_ports {SsFlash_o[0]}]
    114. 

  114. 

  115. set_property PACKAGE_PIN J1 [get_ports {Mosi0_o[0]}]
    116. 

  116. set_property IOSTANDARD LVCMOS33 [get_ports {Mosi0_o[0]}]
    117. 

  117. 

  118. set_property PACKAGE_PIN J3 [get_ports {Mosi1_io[0]}]
    119. 

  119. set_property IOSTANDARD LVCMOS33 [get_ports {Mosi1_io[0]}]
    120. 

  120. 

  121. set_property PACKAGE_PIN M3 [get_ports {Mosi2_o[0]}]
    122. 

  122. set_property IOSTANDARD LVCMOS33 [get_ports {Mosi2_o[0]}]
    123. 

  123. 

  124. set_property PACKAGE_PIN L1 [get_ports {Mosi3_o[0]}]
    125. 

  125. set_property IOSTANDARD LVCMOS33 [get_ports {Mosi3_o[0]}]
    126. 

  126. 

  127. set_property PACKAGE_PIN J2 [get_ports {SpiRst_o[0]}]
    128. 

  128. set_property IOSTANDARD LVCMOS33 [get_ports {SpiRst_o[0]}]
    129. 

  129. 

  130. 

  131. 

  132. set_property PACKAGE_PIN H2 [get_ports {SpiDir_o[0]}]
    133. 

  133. set_property IOSTANDARD LVCMOS33 [get_ports {SpiDir_o[0]}]
    134. 

  134. 

  135. 

  136. 

  137. 

  138. 

  139. 

  140. 

  141. 

  142. 

  143. #SPI1
    144. 

  144. set_property PACKAGE_PIN N2 [get_ports {Sck_o[1]}]
    145. 

  145. set_property IOSTANDARD LVCMOS33 [get_ports {Sck_o[1]}]
    146. 

  146. set_property PACKAGE_PIN N4 [get_ports {Ss_o[1]}]
    147. 

  147. set_property IOSTANDARD LVCMOS33 [get_ports {Ss_o[1]}]
    148. 

  148. set_property PACKAGE_PIN P1 [get_ports {SsFlash_o[1]}]
    149. 

  149. set_property IOSTANDARD LVCMOS33 [get_ports {SsFlash_o[1]}]
    150. 

  150. set_property PACKAGE_PIN N3 [get_ports {Mosi0_o[1]}]
    151. 

  151. set_property IOSTANDARD LVCMOS33 [get_ports {Mosi0_o[1]}]
    152. 

  152. set_property PACKAGE_PIN R2 [get_ports {Mosi1_io[1]}]
    153. 

  153. set_property IOSTANDARD LVCMOS33 [get_ports {Mosi1_io[1]}]
    154. 

  154. set_property PACKAGE_PIN N1 [get_ports {Mosi2_o[1]}]
    155. 

  155. set_property IOSTANDARD LVCMOS33 [get_ports {Mosi2_o[1]}]
    156. 

  156. set_property PACKAGE_PIN M2 [get_ports {Mosi3_o[1]}]
    157. 

  157. set_property IOSTANDARD LVCMOS33 [get_ports {Mosi3_o[1]}]
    158. 

  158. set_property PACKAGE_PIN P2 [get_ports {SpiRst_o[1]}]
    159. 

  159. set_property IOSTANDARD LVCMOS33 [get_ports {SpiRst_o[1]}]
    160. 

  160. 

  161. set_property PACKAGE_PIN M1 [get_ports {SpiDir_o[1]}]
    162. 

  162. set_property IOSTANDARD LVCMOS33 [get_ports {SpiDir_o[1]}]
    163. 

  163. 

  164. 

  165. 

  166. #SPI2
    167. 

  167. set_property PACKAGE_PIN E2 [get_ports {Sck_o[2]}]
    168. 

  168. set_property IOSTANDARD LVCMOS33 [get_ports {Sck_o[2]}]
    169. 

  169. set_property PACKAGE_PIN E1 [get_ports {Ss_o[2]}]
    170. 

  170. set_property IOSTANDARD LVCMOS33 [get_ports {Ss_o[2]}]
    171. 

  171. set_property PACKAGE_PIN F1 [get_ports {SsFlash_o[2]}]
    172. 

  172. set_property IOSTANDARD LVCMOS33 [get_ports {SsFlash_o[2]}]
    173. 

  173. set_property PACKAGE_PIN D1 [get_ports {Mosi0_o[2]}]
    174. 

  174. set_property IOSTANDARD LVCMOS33 [get_ports {Mosi0_o[2]}]
    175. 

  175. set_property PACKAGE_PIN D2 [get_ports {Mosi1_io[2]}]
    176. 

  176. set_property IOSTANDARD LVCMOS33 [get_ports {Mosi1_io[2]}]
    177. 

  177. set_property PACKAGE_PIN F2 [get_ports {Mosi2_o[2]}]
    178. 

  178. set_property IOSTANDARD LVCMOS33 [get_ports {Mosi2_o[2]}]
    179. 

  179. set_property PACKAGE_PIN G1 [get_ports {Mosi3_o[2]}]
    180. 

  180. set_property IOSTANDARD LVCMOS33 [get_ports {Mosi3_o[2]}]
    181. 

  181. set_property PACKAGE_PIN E3 [get_ports {SpiRst_o[2]}]
    182. 

  182. set_property IOSTANDARD LVCMOS33 [get_ports {SpiRst_o[2]}]
    183. 

  183. 

  184. 

  185. set_property PACKAGE_PIN C1 [get_ports {SpiDir_o[2]}]
    186. 

  186. set_property IOSTANDARD LVCMOS33 [get_ports {SpiDir_o[2]}]
    187. 

  187. 

  188. 

  189. #SPI3
    190. 

  190. set_property PACKAGE_PIN R10 [get_ports {Sck_o[3]}]
    191. 

  191. set_property IOSTANDARD LVCMOS33 [get_ports {Sck_o[3]}]
    192. 

  192. set_property PACKAGE_PIN P10 [get_ports {Ss_o[3]}]
    193. 

  193. set_property IOSTANDARD LVCMOS33 [get_ports {Ss_o[3]}]
    194. 

  194. set_property PACKAGE_PIN N10 [get_ports {SsFlash_o[3]}]
    195. 

  195. set_property IOSTANDARD LVCMOS33 [get_ports {SsFlash_o[3]}]
    196. 

  196. set_property PACKAGE_PIN N8 [get_ports {Mosi0_o[3]}]
    197. 

  197. set_property IOSTANDARD LVCMOS33 [get_ports {Mosi0_o[3]}]
    198. 

  198. set_property PACKAGE_PIN R8 [get_ports {Mosi1_io[3]}]
    199. 

  199. set_property IOSTANDARD LVCMOS33 [get_ports {Mosi1_io[3]}]
    200. 

  200. set_property PACKAGE_PIN R11 [get_ports {Mosi2_o[3]}]
    201. 

  201. set_property IOSTANDARD LVCMOS33 [get_ports {Mosi2_o[3]}]
    202. 

  202. set_property PACKAGE_PIN P11 [get_ports {Mosi3_o[3]}]
    203. 

  203. set_property IOSTANDARD LVCMOS33 [get_ports {Mosi3_o[3]}]
    204. 

  204. set_property PACKAGE_PIN R9 [get_ports {SpiRst_o[3]}]
    205. 

  205. set_property IOSTANDARD LVCMOS33 [get_ports {SpiRst_o[3]}]
    206. 

  206. 

  207. set_property PACKAGE_PIN P7 [get_ports {SpiDir_o[3]}]
    208. 

  208. set_property IOSTANDARD LVCMOS33 [get_ports {SpiDir_o[3]}]
    209. 

  209. 

  210. 

  211. 

  212. #SPI4
    213. 

  213. set_property PACKAGE_PIN R14 [get_ports {Sck_o[4]}]
    214. 

  214. set_property IOSTANDARD LVCMOS33 [get_ports {Sck_o[4]}]
    215. 

  215. set_property PACKAGE_PIN N14 [get_ports {Ss_o[4]}]
    216. 

  216. set_property IOSTANDARD LVCMOS33 [get_ports {Ss_o[4]}]
    217. 

  217. set_property PACKAGE_PIN P14 [get_ports {SsFlash_o[4]}]
    218. 

  218. set_property IOSTANDARD LVCMOS33 [get_ports {SsFlash_o[4]}]
    219. 

  219. set_property PACKAGE_PIN R13 [get_ports {Mosi0_o[4]}]
    220. 

  220. set_property IOSTANDARD LVCMOS33 [get_ports {Mosi0_o[4]}]
    221. 

  221. set_property PACKAGE_PIN P12 [get_ports {Mosi1_io[4]}]
    222. 

  222. set_property IOSTANDARD LVCMOS33 [get_ports {Mosi1_io[4]}]
    223. 

  223. set_property PACKAGE_PIN M15 [get_ports {Mosi2_o[4]}]
    224. 

  224. set_property IOSTANDARD LVCMOS33 [get_ports {Mosi2_o[4]}]
    225. 

  225. set_property PACKAGE_PIN M14 [get_ports {Mosi3_o[4]}]
    226. 

  226. set_property IOSTANDARD LVCMOS33 [get_ports {Mosi3_o[4]}]
    227. 

  227. set_property PACKAGE_PIN N15 [get_ports {SpiRst_o[4]}]
    228. 

  228. set_property IOSTANDARD LVCMOS33 [get_ports {SpiRst_o[4]}]
    229. 

  229. 

  230. 

  231. set_property PACKAGE_PIN R12 [get_ports {SpiDir_o[4]}]
    232. 

  232. set_property IOSTANDARD LVCMOS33 [get_ports {SpiDir_o[4]}]
    233. 

  233. 

  234. 

  235. 

  236. #SPI5
    237. 

  237. set_property PACKAGE_PIN P6 [get_ports {Sck_o[5]}]
    238. 

  238. set_property IOSTANDARD LVCMOS33 [get_ports {Sck_o[5]}]
    239. 

  239. set_property PACKAGE_PIN R5 [get_ports {Ss_o[5]}]
    240. 

  240. set_property IOSTANDARD LVCMOS33 [get_ports {Ss_o[5]}]
    241. 

  241. set_property PACKAGE_PIN R6 [get_ports {SsFlash_o[5]}]
    242. 

  242. set_property IOSTANDARD LVCMOS33 [get_ports {SsFlash_o[5]}]
    243. 

  243. set_property PACKAGE_PIN R4 [get_ports {Mosi0_o[5]}]
    244. 

  244. set_property IOSTANDARD LVCMOS33 [get_ports {Mosi0_o[5]}]
    245. 

  245. set_property PACKAGE_PIN P3 [get_ports {Mosi1_io[5]}]
    246. 

  246. set_property IOSTANDARD LVCMOS33 [get_ports {Mosi1_io[5]}]
    247. 

  247. set_property PACKAGE_PIN N7 [get_ports {Mosi2_o[5]}]
    248. 

  248. set_property IOSTANDARD LVCMOS33 [get_ports {Mosi2_o[5]}]
    249. 

  249. set_property PACKAGE_PIN R7 [get_ports {Mosi3_o[5]}]
    250. 

  250. set_property IOSTANDARD LVCMOS33 [get_ports {Mosi3_o[5]}]
    251. 

  251. set_property PACKAGE_PIN N6 [get_ports {SpiRst_o[5]}]
    252. 

  252. set_property IOSTANDARD LVCMOS33 [get_ports {SpiRst_o[5]}]
    253. 

  253. 

  254. 

  255. set_property PACKAGE_PIN R3 [get_ports {SpiDir_o[5]}]
    256. 

  256. set_property IOSTANDARD LVCMOS33 [get_ports {SpiDir_o[5]}]
    257. 

  257. 

  258. 

  259. 

  260. #SPI6
    261. 

  261. set_property PACKAGE_PIN B5 [get_ports {Sck_o[6]}]
    262. 

  262. set_property IOSTANDARD LVCMOS33 [get_ports {Sck_o[6]}]
    263. 

  263. set_property PACKAGE_PIN B3 [get_ports {Ss_o[6]}]
    264. 

  264. set_property IOSTANDARD LVCMOS33 [get_ports {Ss_o[6]}]
    265. 

  265. set_property PACKAGE_PIN A4 [get_ports {SsFlash_o[6]}]
    266. 

  266. set_property IOSTANDARD LVCMOS33 [get_ports {SsFlash_o[6]}]
    267. 

  267. set_property PACKAGE_PIN B1 [get_ports {Mosi0_o[6]}]
    268. 

  268. set_property IOSTANDARD LVCMOS33 [get_ports {Mosi0_o[6]}]
    269. 

  269. set_property PACKAGE_PIN C4 [get_ports {Mosi1_io[6]}]
    270. 

  270. set_property IOSTANDARD LVCMOS33 [get_ports {Mosi1_io[6]}]
    271. 

  271. set_property PACKAGE_PIN B4 [get_ports {Mosi2_o[6]}]
    272. 

  272. set_property IOSTANDARD LVCMOS33 [get_ports {Mosi2_o[6]}]
    273. 

  273. set_property PACKAGE_PIN A3 [get_ports {Mosi3_o[6]}]
    274. 

  274. set_property IOSTANDARD LVCMOS33 [get_ports {Mosi3_o[6]}]
    275. 

  275. set_property PACKAGE_PIN A2 [get_ports {SpiRst_o[6]}]
    276. 

  276. set_property IOSTANDARD LVCMOS33 [get_ports {SpiRst_o[6]}]
    277. 

  277. 

  278. set_property PACKAGE_PIN B2 [get_ports {SpiDir_o[6]}]
    279. 

  279. set_property IOSTANDARD LVCMOS33 [get_ports {SpiDir_o[6]}]
    280. 

  280. 

  281. 

  282. set_property PACKAGE_PIN M7 [get_ports LD_o]
    283. 

  283. set_property IOSTANDARD LVCMOS33 [get_ports LD_o]
    284. 

  284. 

  285. #==========================================================================
    286. 

  286. #	INPUT CLOCKS
    287. 

  287. 

  288. set_property PACKAGE_PIN M10 [get_ports Clk123_i]
    289. 

  289. set_property IOSTANDARD LVCMOS33 [get_ports Clk123_i]
    290. 

  290. create_clock -period 8.130 -name Clk123_i -waveform {0.000 4.065} -add [get_ports Clk123_i]
    291. 

  291. 

  292. set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets Clk123_i_IBUF]
    293. 

  293. # set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets SmcAre_i_IBUF]
    294. 

  294. 

  295. 

  296. 

  297. 

  298. 

  299. 

  300. set_false_path -from [get_clocks -of_objects [get_pins ClkManager/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT0]] -to [get_clocks -of_objects [get_pins ClkManager/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT1]]
    301. 

  301. set_false_path -from [get_clocks -of_objects [get_pins ClkManager/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT0]] -to [get_clocks -of_objects [get_pins ClkManager/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT2]]
    302. 

  302. set_false_path -from [get_clocks -of_objects [get_pins ClkManager/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT0]] -to [get_clocks -of_objects [get_pins ClkManager/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT3]]
    303. 

  303. set_false_path -from [get_clocks -of_objects [get_pins ClkManager/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT0]] -to [get_clocks -of_objects [get_pins ClkManager/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT5]]
    304. 

  304. set_false_path -from [get_clocks -of_objects [get_pins ClkManager/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT0]] -to [get_clocks -of_objects [get_pins ClkManager/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT4]]
    305. 

  305. set_false_path -from [get_clocks -of_objects [get_pins ClkManager/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT0]] -to [get_clocks -of_objects [get_pins ClkManager/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT6]]
    306. 

  306. 

  307. set_false_path -from [get_clocks -of_objects [get_pins ClkManager/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT1]] -to [get_clocks -of_objects [get_pins ClkManager/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT0]]
    308. 

  308. set_false_path -from [get_clocks -of_objects [get_pins ClkManager/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT1]] -to [get_clocks -of_objects [get_pins ClkManager/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT2]]
    309. 

  309. set_false_path -from [get_clocks -of_objects [get_pins ClkManager/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT1]] -to [get_clocks -of_objects [get_pins ClkManager/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT3]]
    310. 

  310. set_false_path -from [get_clocks -of_objects [get_pins ClkManager/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT1]] -to [get_clocks -of_objects [get_pins ClkManager/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT4]]
    311. 

  311. set_false_path -from [get_clocks -of_objects [get_pins ClkManager/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT1]] -to [get_clocks -of_objects [get_pins ClkManager/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT5]]
    312. 

  312. set_false_path -from [get_clocks -of_objects [get_pins ClkManager/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT1]] -to [get_clocks -of_objects [get_pins ClkManager/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT6]]
    313. 

  313. 

  314. set_false_path -from [get_clocks -of_objects [get_pins ClkManager/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT2]] -to [get_clocks -of_objects [get_pins ClkManager/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT0]]
    315. 

  315. set_false_path -from [get_clocks -of_objects [get_pins ClkManager/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT2]] -to [get_clocks -of_objects [get_pins ClkManager/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT1]]
    316. 

  316. set_false_path -from [get_clocks -of_objects [get_pins ClkManager/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT2]] -to [get_clocks -of_objects [get_pins ClkManager/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT3]]
    317. 

  317. set_false_path -from [get_clocks -of_objects [get_pins ClkManager/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT2]] -to [get_clocks -of_objects [get_pins ClkManager/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT4]]
    318. 

  318. set_false_path -from [get_clocks -of_objects [get_pins ClkManager/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT2]] -to [get_clocks -of_objects [get_pins ClkManager/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT5]]
    319. 

  319. set_false_path -from [get_clocks -of_objects [get_pins ClkManager/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT2]] -to [get_clocks -of_objects [get_pins ClkManager/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT6]]
    320. 

  320. 

  321. set_false_path -from [get_clocks -of_objects [get_pins ClkManager/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT3]] -to [get_clocks -of_objects [get_pins ClkManager/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT0]]
    322. 

  322. set_false_path -from [get_clocks -of_objects [get_pins ClkManager/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT3]] -to [get_clocks -of_objects [get_pins ClkManager/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT1]]
    323. 

  323. set_false_path -from [get_clocks -of_objects [get_pins ClkManager/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT3]] -to [get_clocks -of_objects [get_pins ClkManager/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT2]]
    324. 

  324. set_false_path -from [get_clocks -of_objects [get_pins ClkManager/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT3]] -to [get_clocks -of_objects [get_pins ClkManager/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT4]]
    325. 

  325. set_false_path -from [get_clocks -of_objects [get_pins ClkManager/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT3]] -to [get_clocks -of_objects [get_pins ClkManager/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT5]]
    326. 

  326. set_false_path -from [get_clocks -of_objects [get_pins ClkManager/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT3]] -to [get_clocks -of_objects [get_pins ClkManager/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT6]]
    327. 

  327. 

  328. set_false_path -from [get_clocks -of_objects [get_pins ClkManager/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT4]] -to [get_clocks -of_objects [get_pins ClkManager/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT0]]
    329. 

  329. set_false_path -from [get_clocks -of_objects [get_pins ClkManager/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT4]] -to [get_clocks -of_objects [get_pins ClkManager/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT1]]
    330. 

  330. set_false_path -from [get_clocks -of_objects [get_pins ClkManager/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT4]] -to [get_clocks -of_objects [get_pins ClkManager/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT2]]
    331. 

  331. set_false_path -from [get_clocks -of_objects [get_pins ClkManager/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT4]] -to [get_clocks -of_objects [get_pins ClkManager/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT3]]
    332. 

  332. set_false_path -from [get_clocks -of_objects [get_pins ClkManager/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT4]] -to [get_clocks -of_objects [get_pins ClkManager/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT5]]
    333. 

  333. set_false_path -from [get_clocks -of_objects [get_pins ClkManager/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT4]] -to [get_clocks -of_objects [get_pins ClkManager/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT6]]
    334. 

  334. 

  335. set_false_path -from [get_clocks -of_objects [get_pins ClkManager/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT5]] -to [get_clocks -of_objects [get_pins ClkManager/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT0]]
    336. 

  336. set_false_path -from [get_clocks -of_objects [get_pins ClkManager/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT5]] -to [get_clocks -of_objects [get_pins ClkManager/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT1]]
    337. 

  337. set_false_path -from [get_clocks -of_objects [get_pins ClkManager/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT5]] -to [get_clocks -of_objects [get_pins ClkManager/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT2]]
    338. 

  338. set_false_path -from [get_clocks -of_objects [get_pins ClkManager/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT5]] -to [get_clocks -of_objects [get_pins ClkManager/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT3]]
    339. 

  339. set_false_path -from [get_clocks -of_objects [get_pins ClkManager/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT5]] -to [get_clocks -of_objects [get_pins ClkManager/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT4]]
    340. 

  340. set_false_path -from [get_clocks -of_objects [get_pins ClkManager/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT5]] -to [get_clocks -of_objects [get_pins ClkManager/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT6]]
    341. 

  341. 

  342. set_false_path -from [get_clocks -of_objects [get_pins ClkManager/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT6]] -to [get_clocks -of_objects [get_pins ClkManager/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT0]]
    343. 

  343. set_false_path -from [get_clocks -of_objects [get_pins ClkManager/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT6]] -to [get_clocks -of_objects [get_pins ClkManager/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT1]]
    344. 

  344. set_false_path -from [get_clocks -of_objects [get_pins ClkManager/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT6]] -to [get_clocks -of_objects [get_pins ClkManager/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT2]]
    345. 

  345. set_false_path -from [get_clocks -of_objects [get_pins ClkManager/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT6]] -to [get_clocks -of_objects [get_pins ClkManager/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT3]]
    346. 

  346. set_false_path -from [get_clocks -of_objects [get_pins ClkManager/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT6]] -to [get_clocks -of_objects [get_pins ClkManager/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT4]]
    347. 

  347. set_false_path -from [get_clocks -of_objects [get_pins ClkManager/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT6]] -to [get_clocks -of_objects [get_pins ClkManager/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT5]]
    348. 

  348. 

  349. 

  350. 

  351. 

  352. 

  353. # set_clock_groups -async -group [get_clocks Clk123_i] -group [get_clocks -of_objects [get_pins ClkManager/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT0]]
    354. 

  354. # set_clock_groups -async -group [get_clocks Clk123_i] -group [get_clocks -of_objects [get_pins ClkManager/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT1]]
    355. 

  355. # set_clock_groups -async -group [get_clocks Clk123_i] -group [get_clocks -of_objects [get_pins ClkManager/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT2]]
    356. 

  356. # set_clock_groups -async -group [get_clocks Clk123_i] -group [get_clocks -of_objects [get_pins ClkManager/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT3]]
    357. 

  357. # set_clock_groups -async -group [get_clocks Clk123_i] -group [get_clocks -of_objects [get_pins ClkManager/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT4]]
    358. 

  358. # set_clock_groups -async -group [get_clocks Clk123_i] -group [get_clocks -of_objects [get_pins ClkManager/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT5]]
    359. 

  359. # set_clock_groups -async -group [get_clocks Clk123_i] -group [get_clocks -of_objects [get_pins ClkManager/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT6]]
    360. 

  360. 

  361. 

  362. set_false_path -from [get_clocks Clk123_i] -to [get_clocks -of_objects [get_pins ClkManager/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT6]]
    363. 

  363. set_false_path -from [get_clocks -of_objects [get_pins ClkManager/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT6]] -to [get_clocks Clk123_i]
    364. 

  364. # set_false_path -from [get_clocks -of_objects [get_pins ClkManager/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT6]] -to [get_clocks -of_objects [get_pins ClkManager/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT6]]
    365. 

  365. 

  366. set_false_path -from [get_clocks Clk123_i] -to [get_clocks -of_objects [get_pins ClkManager/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT5]]
    367. 

  367. set_false_path -from [get_clocks -of_objects [get_pins ClkManager/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT5]] -to [get_clocks Clk123_i]
    368. 

  368. # set_false_path -from [get_clocks -of_objects [get_pins ClkManager/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT5]] -to [get_clocks -of_objects [get_pins ClkManager/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT5]]
    369. 

  369. 

  370. 

  371. set_false_path -from [get_clocks Clk123_i] -to [get_clocks -of_objects [get_pins ClkManager/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT4]]
    372. 

  372. set_false_path -from [get_clocks -of_objects [get_pins ClkManager/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT4]] -to [get_clocks Clk123_i]
    373. 

  373. # set_false_path -from [get_clocks -of_objects [get_pins ClkManager/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT4]] -to [get_clocks -of_objects [get_pins ClkManager/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT4]]
    374. 

  374. 

  375. 

  376. set_false_path -from [get_clocks Clk123_i] -to [get_clocks -of_objects [get_pins ClkManager/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT3]]
    377. 

  377. set_false_path -from [get_clocks -of_objects [get_pins ClkManager/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT3]] -to [get_clocks Clk123_i]
    378. 

  378. # set_false_path -from [get_clocks -of_objects [get_pins ClkManager/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT3]] -to [get_clocks -of_objects [get_pins ClkManager/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT3]]
    379. 

  379. 

  380. 

  381. set_false_path -from [get_clocks Clk123_i] -to [get_clocks -of_objects [get_pins ClkManager/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT2]]
    382. 

  382. set_false_path -from [get_clocks -of_objects [get_pins ClkManager/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT2]] -to [get_clocks Clk123_i]
    383. 

  383. # set_false_path -from [get_clocks -of_objects [get_pins ClkManager/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT2]] -to [get_clocks -of_objects [get_pins ClkManager/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT2]]
    384. 

  384. 

  385. 

  386. set_false_path -from [get_clocks Clk123_i] -to [get_clocks -of_objects [get_pins ClkManager/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT1]]
    387. 

  387. set_false_path -from [get_clocks -of_objects [get_pins ClkManager/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT1]] -to [get_clocks Clk123_i]
    388. 

  388. # set_false_path -from [get_clocks -of_objects [get_pins ClkManager/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT1]] -to [get_clocks -of_objects [get_pins ClkManager/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT1]]
    389. 

  389. 

  390. 

  391. set_false_path -from [get_clocks Clk123_i] -to [get_clocks -of_objects [get_pins ClkManager/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT0]]
    392. 

  392. set_false_path -from [get_clocks -of_objects [get_pins ClkManager/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT0]] -to [get_clocks Clk123_i]
    393. 

  393. # set_false_path -from [get_clocks -of_objects [get_pins ClkManager/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT0]] -to [get_clocks -of_objects [get_pins ClkManager/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT0]]
    394. 

  394. 

  395. 

  396. connect_debug_port u_ila_0/probe4 [get_nets [list {Mosi1_io_IBUF[0]}]]
    397. 

  397. connect_debug_port u_ila_0/probe11 [get_nets [list {Mosi1_io_OBUF[0]}]]
    398. 

  398. connect_debug_port u_ila_0/probe12 [get_nets [list {dataToRxFifo[0][31]} {dataToRxFifo[0][30]} {dataToRxFifo[0][29]} {dataToRxFifo[0][28]} {dataToRxFifo[0][27]} {dataToRxFifo[0][26]} {dataToRxFifo[0][25]} {dataToRxFifo[0][24]} {dataToRxFifo[0][23]} {dataToRxFifo[0][22]} {dataToRxFifo[0][21]} {dataToRxFifo[0][20]} {dataToRxFifo[0][19]} {dataToRxFifo[0][18]} {dataToRxFifo[0][17]} {dataToRxFifo[0][16]} {dataToRxFifo[0][15]} {dataToRxFifo[0][14]} {dataToRxFifo[0][13]} {dataToRxFifo[0][12]} {dataToRxFifo[0][11]} {dataToRxFifo[0][10]} {dataToRxFifo[0][9]} {dataToRxFifo[0][8]} {dataToRxFifo[0][7]} {dataToRxFifo[0][6]} {dataToRxFifo[0][5]} {dataToRxFifo[0][4]} {dataToRxFifo[0][3]} {dataToRxFifo[0][2]} {dataToRxFifo[0][1]} {dataToRxFifo[0][0]}]]
    399. 

  399. connect_debug_port u_ila_0/probe22 [get_nets [list {toSpiData[0][31]} {toSpiData[0][30]} {toSpiData[0][29]} {toSpiData[0][28]} {toSpiData[0][27]} {toSpiData[0][26]} {toSpiData[0][25]} {toSpiData[0][24]} {toSpiData[0][23]} {toSpiData[0][22]} {toSpiData[0][21]} {toSpiData[0][20]} {toSpiData[0][19]} {toSpiData[0][18]} {toSpiData[0][17]} {toSpiData[0][16]} {toSpiData[0][15]} {toSpiData[0][14]} {toSpiData[0][13]} {toSpiData[0][12]} {toSpiData[0][11]} {toSpiData[0][10]} {toSpiData[0][9]} {toSpiData[0][8]} {toSpiData[0][7]} {toSpiData[0][6]} {toSpiData[0][5]} {toSpiData[0][4]} {toSpiData[0][3]} {toSpiData[0][2]} {toSpiData[0][1]} {toSpiData[0][0]}]]
    400. 

  400. connect_debug_port u_ila_0/probe24 [get_nets [list {toSpiData[6][31]} {toSpiData[6][30]} {toSpiData[6][29]} {toSpiData[6][28]} {toSpiData[6][27]} {toSpiData[6][26]} {toSpiData[6][25]} {toSpiData[6][24]} {toSpiData[6][23]} {toSpiData[6][22]} {toSpiData[6][21]} {toSpiData[6][20]} {toSpiData[6][19]} {toSpiData[6][18]} {toSpiData[6][17]} {toSpiData[6][16]} {toSpiData[6][15]} {toSpiData[6][14]} {toSpiData[6][13]} {toSpiData[6][12]} {toSpiData[6][11]} {toSpiData[6][10]} {toSpiData[6][9]} {toSpiData[6][8]} {toSpiData[6][7]} {toSpiData[6][6]} {toSpiData[6][5]} {toSpiData[6][4]} {toSpiData[6][3]} {toSpiData[6][2]} {toSpiData[6][1]} {toSpiData[6][0]}]]
    401. 

  401. connect_debug_port u_ila_0/probe25 [get_nets [list {SpiGen[0].DataFifoWrapper/RxFifoCtrlReg_o[2]}]]
    402. 

  402. connect_debug_port u_ila_0/probe26 [get_nets [list {SpiGen[0].DataFifoWrapper/ToSpiData_o[0]} {SpiGen[0].DataFifoWrapper/ToSpiData_o[1]} {SpiGen[0].DataFifoWrapper/ToSpiData_o[2]} {SpiGen[0].DataFifoWrapper/ToSpiData_o[3]} {SpiGen[0].DataFifoWrapper/ToSpiData_o[4]} {SpiGen[0].DataFifoWrapper/ToSpiData_o[5]} {SpiGen[0].DataFifoWrapper/ToSpiData_o[6]} {SpiGen[0].DataFifoWrapper/ToSpiData_o[7]} {SpiGen[0].DataFifoWrapper/ToSpiData_o[8]} {SpiGen[0].DataFifoWrapper/ToSpiData_o[9]} {SpiGen[0].DataFifoWrapper/ToSpiData_o[10]} {SpiGen[0].DataFifoWrapper/ToSpiData_o[11]} {SpiGen[0].DataFifoWrapper/ToSpiData_o[12]} {SpiGen[0].DataFifoWrapper/ToSpiData_o[13]} {SpiGen[0].DataFifoWrapper/ToSpiData_o[14]} {SpiGen[0].DataFifoWrapper/ToSpiData_o[15]} {SpiGen[0].DataFifoWrapper/ToSpiData_o[16]} {SpiGen[0].DataFifoWrapper/ToSpiData_o[17]} {SpiGen[0].DataFifoWrapper/ToSpiData_o[18]} {SpiGen[0].DataFifoWrapper/ToSpiData_o[19]} {SpiGen[0].DataFifoWrapper/ToSpiData_o[20]} {SpiGen[0].DataFifoWrapper/ToSpiData_o[21]} {SpiGen[0].DataFifoWrapper/ToSpiData_o[22]} {SpiGen[0].DataFifoWrapper/ToSpiData_o[23]} {SpiGen[0].DataFifoWrapper/ToSpiData_o[24]} {SpiGen[0].DataFifoWrapper/ToSpiData_o[25]} {SpiGen[0].DataFifoWrapper/ToSpiData_o[26]} {SpiGen[0].DataFifoWrapper/ToSpiData_o[27]} {SpiGen[0].DataFifoWrapper/ToSpiData_o[28]} {SpiGen[0].DataFifoWrapper/ToSpiData_o[29]} {SpiGen[0].DataFifoWrapper/ToSpiData_o[30]} {SpiGen[0].DataFifoWrapper/ToSpiData_o[31]}]]
    403. 

  403. connect_debug_port u_ila_0/probe27 [get_nets [list {SpiGen[6].DataFifoWrapper/RxFifoCtrlReg_o[1]} {SpiGen[6].DataFifoWrapper/RxFifoCtrlReg_o[2]}]]
    404. 

  404. connect_debug_port u_ila_0/probe28 [get_nets [list {SpiGen[0].DataFifoWrapper/FifoCtrl_inst/txFifoUpDnCnt_reg00_out[0]} {SpiGen[0].DataFifoWrapper/FifoCtrl_inst/txFifoUpDnCnt_reg00_out[1]} {SpiGen[0].DataFifoWrapper/FifoCtrl_inst/txFifoUpDnCnt_reg00_out[2]} {SpiGen[0].DataFifoWrapper/FifoCtrl_inst/txFifoUpDnCnt_reg00_out[3]} {SpiGen[0].DataFifoWrapper/FifoCtrl_inst/txFifoUpDnCnt_reg00_out[4]} {SpiGen[0].DataFifoWrapper/FifoCtrl_inst/txFifoUpDnCnt_reg00_out[5]} {SpiGen[0].DataFifoWrapper/FifoCtrl_inst/txFifoUpDnCnt_reg00_out[6]} {SpiGen[0].DataFifoWrapper/FifoCtrl_inst/txFifoUpDnCnt_reg00_out[7]}]]
    405. 

  405. connect_debug_port u_ila_0/probe29 [get_nets [list {SpiGen[0].DataFifoWrapper/FifoCtrl_inst/txFifoWrPtr[0]} {SpiGen[0].DataFifoWrapper/FifoCtrl_inst/txFifoWrPtr[1]} {SpiGen[0].DataFifoWrapper/FifoCtrl_inst/txFifoWrPtr[2]} {SpiGen[0].DataFifoWrapper/FifoCtrl_inst/txFifoWrPtr[3]} {SpiGen[0].DataFifoWrapper/FifoCtrl_inst/txFifoWrPtr[4]} {SpiGen[0].DataFifoWrapper/FifoCtrl_inst/txFifoWrPtr[5]} {SpiGen[0].DataFifoWrapper/FifoCtrl_inst/txFifoWrPtr[6]} {SpiGen[0].DataFifoWrapper/FifoCtrl_inst/txFifoWrPtr[7]}]]
    406. 

  406. connect_debug_port u_ila_0/probe30 [get_nets [list {SpiGen[0].DataFifoWrapper/FifoCtrl_inst/txFifoRdPtr[0]} {SpiGen[0].DataFifoWrapper/FifoCtrl_inst/txFifoRdPtr[1]} {SpiGen[0].DataFifoWrapper/FifoCtrl_inst/txFifoRdPtr[2]} {SpiGen[0].DataFifoWrapper/FifoCtrl_inst/txFifoRdPtr[3]} {SpiGen[0].DataFifoWrapper/FifoCtrl_inst/txFifoRdPtr[4]} {SpiGen[0].DataFifoWrapper/FifoCtrl_inst/txFifoRdPtr[5]} {SpiGen[0].DataFifoWrapper/FifoCtrl_inst/txFifoRdPtr[6]} {SpiGen[0].DataFifoWrapper/FifoCtrl_inst/txFifoRdPtr[7]}]]
    407. 

  407. connect_debug_port u_ila_0/probe31 [get_nets [list {SpiGen[0].DataFifoWrapper/FifoCtrl_inst/txFifoRdPtrSync[0]} {SpiGen[0].DataFifoWrapper/FifoCtrl_inst/txFifoRdPtrSync[1]} {SpiGen[0].DataFifoWrapper/FifoCtrl_inst/txFifoRdPtrSync[2]} {SpiGen[0].DataFifoWrapper/FifoCtrl_inst/txFifoRdPtrSync[3]} {SpiGen[0].DataFifoWrapper/FifoCtrl_inst/txFifoRdPtrSync[4]} {SpiGen[0].DataFifoWrapper/FifoCtrl_inst/txFifoRdPtrSync[5]} {SpiGen[0].DataFifoWrapper/FifoCtrl_inst/txFifoRdPtrSync[6]} {SpiGen[0].DataFifoWrapper/FifoCtrl_inst/txFifoRdPtrSync[7]}]]
    408. 

  408. connect_debug_port u_ila_0/probe32 [get_nets [list emptyFlagTx_0]]
    409. 

  409. connect_debug_port u_ila_0/probe33 [get_nets [list {SpiGen[0].DataFifoWrapper/emptyFlagTxForDsp}]]
    410. 

  410. connect_debug_port u_ila_0/probe34 [get_nets [list {SpiGen[6].DataFifoWrapper/emptyFlagTxForDsp}]]
    411. 

  411. connect_debug_port u_ila_0/probe35 [get_nets [list {SpiGen[0].DataFifoWrapper/rxFifoRdEn}]]
    412. 

  412. connect_debug_port u_ila_0/probe36 [get_nets [list {SpiGen[6].DataFifoWrapper/rxFifoRdEn}]]
    413. 

  413. connect_debug_port u_ila_0/probe37 [get_nets [list {SpiGen[0].DataFifoWrapper/rxFifoWrEn}]]
    414. 

  414. connect_debug_port u_ila_0/probe38 [get_nets [list {SpiGen[6].DataFifoWrapper/rxFifoWrEn}]]
    415. 

  415. connect_debug_port u_ila_0/probe41 [get_nets [list spiTxEnSync_0]]
    416. 

  416. connect_debug_port u_ila_0/probe42 [get_nets [list {SpiGen[6].DataFifoWrapper/txFifoRdEn}]]
    417. 

  417. connect_debug_port u_ila_0/probe43 [get_nets [list {SpiGen[0].DataFifoWrapper/txFifoRdEn}]]
    418. 

  418. connect_debug_port u_ila_0/probe44 [get_nets [list {SpiGen[0].DataFifoWrapper/txFifoWrEn}]]
    419. 

  419. connect_debug_port u_ila_0/probe45 [get_nets [list {SpiGen[6].DataFifoWrapper/txFifoWrEn}]]
    420. 

  420. connect_debug_port u_ila_0/probe46 [get_nets [list spiTxEnSync_6]]
    421. 

  421. 

  422. 

  423. set_clock_groups -asynchronous -group [get_clocks [list Clk123_i [get_clocks -of_objects [get_pins ClkManager/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT1]] [get_clocks -of_objects [get_pins ClkManager/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT2]] [get_clocks -of_objects [get_pins ClkManager/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT3]] [get_clocks -of_objects [get_pins ClkManager/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT4]] [get_clocks -of_objects [get_pins ClkManager/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT5]] [get_clocks -of_objects [get_pins ClkManager/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT6]]]]
    424. 

  424. 

  425. create_debug_core u_ila_0 ila
    426. 

  426. set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0]
    427. 

  427. set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_0]
    428. 

  428. set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0]
    429. 

  429. set_property C_DATA_DEPTH 1024 [get_debug_cores u_ila_0]
    430. 

  430. set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_0]
    431. 

  431. set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0]
    432. 

  432. set_property C_TRIGIN_EN false [get_debug_cores u_ila_0]
    433. 

  433. set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0]
    434. 

  434. set_property port_width 1 [get_debug_ports u_ila_0/clk]
    435. 

  435. connect_debug_port u_ila_0/clk [get_nets [list gclk]]
    436. 

  436. set_property PROBE_TYPE DATA [get_debug_ports u_ila_0/probe0]
    437. 

  437. set_property port_width 32 [get_debug_ports u_ila_0/probe0]
    438. 

  438. connect_debug_port u_ila_0/probe0 [get_nets [list {toFifoData[0]} {toFifoData[1]} {toFifoData[2]} {toFifoData[3]} {toFifoData[4]} {toFifoData[5]} {toFifoData[6]} {toFifoData[7]} {toFifoData[8]} {toFifoData[9]} {toFifoData[10]} {toFifoData[11]} {toFifoData[12]} {toFifoData[13]} {toFifoData[14]} {toFifoData[15]} {toFifoData[16]} {toFifoData[17]} {toFifoData[18]} {toFifoData[19]} {toFifoData[20]} {toFifoData[21]} {toFifoData[22]} {toFifoData[23]} {toFifoData[24]} {toFifoData[25]} {toFifoData[26]} {toFifoData[27]} {toFifoData[28]} {toFifoData[29]} {toFifoData[30]} {toFifoData[31]}]]
    439. 

  439. create_debug_port u_ila_0 probe
    440. 

  440. set_property PROBE_TYPE DATA [get_debug_ports u_ila_0/probe1]
    441. 

  441. set_property port_width 9 [get_debug_ports u_ila_0/probe1]
    442. 

  442. connect_debug_port u_ila_0/probe1 [get_nets [list {toRegMapAddr[1]} {toRegMapAddr[2]} {toRegMapAddr[3]} {toRegMapAddr[4]} {toRegMapAddr[5]} {toRegMapAddr[6]} {toRegMapAddr[7]} {toRegMapAddr[8]} {toRegMapAddr[9]}]]
    443. 

  443. create_debug_port u_ila_0 probe
    444. 

  444. set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2]
    445. 

  445. set_property port_width 16 [get_debug_ports u_ila_0/probe2]
    446. 

  446. connect_debug_port u_ila_0/probe2 [get_nets [list {spi0RxFifoCtrl[0]} {spi0RxFifoCtrl[1]} {spi0RxFifoCtrl[2]} {spi0RxFifoCtrl[3]} {spi0RxFifoCtrl[4]} {spi0RxFifoCtrl[5]} {spi0RxFifoCtrl[6]} {spi0RxFifoCtrl[7]} {spi0RxFifoCtrl[8]} {spi0RxFifoCtrl[9]} {spi0RxFifoCtrl[10]} {spi0RxFifoCtrl[11]} {spi0RxFifoCtrl[12]} {spi0RxFifoCtrl[13]} {spi0RxFifoCtrl[14]} {spi0RxFifoCtrl[15]}]]
    447. 

  447. create_debug_port u_ila_0 probe
    448. 

  448. set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3]
    449. 

  449. set_property port_width 16 [get_debug_ports u_ila_0/probe3]
    450. 

  450. connect_debug_port u_ila_0/probe3 [get_nets [list {spi0TxFifoCtrl[0]} {spi0TxFifoCtrl[1]} {spi0TxFifoCtrl[2]} {spi0TxFifoCtrl[3]} {spi0TxFifoCtrl[4]} {spi0TxFifoCtrl[5]} {spi0TxFifoCtrl[6]} {spi0TxFifoCtrl[7]} {spi0TxFifoCtrl[8]} {spi0TxFifoCtrl[9]} {spi0TxFifoCtrl[10]} {spi0TxFifoCtrl[11]} {spi0TxFifoCtrl[12]} {spi0TxFifoCtrl[13]} {spi0TxFifoCtrl[14]} {spi0TxFifoCtrl[15]}]]
    451. 

  451. create_debug_port u_ila_0 probe
    452. 

  452. set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4]
    453. 

  453. set_property port_width 8 [get_debug_ports u_ila_0/probe4]
    454. 

  454. connect_debug_port u_ila_0/probe4 [get_nets [list {RegMap_inst/Spi0ClkReg_o[0]} {RegMap_inst/Spi0ClkReg_o[1]} {RegMap_inst/Spi0ClkReg_o[2]} {RegMap_inst/Spi0ClkReg_o[3]} {RegMap_inst/Spi0ClkReg_o[4]} {RegMap_inst/Spi0ClkReg_o[5]} {RegMap_inst/Spi0ClkReg_o[6]} {RegMap_inst/Spi0ClkReg_o[7]}]]
    455. 

  455. create_debug_port u_ila_0 probe
    456. 

  456. set_property PROBE_TYPE DATA [get_debug_ports u_ila_0/probe5]
    457. 

  457. set_property port_width 11 [get_debug_ports u_ila_0/probe5]
    458. 

  458. connect_debug_port u_ila_0/probe5 [get_nets [list {RegMap_inst/TxFifoCtrlReg0_i[0]} {RegMap_inst/TxFifoCtrlReg0_i[1]} {RegMap_inst/TxFifoCtrlReg0_i[2]} {RegMap_inst/TxFifoCtrlReg0_i[8]} {RegMap_inst/TxFifoCtrlReg0_i[9]} {RegMap_inst/TxFifoCtrlReg0_i[10]} {RegMap_inst/TxFifoCtrlReg0_i[11]} {RegMap_inst/TxFifoCtrlReg0_i[12]} {RegMap_inst/TxFifoCtrlReg0_i[13]} {RegMap_inst/TxFifoCtrlReg0_i[14]} {RegMap_inst/TxFifoCtrlReg0_i[15]}]]
    459. 

  459. create_debug_port u_ila_0 probe
    460. 

  460. set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe6]
    461. 

  461. set_property port_width 16 [get_debug_ports u_ila_0/probe6]
    462. 

  462. connect_debug_port u_ila_0/probe6 [get_nets [list {spi0Ctrl[0]} {spi0Ctrl[1]} {spi0Ctrl[2]} {spi0Ctrl[3]} {spi0Ctrl[4]} {spi0Ctrl[5]} {spi0Ctrl[6]} {spi0Ctrl[7]} {spi0Ctrl[8]} {spi0Ctrl[9]} {spi0Ctrl[10]} {spi0Ctrl[11]} {spi0Ctrl[12]} {spi0Ctrl[13]} {spi0Ctrl[14]} {spi0Ctrl[15]}]]
    463. 

  463. create_debug_port u_ila_0 probe
    464. 

  464. set_property PROBE_TYPE DATA [get_debug_ports u_ila_0/probe7]
    465. 

  465. set_property port_width 1 [get_debug_ports u_ila_0/probe7]
    466. 

  466. connect_debug_port u_ila_0/probe7 [get_nets [list {Mosi0_o_OBUF[0]}]]
    467. 

  467. create_debug_port u_ila_0 probe
    468. 

  468. set_property PROBE_TYPE DATA [get_debug_ports u_ila_0/probe8]
    469. 

  469. set_property port_width 1 [get_debug_ports u_ila_0/probe8]
    470. 

  470. connect_debug_port u_ila_0/probe8 [get_nets [list {Mosi2_o_OBUF[0]}]]
    471. 

  471. create_debug_port u_ila_0 probe
    472. 

  472. set_property PROBE_TYPE DATA [get_debug_ports u_ila_0/probe9]
    473. 

  473. set_property port_width 1 [get_debug_ports u_ila_0/probe9]
    474. 

  474. connect_debug_port u_ila_0/probe9 [get_nets [list {Mosi3_o_OBUF[0]}]]
    475. 

  475. create_debug_port u_ila_0 probe
    476. 

  476. set_property PROBE_TYPE DATA [get_debug_ports u_ila_0/probe10]
    477. 

  477. set_property port_width 11 [get_debug_ports u_ila_0/probe10]
    478. 

  478. connect_debug_port u_ila_0/probe10 [get_nets [list {SmcAddr_i_IBUF[0]} {SmcAddr_i_IBUF[1]} {SmcAddr_i_IBUF[2]} {SmcAddr_i_IBUF[3]} {SmcAddr_i_IBUF[4]} {SmcAddr_i_IBUF[5]} {SmcAddr_i_IBUF[6]} {SmcAddr_i_IBUF[7]} {SmcAddr_i_IBUF[8]} {SmcAddr_i_IBUF[9]} {SmcAddr_i_IBUF[10]}]]
    479. 

  479. create_debug_port u_ila_0 probe
    480. 

  480. set_property PROBE_TYPE DATA [get_debug_ports u_ila_0/probe11]
    481. 

  481. set_property port_width 1 [get_debug_ports u_ila_0/probe11]
    482. 

  482. connect_debug_port u_ila_0/probe11 [get_nets [list {Sck_o_OBUF[0]}]]
    483. 

  483. create_debug_port u_ila_0 probe
    484. 

  484. set_property PROBE_TYPE DATA [get_debug_ports u_ila_0/probe12]
    485. 

  485. set_property port_width 16 [get_debug_ports u_ila_0/probe12]
    486. 

  486. connect_debug_port u_ila_0/probe12 [get_nets [list {SmcData_io_IBUF[0]} {SmcData_io_IBUF[1]} {SmcData_io_IBUF[2]} {SmcData_io_IBUF[3]} {SmcData_io_IBUF[4]} {SmcData_io_IBUF[5]} {SmcData_io_IBUF[6]} {SmcData_io_IBUF[7]} {SmcData_io_IBUF[8]} {SmcData_io_IBUF[9]} {SmcData_io_IBUF[10]} {SmcData_io_IBUF[11]} {SmcData_io_IBUF[12]} {SmcData_io_IBUF[13]} {SmcData_io_IBUF[14]} {SmcData_io_IBUF[15]}]]
    487. 

  487. create_debug_port u_ila_0 probe
    488. 

  488. set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe13]
    489. 

  489. set_property port_width 1 [get_debug_ports u_ila_0/probe13]
    490. 

  490. connect_debug_port u_ila_0/probe13 [get_nets [list {SsFlash_o_OBUF[0]}]]
    491. 

  491. create_debug_port u_ila_0 probe
    492. 

  492. set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe14]
    493. 

  493. set_property port_width 1 [get_debug_ports u_ila_0/probe14]
    494. 

  494. connect_debug_port u_ila_0/probe14 [get_nets [list {Ss_o_OBUF[0]}]]
    495. 

  495. create_debug_port u_ila_0 probe
    496. 

  496. set_property PROBE_TYPE DATA [get_debug_ports u_ila_0/probe15]
    497. 

  497. set_property port_width 32 [get_debug_ports u_ila_0/probe15]
    498. 

  498. connect_debug_port u_ila_0/probe15 [get_nets [list {dataFromRxFifo[0][31]} {dataFromRxFifo[0][30]} {dataFromRxFifo[0][29]} {dataFromRxFifo[0][28]} {dataFromRxFifo[0][27]} {dataFromRxFifo[0][26]} {dataFromRxFifo[0][25]} {dataFromRxFifo[0][24]} {dataFromRxFifo[0][23]} {dataFromRxFifo[0][22]} {dataFromRxFifo[0][21]} {dataFromRxFifo[0][20]} {dataFromRxFifo[0][19]} {dataFromRxFifo[0][18]} {dataFromRxFifo[0][17]} {dataFromRxFifo[0][16]} {dataFromRxFifo[0][15]} {dataFromRxFifo[0][14]} {dataFromRxFifo[0][13]} {dataFromRxFifo[0][12]} {dataFromRxFifo[0][11]} {dataFromRxFifo[0][10]} {dataFromRxFifo[0][9]} {dataFromRxFifo[0][8]} {dataFromRxFifo[0][7]} {dataFromRxFifo[0][6]} {dataFromRxFifo[0][5]} {dataFromRxFifo[0][4]} {dataFromRxFifo[0][3]} {dataFromRxFifo[0][2]} {dataFromRxFifo[0][1]} {dataFromRxFifo[0][0]}]]
    499. 

  499. create_debug_port u_ila_0 probe
    500. 

  500. set_property PROBE_TYPE DATA [get_debug_ports u_ila_0/probe16]
    501. 

  501. set_property port_width 16 [get_debug_ports u_ila_0/probe16]
    502. 

  502. connect_debug_port u_ila_0/probe16 [get_nets [list {ansData[0]} {ansData[1]} {ansData[2]} {ansData[3]} {ansData[4]} {ansData[5]} {ansData[6]} {ansData[7]} {ansData[8]} {ansData[9]} {ansData[10]} {ansData[11]} {ansData[12]} {ansData[13]} {ansData[14]} {ansData[15]}]]
    503. 

  503. create_debug_port u_ila_0 probe
    504. 

  504. set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe17]
    505. 

  505. set_property port_width 1 [get_debug_ports u_ila_0/probe17]
    506. 

  506. connect_debug_port u_ila_0/probe17 [get_nets [list {SpiRst_o_OBUF[0]}]]
    507. 

  507. create_debug_port u_ila_0 probe
    508. 

  508. set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe18]
    509. 

  509. set_property port_width 16 [get_debug_ports u_ila_0/probe18]
    510. 

  510. connect_debug_port u_ila_0/probe18 [get_nets [list {spi0CsCtrl[0]} {spi0CsCtrl[1]} {spi0CsCtrl[2]} {spi0CsCtrl[3]} {spi0CsCtrl[4]} {spi0CsCtrl[5]} {spi0CsCtrl[6]} {spi0CsCtrl[7]} {spi0CsCtrl[8]} {spi0CsCtrl[9]} {spi0CsCtrl[10]} {spi0CsCtrl[11]} {spi0CsCtrl[12]} {spi0CsCtrl[13]} {spi0CsCtrl[14]} {spi0CsCtrl[15]}]]
    511. 

  511. create_debug_port u_ila_0 probe
    512. 

  512. set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe19]
    513. 

  513. set_property port_width 16 [get_debug_ports u_ila_0/probe19]
    514. 

  514. connect_debug_port u_ila_0/probe19 [get_nets [list {spi0CsDelay[0]} {spi0CsDelay[1]} {spi0CsDelay[2]} {spi0CsDelay[3]} {spi0CsDelay[4]} {spi0CsDelay[5]} {spi0CsDelay[6]} {spi0CsDelay[7]} {spi0CsDelay[8]} {spi0CsDelay[9]} {spi0CsDelay[10]} {spi0CsDelay[11]} {spi0CsDelay[12]} {spi0CsDelay[13]} {spi0CsDelay[14]} {spi0CsDelay[15]}]]
    515. 

  515. create_debug_port u_ila_0 probe
    516. 

  516. set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe20]
    517. 

  517. set_property port_width 1 [get_debug_ports u_ila_0/probe20]
    518. 

  518. connect_debug_port u_ila_0/probe20 [get_nets [list SmcAre_i_IBUF]]
    519. 

  519. create_debug_port u_ila_0 probe
    520. 

  520. set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe21]
    521. 

  521. set_property port_width 1 [get_debug_ports u_ila_0/probe21]
    522. 

  522. connect_debug_port u_ila_0/probe21 [get_nets [list SmcAwe_i_IBUF]]
    523. 

  523. set_clock_groups -logically_exclusive -group [get_clocks [list [get_clocks -of_objects [get_pins ClkManager/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT0]] [get_clocks -of_objects [get_pins ClkManager/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT1]] [get_clocks -of_objects [get_pins ClkManager/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT2]] [get_clocks -of_objects [get_pins ClkManager/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT3]] [get_clocks -of_objects [get_pins ClkManager/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT4]] [get_clocks -of_objects [get_pins ClkManager/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT5]] [get_clocks -of_objects [get_pins ClkManager/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT6]]]]
    524. 

  524. set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub]
    525. 

  525. set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub]
    526. 

  526. set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub]
    527. 

  527. connect_debug_port dbg_hub/clk [get_nets gclk]
    528.