| 123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343 |
- module SPIm (
- input Clk_i,
- input Rst_i,
- input Start_i,
- input CPHA_i,
- input [31:0] SPIdata,
- input SpiDataVal_i,
- input SELST_i,
- input [1:0] WidthSel_i,
- input LAG_i,
- input LEAD_i,
- input EndianSel_i,
- input [5:0] Stop_i,
- input PulsePol_i,
- output reg Mosi0_o,
- output reg Sck_o,
- output Ss_o,
- output reg Val_o
- );
- //================================================================================
- // REG/WIRE
- //================================================================================
- reg startFlag;
- reg [2:0] ssCnt;
- reg Ss;
- reg SSr;
- reg [7:0] mosiReg0;
- reg [3:0] ssNum;
- reg [2:0] delayCnt;
- reg stopFlag;
- wire SsPol = SELST_i ? Ss : ~Ss;
- //================================================================================
- // ASSIGNMENTS
- //================================================================================
- assign Ss_o = SsPol;
- //================================================================================
- // CODING
- //================================================================================
- always @(negedge Clk_i) begin
- if (Rst_i) begin
- delayCnt <= 1'b0;
- end
- else begin
- if (stopFlag &&delayCnt < Stop_i) begin
- delayCnt <= delayCnt + 1'b1;
- end
- else begin
- delayCnt <= 1'b0;
- end
- end
- end
- always @(posedge Clk_i) begin
- if (Rst_i) begin
- stopFlag <= 1'b0;
- end
- else begin
- if (SELST_i) begin
- if (Ss && !SSr) begin
- stopFlag <= 1'b1;
- end
- else if ( delayCnt == Stop_i) begin
- stopFlag <= 1'b0;
- end
- end
- else begin
- if (!Ss && SSr) begin
- stopFlag <= 1'b1;
- end
- else if (delayCnt == Stop_i) begin
- stopFlag <= 1'b0;
- end
- end
- end
- end
- always @(*) begin
- if (PulsePol_i) begin
- if (CPHA_i) begin
- if (LEAD_i == 0) begin
- if (!Ss && (ssCnt <= ssNum+LAG_i+LEAD_i && ssCnt > LAG_i) ) begin
- Sck_o = ~(~Clk_i);
- end
- else begin
- Sck_o = 1'b0;
- end
- end
- else begin
- if (!Ss && (ssCnt < ssNum+LAG_i+LEAD_i && ssCnt > LAG_i)) begin
- Sck_o = ~(~Clk_i);
- end
- else begin
- Sck_o = 1'b0;
- end
- end
- end
- else begin
- if (LEAD_i == 0) begin
- if (!Ss && (ssCnt <= ssNum+LAG_i+LEAD_i && ssCnt > LAG_i) ) begin
- Sck_o = ~(Clk_i);
- end
- else begin
- Sck_o = 1'b0;
- end
- end
- else begin
- if (!Ss && (ssCnt < ssNum + LAG_i + LEAD_i && ssCnt > LAG_i)) begin
- Sck_o = ~(Clk_i);
- end
- else begin
- Sck_o = 1'b0;
- end
- end
- end
- end
- else begin
- if (CPHA_i) begin
- if (LEAD_i == 0) begin
- if (!Ss && (ssCnt <= ssNum+LAG_i+LEAD_i && ssCnt > LAG_i) ) begin
- Sck_o = ~(Clk_i);
- end
- else begin
- Sck_o = 1'b0;
- end
- end
- else begin
- if (!Ss && (ssCnt <ssNum + LAG_i + LAG_i && ssCnt > LAG_i)) begin
- Sck_o = ~(Clk_i);
- end
- else begin
- Sck_o = 1'b0;
- end
- end
- end
- else begin
- if (LEAD_i == 0) begin
- if (!Ss && (ssCnt <= ssNum+LAG_i+LEAD_i && ssCnt > LAG_i) ) begin
- Sck_o = ~(~Clk_i);
- end
- else begin
- Sck_o = 1'b0;
- end
- end
- else begin
- if (!Ss && (ssCnt < ssNum + LAG_i + LEAD_i && ssCnt > LAG_i)) begin
- Sck_o = ~(~Clk_i);
- end
- else begin
- Sck_o = 1'b0;
- end
- end
- end
- end
- end
- always @(*) begin
- if (Rst_i) begin
- Mosi0_o = 1'b0;
- end
- else begin
- if (!EndianSel_i) begin
- case (WidthSel_i)
- 0 : begin
- Mosi0_o = (!Ss&& (ssCnt < ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg0[7]):1'b0;
- end
- 1 : begin
- Mosi0_o = (!Ss&& (ssCnt < ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg0[15]):1'b0;
- end
- 2 : begin
- Mosi0_o = (!Ss&& (ssCnt < ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg0[23]):1'b0;
- end
- 3 : begin
- Mosi0_o = (!Ss&& (ssCnt < ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg0[31]):1'b0;
- end
- endcase
- end
- else begin
- case (WidthSel_i)
- 0 : begin
- Mosi0_o = (!Ss&& (ssCnt < ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg0[0]):1'b0;
- end
- 1 : begin
- Mosi0_o = (!Ss&& (ssCnt < ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg0[0]):1'b0;
- end
- 2 : begin
- Mosi0_o = (!Ss&& (ssCnt < ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg0[0]):1'b0;
- end
- 3 : begin
- Mosi0_o = (!Ss&& (ssCnt < ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg0[0]):1'b0;
- end
- endcase
- end
- end
- end
- always @(posedge Clk_i) begin
- SSr <= Ss;
- end
- always @(*) begin
- if (Rst_i) begin
- startFlag = 1'b0;
- end
- else begin
- if (Start_i && !stopFlag) begin
- startFlag = 1'b1;
- end
- else begin
- startFlag = 1'b0;
- end
- end
- end
- always @(*) begin
- if (SELST_i) begin
- if (Ss && !SSr) begin
- Val_o = 1'b1;
- end
- else begin
- Val_o = 1'b0;
- end
- end
- else begin
- if (!Ss&& SSr) begin
- Val_o = 1'b1;
- end
- else begin
- Val_o = 1'b0;
- end
- end
- end
- always @(*) begin
- if (Rst_i) begin
- ssNum = 1'b0;
- end
- else begin
- case (WidthSel_i)
- 0 : begin
- ssNum = 8;
- end
- 1 : begin
- ssNum = 16;
- end
- 2 : begin
- ssNum = 24;
- end
- 3 : begin
- ssNum = 32;
- end
- endcase
- end
- end
- always @(negedge Clk_i) begin
- if (Rst_i) begin
- ssCnt <= 1'b0;
- end
- else if (ssCnt < (ssNum+LAG_i+LEAD_i) && startFlag ) begin
- ssCnt <= ssCnt + 1'b1;
- end
- else begin
- if (ssCnt == ssNum-1 || !startFlag) begin
- ssCnt <= 1'b0;
- end
- end
- end
- always @(negedge Clk_i) begin
- if (Rst_i) begin
- Ss <= 1'b1;
- end
- else begin
- if (ssCnt < (ssNum+LAG_i+LEAD_i) && startFlag ) begin
- Ss <= 1'b0;
- end
- else begin
- Ss <= 1'b1;
- end
- end
- end
- always @(negedge Clk_i) begin
- if (Rst_i) begin
- mosiReg0 <= SPIdata[31:0];
- end
- else begin
- if (!EndianSel_i) begin
- if (!SSr && (ssCnt > LAG_i && ssCnt < ssNum + LAG_i + LEAD_i)) begin
- mosiReg0 <= mosiReg0 << 1;
- end
- else begin
- mosiReg0 <= SPIdata[31:0];
- end
- end
- else begin
- if (!SSr && (ssCnt > LAG_i && ssCnt < ssNum + LAG_i + LEAD_i)) begin
- mosiReg0 <= mosiReg0 >> 1;
- end
- else begin
- mosiReg0 <= SPIdata[31:0];
- end
- end
- end
- end
- endmodule
|