S5443_V3/sources_1/new/ClkManager/MmcmClkMux.v

module MmcmClkMux(
input Rst_i,
input [2:0]clkNum,
input Clk0_i,
input Clk1_i,
input Clk2_i,
input Clk3_i,
input Clk4_i,
input Clk5_i,
input Clk6_i, 

output   ClkOutMMCM_o

);
//================================================================================
//	REG/WIRE
//================================================================================
reg clkOutMMCMReg;

wire clkOutMMCM;
//================================================================================
//	ASSIGNMENTS
//===============================================================================
assign clkOutMMCM = clkOutMMCMReg;
//================================================================================
//	CODING
//================================================================================ 
always @(*) begin 
    if (Rst_i) begin 
        clkOutMMCMReg = 0;
    end
    else begin 
        case (clkNum) 
            0: clkOutMMCMReg = Clk0_i;
            1: clkOutMMCMReg = Clk1_i;
            2: clkOutMMCMReg = Clk2_i;
            3: clkOutMMCMReg = Clk3_i;
            4: clkOutMMCMReg = Clk4_i;
            5: clkOutMMCMReg = Clk5_i;
            6: clkOutMMCMReg = Clk6_i;
            default: clkOutMMCMReg = 0;
        endcase
    end
end

BUFG BUFG_inst (
   .O(ClkOutMMCM_o), // 1-bit output: Clock output
   .I(clkOutMMCM)  // 1-bit input: Clock input
);

endmodule