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S5443_3.xdc

S5443_3.xdc 52 KB
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  1. set_property PACKAGE_PIN C15 [get_ports {SmcAddr_i[0]}]
    2. 

  2. set_property IOSTANDARD LVCMOS33 [get_ports {SmcAddr_i[0]}]
    3. 

  3. set_property PACKAGE_PIN C13 [get_ports {SmcAddr_i[1]}]
    4. 

  4. set_property IOSTANDARD LVCMOS33 [get_ports {SmcAddr_i[1]}]
    5. 

  5. set_property PACKAGE_PIN D15 [get_ports {SmcAddr_i[2]}]
    6. 

  6. set_property IOSTANDARD LVCMOS33 [get_ports {SmcAddr_i[2]}]
    7. 

  7. set_property PACKAGE_PIN C14 [get_ports {SmcAddr_i[3]}]
    8. 

  8. set_property IOSTANDARD LVCMOS33 [get_ports {SmcAddr_i[3]}]
    9. 

  9. set_property PACKAGE_PIN E15 [get_ports {SmcAddr_i[4]}]
    10. 

  10. set_property IOSTANDARD LVCMOS33 [get_ports {SmcAddr_i[4]}]
    11. 

  11. set_property PACKAGE_PIN D13 [get_ports {SmcAddr_i[5]}]
    12. 

  12. set_property IOSTANDARD LVCMOS33 [get_ports {SmcAddr_i[5]}]
    13. 

  13. set_property PACKAGE_PIN F15 [get_ports {SmcAddr_i[6]}]
    14. 

  14. set_property IOSTANDARD LVCMOS33 [get_ports {SmcAddr_i[6]}]
    15. 

  15. set_property PACKAGE_PIN E14 [get_ports {SmcAddr_i[7]}]
    16. 

  16. set_property IOSTANDARD LVCMOS33 [get_ports {SmcAddr_i[7]}]
    17. 

  17. set_property PACKAGE_PIN J15 [get_ports {SmcAddr_i[8]}]
    18. 

  18. set_property IOSTANDARD LVCMOS33 [get_ports {SmcAddr_i[8]}]
    19. 

  19. set_property PACKAGE_PIN F14 [get_ports {SmcAddr_i[9]}]
    20. 

  20. set_property IOSTANDARD LVCMOS33 [get_ports {SmcAddr_i[9]}]
    21. 

  21. set_property PACKAGE_PIN K15 [get_ports {SmcAddr_i[10]}]
    22. 

  22. set_property IOSTANDARD LVCMOS33 [get_ports {SmcAddr_i[10]}]
    23. 

  23. 

  24. 

  25. 

  26. set_property PACKAGE_PIN B15 [get_ports {SmcData_i[0]}]
    27. 

  27. set_property IOSTANDARD LVCMOS33 [get_ports {SmcData_i[0]}]
    28. 

  28. set_property PACKAGE_PIN B14 [get_ports {SmcData_i[1]}]
    29. 

  29. set_property IOSTANDARD LVCMOS33 [get_ports {SmcData_i[1]}]
    30. 

  30. set_property PACKAGE_PIN B11 [get_ports {SmcData_i[2]}]
    31. 

  31. set_property IOSTANDARD LVCMOS33 [get_ports {SmcData_i[2]}]
    32. 

  32. set_property PACKAGE_PIN B12 [get_ports {SmcData_i[3]}]
    33. 

  33. set_property IOSTANDARD LVCMOS33 [get_ports {SmcData_i[3]}]
    34. 

  34. set_property PACKAGE_PIN A12 [get_ports {SmcData_i[4]}]
    35. 

  35. set_property IOSTANDARD LVCMOS33 [get_ports {SmcData_i[4]}]
    36. 

  36. set_property PACKAGE_PIN B9 [get_ports {SmcData_i[5]}]
    37. 

  37. set_property IOSTANDARD LVCMOS33 [get_ports {SmcData_i[5]}]
    38. 

  38. set_property PACKAGE_PIN K14 [get_ports {SmcData_i[6]}]
    39. 

  39. set_property IOSTANDARD LVCMOS33 [get_ports {SmcData_i[6]}]
    40. 

  40. set_property PACKAGE_PIN A11 [get_ports {SmcData_i[7]}]
    41. 

  41. set_property IOSTANDARD LVCMOS33 [get_ports {SmcData_i[7]}]
    42. 

  42. set_property PACKAGE_PIN A6 [get_ports {SmcData_i[8]}]
    43. 

  43. set_property IOSTANDARD LVCMOS33 [get_ports {SmcData_i[8]}]
    44. 

  44. set_property PACKAGE_PIN A13 [get_ports {SmcData_i[9]}]
    45. 

  45. set_property IOSTANDARD LVCMOS33 [get_ports {SmcData_i[9]}]
    46. 

  46. set_property PACKAGE_PIN A10 [get_ports {SmcData_i[10]}]
    47. 

  47. set_property IOSTANDARD LVCMOS33 [get_ports {SmcData_i[10]}]
    48. 

  48. set_property PACKAGE_PIN B6 [get_ports {SmcData_i[11]}]
    49. 

  49. set_property IOSTANDARD LVCMOS33 [get_ports {SmcData_i[11]}]
    50. 

  50. set_property PACKAGE_PIN A5 [get_ports {SmcData_i[12]}]
    51. 

  51. set_property IOSTANDARD LVCMOS33 [get_ports {SmcData_i[12]}]
    52. 

  52. set_property PACKAGE_PIN B10 [get_ports {SmcData_i[13]}]
    53. 

  53. set_property IOSTANDARD LVCMOS33 [get_ports {SmcData_i[13]}]
    54. 

  54. set_property PACKAGE_PIN A8 [get_ports {SmcData_i[14]}]
    55. 

  55. set_property IOSTANDARD LVCMOS33 [get_ports {SmcData_i[14]}]
    56. 

  56. set_property PACKAGE_PIN A14 [get_ports {SmcData_i[15]}]
    57. 

  57. set_property IOSTANDARD LVCMOS33 [get_ports {SmcData_i[15]}]
    58. 

  58. 

  59. set_property PACKAGE_PIN B13 [get_ports SmcAmsN_i]
    60. 

  60. set_property IOSTANDARD LVCMOS33 [get_ports SmcAmsN_i]
    61. 

  61. 

  62. 

  63. set_property PACKAGE_PIN C6 [get_ports Led_o]
    64. 

  64. set_property IOSTANDARD LVCMOS33 [get_ports Led_o]
    65. 

  65. 

  66. set_property PACKAGE_PIN A9 [get_ports SmcAwe_i]
    67. 

  67. set_property IOSTANDARD LVCMOS33 [get_ports SmcAwe_i]
    68. 

  68. 

  69. set_property PACKAGE_PIN C5 [get_ports SmcAre_i]
    70. 

  70. set_property IOSTANDARD LVCMOS33 [get_ports SmcAre_i]
    71. 

  71. 

  72. set_property PACKAGE_PIN C8 [get_ports SmcAoe_i]
    73. 

  73. set_property IOSTANDARD LVCMOS33 [get_ports SmcAoe_i]
    74. 

  74. 

  75. set_property PACKAGE_PIN L15 [get_ports {SmcBe_i[1]}]
    76. 

  76. set_property IOSTANDARD LVCMOS33 [get_ports {SmcBe_i[1]}]
    77. 

  77. set_property PACKAGE_PIN L14 [get_ports {SmcBe_i[0]}]
    78. 

  78. set_property IOSTANDARD LVCMOS33 [get_ports {SmcBe_i[0]}]
    79. 

  79. 

  80. 

  81. #==========================================================================
    82. 

  82. #	SPI INTERFACES
    83. 

  83. 

  84. #SPI0
    85. 

  85. set_property PACKAGE_PIN K1 [get_ports {Sck_o[0]}]
    86. 

  86. set_property IOSTANDARD LVCMOS33 [get_ports {Sck_o[0]}]
    87. 

  87. 

  88. set_property PACKAGE_PIN H1 [get_ports {Ss_o[0]}]
    89. 

  89. set_property IOSTANDARD LVCMOS33 [get_ports {Ss_o[0]}]
    90. 

  90. 

  91. set_property PACKAGE_PIN K2 [get_ports {SsFlash_o[0]}]
    92. 

  92. set_property IOSTANDARD LVCMOS33 [get_ports {SsFlash_o[0]}]
    93. 

  93. 

  94. set_property PACKAGE_PIN J1 [get_ports {Mosi0_o[0]}]
    95. 

  95. set_property IOSTANDARD LVCMOS33 [get_ports {Mosi0_o[0]}]
    96. 

  96. 

  97. set_property PACKAGE_PIN J3 [get_ports {Mosi1_io[0]}]
    98. 

  98. set_property IOSTANDARD LVCMOS33 [get_ports {Mosi1_io[0]}]
    99. 

  99. 

  100. set_property PACKAGE_PIN F2 [get_ports {Mosi2_o[0]}]
    101. 

  101. set_property IOSTANDARD LVCMOS33 [get_ports {Mosi2_o[0]}]
    102. 

  102. 

  103. set_property PACKAGE_PIN L1 [get_ports {Mosi3_o[0]}]
    104. 

  104. set_property IOSTANDARD LVCMOS33 [get_ports {Mosi3_o[0]}]
    105. 

  105. 

  106. set_property PACKAGE_PIN J2 [get_ports {SpiRst_o[0]}]
    107. 

  107. set_property IOSTANDARD LVCMOS33 [get_ports {SpiRst_o[0]}]
    108. 

  108. 

  109. set_property PACKAGE_PIN M13 [get_ports {Ld_i[0]}]
    110. 

  110. set_property IOSTANDARD LVCMOS33 [get_ports {Ld_i[0]}]
    111. 

  111. 

  112. set_property PACKAGE_PIN H2 [get_ports {SpiDir_o[0]}]
    113. 

  113. set_property IOSTANDARD LVCMOS33 [get_ports {SpiDir_o[0]}]
    114. 

  114. 

  115. 

  116. 

  117. 

  118. 

  119. 

  120. 

  121. 

  122. 

  123. #SPI1
    124. 

  124. set_property PACKAGE_PIN N2 [get_ports {Sck_o[1]}]
    125. 

  125. set_property IOSTANDARD LVCMOS33 [get_ports {Sck_o[1]}]
    126. 

  126. set_property PACKAGE_PIN N4 [get_ports {Ss_o[1]}]
    127. 

  127. set_property IOSTANDARD LVCMOS33 [get_ports {Ss_o[1]}]
    128. 

  128. set_property PACKAGE_PIN P1 [get_ports {SsFlash_o[1]}]
    129. 

  129. set_property IOSTANDARD LVCMOS33 [get_ports {SsFlash_o[1]}]
    130. 

  130. set_property PACKAGE_PIN N3 [get_ports {Mosi0_o[1]}]
    131. 

  131. set_property IOSTANDARD LVCMOS33 [get_ports {Mosi0_o[1]}]
    132. 

  132. set_property PACKAGE_PIN R2 [get_ports {Mosi1_io[1]}]
    133. 

  133. set_property IOSTANDARD LVCMOS33 [get_ports {Mosi1_io[1]}]
    134. 

  134. set_property PACKAGE_PIN N1 [get_ports {Mosi2_o[1]}]
    135. 

  135. set_property IOSTANDARD LVCMOS33 [get_ports {Mosi2_o[1]}]
    136. 

  136. set_property PACKAGE_PIN M2 [get_ports {Mosi3_o[1]}]
    137. 

  137. set_property IOSTANDARD LVCMOS33 [get_ports {Mosi3_o[1]}]
    138. 

  138. set_property PACKAGE_PIN P2 [get_ports {SpiRst_o[1]}]
    139. 

  139. set_property IOSTANDARD LVCMOS33 [get_ports {SpiRst_o[1]}]
    140. 

  140. set_property PACKAGE_PIN N11 [get_ports {Ld_i[1]}]
    141. 

  141. set_property IOSTANDARD LVCMOS33 [get_ports {Ld_i[1]}]
    142. 

  142. 

  143. set_property PACKAGE_PIN M1 [get_ports {SpiDir_o[1]}]
    144. 

  144. set_property IOSTANDARD LVCMOS33 [get_ports {SpiDir_o[1]}]
    145. 

  145. 

  146. 

  147. 

  148. #SPI2
    149. 

  149. set_property PACKAGE_PIN E2 [get_ports {Sck_o[2]}]
    150. 

  150. set_property IOSTANDARD LVCMOS33 [get_ports {Sck_o[2]}]
    151. 

  151. set_property PACKAGE_PIN E1 [get_ports {Ss_o[2]}]
    152. 

  152. set_property IOSTANDARD LVCMOS33 [get_ports {Ss_o[2]}]
    153. 

  153. set_property PACKAGE_PIN F1 [get_ports {SsFlash_o[2]}]
    154. 

  154. set_property IOSTANDARD LVCMOS33 [get_ports {SsFlash_o[2]}]
    155. 

  155. set_property PACKAGE_PIN D1 [get_ports {Mosi0_o[2]}]
    156. 

  156. set_property IOSTANDARD LVCMOS33 [get_ports {Mosi0_o[2]}]
    157. 

  157. set_property PACKAGE_PIN D2 [get_ports {Mosi1_io[2]}]
    158. 

  158. set_property IOSTANDARD LVCMOS33 [get_ports {Mosi1_io[2]}]
    159. 

  159. set_property PACKAGE_PIN F2 [get_ports {Mosi2_o[2]}]
    160. 

  160. set_property IOSTANDARD LVCMOS33 [get_ports {Mosi2_o[2]}]
    161. 

  161. set_property PACKAGE_PIN G1 [get_ports {Mosi3_o[2]}]
    162. 

  162. set_property IOSTANDARD LVCMOS33 [get_ports {Mosi3_o[2]}]
    163. 

  163. set_property PACKAGE_PIN E3 [get_ports {SpiRst_o[2]}]
    164. 

  164. set_property IOSTANDARD LVCMOS33 [get_ports {SpiRst_o[2]}]
    165. 

  165. set_property PACKAGE_PIN N9 [get_ports {Ld_i[2]}]
    166. 

  166. set_property IOSTANDARD LVCMOS33 [get_ports {Ld_i[2]}]
    167. 

  167. 

  168. 

  169. set_property PACKAGE_PIN C1 [get_ports {SpiDir_o[2]}]
    170. 

  170. set_property IOSTANDARD LVCMOS33 [get_ports {SpiDir_o[2]}]
    171. 

  171. 

  172. 

  173. #SPI3
    174. 

  174. set_property PACKAGE_PIN R10 [get_ports {Sck_o[3]}]
    175. 

  175. set_property IOSTANDARD LVCMOS33 [get_ports {Sck_o[3]}]
    176. 

  176. set_property PACKAGE_PIN P10 [get_ports {Ss_o[3]}]
    177. 

  177. set_property IOSTANDARD LVCMOS33 [get_ports {Ss_o[3]}]
    178. 

  178. set_property PACKAGE_PIN N10 [get_ports {SsFlash_o[3]}]
    179. 

  179. set_property IOSTANDARD LVCMOS33 [get_ports {SsFlash_o[3]}]
    180. 

  180. set_property PACKAGE_PIN N8 [get_ports {Mosi0_o[3]}]
    181. 

  181. set_property IOSTANDARD LVCMOS33 [get_ports {Mosi0_o[3]}]
    182. 

  182. set_property PACKAGE_PIN R8 [get_ports {Mosi1_io[3]}]
    183. 

  183. set_property IOSTANDARD LVCMOS33 [get_ports {Mosi1_io[3]}]
    184. 

  184. set_property PACKAGE_PIN R11 [get_ports {Mosi2_o[3]}]
    185. 

  185. set_property IOSTANDARD LVCMOS33 [get_ports {Mosi2_o[3]}]
    186. 

  186. set_property PACKAGE_PIN P11 [get_ports {Mosi3_o[3]}]
    187. 

  187. set_property IOSTANDARD LVCMOS33 [get_ports {Mosi3_o[3]}]
    188. 

  188. set_property PACKAGE_PIN R9 [get_ports {SpiRst_o[3]}]
    189. 

  189. set_property IOSTANDARD LVCMOS33 [get_ports {SpiRst_o[3]}]
    190. 

  190. set_property PACKAGE_PIN N13 [get_ports {Ld_i[3]}]
    191. 

  191. set_property IOSTANDARD LVCMOS33 [get_ports {Ld_i[3]}]
    192. 

  192. 

  193. set_property PACKAGE_PIN P7 [get_ports {SpiDir_o[3]}]
    194. 

  194. set_property IOSTANDARD LVCMOS33 [get_ports {SpiDir_o[3]}]
    195. 

  195. 

  196. 

  197. 

  198. #SPI4
    199. 

  199. set_property PACKAGE_PIN R14 [get_ports {Sck_o[4]}]
    200. 

  200. set_property IOSTANDARD LVCMOS33 [get_ports {Sck_o[4]}]
    201. 

  201. set_property PACKAGE_PIN N14 [get_ports {Ss_o[4]}]
    202. 

  202. set_property IOSTANDARD LVCMOS33 [get_ports {Ss_o[4]}]
    203. 

  203. set_property PACKAGE_PIN P14 [get_ports {SsFlash_o[4]}]
    204. 

  204. set_property IOSTANDARD LVCMOS33 [get_ports {SsFlash_o[4]}]
    205. 

  205. set_property PACKAGE_PIN R13 [get_ports {Mosi0_o[4]}]
    206. 

  206. set_property IOSTANDARD LVCMOS33 [get_ports {Mosi0_o[4]}]
    207. 

  207. set_property PACKAGE_PIN P12 [get_ports {Mosi1_io[4]}]
    208. 

  208. set_property IOSTANDARD LVCMOS33 [get_ports {Mosi1_io[4]}]
    209. 

  209. set_property PACKAGE_PIN M15 [get_ports {Mosi2_o[4]}]
    210. 

  210. set_property IOSTANDARD LVCMOS33 [get_ports {Mosi2_o[4]}]
    211. 

  211. set_property PACKAGE_PIN M14 [get_ports {Mosi3_o[4]}]
    212. 

  212. set_property IOSTANDARD LVCMOS33 [get_ports {Mosi3_o[4]}]
    213. 

  213. set_property PACKAGE_PIN N15 [get_ports {SpiRst_o[4]}]
    214. 

  214. set_property IOSTANDARD LVCMOS33 [get_ports {SpiRst_o[4]}]
    215. 

  215. set_property PACKAGE_PIN P15 [get_ports {Ld_i[4]}]
    216. 

  216. set_property IOSTANDARD LVCMOS33 [get_ports {Ld_i[4]}]
    217. 

  217. 

  218. set_property PACKAGE_PIN R12 [get_ports {SpiDir_o[4]}]
    219. 

  219. set_property IOSTANDARD LVCMOS33 [get_ports {SpiDir_o[4]}]
    220. 

  220. 

  221. 

  222. 

  223. #SPI5
    224. 

  224. set_property PACKAGE_PIN P6 [get_ports {Sck_o[5]}]
    225. 

  225. set_property IOSTANDARD LVCMOS33 [get_ports {Sck_o[5]}]
    226. 

  226. set_property PACKAGE_PIN R5 [get_ports {Ss_o[5]}]
    227. 

  227. set_property IOSTANDARD LVCMOS33 [get_ports {Ss_o[5]}]
    228. 

  228. set_property PACKAGE_PIN R6 [get_ports {SsFlash_o[5]}]
    229. 

  229. set_property IOSTANDARD LVCMOS33 [get_ports {SsFlash_o[5]}]
    230. 

  230. set_property PACKAGE_PIN R4 [get_ports {Mosi0_o[5]}]
    231. 

  231. set_property IOSTANDARD LVCMOS33 [get_ports {Mosi0_o[5]}]
    232. 

  232. set_property PACKAGE_PIN R3 [get_ports {Mosi1_io[5]}]
    233. 

  233. set_property IOSTANDARD LVCMOS33 [get_ports {Mosi1_io[5]}]
    234. 

  234. set_property PACKAGE_PIN N7 [get_ports {Mosi2_o[5]}]
    235. 

  235. set_property IOSTANDARD LVCMOS33 [get_ports {Mosi2_o[5]}]
    236. 

  236. set_property PACKAGE_PIN R7 [get_ports {Mosi3_o[5]}]
    237. 

  237. set_property IOSTANDARD LVCMOS33 [get_ports {Mosi3_o[5]}]
    238. 

  238. set_property PACKAGE_PIN N6 [get_ports {SpiRst_o[5]}]
    239. 

  239. set_property IOSTANDARD LVCMOS33 [get_ports {SpiRst_o[5]}]
    240. 

  240. set_property PACKAGE_PIN N12 [get_ports {Ld_i[5]}]
    241. 

  241. set_property IOSTANDARD LVCMOS33 [get_ports {Ld_i[5]}]
    242. 

  242. 

  243. set_property PACKAGE_PIN R3 [get_ports {SpiDir_o[5]}]
    244. 

  244. set_property IOSTANDARD LVCMOS33 [get_ports {SpiDir_o[5]}]
    245. 

  245. 

  246. 

  247. 

  248. #SPI6
    249. 

  249. set_property PACKAGE_PIN B5 [get_ports {Sck_o[6]}]
    250. 

  250. set_property IOSTANDARD LVCMOS33 [get_ports {Sck_o[6]}]
    251. 

  251. set_property PACKAGE_PIN B3 [get_ports {Ss_o[6]}]
    252. 

  252. set_property IOSTANDARD LVCMOS33 [get_ports {Ss_o[6]}]
    253. 

  253. set_property PACKAGE_PIN A4 [get_ports {SsFlash_o[6]}]
    254. 

  254. set_property IOSTANDARD LVCMOS33 [get_ports {SsFlash_o[6]}]
    255. 

  255. set_property PACKAGE_PIN B1 [get_ports {Mosi0_o[6]}]
    256. 

  256. set_property IOSTANDARD LVCMOS33 [get_ports {Mosi0_o[6]}]
    257. 

  257. set_property PACKAGE_PIN C4 [get_ports {Mosi1_io[6]}]
    258. 

  258. set_property IOSTANDARD LVCMOS33 [get_ports {Mosi1_io[6]}]
    259. 

  259. set_property PACKAGE_PIN B4 [get_ports {Mosi2_o[6]}]
    260. 

  260. set_property IOSTANDARD LVCMOS33 [get_ports {Mosi2_o[6]}]
    261. 

  261. set_property PACKAGE_PIN A3 [get_ports {Mosi3_o[6]}]
    262. 

  262. set_property IOSTANDARD LVCMOS33 [get_ports {Mosi3_o[6]}]
    263. 

  263. set_property PACKAGE_PIN A2 [get_ports {SpiRst_o[6]}]
    264. 

  264. set_property IOSTANDARD LVCMOS33 [get_ports {SpiRst_o[6]}]
    265. 

  265. set_property PACKAGE_PIN M8 [get_ports {Ld_i[6]}]
    266. 

  266. set_property IOSTANDARD LVCMOS33 [get_ports {Ld_i[6]}]
    267. 

  267. 

  268. set_property PACKAGE_PIN B2 [get_ports {SpiDir_o[6]}]
    269. 

  269. set_property IOSTANDARD LVCMOS33 [get_ports {SpiDir_o[6]}]
    270. 

  270. 

  271. 

  272. set_property PACKAGE_PIN M7 [get_ports LD_o]
    273. 

  273. set_property IOSTANDARD LVCMOS33 [get_ports LD_o]
    274. 

  274. 

  275. #==========================================================================
    276. 

  276. #	INPUT CLOCKS
    277. 

  277. 

  278. set_property PACKAGE_PIN M10 [get_ports Clk123_i]
    279. 

  279. set_property IOSTANDARD LVCMOS33 [get_ports Clk123_i]
    280. 

  280. create_clock -period 8.130 -name Clk123_i -waveform {0.000 4.065} -add [get_ports Clk123_i]
    281. 

  281. 

  282. set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets Clk123_i_IBUF]
    283. 

  283. set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets SmcAre_i_IBUF]
    284. 

  284. 

  285. # set ClkDiv_inst_input [[get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKIN1]]
    286. 

  286. # set ClkDiv_inst_output [[get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT0]]
    287. 

  287. 

  288. 

  289. 

  290. 

  291. set_false_path -from [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT0]] -to [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT1]]
    292. 

  292. set_false_path -from [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT0]] -to [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT2]]
    293. 

  293. set_false_path -from [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT0]] -to [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT3]]
    294. 

  294. set_false_path -from [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT0]] -to [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT5]]
    295. 

  295. set_false_path -from [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT0]] -to [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT4]]
    296. 

  296. set_false_path -from [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT0]] -to [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT6]]
    297. 

  297. 

  298. set_false_path -from [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT1]] -to [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT0]]
    299. 

  299. set_false_path -from [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT1]] -to [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT2]]
    300. 

  300. set_false_path -from [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT1]] -to [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT3]]
    301. 

  301. set_false_path -from [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT1]] -to [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT4]]
    302. 

  302. set_false_path -from [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT1]] -to [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT5]]
    303. 

  303. set_false_path -from [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT1]] -to [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT6]]
    304. 

  304. 

  305. set_false_path -from [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT2]] -to [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT0]]
    306. 

  306. set_false_path -from [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT2]] -to [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT1]]
    307. 

  307. set_false_path -from [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT2]] -to [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT3]]
    308. 

  308. set_false_path -from [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT2]] -to [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT4]]
    309. 

  309. set_false_path -from [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT2]] -to [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT5]]
    310. 

  310. set_false_path -from [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT2]] -to [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT6]]
    311. 

  311. 

  312. set_false_path -from [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT3]] -to [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT0]]
    313. 

  313. set_false_path -from [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT3]] -to [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT1]]
    314. 

  314. set_false_path -from [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT3]] -to [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT2]]
    315. 

  315. set_false_path -from [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT3]] -to [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT4]]
    316. 

  316. set_false_path -from [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT3]] -to [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT5]]
    317. 

  317. set_false_path -from [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT3]] -to [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT6]]
    318. 

  318. 

  319. set_false_path -from [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT4]] -to [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT0]]
    320. 

  320. set_false_path -from [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT4]] -to [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT1]]
    321. 

  321. set_false_path -from [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT4]] -to [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT2]]
    322. 

  322. set_false_path -from [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT4]] -to [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT3]]
    323. 

  323. set_false_path -from [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT4]] -to [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT5]]
    324. 

  324. set_false_path -from [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT4]] -to [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT6]]
    325. 

  325. 

  326. set_false_path -from [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT5]] -to [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT0]]
    327. 

  327. set_false_path -from [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT5]] -to [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT1]]
    328. 

  328. set_false_path -from [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT5]] -to [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT2]]
    329. 

  329. set_false_path -from [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT5]] -to [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT3]]
    330. 

  330. set_false_path -from [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT5]] -to [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT4]]
    331. 

  331. set_false_path -from [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT5]] -to [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT6]]
    332. 

  332. 

  333. set_false_path -from [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT6]] -to [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT0]]
    334. 

  334. set_false_path -from [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT6]] -to [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT1]]
    335. 

  335. set_false_path -from [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT6]] -to [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT2]]
    336. 

  336. set_false_path -from [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT6]] -to [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT3]]
    337. 

  337. set_false_path -from [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT6]] -to [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT4]]
    338. 

  338. set_false_path -from [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT6]] -to [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT5]]
    339. 

  339. 

  340. 

  341. 

  342. 

  343. 

  344. 

  345. 

  346. 

  347. 

  348. 

  349. 

  350. 

  351. 

  352. connect_debug_port u_ila_0/probe2 [get_nets [list {SpiTxRxEn[0]} {SpiTxRxEn[1]} {SpiTxRxEn[2]} {SpiTxRxEn[3]} {SpiTxRxEn[4]} {SpiTxRxEn[5]} {SpiTxRxEn[6]}]]
    353. 

  353. connect_debug_port u_ila_0/probe9 [get_nets [list Mosi0Q_0]]
    354. 

  354. connect_debug_port u_ila_0/probe19 [get_nets [list valToTxQ_0]]
    355. 

  355. 

  356. 

  357. 

  358. 

  359. # set_max_delay -from [get_clocks Clk123_i] -to [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT5]] 10.000
    360. 

  360. 

  361. 

  362. 

  363. connect_debug_port u_ila_0/probe11 [get_nets [list Mosi0Q]]
    364. 

  364. connect_debug_port u_ila_0/probe12 [get_nets [list SckQ_0]]
    365. 

  365. connect_debug_port u_ila_0/probe18 [get_nets [list SsQ_0]]
    366. 

  366. 

  367. 

  368. 

  369. 

  370. 

  371. connect_debug_port u_ila_0/probe0 [get_nets [list {Mosi1_o_OBUF[0]}]]
    372. 

  372. connect_debug_port u_ila_0/probe0 [get_nets [list {Mosi1_o_OBUF[0]}]]
    373. 

  373. connect_debug_port u_ila_0/probe6 [get_nets [list {toFifoData[0]} {toFifoData[1]} {toFifoData[2]} {toFifoData[3]} {toFifoData[4]} {toFifoData[5]} {toFifoData[6]} {toFifoData[7]} {toFifoData[8]} {toFifoData[9]} {toFifoData[10]} {toFifoData[11]} {toFifoData[12]} {toFifoData[13]} {toFifoData[14]} {toFifoData[15]} {toFifoData[16]} {toFifoData[17]} {toFifoData[18]} {toFifoData[19]} {toFifoData[20]} {toFifoData[21]} {toFifoData[22]} {toFifoData[23]} {toFifoData[24]} {toFifoData[25]} {toFifoData[26]} {toFifoData[27]} {toFifoData[28]} {toFifoData[29]} {toFifoData[30]} {toFifoData[31]}]]
    374. 

  374. connect_debug_port u_ila_0/probe7 [get_nets [list {toSpiData[0][31]} {toSpiData[0][30]} {toSpiData[0][29]} {toSpiData[0][28]} {toSpiData[0][27]} {toSpiData[0][26]} {toSpiData[0][25]} {toSpiData[0][24]} {toSpiData[0][23]} {toSpiData[0][22]} {toSpiData[0][21]} {toSpiData[0][20]} {toSpiData[0][19]} {toSpiData[0][18]} {toSpiData[0][17]} {toSpiData[0][16]} {toSpiData[0][15]} {toSpiData[0][14]} {toSpiData[0][13]} {toSpiData[0][12]} {toSpiData[0][11]} {toSpiData[0][10]} {toSpiData[0][9]} {toSpiData[0][8]} {toSpiData[0][7]} {toSpiData[0][6]} {toSpiData[0][5]} {toSpiData[0][4]} {toSpiData[0][3]} {toSpiData[0][2]} {toSpiData[0][1]} {toSpiData[0][0]}]]
    375. 

  375. set_property PROBE_TYPE DATA [get_debug_ports u_ila_0/probe8]
    376. 

  376. set_property port_width 1 [get_debug_ports u_ila_0/probe8]
    377. 

  377. connect_debug_port u_ila_0/probe8 [get_nets [list {Mosi3_o_OBUF[0]}]]
    378. 

  378. set_property PROBE_TYPE DATA [get_debug_ports u_ila_0/probe9]
    379. 

  379. set_property port_width 11 [get_debug_ports u_ila_0/probe9]
    380. 

  380. connect_debug_port u_ila_0/probe9 [get_nets [list {SmcAddr_i_IBUF[0]} {SmcAddr_i_IBUF[1]} {SmcAddr_i_IBUF[2]} {SmcAddr_i_IBUF[3]} {SmcAddr_i_IBUF[4]} {SmcAddr_i_IBUF[5]} {SmcAddr_i_IBUF[6]} {SmcAddr_i_IBUF[7]} {SmcAddr_i_IBUF[8]} {SmcAddr_i_IBUF[9]} {SmcAddr_i_IBUF[10]}]]
    381. 

  381. set_property PROBE_TYPE DATA [get_debug_ports u_ila_0/probe10]
    382. 

  382. set_property PROBE_TYPE DATA [get_debug_ports u_ila_0/probe10]
    383. 

  383. set_property port_width 1 [get_debug_ports u_ila_0/probe10]
    384. 

  384. connect_debug_port u_ila_0/probe10 [get_nets [list {SpiGen[0].DataFifoWrapper/emptyFlagTx}]]
    385. 

  385. set_property PROBE_TYPE DATA [get_debug_ports u_ila_0/probe11]
    386. 

  386. set_property PROBE_TYPE DATA [get_debug_ports u_ila_0/probe11]
    387. 

  387. set_property port_width 1 [get_debug_ports u_ila_0/probe11]
    388. 

  388. connect_debug_port u_ila_0/probe11 [get_nets [list {SpiGen[0].DataFifoWrapper/fullFlagTx}]]
    389. 

  389. set_property PROBE_TYPE DATA [get_debug_ports u_ila_0/probe12]
    390. 

  390. set_property port_width 1 [get_debug_ports u_ila_0/probe12]
    391. 

  391. connect_debug_port u_ila_0/probe12 [get_nets [list Mosi0R]]
    392. 

  392. set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe13]
    393. 

  393. set_property port_width 1 [get_debug_ports u_ila_0/probe13]
    394. 

  394. connect_debug_port u_ila_0/probe13 [get_nets [list SckQ]]
    395. 

  395. set_property PROBE_TYPE DATA [get_debug_ports u_ila_0/probe14]
    396. 

  396. set_property port_width 1 [get_debug_ports u_ila_0/probe14]
    397. 

  397. connect_debug_port u_ila_0/probe14 [get_nets [list SckR_0]]
    398. 

  398. set_property PROBE_TYPE DATA [get_debug_ports u_ila_0/probe15]
    399. 

  399. set_property port_width 1 [get_debug_ports u_ila_0/probe15]
    400. 

  400. connect_debug_port u_ila_0/probe15 [get_nets [list SmcAoe_i_IBUF]]
    401. 

  401. set_property PROBE_TYPE DATA [get_debug_ports u_ila_0/probe16]
    402. 

  402. set_property port_width 1 [get_debug_ports u_ila_0/probe16]
    403. 

  403. connect_debug_port u_ila_0/probe16 [get_nets [list SmcAre_i_IBUF]]
    404. 

  404. set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe17]
    405. 

  405. set_property port_width 1 [get_debug_ports u_ila_0/probe17]
    406. 

  406. connect_debug_port u_ila_0/probe17 [get_nets [list SmcAwe_i_IBUF]]
    407. 

  407. set_property PROBE_TYPE DATA [get_debug_ports u_ila_0/probe18]
    408. 

  408. set_property PROBE_TYPE DATA [get_debug_ports u_ila_0/probe18]
    409. 

  409. set_property port_width 1 [get_debug_ports u_ila_0/probe18]
    410. 

  410. connect_debug_port u_ila_0/probe18 [get_nets [list SpiTxRxEn]]
    411. 

  411. set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe19]
    412. 

  412. set_property port_width 1 [get_debug_ports u_ila_0/probe19]
    413. 

  413. connect_debug_port u_ila_0/probe19 [get_nets [list SsQ]]
    414. 

  414. set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe20]
    415. 

  415. set_property port_width 1 [get_debug_ports u_ila_0/probe20]
    416. 

  416. connect_debug_port u_ila_0/probe20 [get_nets [list SsR_0]]
    417. 

  417. set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe21]
    418. 

  418. set_property port_width 1 [get_debug_ports u_ila_0/probe21]
    419. 

  419. connect_debug_port u_ila_0/probe21 [get_nets [list {SpiGen[0].QuadSPIm_inst/Start_i}]]
    420. 

  420. set_property PROBE_TYPE DATA [get_debug_ports u_ila_0/probe22]
    421. 

  421. set_property port_width 1 [get_debug_ports u_ila_0/probe22]
    422. 

  422. connect_debug_port u_ila_0/probe22 [get_nets [list {SpiGen[0].DataFifoWrapper/ToFifoVal_i}]]
    423. 

  423. set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe23]
    424. 

  424. set_property port_width 1 [get_debug_ports u_ila_0/probe23]
    425. 

  425. connect_debug_port u_ila_0/probe23 [get_nets [list {SpiGen[0].DataFifoWrapper/txFifoRdEn}]]
    426. 

  426. set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe24]
    427. 

  427. set_property port_width 1 [get_debug_ports u_ila_0/probe24]
    428. 

  428. connect_debug_port u_ila_0/probe24 [get_nets [list {SpiGen[0].DataFifoWrapper/txFifoWrEn}]]
    429. 

  429. 

  430. connect_debug_port u_ila_0/probe5 [get_nets [list {SmcBe_i_IBUF[0]} {SmcBe_i_IBUF[1]}]]
    431. 

  431. 

  432. 

  433. 

  434. 

  435. 

  436. set_false_path -from [get_clocks Clk123_i] -to [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT6]]
    437. 

  437. set_false_path -from [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT6]] -to [get_clocks Clk123_i]
    438. 

  438. set_false_path -from [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT6]] -to [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT6]]
    439. 

  439. 

  440. set_false_path -from [get_clocks Clk123_i] -to [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT5]]
    441. 

  441. set_false_path -from [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT5]] -to [get_clocks Clk123_i]
    442. 

  442. set_false_path -from [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT5]] -to [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT5]]
    443. 

  443. 

  444. 

  445. set_false_path -from [get_clocks Clk123_i] -to [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT4]]
    446. 

  446. set_false_path -from [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT4]] -to [get_clocks Clk123_i]
    447. 

  447. set_false_path -from [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT4]] -to [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT4]]
    448. 

  448. 

  449. 

  450. set_false_path -from [get_clocks Clk123_i] -to [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT3]]
    451. 

  451. set_false_path -from [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT3]] -to [get_clocks Clk123_i]
    452. 

  452. set_false_path -from [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT3]] -to [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT3]]
    453. 

  453. 

  454. 

  455. set_false_path -from [get_clocks Clk123_i] -to [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT2]]
    456. 

  456. set_false_path -from [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT2]] -to [get_clocks Clk123_i]
    457. 

  457. set_false_path -from [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT2]] -to [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT2]]
    458. 

  458. 

  459. 

  460. set_false_path -from [get_clocks Clk123_i] -to [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT1]]
    461. 

  461. set_false_path -from [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT1]] -to [get_clocks Clk123_i]
    462. 

  462. set_false_path -from [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT1]] -to [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT1]]
    463. 

  463. 

  464. 

  465. set_false_path -from [get_clocks Clk123_i] -to [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT0]]
    466. 

  466. set_false_path -from [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT0]] -to [get_clocks Clk123_i]
    467. 

  467. set_false_path -from [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT0]] -to [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT0]]
    468. 

  468. 

  469. 

  470. 

  471. 

  472. connect_debug_port u_ila_0/probe23 [get_nets [list {DataOutMuxer/dataFromRxFifoR1_reg[16]_i_1_n_0}]]
    473. 

  473. connect_debug_port u_ila_0/probe24 [get_nets [list {DataOutMuxer/dataFromRxFifoR1_reg[17]_i_1_n_0}]]
    474. 

  474. connect_debug_port u_ila_0/probe25 [get_nets [list {DataOutMuxer/dataFromRxFifoR1_reg[18]_i_1_n_0}]]
    475. 

  475. connect_debug_port u_ila_0/probe26 [get_nets [list {DataOutMuxer/dataFromRxFifoR1_reg[19]_i_1_n_0}]]
    476. 

  476. connect_debug_port u_ila_0/probe27 [get_nets [list {DataOutMuxer/dataFromRxFifoR1_reg[20]_i_1_n_0}]]
    477. 

  477. connect_debug_port u_ila_0/probe28 [get_nets [list {DataOutMuxer/dataFromRxFifoR1_reg[21]_i_1_n_0}]]
    478. 

  478. connect_debug_port u_ila_0/probe29 [get_nets [list {DataOutMuxer/dataFromRxFifoR1_reg[22]_i_1_n_0}]]
    479. 

  479. connect_debug_port u_ila_0/probe30 [get_nets [list {DataOutMuxer/dataFromRxFifoR1_reg[23]_i_1_n_0}]]
    480. 

  480. connect_debug_port u_ila_0/probe31 [get_nets [list {DataOutMuxer/dataFromRxFifoR1_reg[24]_i_1_n_0}]]
    481. 

  481. connect_debug_port u_ila_0/probe32 [get_nets [list {DataOutMuxer/dataFromRxFifoR1_reg[25]_i_1_n_0}]]
    482. 

  482. connect_debug_port u_ila_0/probe33 [get_nets [list {DataOutMuxer/dataFromRxFifoR1_reg[26]_i_1_n_0}]]
    483. 

  483. connect_debug_port u_ila_0/probe34 [get_nets [list {DataOutMuxer/dataFromRxFifoR1_reg[27]_i_1_n_0}]]
    484. 

  484. connect_debug_port u_ila_0/probe35 [get_nets [list {DataOutMuxer/dataFromRxFifoR1_reg[28]_i_1_n_0}]]
    485. 

  485. connect_debug_port u_ila_0/probe36 [get_nets [list {DataOutMuxer/dataFromRxFifoR1_reg[29]_i_1_n_0}]]
    486. 

  486. connect_debug_port u_ila_0/probe37 [get_nets [list {DataOutMuxer/dataFromRxFifoR1_reg[30]_i_1_n_0}]]
    487. 

  487. 

  488. 

  489. 

  490. 

  491. 

  492. 

  493. 

  494. 

  495. 

  496. connect_debug_port u_ila_0/probe1 [get_nets [list {SpiGen[0].DataFifoWrapper/wr_data_count[0]} {SpiGen[0].DataFifoWrapper/wr_data_count[1]} {SpiGen[0].DataFifoWrapper/wr_data_count[2]} {SpiGen[0].DataFifoWrapper/wr_data_count[3]} {SpiGen[0].DataFifoWrapper/wr_data_count[4]} {SpiGen[0].DataFifoWrapper/wr_data_count[5]} {SpiGen[0].DataFifoWrapper/wr_data_count[6]} {SpiGen[0].DataFifoWrapper/wr_data_count[7]} {SpiGen[0].DataFifoWrapper/wr_data_count[8]} {SpiGen[0].DataFifoWrapper/wr_data_count[9]} {SpiGen[0].DataFifoWrapper/wr_data_count[10]} {SpiGen[0].DataFifoWrapper/wr_data_count[11]}]]
    497. 

  497. connect_debug_port u_ila_0/probe2 [get_nets [list {SpiGen[0].DataFifoWrapper/rd_data_count[0]} {SpiGen[0].DataFifoWrapper/rd_data_count[1]} {SpiGen[0].DataFifoWrapper/rd_data_count[2]} {SpiGen[0].DataFifoWrapper/rd_data_count[3]} {SpiGen[0].DataFifoWrapper/rd_data_count[4]} {SpiGen[0].DataFifoWrapper/rd_data_count[5]} {SpiGen[0].DataFifoWrapper/rd_data_count[6]} {SpiGen[0].DataFifoWrapper/rd_data_count[7]} {SpiGen[0].DataFifoWrapper/rd_data_count[8]} {SpiGen[0].DataFifoWrapper/rd_data_count[9]} {SpiGen[0].DataFifoWrapper/rd_data_count[10]} {SpiGen[0].DataFifoWrapper/rd_data_count[11]}]]
    498. 

  498. 

  499. 

  500. 

  501. 

  502. 

  503. connect_debug_port u_ila_0/probe17 [get_nets [list {SpiGen[0].DataFifoWrapper/emptyFlagRx}]]
    504. 

  504. connect_debug_port u_ila_0/probe18 [get_nets [list {SpiGen[0].DataFifoWrapper/emptyFlagTx}]]
    505. 

  505. connect_debug_port u_ila_0/probe21 [get_nets [list {SpiGen[0].DataFifoWrapper/fullFlagTx}]]
    506. 

  506. connect_debug_port u_ila_0/probe31 [get_nets [list {SpiGen[0].DataFifoWrapper/valid}]]
    507. 

  507. 

  508. 

  509. 

  510. 

  511. 

  512. connect_debug_port u_ila_0/probe7 [get_nets [list {SpiGen[0].DataFifoWrapper/TxFifoWrdCnt_i[0]} {SpiGen[0].DataFifoWrapper/TxFifoWrdCnt_i[1]} {SpiGen[0].DataFifoWrapper/TxFifoWrdCnt_i[2]} {SpiGen[0].DataFifoWrapper/TxFifoWrdCnt_i[3]} {SpiGen[0].DataFifoWrapper/TxFifoWrdCnt_i[4]} {SpiGen[0].DataFifoWrapper/TxFifoWrdCnt_i[5]} {SpiGen[0].DataFifoWrapper/TxFifoWrdCnt_i[6]} {SpiGen[0].DataFifoWrapper/TxFifoWrdCnt_i[7]}]]
    513. 

  513. connect_debug_port u_ila_0/probe8 [get_nets [list {SpiGen[0].DataFifoWrapper/RxFifoWrdCnt_i[0]} {SpiGen[0].DataFifoWrapper/RxFifoWrdCnt_i[1]} {SpiGen[0].DataFifoWrapper/RxFifoWrdCnt_i[2]} {SpiGen[0].DataFifoWrapper/RxFifoWrdCnt_i[3]} {SpiGen[0].DataFifoWrapper/RxFifoWrdCnt_i[4]} {SpiGen[0].DataFifoWrapper/RxFifoWrdCnt_i[5]} {SpiGen[0].DataFifoWrapper/RxFifoWrdCnt_i[6]} {SpiGen[0].DataFifoWrapper/RxFifoWrdCnt_i[7]}]]
    514. 

  514. 

  515. connect_debug_port u_ila_0/probe17 [get_nets [list {rxFifoCtrlReg[0][30]} {rxFifoCtrlReg[0][29]} {rxFifoCtrlReg[0][23]} {rxFifoCtrlReg[0][22]} {rxFifoCtrlReg[0][21]} {rxFifoCtrlReg[0][20]} {rxFifoCtrlReg[0][19]} {rxFifoCtrlReg[0][18]} {rxFifoCtrlReg[0][17]} {rxFifoCtrlReg[0][16]}]]
    516. 

  516. connect_debug_port u_ila_0/probe18 [get_nets [list {txFifoCtrlReg[0][30]} {txFifoCtrlReg[0][29]} {txFifoCtrlReg[0][23]} {txFifoCtrlReg[0][22]} {txFifoCtrlReg[0][21]} {txFifoCtrlReg[0][20]} {txFifoCtrlReg[0][19]} {txFifoCtrlReg[0][18]} {txFifoCtrlReg[0][17]} {txFifoCtrlReg[0][16]}]]
    517. 

  517. 

  518. 

  519. connect_debug_port u_ila_0/probe7 [get_nets [list {RegMap_inst/RxFifoCtrlReg0_i[16]} {RegMap_inst/RxFifoCtrlReg0_i[17]} {RegMap_inst/RxFifoCtrlReg0_i[18]} {RegMap_inst/RxFifoCtrlReg0_i[19]} {RegMap_inst/RxFifoCtrlReg0_i[20]} {RegMap_inst/RxFifoCtrlReg0_i[21]} {RegMap_inst/RxFifoCtrlReg0_i[22]} {RegMap_inst/RxFifoCtrlReg0_i[23]} {RegMap_inst/RxFifoCtrlReg0_i[29]} {RegMap_inst/RxFifoCtrlReg0_i[30]} {RegMap_inst/RxFifoCtrlReg0_i[31]}]]
    520. 

  520. connect_debug_port u_ila_0/probe12 [get_nets [list {RegMap_inst/TxFifoCtrlReg0_i[16]} {RegMap_inst/TxFifoCtrlReg0_i[17]} {RegMap_inst/TxFifoCtrlReg0_i[18]} {RegMap_inst/TxFifoCtrlReg0_i[19]} {RegMap_inst/TxFifoCtrlReg0_i[20]} {RegMap_inst/TxFifoCtrlReg0_i[21]} {RegMap_inst/TxFifoCtrlReg0_i[22]} {RegMap_inst/TxFifoCtrlReg0_i[23]} {RegMap_inst/TxFifoCtrlReg0_i[29]} {RegMap_inst/TxFifoCtrlReg0_i[30]} {RegMap_inst/TxFifoCtrlReg0_i[31]}]]
    521. 

  521. connect_debug_port u_ila_0/probe21 [get_nets [list {rxFifoCtrlReg[0][15]} {rxFifoCtrlReg[0][14]} {rxFifoCtrlReg[0][13]} {rxFifoCtrlReg[0][12]} {rxFifoCtrlReg[0][11]} {rxFifoCtrlReg[0][10]} {rxFifoCtrlReg[0][9]} {rxFifoCtrlReg[0][8]} {rxFifoCtrlReg[0][2]} {rxFifoCtrlReg[0][1]}]]
    522. 

  522. connect_debug_port u_ila_0/probe24 [get_nets [list {txFifoCtrlReg[0][15]} {txFifoCtrlReg[0][14]} {txFifoCtrlReg[0][13]} {txFifoCtrlReg[0][12]} {txFifoCtrlReg[0][11]} {txFifoCtrlReg[0][10]} {txFifoCtrlReg[0][9]} {txFifoCtrlReg[0][8]} {txFifoCtrlReg[0][2]} {txFifoCtrlReg[0][1]}]]
    523. 

  523. 

  524. create_debug_core u_ila_0 ila
    525. 

  525. set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0]
    526. 

  526. set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_0]
    527. 

  527. set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0]
    528. 

  528. set_property C_DATA_DEPTH 1024 [get_debug_cores u_ila_0]
    529. 

  529. set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_0]
    530. 

  530. set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0]
    531. 

  531. set_property C_TRIGIN_EN false [get_debug_cores u_ila_0]
    532. 

  532. set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0]
    533. 

  533. set_property port_width 1 [get_debug_ports u_ila_0/clk]
    534. 

  534. connect_debug_port u_ila_0/clk [get_nets [list gclk]]
    535. 

  535. set_property PROBE_TYPE DATA [get_debug_ports u_ila_0/probe0]
    536. 

  536. set_property port_width 8 [get_debug_ports u_ila_0/probe0]
    537. 

  537. connect_debug_port u_ila_0/probe0 [get_nets [list {SpiGen[0].DataFifoWrapper/FifoCtrl_inst/rxFifoRdPtr[0]} {SpiGen[0].DataFifoWrapper/FifoCtrl_inst/rxFifoRdPtr[1]} {SpiGen[0].DataFifoWrapper/FifoCtrl_inst/rxFifoRdPtr[2]} {SpiGen[0].DataFifoWrapper/FifoCtrl_inst/rxFifoRdPtr[3]} {SpiGen[0].DataFifoWrapper/FifoCtrl_inst/rxFifoRdPtr[4]} {SpiGen[0].DataFifoWrapper/FifoCtrl_inst/rxFifoRdPtr[5]} {SpiGen[0].DataFifoWrapper/FifoCtrl_inst/rxFifoRdPtr[6]} {SpiGen[0].DataFifoWrapper/FifoCtrl_inst/rxFifoRdPtr[7]}]]
    538. 

  538. create_debug_port u_ila_0 probe
    539. 

  539. set_property PROBE_TYPE DATA [get_debug_ports u_ila_0/probe1]
    540. 

  540. set_property port_width 8 [get_debug_ports u_ila_0/probe1]
    541. 

  541. connect_debug_port u_ila_0/probe1 [get_nets [list {SpiGen[0].DataFifoWrapper/FifoCtrl_inst/txFifoRdPtr[0]} {SpiGen[0].DataFifoWrapper/FifoCtrl_inst/txFifoRdPtr[1]} {SpiGen[0].DataFifoWrapper/FifoCtrl_inst/txFifoRdPtr[2]} {SpiGen[0].DataFifoWrapper/FifoCtrl_inst/txFifoRdPtr[3]} {SpiGen[0].DataFifoWrapper/FifoCtrl_inst/txFifoRdPtr[4]} {SpiGen[0].DataFifoWrapper/FifoCtrl_inst/txFifoRdPtr[5]} {SpiGen[0].DataFifoWrapper/FifoCtrl_inst/txFifoRdPtr[6]} {SpiGen[0].DataFifoWrapper/FifoCtrl_inst/txFifoRdPtr[7]}]]
    542. 

  542. create_debug_port u_ila_0 probe
    543. 

  543. set_property PROBE_TYPE DATA [get_debug_ports u_ila_0/probe2]
    544. 

  544. set_property port_width 32 [get_debug_ports u_ila_0/probe2]
    545. 

  545. connect_debug_port u_ila_0/probe2 [get_nets [list {SpiGen[0].DataFifoWrapper/ToSpiData_o[0]} {SpiGen[0].DataFifoWrapper/ToSpiData_o[1]} {SpiGen[0].DataFifoWrapper/ToSpiData_o[2]} {SpiGen[0].DataFifoWrapper/ToSpiData_o[3]} {SpiGen[0].DataFifoWrapper/ToSpiData_o[4]} {SpiGen[0].DataFifoWrapper/ToSpiData_o[5]} {SpiGen[0].DataFifoWrapper/ToSpiData_o[6]} {SpiGen[0].DataFifoWrapper/ToSpiData_o[7]} {SpiGen[0].DataFifoWrapper/ToSpiData_o[8]} {SpiGen[0].DataFifoWrapper/ToSpiData_o[9]} {SpiGen[0].DataFifoWrapper/ToSpiData_o[10]} {SpiGen[0].DataFifoWrapper/ToSpiData_o[11]} {SpiGen[0].DataFifoWrapper/ToSpiData_o[12]} {SpiGen[0].DataFifoWrapper/ToSpiData_o[13]} {SpiGen[0].DataFifoWrapper/ToSpiData_o[14]} {SpiGen[0].DataFifoWrapper/ToSpiData_o[15]} {SpiGen[0].DataFifoWrapper/ToSpiData_o[16]} {SpiGen[0].DataFifoWrapper/ToSpiData_o[17]} {SpiGen[0].DataFifoWrapper/ToSpiData_o[18]} {SpiGen[0].DataFifoWrapper/ToSpiData_o[19]} {SpiGen[0].DataFifoWrapper/ToSpiData_o[20]} {SpiGen[0].DataFifoWrapper/ToSpiData_o[21]} {SpiGen[0].DataFifoWrapper/ToSpiData_o[22]} {SpiGen[0].DataFifoWrapper/ToSpiData_o[23]} {SpiGen[0].DataFifoWrapper/ToSpiData_o[24]} {SpiGen[0].DataFifoWrapper/ToSpiData_o[25]} {SpiGen[0].DataFifoWrapper/ToSpiData_o[26]} {SpiGen[0].DataFifoWrapper/ToSpiData_o[27]} {SpiGen[0].DataFifoWrapper/ToSpiData_o[28]} {SpiGen[0].DataFifoWrapper/ToSpiData_o[29]} {SpiGen[0].DataFifoWrapper/ToSpiData_o[30]} {SpiGen[0].DataFifoWrapper/ToSpiData_o[31]}]]
    546. 

  546. create_debug_port u_ila_0 probe
    547. 

  547. set_property PROBE_TYPE DATA [get_debug_ports u_ila_0/probe3]
    548. 

  548. set_property port_width 8 [get_debug_ports u_ila_0/probe3]
    549. 

  549. connect_debug_port u_ila_0/probe3 [get_nets [list {SpiGen[0].DataFifoWrapper/FifoCtrl_inst/txFifoUpDnCnt[0]} {SpiGen[0].DataFifoWrapper/FifoCtrl_inst/txFifoUpDnCnt[1]} {SpiGen[0].DataFifoWrapper/FifoCtrl_inst/txFifoUpDnCnt[2]} {SpiGen[0].DataFifoWrapper/FifoCtrl_inst/txFifoUpDnCnt[3]} {SpiGen[0].DataFifoWrapper/FifoCtrl_inst/txFifoUpDnCnt[4]} {SpiGen[0].DataFifoWrapper/FifoCtrl_inst/txFifoUpDnCnt[5]} {SpiGen[0].DataFifoWrapper/FifoCtrl_inst/txFifoUpDnCnt[6]} {SpiGen[0].DataFifoWrapper/FifoCtrl_inst/txFifoUpDnCnt[7]}]]
    550. 

  550. create_debug_port u_ila_0 probe
    551. 

  551. set_property PROBE_TYPE DATA [get_debug_ports u_ila_0/probe4]
    552. 

  552. set_property port_width 8 [get_debug_ports u_ila_0/probe4]
    553. 

  553. connect_debug_port u_ila_0/probe4 [get_nets [list {SpiGen[0].DataFifoWrapper/FifoCtrl_inst/rxFifoUpDnCnt[0]} {SpiGen[0].DataFifoWrapper/FifoCtrl_inst/rxFifoUpDnCnt[1]} {SpiGen[0].DataFifoWrapper/FifoCtrl_inst/rxFifoUpDnCnt[2]} {SpiGen[0].DataFifoWrapper/FifoCtrl_inst/rxFifoUpDnCnt[3]} {SpiGen[0].DataFifoWrapper/FifoCtrl_inst/rxFifoUpDnCnt[4]} {SpiGen[0].DataFifoWrapper/FifoCtrl_inst/rxFifoUpDnCnt[5]} {SpiGen[0].DataFifoWrapper/FifoCtrl_inst/rxFifoUpDnCnt[6]} {SpiGen[0].DataFifoWrapper/FifoCtrl_inst/rxFifoUpDnCnt[7]}]]
    554. 

  554. create_debug_port u_ila_0 probe
    555. 

  555. set_property PROBE_TYPE DATA [get_debug_ports u_ila_0/probe5]
    556. 

  556. set_property port_width 8 [get_debug_ports u_ila_0/probe5]
    557. 

  557. connect_debug_port u_ila_0/probe5 [get_nets [list {SpiGen[0].DataFifoWrapper/FifoCtrl_inst/txFifoWrPtr[0]} {SpiGen[0].DataFifoWrapper/FifoCtrl_inst/txFifoWrPtr[1]} {SpiGen[0].DataFifoWrapper/FifoCtrl_inst/txFifoWrPtr[2]} {SpiGen[0].DataFifoWrapper/FifoCtrl_inst/txFifoWrPtr[3]} {SpiGen[0].DataFifoWrapper/FifoCtrl_inst/txFifoWrPtr[4]} {SpiGen[0].DataFifoWrapper/FifoCtrl_inst/txFifoWrPtr[5]} {SpiGen[0].DataFifoWrapper/FifoCtrl_inst/txFifoWrPtr[6]} {SpiGen[0].DataFifoWrapper/FifoCtrl_inst/txFifoWrPtr[7]}]]
    558. 

  558. create_debug_port u_ila_0 probe
    559. 

  559. set_property PROBE_TYPE DATA [get_debug_ports u_ila_0/probe6]
    560. 

  560. set_property port_width 8 [get_debug_ports u_ila_0/probe6]
    561. 

  561. connect_debug_port u_ila_0/probe6 [get_nets [list {SpiGen[0].DataFifoWrapper/FifoCtrl_inst/rxFifoWrPtr[0]} {SpiGen[0].DataFifoWrapper/FifoCtrl_inst/rxFifoWrPtr[1]} {SpiGen[0].DataFifoWrapper/FifoCtrl_inst/rxFifoWrPtr[2]} {SpiGen[0].DataFifoWrapper/FifoCtrl_inst/rxFifoWrPtr[3]} {SpiGen[0].DataFifoWrapper/FifoCtrl_inst/rxFifoWrPtr[4]} {SpiGen[0].DataFifoWrapper/FifoCtrl_inst/rxFifoWrPtr[5]} {SpiGen[0].DataFifoWrapper/FifoCtrl_inst/rxFifoWrPtr[6]} {SpiGen[0].DataFifoWrapper/FifoCtrl_inst/rxFifoWrPtr[7]}]]
    562. 

  562. create_debug_port u_ila_0 probe
    563. 

  563. set_property PROBE_TYPE DATA [get_debug_ports u_ila_0/probe7]
    564. 

  564. set_property port_width 11 [get_debug_ports u_ila_0/probe7]
    565. 

  565. connect_debug_port u_ila_0/probe7 [get_nets [list {RegMap_inst/TxFifoCtrlReg0_i[0]} {RegMap_inst/TxFifoCtrlReg0_i[1]} {RegMap_inst/TxFifoCtrlReg0_i[2]} {RegMap_inst/TxFifoCtrlReg0_i[8]} {RegMap_inst/TxFifoCtrlReg0_i[9]} {RegMap_inst/TxFifoCtrlReg0_i[10]} {RegMap_inst/TxFifoCtrlReg0_i[11]} {RegMap_inst/TxFifoCtrlReg0_i[12]} {RegMap_inst/TxFifoCtrlReg0_i[13]} {RegMap_inst/TxFifoCtrlReg0_i[14]} {RegMap_inst/TxFifoCtrlReg0_i[15]}]]
    566. 

  566. create_debug_port u_ila_0 probe
    567. 

  567. set_property PROBE_TYPE DATA [get_debug_ports u_ila_0/probe8]
    568. 

  568. set_property port_width 11 [get_debug_ports u_ila_0/probe8]
    569. 

  569. connect_debug_port u_ila_0/probe8 [get_nets [list {RegMap_inst/RxFifoCtrlReg0_i[0]} {RegMap_inst/RxFifoCtrlReg0_i[1]} {RegMap_inst/RxFifoCtrlReg0_i[2]} {RegMap_inst/RxFifoCtrlReg0_i[8]} {RegMap_inst/RxFifoCtrlReg0_i[9]} {RegMap_inst/RxFifoCtrlReg0_i[10]} {RegMap_inst/RxFifoCtrlReg0_i[11]} {RegMap_inst/RxFifoCtrlReg0_i[12]} {RegMap_inst/RxFifoCtrlReg0_i[13]} {RegMap_inst/RxFifoCtrlReg0_i[14]} {RegMap_inst/RxFifoCtrlReg0_i[15]}]]
    570. 

  570. create_debug_port u_ila_0 probe
    571. 

  571. set_property PROBE_TYPE DATA [get_debug_ports u_ila_0/probe9]
    572. 

  572. set_property port_width 32 [get_debug_ports u_ila_0/probe9]
    573. 

  573. connect_debug_port u_ila_0/probe9 [get_nets [list {dataFromRxFifo[0][31]} {dataFromRxFifo[0][30]} {dataFromRxFifo[0][29]} {dataFromRxFifo[0][28]} {dataFromRxFifo[0][27]} {dataFromRxFifo[0][26]} {dataFromRxFifo[0][25]} {dataFromRxFifo[0][24]} {dataFromRxFifo[0][23]} {dataFromRxFifo[0][22]} {dataFromRxFifo[0][21]} {dataFromRxFifo[0][20]} {dataFromRxFifo[0][19]} {dataFromRxFifo[0][18]} {dataFromRxFifo[0][17]} {dataFromRxFifo[0][16]} {dataFromRxFifo[0][15]} {dataFromRxFifo[0][14]} {dataFromRxFifo[0][13]} {dataFromRxFifo[0][12]} {dataFromRxFifo[0][11]} {dataFromRxFifo[0][10]} {dataFromRxFifo[0][9]} {dataFromRxFifo[0][8]} {dataFromRxFifo[0][7]} {dataFromRxFifo[0][6]} {dataFromRxFifo[0][5]} {dataFromRxFifo[0][4]} {dataFromRxFifo[0][3]} {dataFromRxFifo[0][2]} {dataFromRxFifo[0][1]} {dataFromRxFifo[0][0]}]]
    574. 

  574. create_debug_port u_ila_0 probe
    575. 

  575. set_property PROBE_TYPE DATA [get_debug_ports u_ila_0/probe10]
    576. 

  576. set_property port_width 32 [get_debug_ports u_ila_0/probe10]
    577. 

  577. connect_debug_port u_ila_0/probe10 [get_nets [list {toFifoData[0]} {toFifoData[1]} {toFifoData[2]} {toFifoData[3]} {toFifoData[4]} {toFifoData[5]} {toFifoData[6]} {toFifoData[7]} {toFifoData[8]} {toFifoData[9]} {toFifoData[10]} {toFifoData[11]} {toFifoData[12]} {toFifoData[13]} {toFifoData[14]} {toFifoData[15]} {toFifoData[16]} {toFifoData[17]} {toFifoData[18]} {toFifoData[19]} {toFifoData[20]} {toFifoData[21]} {toFifoData[22]} {toFifoData[23]} {toFifoData[24]} {toFifoData[25]} {toFifoData[26]} {toFifoData[27]} {toFifoData[28]} {toFifoData[29]} {toFifoData[30]} {toFifoData[31]}]]
    578. 

  578. create_debug_port u_ila_0 probe
    579. 

  579. set_property PROBE_TYPE DATA [get_debug_ports u_ila_0/probe11]
    580. 

  580. set_property port_width 1 [get_debug_ports u_ila_0/probe11]
    581. 

  581. connect_debug_port u_ila_0/probe11 [get_nets [list {Ss_o_OBUF[0]}]]
    582. 

  582. create_debug_port u_ila_0 probe
    583. 

  583. set_property PROBE_TYPE DATA [get_debug_ports u_ila_0/probe12]
    584. 

  584. set_property port_width 16 [get_debug_ports u_ila_0/probe12]
    585. 

  585. connect_debug_port u_ila_0/probe12 [get_nets [list {smcData[0]} {smcData[1]} {smcData[2]} {smcData[3]} {smcData[4]} {smcData[5]} {smcData[6]} {smcData[7]} {smcData[8]} {smcData[9]} {smcData[10]} {smcData[11]} {smcData[12]} {smcData[13]} {smcData[14]} {smcData[15]}]]
    586. 

  586. create_debug_port u_ila_0 probe
    587. 

  587. set_property PROBE_TYPE DATA [get_debug_ports u_ila_0/probe13]
    588. 

  588. set_property port_width 1 [get_debug_ports u_ila_0/probe13]
    589. 

  589. connect_debug_port u_ila_0/probe13 [get_nets [list {Mosi3_o_OBUF[0]}]]
    590. 

  590. create_debug_port u_ila_0 probe
    591. 

  591. set_property PROBE_TYPE DATA [get_debug_ports u_ila_0/probe14]
    592. 

  592. set_property port_width 1 [get_debug_ports u_ila_0/probe14]
    593. 

  593. connect_debug_port u_ila_0/probe14 [get_nets [list {Mosi2_o_OBUF[0]}]]
    594. 

  594. create_debug_port u_ila_0 probe
    595. 

  595. set_property PROBE_TYPE DATA [get_debug_ports u_ila_0/probe15]
    596. 

  596. set_property port_width 11 [get_debug_ports u_ila_0/probe15]
    597. 

  597. connect_debug_port u_ila_0/probe15 [get_nets [list {SmcAddr_i_IBUF[0]} {SmcAddr_i_IBUF[1]} {SmcAddr_i_IBUF[2]} {SmcAddr_i_IBUF[3]} {SmcAddr_i_IBUF[4]} {SmcAddr_i_IBUF[5]} {SmcAddr_i_IBUF[6]} {SmcAddr_i_IBUF[7]} {SmcAddr_i_IBUF[8]} {SmcAddr_i_IBUF[9]} {SmcAddr_i_IBUF[10]}]]
    598. 

  598. create_debug_port u_ila_0 probe
    599. 

  599. set_property PROBE_TYPE DATA [get_debug_ports u_ila_0/probe16]
    600. 

  600. set_property port_width 1 [get_debug_ports u_ila_0/probe16]
    601. 

  601. connect_debug_port u_ila_0/probe16 [get_nets [list {Mosi1_io_OBUF[0]}]]
    602. 

  602. create_debug_port u_ila_0 probe
    603. 

  603. set_property PROBE_TYPE DATA [get_debug_ports u_ila_0/probe17]
    604. 

  604. set_property port_width 1 [get_debug_ports u_ila_0/probe17]
    605. 

  605. connect_debug_port u_ila_0/probe17 [get_nets [list {Mosi0_o_OBUF[0]}]]
    606. 

  606. create_debug_port u_ila_0 probe
    607. 

  607. set_property PROBE_TYPE DATA [get_debug_ports u_ila_0/probe18]
    608. 

  608. set_property port_width 32 [get_debug_ports u_ila_0/probe18]
    609. 

  609. connect_debug_port u_ila_0/probe18 [get_nets [list {toSpiData[0][31]} {toSpiData[0][30]} {toSpiData[0][29]} {toSpiData[0][28]} {toSpiData[0][27]} {toSpiData[0][26]} {toSpiData[0][25]} {toSpiData[0][24]} {toSpiData[0][23]} {toSpiData[0][22]} {toSpiData[0][21]} {toSpiData[0][20]} {toSpiData[0][19]} {toSpiData[0][18]} {toSpiData[0][17]} {toSpiData[0][16]} {toSpiData[0][15]} {toSpiData[0][14]} {toSpiData[0][13]} {toSpiData[0][12]} {toSpiData[0][11]} {toSpiData[0][10]} {toSpiData[0][9]} {toSpiData[0][8]} {toSpiData[0][7]} {toSpiData[0][6]} {toSpiData[0][5]} {toSpiData[0][4]} {toSpiData[0][3]} {toSpiData[0][2]} {toSpiData[0][1]} {toSpiData[0][0]}]]
    610. 

  610. create_debug_port u_ila_0 probe
    611. 

  611. set_property PROBE_TYPE DATA [get_debug_ports u_ila_0/probe19]
    612. 

  612. set_property port_width 32 [get_debug_ports u_ila_0/probe19]
    613. 

  613. connect_debug_port u_ila_0/probe19 [get_nets [list {dataToRxFifo[0][31]} {dataToRxFifo[0][30]} {dataToRxFifo[0][29]} {dataToRxFifo[0][28]} {dataToRxFifo[0][27]} {dataToRxFifo[0][26]} {dataToRxFifo[0][25]} {dataToRxFifo[0][24]} {dataToRxFifo[0][23]} {dataToRxFifo[0][22]} {dataToRxFifo[0][21]} {dataToRxFifo[0][20]} {dataToRxFifo[0][19]} {dataToRxFifo[0][18]} {dataToRxFifo[0][17]} {dataToRxFifo[0][16]} {dataToRxFifo[0][15]} {dataToRxFifo[0][14]} {dataToRxFifo[0][13]} {dataToRxFifo[0][12]} {dataToRxFifo[0][11]} {dataToRxFifo[0][10]} {dataToRxFifo[0][9]} {dataToRxFifo[0][8]} {dataToRxFifo[0][7]} {dataToRxFifo[0][6]} {dataToRxFifo[0][5]} {dataToRxFifo[0][4]} {dataToRxFifo[0][3]} {dataToRxFifo[0][2]} {dataToRxFifo[0][1]} {dataToRxFifo[0][0]}]]
    614. 

  614. create_debug_port u_ila_0 probe
    615. 

  615. set_property PROBE_TYPE DATA [get_debug_ports u_ila_0/probe20]
    616. 

  616. set_property port_width 16 [get_debug_ports u_ila_0/probe20]
    617. 

  617. connect_debug_port u_ila_0/probe20 [get_nets [list {ansData[0]} {ansData[1]} {ansData[2]} {ansData[3]} {ansData[4]} {ansData[5]} {ansData[6]} {ansData[7]} {ansData[8]} {ansData[9]} {ansData[10]} {ansData[11]} {ansData[12]} {ansData[13]} {ansData[14]} {ansData[15]}]]
    618. 

  618. create_debug_port u_ila_0 probe
    619. 

  619. set_property PROBE_TYPE DATA [get_debug_ports u_ila_0/probe21]
    620. 

  620. set_property port_width 16 [get_debug_ports u_ila_0/probe21]
    621. 

  621. connect_debug_port u_ila_0/probe21 [get_nets [list {muxedData[0]} {muxedData[1]} {muxedData[2]} {muxedData[3]} {muxedData[4]} {muxedData[5]} {muxedData[6]} {muxedData[7]} {muxedData[8]} {muxedData[9]} {muxedData[10]} {muxedData[11]} {muxedData[12]} {muxedData[13]} {muxedData[14]} {muxedData[15]}]]
    622. 

  622. create_debug_port u_ila_0 probe
    623. 

  623. set_property PROBE_TYPE DATA [get_debug_ports u_ila_0/probe22]
    624. 

  624. set_property port_width 1 [get_debug_ports u_ila_0/probe22]
    625. 

  625. connect_debug_port u_ila_0/probe22 [get_nets [list {Sck_o_OBUF[0]}]]
    626. 

  626. create_debug_port u_ila_0 probe
    627. 

  627. set_property PROBE_TYPE DATA [get_debug_ports u_ila_0/probe23]
    628. 

  628. set_property port_width 16 [get_debug_ports u_ila_0/probe23]
    629. 

  629. connect_debug_port u_ila_0/probe23 [get_nets [list {ansDataRR[0]} {ansDataRR[1]} {ansDataRR[2]} {ansDataRR[3]} {ansDataRR[4]} {ansDataRR[5]} {ansDataRR[6]} {ansDataRR[7]} {ansDataRR[8]} {ansDataRR[9]} {ansDataRR[10]} {ansDataRR[11]} {ansDataRR[12]} {ansDataRR[13]} {ansDataRR[14]} {ansDataRR[15]}]]
    630. 

  630. create_debug_port u_ila_0 probe
    631. 

  631. set_property PROBE_TYPE DATA [get_debug_ports u_ila_0/probe24]
    632. 

  632. set_property port_width 1 [get_debug_ports u_ila_0/probe24]
    633. 

  633. connect_debug_port u_ila_0/probe24 [get_nets [list MainMmcm/clkMan]]
    634. 

  634. create_debug_port u_ila_0 probe
    635. 

  635. set_property PROBE_TYPE DATA [get_debug_ports u_ila_0/probe25]
    636. 

  636. set_property port_width 1 [get_debug_ports u_ila_0/probe25]
    637. 

  637. connect_debug_port u_ila_0/probe25 [get_nets [list {SpiGen[0].DataFifoWrapper/FifoRxRst_i}]]
    638. 

  638. create_debug_port u_ila_0 probe
    639. 

  639. set_property PROBE_TYPE DATA [get_debug_ports u_ila_0/probe26]
    640. 

  640. set_property port_width 1 [get_debug_ports u_ila_0/probe26]
    641. 

  641. connect_debug_port u_ila_0/probe26 [get_nets [list {SpiGen[0].DataFifoWrapper/FifoTxRst_i}]]
    642. 

  642. create_debug_port u_ila_0 probe
    643. 

  643. set_property PROBE_TYPE DATA [get_debug_ports u_ila_0/probe27]
    644. 

  644. set_property port_width 1 [get_debug_ports u_ila_0/probe27]
    645. 

  645. connect_debug_port u_ila_0/probe27 [get_nets [list {SpiGen[0].DataFifoWrapper/rxFifoRdEn}]]
    646. 

  646. create_debug_port u_ila_0 probe
    647. 

  647. set_property PROBE_TYPE DATA [get_debug_ports u_ila_0/probe28]
    648. 

  648. set_property port_width 1 [get_debug_ports u_ila_0/probe28]
    649. 

  649. connect_debug_port u_ila_0/probe28 [get_nets [list {SpiGen[0].DataFifoWrapper/rxFifoWrEn}]]
    650. 

  650. create_debug_port u_ila_0 probe
    651. 

  651. set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe29]
    652. 

  652. set_property port_width 1 [get_debug_ports u_ila_0/probe29]
    653. 

  653. connect_debug_port u_ila_0/probe29 [get_nets [list SmcAre_i_IBUF]]
    654. 

  654. create_debug_port u_ila_0 probe
    655. 

  655. set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe30]
    656. 

  656. set_property port_width 1 [get_debug_ports u_ila_0/probe30]
    657. 

  657. connect_debug_port u_ila_0/probe30 [get_nets [list SmcAwe_i_IBUF]]
    658. 

  658. create_debug_port u_ila_0 probe
    659. 

  659. set_property PROBE_TYPE DATA [get_debug_ports u_ila_0/probe31]
    660. 

  660. set_property port_width 1 [get_debug_ports u_ila_0/probe31]
    661. 

  661. connect_debug_port u_ila_0/probe31 [get_nets [list spiClkBus]]
    662. 

  662. create_debug_port u_ila_0 probe
    663. 

  663. set_property PROBE_TYPE DATA [get_debug_ports u_ila_0/probe32]
    664. 

  664. set_property port_width 1 [get_debug_ports u_ila_0/probe32]
    665. 

  665. connect_debug_port u_ila_0/probe32 [get_nets [list {SpiGen[0].DataFifoWrapper/FifoCtrl_inst/ToFifoTxWriteVal_i}]]
    666. 

  666. create_debug_port u_ila_0 probe
    667. 

  667. set_property PROBE_TYPE DATA [get_debug_ports u_ila_0/probe33]
    668. 

  668. set_property port_width 1 [get_debug_ports u_ila_0/probe33]
    669. 

  669. connect_debug_port u_ila_0/probe33 [get_nets [list {SpiGen[0].DataFifoWrapper/txFifoRdEn}]]
    670. 

  670. create_debug_port u_ila_0 probe
    671. 

  671. set_property PROBE_TYPE DATA [get_debug_ports u_ila_0/probe34]
    672. 

  672. set_property port_width 1 [get_debug_ports u_ila_0/probe34]
    673. 

  673. connect_debug_port u_ila_0/probe34 [get_nets [list {SpiGen[0].DataFifoWrapper/txFifoWrEn}]]
    674. 

  674. set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub]
    675. 

  675. set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub]
    676. 

  676. set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub]
    677. 

  677. connect_debug_port dbg_hub/clk [get_nets gclk]
    678.