S5443_V3/sources_1/new/DataFifo/FifoCtrl.v

module FifoCtrl #(
    parameter Fifo0ReadMsbAddr		= 12'h0+12'd28,
	parameter Fifo1ReadMsbAddr		= 12'h50+12'd28,
	parameter Fifo2ReadMsbAddr		= 12'hf0+12'd28,
	parameter Fifo3ReadMsbAddr		= 12'h140+12'd28,
	parameter Fifo4ReadMsbAddr		= 12'h190+12'd28,
	parameter Fifo5ReadMsbAddr		= 12'h1e0+12'd28,
	parameter Fifo6ReadMsbAddr		= 12'h230+12'd28




)(
  input ToFifoTxWriteVal_i,
  input ToFifoTxReadVal_i,
  input ToFifoRxWriteVal_i,
  input ToFifoRxReadVal_i,

  input FifoTxFull_i,
  input FifoTxEmpty_i,
  input FifoRxFull_i,
  input FifoRxEmpty_i,
  input [11:0] SmcAddr_i,

  input   [7:0] TxFifoWrdCnt_i,
  input   [7:0] RxFifoWrdCnt_i,

  input FifoTxWrClock_i,
  input FifoTxRdClock_i,
  input FifoRxWrClock_i,
  input FifoRxRdClock_i,

  input FifoTxRst_i,
  input FifoRxRst_i,


  output  [7:0] RxFifoUpDnCnt_o,
  output  [7:0] TxFifoUpDnCnt_o,

  output FifoTxWriteEn_o,
  output FifoTxReadEn_o,
  output FifoRxWriteEn_o,
  output FifoRxReadEn_o

);


reg FifoTxWriteEn;
reg FifoTxReadEn;
reg FifoRxWriteEn;
reg FifoRxReadEn;

(* dont_touch = "true" *)reg [7:0] txFifoWrPtr;
(* dont_touch = "true" *)reg [7:0] txFifoRdPtr;
(* dont_touch = "true" *)reg [7:0] rxFifoWrPtr;
(* dont_touch = "true" *)reg [7:0] rxFifoRdPtr;

(* dont_touch = "true" *) reg [7:0] rxFifoUpDnCnt;
(* dont_touch = "true" *) reg [7:0] txFifoUpDnCnt;



wire	requestToFifo0	=(SmcAddr_i == Fifo0ReadMsbAddr)?1'b1:1'b0;
wire	requestToFifo1	=(SmcAddr_i == Fifo1ReadMsbAddr)?1'b1:1'b0;
wire	requestToFifo2	=(SmcAddr_i == Fifo2ReadMsbAddr)?1'b1:1'b0;
wire	requestToFifo3	=(SmcAddr_i == Fifo3ReadMsbAddr)?1'b1:1'b0;
wire	requestToFifo4	=(SmcAddr_i == Fifo4ReadMsbAddr)?1'b1:1'b0;
wire	requestToFifo5	=(SmcAddr_i == Fifo5ReadMsbAddr)?1'b1:1'b0;
wire	requestToFifo6	=(SmcAddr_i == Fifo6ReadMsbAddr)?1'b1:1'b0;
wire	requestToFifo	=	(requestToFifo0|requestToFifo1|requestToFifo2|requestToFifo3|requestToFifo4|requestToFifo5|requestToFifo6)?1'b1:1'b0;



// //================================================================================
// //	ASSIGNMENTS

assign FifoTxWriteEn_o = FifoTxWriteEn;
assign FifoTxReadEn_o = FifoTxReadEn;
assign FifoRxWriteEn_o = FifoRxWriteEn;
assign FifoRxReadEn_o = FifoRxReadEn;


assign RxFifoUpDnCnt_o = rxFifoUpDnCnt;
assign TxFifoUpDnCnt_o = txFifoUpDnCnt;


// //================================================================================



always @(posedge FifoTxWrClock_i) begin 
    if (ToFifoTxWriteVal_i && !FifoTxFull_i) begin 
        FifoTxWriteEn <= 1'b1;
    end
    else begin 
        FifoTxWriteEn <= 1'b0;
    end
end


always @(posedge FifoTxRdClock_i ) begin 
    if (ToFifoTxReadVal_i && !FifoTxEmpty_i) begin 
        FifoTxReadEn <= 1'b1;
    end
    else begin 
        FifoTxReadEn <= 1'b0;
    end
end


always @(posedge FifoRxWrClock_i) begin 
    if (ToFifoRxWriteVal_i && !FifoRxFull_i) begin 
        FifoRxWriteEn <= 1'b1;
    end
    else begin 
        FifoRxWriteEn <= 1'b0;
    end
end


always @(posedge FifoRxRdClock_i) begin 
    if (ToFifoRxReadVal_i && !FifoRxEmpty_i && requestToFifo) begin 
        FifoRxReadEn <= 1'b1;
    end
    else begin 
        FifoRxReadEn <= 1'b0;
    end
end


always @(posedge FifoTxWrClock_i ) begin 
    if (FifoTxRst_i) begin 
        txFifoWrPtr <= 8'h0;
    end
    else begin 
        if (FifoTxWriteEn  ) begin 
            txFifoWrPtr <= txFifoWrPtr + 1'b1;
        end
    end
end

always @(posedge FifoTxRdClock_i ) begin 
    if (FifoTxRst_i) begin 
        txFifoRdPtr <= 8'h0;
    end
    else begin 
        if (FifoTxReadEn ) begin 
            txFifoRdPtr <= txFifoRdPtr + 1'b1;
        end
    end
end


always @(posedge FifoRxWrClock_i) begin 
    if (FifoRxRst_i) begin 
        rxFifoWrPtr <= 8'h0;
    end
    else begin
        if (FifoRxWriteEn ) begin 
            rxFifoWrPtr <= rxFifoWrPtr + 1'b1;
        end
    end
end

always @(posedge FifoRxRdClock_i) begin 
    if (FifoRxRst_i) begin 
        rxFifoRdPtr <= 8'h0;
    end
    else begin 
        if (FifoRxReadEn ) begin 
            rxFifoRdPtr <= rxFifoRdPtr + 1'b1;
        end
    end
end


always @(posedge FifoRxRdClock_i) begin 
    if (FifoRxRst_i) begin 
        rxFifoUpDnCnt <= 8'h0;
    end
    else begin 
        rxFifoUpDnCnt <= rxFifoWrPtr - rxFifoRdPtr;
    end
end

always @(posedge FifoTxRdClock_i) begin 
    if (FifoTxRst_i) begin 
        txFifoUpDnCnt <= 8'h0;
    end
    else begin 
        txFifoUpDnCnt <= txFifoWrPtr - txFifoRdPtr;
    end
end





// //================================================================================

endmodule