S5443_V3/sources_1/new/Mux/DataMuxer.v

module SmcDataMux 
#(
    parameter	CmdRegWidth	=	16,
    parameter	AddrRegWidth=	12,
	
	parameter	FifoNum	=	7,
	
	// parameter	Fifo0WriteLsbAddr	=	12'h0+12'h24,
	// parameter	Fifo0WriteMsbAddr	=	12'h0+12'h26,
	// parameter	Fifo1WriteLsbAddr	=	12'h50+12'h24,
	// parameter	Fifo2WriteMsbAddr	=	12'hF0+12'h26,
	// parameter	Fifo3WriteLsbAddr	=	12'h140+12'h24,
	// parameter	Fifo4WriteMsbAddr	=	12'h190+12'h26,
	// parameter	Fifo5WriteLsbAddr	=	12'h1e0+12'h24,
	// parameter	Fifo6WriteMsbAddr	=	12'h230+12'h26
	
	parameter	Fifo0WriteLsbAddr	=	12'h0+12'h0,
	parameter	Fifo0WriteMsbAddr	=	12'h0+12'h2,
	parameter	Fifo1WriteLsbAddr	=	12'h0+12'h4,
	parameter	Fifo1WriteMsbAddr	=	12'h0+12'h6,
	parameter	Fifo2WriteLsbAddr	=	12'h0+12'h8,
	parameter	Fifo2WriteMsbAddr	=	12'h00+12'ha,
	parameter	Fifo3WriteLsbAddr	=	12'h0+12'hc,
	parameter	Fifo3WriteMsbAddr	=	12'h0+12'he,
	parameter	Fifo4WriteLsbAddr	=	12'h0+12'h10,
	parameter	Fifo4WriteMsbAddr	=	12'h190+12'h9,
	parameter	Fifo5WriteLsbAddr	=	12'h1e0+12'h10,
	parameter	Fifo5WriteMsbAddr	=	12'h1e0+12'h11,
	parameter	Fifo6WriteLsbAddr	=	12'h230+12'h12,
	parameter	Fifo6WriteMsbAddr	=	12'h230+12'h13
)
(
    input	Clk_i,
    input	Rst_i,

	input	SmcVal_i,
	input	[CmdRegWidth-1:0]	SmcData_i,
    input	[AddrRegWidth-1:0]	SmcAddr_i,

	output	reg	ToRegMapVal_o,
	output	reg	[CmdRegWidth-1:0]	ToRegMapData_o,
    output	reg	[AddrRegWidth-1:0]	ToRegMapAddr_o,
	
	output	reg	[FifoNum-1:0]	ToFifoVal_o,
	output	reg	[CmdRegWidth*2*FifoNum-1:0]	ToFifoData_o
	
);
//================================================================================
//	REG/WIRE
//================================================================================
	wire	requestToFifo0	=	(SmcAddr_i==Fifo0WriteLsbAddr||SmcAddr_i==Fifo0WriteMsbAddr);
	wire	requestToFifo1	=	(SmcAddr_i==Fifo1WriteLsbAddr||SmcAddr_i==Fifo1WriteMsbAddr);
	wire	requestToFifo2	=	(SmcAddr_i==Fifo2WriteLsbAddr||SmcAddr_i==Fifo2WriteMsbAddr);
	wire	requestToFifo3	=	(SmcAddr_i==Fifo3WriteLsbAddr||SmcAddr_i==Fifo3WriteMsbAddr);
	wire	requestToFifo4	=	(SmcAddr_i==Fifo4WriteLsbAddr||SmcAddr_i==Fifo4WriteMsbAddr);
	wire	requestToFifo5	=	(SmcAddr_i==Fifo5WriteLsbAddr||SmcAddr_i==Fifo5WriteMsbAddr);
	wire	requestToFifo6	=	(SmcAddr_i==Fifo6WriteLsbAddr||SmcAddr_i==Fifo6WriteMsbAddr);
	
	wire	requestToFifo	=	(requestToFifo0|requestToFifo1|requestToFifo2|requestToFifo3|requestToFifo4|requestToFifo5|requestToFifo6);
//================================================================================
//	ASSIGNMENTS
//================================================================================

//================================================================================
//	LOCALPARAMS
//================================================================================

//================================================================================
//	CODING
//================================================================================

always	@(posedge	Clk_i	or	posedge	Rst_i)	begin
	if	(Rst_i)	begin
		ToRegMapVal_o	<=	1'b0;
		ToRegMapData_o	<=	16'h0;
		ToRegMapAddr_o	<=	12'h0;
		
		ToFifoVal_o		<=	7'h0;
		ToFifoData_o	<=	16'h0;
	end	else	begin
		if	(requestToFifo)	begin	
			case(SmcAddr_i)	
				Fifo0WriteLsbAddr:	begin
									ToFifoVal_o[0]	<=	1'b0;
									ToFifoData_o[CmdRegWidth*0+:CmdRegWidth]	<=	SmcData_i;
								end
				Fifo0WriteMsbAddr:	begin
									ToFifoVal_o[0]	<=	SmcVal_i;
									ToFifoData_o[CmdRegWidth*1+:CmdRegWidth]	<=	SmcData_i;
								end
				Fifo1WriteLsbAddr:	begin
									ToFifoVal_o[1]	<=	1'b0;
									ToFifoData_o[CmdRegWidth*2+:CmdRegWidth]	<=	SmcData_i;
								end
				Fifo1WriteMsbAddr:	begin
									ToFifoVal_o[1]	<=	SmcVal_i;
									ToFifoData_o[CmdRegWidth*3+:CmdRegWidth]	<=	SmcData_i;
								end
				Fifo2WriteLsbAddr:	begin
									ToFifoVal_o[2]	<=	1'b0;
									ToFifoData_o[CmdRegWidth*4+:CmdRegWidth]	<=	SmcData_i;
								end
				Fifo2WriteMsbAddr:	begin
									ToFifoVal_o[2]	<=	SmcVal_i;
									ToFifoData_o[CmdRegWidth*5+:CmdRegWidth]	<=	SmcData_i;
								end
				Fifo3WriteLsbAddr:	begin
									ToFifoVal_o[3]	<=	1'b0;
									ToFifoData_o[CmdRegWidth*6+:CmdRegWidth]	<=	SmcData_i;
								end
				Fifo3WriteMsbAddr:	begin
									ToFifoVal_o[3]	<=	SmcVal_i;
									ToFifoData_o[CmdRegWidth*7+:CmdRegWidth]	<=	SmcData_i;
								end
				Fifo4WriteLsbAddr:	begin
									ToFifoVal_o[4]	<=	1'b0;
									ToFifoData_o[CmdRegWidth*8+:CmdRegWidth]	<=	SmcData_i;
								end
				Fifo4WriteMsbAddr:	begin
									ToFifoVal_o[4]	<=	SmcVal_i;
									ToFifoData_o[CmdRegWidth*9+:CmdRegWidth]	<=	SmcData_i;
								end
				Fifo5WriteLsbAddr:	begin
									ToFifoVal_o[5]	<=	1'b0;
									ToFifoData_o[CmdRegWidth*10+:CmdRegWidth]	<=	SmcData_i;
								end
				Fifo5WriteMsbAddr:	begin
									ToFifoVal_o[5]	<=	SmcVal_i;
									ToFifoData_o[CmdRegWidth*11+:CmdRegWidth]	<=	SmcData_i;
								end
				Fifo6WriteLsbAddr:	begin
									ToFifoVal_o[6]	<=	1'b0;
									ToFifoData_o[CmdRegWidth*12+:CmdRegWidth]	<=	SmcData_i;
								end
				Fifo6WriteMsbAddr:	begin
									ToFifoVal_o[6]	<=	SmcVal_i;
									ToFifoData_o[CmdRegWidth*13+:CmdRegWidth]	<=	SmcData_i;
								end
			endcase
		end	else	begin
			ToRegMapVal_o	<=	SmcVal_i;
			ToRegMapData_o	<=	SmcData_i;
			ToRegMapAddr_o	<=	SmcAddr_i;
		end
	end
end
endmodule