S5443_V3/sources_1/new/CDC/Cdc.v

module  Cdc#(
    parameter CmdRegWidth = 32,
    parameter AddrRegWidth = 12
)(
    input Clk_i,
    input [CmdRegWidth-1:0] Spi0CtrlReg_i,
    input [CmdRegWidth-1:0] Spi0ClkReg_i,
    input [CmdRegWidth-1:0] Spi0CsDelayReg_i,
    input [CmdRegWidth-1:0] Spi0CsCtrlReg_i,
    input [CmdRegWidth-1:0] Spi0TxFifoCtrlReg_i,
    input [CmdRegWidth-1:0] Spi0RxFifoCtrlReg_i,
    input [CmdRegWidth-1:0] AnsData_i,


    output reg [CmdRegWidth-1:0] Spi0CtrlRR_o,
    output reg [CmdRegWidth-1:0] Spi0ClkRR_o,
    output reg [CmdRegWidth-1:0] Spi0CsDelayRR_o,
    output reg [CmdRegWidth-1:0] Spi0CsCtrlRR_o,
    output reg [CmdRegWidth-1:0] Spi0TxFifoCtrlRR_o,
    output reg [CmdRegWidth-1:0] Spi0RxFifoCtrlRR_o,
    output reg [CmdRegWidth-1:0] AnsDataRR_o

);


reg [CmdRegWidth-1:0] Spi0CtrlR;
reg [CmdRegWidth-1:0] Spi0ClkRegR;
reg [CmdRegWidth-1:0] Spi0CsDelayR;
reg [CmdRegWidth-1:0] Spi0CsCtrlR;
reg [CmdRegWidth-1:0] Spi0TxFifoCtrlR;
reg [CmdRegWidth-1:0] Spi0RxFifoCtrlR;
reg [CmdRegWidth-1:0] ansDataR;

reg [CmdRegWidth-1:0] Spi0CtrlRR;
reg [CmdRegWidth-1:0] Spi0ClkRegRR;
reg [CmdRegWidth-1:0] Spi0CsDelayRR;
reg [CmdRegWidth-1:0] Spi0CsCtrlRR;
reg [CmdRegWidth-1:0] Spi0TxFifoCtrlRR;
reg [CmdRegWidth-1:0] Spi0RxFifoCtrlRR;
reg [CmdRegWidth-1:0] ansDataRR;








always @(posedge Clk_i) begin
    Spi0CtrlR <= Spi0CtrlReg_i;
    Spi0ClkRegR <= Spi0ClkReg_i;
    Spi0CsDelayR <= Spi0CsDelayReg_i;
    Spi0CsCtrlR  <= Spi0CsCtrlReg_i;
    Spi0TxFifoCtrlR <= Spi0TxFifoCtrlReg_i;
    Spi0RxFifoCtrlR <= Spi0RxFifoCtrlReg_i;
    ansDataR <= AnsData_i;
    Spi0CtrlRR_o <= Spi0CtrlR;
    Spi0ClkRR_o <= Spi0ClkRegR;
    Spi0CsDelayRR_o <= Spi0CsDelayR;
    Spi0CsCtrlRR_o <= Spi0CsCtrlR;
    Spi0TxFifoCtrlRR_o <= Spi0TxFifoCtrlR;
    Spi0RxFifoCtrlRR_o <= Spi0RxFifoCtrlR;
    AnsDataRR_o <= ansDataR;
end











endmodule