S5443_V3/sources_1/new/Mux/DataMuxer.v

module DataMuxer 
#(
    parameter	CmdRegWidth	=	16,
    parameter	AddrRegWidth=	12,
	
	parameter	FifoNum	=	7,
	
	// parameter	Fifo0WriteLsbAddr	=	12'h0+12'h24,
	// parameter	Fifo0WriteMsbAddr	=	12'h0+12'h26,
	// parameter	Fifo1WriteLsbAddr	=	12'h50+12'h24,
	// parameter	Fifo2WriteMsbAddr	=	12'hF0+12'h26,
	// parameter	Fifo3WriteLsbAddr	=	12'h140+12'h24,
	// parameter	Fifo4WriteMsbAddr	=	12'h190+12'h26,
	// parameter	Fifo5WriteLsbAddr	=	12'h1e0+12'h24,
	// parameter	Fifo6WriteMsbAddr	=	12'h230+12'h26
	
	parameter	Fifo0WriteLsbAddr	=	12'h0+12'd24,
	parameter	Fifo0WriteMsbAddr	=	12'h0+12'd26,
	parameter	Fifo1WriteLsbAddr	=	12'h50+12'd24,
	parameter	Fifo1WriteMsbAddr	=	12'h50+12'd26,
	parameter	Fifo2WriteLsbAddr	=	12'hf0+12'd24,
	parameter	Fifo2WriteMsbAddr	=	12'hf0+12'd26,
	parameter	Fifo3WriteLsbAddr	=	12'h140+12'd24,
	parameter	Fifo3WriteMsbAddr	=	12'h140+12'd26,
	parameter	Fifo4WriteLsbAddr	=	12'h190+12'd24,
	parameter	Fifo4WriteMsbAddr	=	12'h190+12'd26,
	parameter	Fifo5WriteLsbAddr	=	12'h1e0+12'd24,
	parameter	Fifo5WriteMsbAddr	=	12'h1e0+12'd26,
	parameter	Fifo6WriteLsbAddr	=	12'h230+12'd24,
	parameter	Fifo6WriteMsbAddr	=	12'h230+12'd26,

	parameter Fifo0ReadLsbAddr		= 12'h0+12'd28,
	parameter Fifo0ReadMsbAddr		= 12'h0+12'd30,
	parameter Fifo1ReadLsbAddr		= 12'h50+12'd28,
	parameter Fifo1ReadMsbAddr		= 12'h50+12'd30,
	parameter Fifo2ReadLsbAddr		= 12'hf0+12'd28,
	parameter Fifo2ReadMsbAddr		= 12'hf0+12'd30,
	parameter Fifo3ReadLsbAddr		= 12'h140+12'd28,
	parameter Fifo3ReadMsbAddr		= 12'h140+12'd30,
	parameter Fifo4ReadLsbAddr		= 12'h190+12'd28,
	parameter Fifo4ReadMsbAddr		= 12'h190+12'd30,
	parameter Fifo5ReadLsbAddr		= 12'h1e0+12'd28,
	parameter Fifo5ReadMsbAddr		= 12'h1e0+12'd30,
	parameter Fifo6ReadLsbAddr		= 12'h230+12'd28,
	parameter Fifo6ReadMsbAddr		= 12'h230+12'd30


)
(
    input	Clk_i,
    input	Rst_i,

	input	SmcVal_i,
	input	[CmdRegWidth-1:0]	SmcData_i,
    input	[AddrRegWidth-1:0]	SmcAddr_i,

	output	RequestToFifo_o,

	output	reg	ToRegMapVal_o,
	output	reg	[CmdRegWidth-1:0]	ToRegMapData_o,
    output	reg	[AddrRegWidth-1:0]	ToRegMapAddr_o,
	
	output	reg	[FifoNum-1:0]	ToFifoVal_o,
	output	reg	[CmdRegWidth*2*FifoNum-1:0]	ToFifoData_o
	
);
//================================================================================
//	REG/WIRE
//================================================================================
	wire	requestToFifo0	=((SmcAddr_i==Fifo0WriteLsbAddr||SmcAddr_i==Fifo0WriteMsbAddr)|| (SmcAddr_i==Fifo0ReadLsbAddr||SmcAddr_i==Fifo0ReadMsbAddr));
	wire	requestToFifo1	=((SmcAddr_i==Fifo1WriteLsbAddr||SmcAddr_i==Fifo1WriteMsbAddr)|| (SmcAddr_i==Fifo1ReadLsbAddr||SmcAddr_i==Fifo1ReadMsbAddr));
	wire	requestToFifo2	=((SmcAddr_i==Fifo2WriteLsbAddr||SmcAddr_i==Fifo2WriteMsbAddr)|| (SmcAddr_i==Fifo2ReadLsbAddr||SmcAddr_i==Fifo2ReadMsbAddr));
	wire	requestToFifo3	=((SmcAddr_i==Fifo3WriteLsbAddr||SmcAddr_i==Fifo3WriteMsbAddr)|| (SmcAddr_i==Fifo3ReadLsbAddr||SmcAddr_i==Fifo3ReadMsbAddr));
	wire	requestToFifo4	=((SmcAddr_i==Fifo4WriteLsbAddr||SmcAddr_i==Fifo4WriteMsbAddr)|| (SmcAddr_i==Fifo4ReadLsbAddr||SmcAddr_i==Fifo4ReadMsbAddr));
	wire	requestToFifo5	=((SmcAddr_i==Fifo5WriteLsbAddr||SmcAddr_i==Fifo5WriteMsbAddr)|| (SmcAddr_i==Fifo5ReadLsbAddr||SmcAddr_i==Fifo5ReadMsbAddr));
	wire	requestToFifo6	=((SmcAddr_i==Fifo6WriteLsbAddr||SmcAddr_i==Fifo6WriteMsbAddr)|| (SmcAddr_i==Fifo6ReadLsbAddr||SmcAddr_i==Fifo6ReadMsbAddr));
	
	wire	requestToFifo	=	(requestToFifo0|requestToFifo1|requestToFifo2|requestToFifo3|requestToFifo4|requestToFifo5|requestToFifo6);
//================================================================================
//	ASSIGNMENTS
//================================================================================
	assign	RequestToFifo_o	=	requestToFifo;
//================================================================================
//	LOCALPARAMS
//================================================================================

//================================================================================
//	CODING
//================================================================================

	always	@(posedge	Clk_i	or	posedge	Rst_i)	begin
		if	(Rst_i)	begin
			ToRegMapVal_o	<=	1'b0;
			ToRegMapData_o	<=	16'h0;
			ToRegMapAddr_o	<=	12'h0;
			
			ToFifoVal_o		<=	7'h0;
			ToFifoData_o	<=	0;
		end	else	begin
			if	(requestToFifo)	begin	
				case(SmcAddr_i)	
					Fifo0WriteLsbAddr:	begin
										ToFifoVal_o[0]	<=	1'b0;
										ToFifoData_o[CmdRegWidth*0+:CmdRegWidth]	<=	SmcData_i;
									end
					Fifo0WriteMsbAddr:	begin
										ToFifoVal_o[0]	<=	SmcVal_i;
										ToFifoData_o[CmdRegWidth*1+:CmdRegWidth]	<=	SmcData_i;
									end
									
					Fifo1WriteLsbAddr:	begin
										ToFifoVal_o[1]	<=	1'b0;
										ToFifoData_o[CmdRegWidth*2+:CmdRegWidth]	<=	SmcData_i;
									end
					Fifo1WriteMsbAddr:	begin
										ToFifoVal_o[1]	<=	SmcVal_i;
										ToFifoData_o[CmdRegWidth*3+:CmdRegWidth]	<=	SmcData_i;
									end
									
					Fifo2WriteLsbAddr:	begin
										ToFifoVal_o[2]	<=	1'b0;
										ToFifoData_o[CmdRegWidth*4+:CmdRegWidth]	<=	SmcData_i;
									end
					Fifo2WriteMsbAddr:	begin
										ToFifoVal_o[2]	<=	SmcVal_i;
										ToFifoData_o[CmdRegWidth*5+:CmdRegWidth]	<=	SmcData_i;
									end
									
					Fifo3WriteLsbAddr:	begin
										ToFifoVal_o[3]	<=	1'b0;
										ToFifoData_o[CmdRegWidth*6+:CmdRegWidth]	<=	SmcData_i;
									end
					Fifo3WriteMsbAddr:	begin
										ToFifoVal_o[3]	<=	SmcVal_i;
										ToFifoData_o[CmdRegWidth*7+:CmdRegWidth]	<=	SmcData_i;
									end
									
					Fifo4WriteLsbAddr:	begin
										ToFifoVal_o[4]	<=	1'b0;
										ToFifoData_o[CmdRegWidth*8+:CmdRegWidth]	<=	SmcData_i;
									end
					Fifo4WriteMsbAddr:	begin
										ToFifoVal_o[4]	<=	SmcVal_i;
										ToFifoData_o[CmdRegWidth*9+:CmdRegWidth]	<=	SmcData_i;
									end
									
					Fifo5WriteLsbAddr:	begin
										ToFifoVal_o[5]	<=	1'b0;
										ToFifoData_o[CmdRegWidth*10+:CmdRegWidth]	<=	SmcData_i;
									end
					Fifo5WriteMsbAddr:	begin
										ToFifoVal_o[5]	<=	SmcVal_i;
										ToFifoData_o[CmdRegWidth*11+:CmdRegWidth]	<=	SmcData_i;
									end
									
					Fifo6WriteLsbAddr:	begin
										ToFifoVal_o[6]	<=	1'b0;
										ToFifoData_o[CmdRegWidth*12+:CmdRegWidth]	<=	SmcData_i;
									end
					Fifo6WriteMsbAddr:	begin
										ToFifoVal_o[6]	<=	SmcVal_i;
										ToFifoData_o[CmdRegWidth*13+:CmdRegWidth]	<=	SmcData_i;
									end
				endcase
				ToRegMapAddr_o	<=	0;
			end	else	begin
				ToRegMapVal_o	<=	SmcVal_i;
				ToFifoVal_o		<=	7'h0;
				ToRegMapData_o	<=	SmcData_i;
				ToRegMapAddr_o	<=	SmcAddr_i;
				ToFifoData_o	<=	0;
			end
		end
	end
	endmodule