S5443_V3/sources_1/new/S5443_3Top.v

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 10/30/2023 11:24:31 AM
// Design Name: 
// Module Name: S5443_3Top
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module S5443_3Top #(
    parameter CmdRegWidth = 32,
    parameter AddrRegWidth = 12,
    parameter SpiNum = 7

)(
    input Clk123_i,
    input [AddrRegWidth-2:0] Addr_i,
    inout [CmdRegWidth/2-1:0] Data_i,
    
    input writeEn_i,
    input readEn_i,
    input [1:0] BE_i,
    input outputEn_i,
    output [SpiNum-1:0] LD_i,

    output  Led_o,
   
    output  [SpiNum-1:0] Mosi0_o,
    output  [SpiNum-1:0] Mosi1_o,
    output  [SpiNum-1:0] Mosi2_o,
    output  [SpiNum-1:0] Mosi3_o,
    output  [SpiNum-1:0] Ss_o,
    output  [SpiNum-1:0] SsFlash_o,
    output  [SpiNum-1:0] Sck_o,
    output  [SpiNum-1:0] SpiRst_o,
    output  LD_o

);

//================================================================================
//  REG/WIRE
//================================================================================
wire Clk100_i;
wire [SpiNum-1:0]Sck;
wire [SpiNum-1:0] Ss; 
wire [SpiNum-1:0]Mosi0;
wire [SpiNum-1:0]Mosi1;
wire [SpiNum-1:0]Mosi2;
wire [SpiNum-1:0]Mosi3;
wire [SpiNum-1:0] ten;
wire clk80;
wire clk61;
wire initRst;
wire gclk;
wire [0:15] baudRate [SpiNum-1:0];


//SPI0
wire [CmdRegWidth-1:0] Spi0Ctrl;
wire [CmdRegWidth-1:0] Spi0Clk;
wire [CmdRegWidth-1:0] Spi0CsDelay;
wire [CmdRegWidth-1:0] Spi0CsCtrl;
wire [CmdRegWidth-1:0] Spi0TxFifoCtrl;
wire [CmdRegWidth-1:0] Spi0RxFifoCtrl;
wire [CmdRegWidth-1:0] Spi0TxFifo;
wire [CmdRegWidth-1:0] Spi0RxFifo;
//SPI1
wire [CmdRegWidth-1:0] Spi1Ctrl;
wire [CmdRegWidth-1:0] Spi1Clk;
wire [CmdRegWidth-1:0] Spi1CsDelay;
wire [CmdRegWidth-1:0] Spi1CsCtrl;
wire [CmdRegWidth-1:0] Spi1TxFifoCtrl;
wire [CmdRegWidth-1:0] Spi1RxFifoCtrl;
wire [CmdRegWidth-1:0] Spi1TxFifo;
wire [CmdRegWidth-1:0] Spi1RxFifo;
//SPI2
wire [CmdRegWidth-1:0] Spi2Ctrl;
wire [CmdRegWidth-1:0] Spi2Clk;
wire [CmdRegWidth-1:0] Spi2CsDelay;
wire [CmdRegWidth-1:0] Spi2CsCtrl;
wire [CmdRegWidth-1:0] Spi2TxFifoCtrl;
wire [CmdRegWidth-1:0] Spi2RxFifoCtrl;
wire [CmdRegWidth-1:0] Spi2TxFifo;
wire [CmdRegWidth-1:0] Spi2RxFifo;
//SPI3
wire [CmdRegWidth-1:0] Spi3Ctrl;
wire [CmdRegWidth-1:0] Spi3Clk;
wire [CmdRegWidth-1:0] Spi3CsDelay;
wire [CmdRegWidth-1:0] Spi3CsCtrl;
wire [CmdRegWidth-1:0] Spi3TxFifoCtrl;
wire [CmdRegWidth-1:0] Spi3RxFifoCtrl;
wire [CmdRegWidth-1:0] Spi3TxFifo;
wire [CmdRegWidth-1:0] Spi3RxFifo;
//SPI4
wire [CmdRegWidth-1:0] Spi4Ctrl;
wire [CmdRegWidth-1:0] Spi4Clk;
wire [CmdRegWidth-1:0] Spi4CsDelay;
wire [CmdRegWidth-1:0] Spi4CsCtrl;
wire [CmdRegWidth-1:0] Spi4TxFifoCtrl;
wire [CmdRegWidth-1:0] Spi4RxFifoCtrl;
wire [CmdRegWidth-1:0] Spi4TxFifo;
wire [CmdRegWidth-1:0] Spi4RxFifo;
//SPI5
wire [CmdRegWidth-1:0] Spi5Ctrl;
wire [CmdRegWidth-1:0] Spi5Clk;
wire [CmdRegWidth-1:0] Spi5CsDelay;
wire [CmdRegWidth-1:0] Spi5CsCtrl;
wire [CmdRegWidth-1:0] Spi5TxFifoCtrl;
wire [CmdRegWidth-1:0] Spi5RxFifoCtrl;
wire [CmdRegWidth-1:0] Spi5TxFifo;
wire [CmdRegWidth-1:0] Spi5RxFifo;
//SPI6
wire [CmdRegWidth-1:0] Spi6Ctrl;
wire [CmdRegWidth-1:0] Spi6Clk;
wire [CmdRegWidth-1:0] Spi6CsDelay;
wire [CmdRegWidth-1:0] Spi6CsCtrl;
wire [CmdRegWidth-1:0] Spi6TxFifoCtrl;
wire [CmdRegWidth-1:0] Spi6RxFifoCtrl;
wire [CmdRegWidth-1:0] Spi6TxFifo;
wire [CmdRegWidth-1:0] Spi6RxFifo;

wire [CmdRegWidth-1:0] SpiTxRxEn;
wire [CmdRegWidth-1:0] GPIOA;


wire	[AddrRegWidth-1:0]	toRegMapAddr;
wire	[CmdRegWidth-1:0]	toRegMapData;
wire	toRegMapVal;

wire	[SpiNum-1:0]	toFifoVal;
wire	[CmdRegWidth*SpiNum-1:0]	toFifoData;

wire	[SpiNum-1:0]	toSpiVal;
wire	[CmdRegWidth-1:0]	toSpiData;

wire [0:1] widthSel [SpiNum-1:0];
wire [SpiNum-1:0] CPOL;
wire [SpiNum-1:0] CPHA;
wire [SpiNum-1:0] endianSel;
wire [SpiNum-1:0] selSt;

wire [0:5] stopDelay [SpiNum-1:0];
wire [SpiNum-1:0] leadx;
wire [SpiNum-1:0] lagx; 
wire [SpiNum-1:0] FifoRxRst;
wire [SpiNum-1:0] FifoTxRst;
wire [0:7]  WordCntTx [SpiNum-1:0];
wire [0:7]  WordCntRx [SpiNum-1:0];

wire [SpiNum-1:0] CS0;
wire [SpiNum-1:0] CS1;

wire [SpiNum-1:0] Assel;



//================================================================================
//  ASSIGNMENTS
//================================================================================
assign addr = {Addr_i, 1'b0};
assign Data_i = (!outputEn_i) ? data : 16'bz;
assign ten = SpiTxRxEn[6:0];
assign Mosi0_o = Mosi0;
assign Mosi1_o = Mosi1;
assign Mosi2_o = Mosi2;
assign Mosi3_o = Mosi3;
assign Ss_o[0] = (Assel[0])? ((CS0[0])? Ss[0]:~Ss[0]):CS0[0];
assign Ss_o[1] = (Assel[1])? ((CS0[1])? Ss[1]:~Ss[1]):CS0[1];
assign Ss_o[2] = (Assel[2])? ((CS0[2])? Ss[2]:~Ss[2]):CS0[2];
assign Ss_o[3] = (Assel[3])? ((CS0[3])? Ss[3]:~Ss[3]):CS0[3];
assign Ss_o[4] = (Assel[4])? ((CS0[4])? Ss[4]:~Ss[4]):CS0[4];
assign Ss_o[5] = (Assel[5])? ((CS0[5])? Ss[5]:~Ss[5]):CS0[5];
assign Ss_o[6] = (Assel[6])? ((CS0[6])? Ss[6]:~Ss[6]):CS0[6];
assign SsFlash_o[0] = (Assel[0])?(CS1[0]? Ss[0]:~Ss[0]):CS1[0];
assign SsFlash_o[1] = (Assel[1])?(CS1[1]? Ss[1]:~Ss[1]):CS1[1];
assign SsFlash_o[2] = (Assel[2])?(CS1[2]? Ss[2]:~Ss[2]):CS1[2];
assign SsFlash_o[3] = (Assel[3])?(CS1[3]? Ss[3]:~Ss[3]):CS1[3];
assign SsFlash_o[4] = (Assel[4])?(CS1[4]? Ss[4]:~Ss[4]):CS1[4];
assign SsFlash_o[5] = (Assel[5])?(CS1[5]? Ss[5]:~Ss[5]):CS1[5];
assign SsFlash_o[6] = (Assel[6])?(CS1[6]? Ss[6]:~Ss[6]):CS1[6];
assign Sck_o = Sck;

assign widthSel[0] = Spi0Ctrl[6:5];
assign widthSel[1] = Spi1Ctrl[6:5];
assign widthSel[2] = Spi2Ctrl[6:5];
assign widthSel[3] = Spi3Ctrl[6:5];
assign widthSel[4] = Spi4Ctrl[6:5];
assign widthSel[5] = Spi5Ctrl[6:5];
assign widthSel[6] = Spi6Ctrl[6:5];

assign CPOL[0] = Spi0Ctrl[2];
assign CPOL[1] = Spi1Ctrl[2];
assign CPOL[2] = Spi2Ctrl[2];
assign CPOL[3] = Spi3Ctrl[2];
assign CPOL[4] = Spi4Ctrl[2];
assign CPOL[5] = Spi5Ctrl[2];
assign CPOL[6] = Spi6Ctrl[2];

assign CPHA[0] = Spi0Ctrl[1];
assign CPHA[1] = Spi1Ctrl[1];
assign CPHA[2] = Spi2Ctrl[1];
assign CPHA[3] = Spi3Ctrl[1];
assign CPHA[4] = Spi4Ctrl[1];
assign CPHA[5] = Spi5Ctrl[1];
assign CPHA[6] = Spi6Ctrl[1];

assign endianSel[0] = Spi0Ctrl[8];
assign endianSel[1] = Spi1Ctrl[8];
assign endianSel[2] = Spi2Ctrl[8];
assign endianSel[3] = Spi3Ctrl[8];
assign endianSel[4] = Spi4Ctrl[8];
assign endianSel[5] = Spi5Ctrl[8];
assign endianSel[6] = Spi6Ctrl[8];

assign selSt[0] = Spi0Ctrl[4];
assign selSt[1] = Spi1Ctrl[4];
assign selSt[2] = Spi2Ctrl[4];
assign selSt[3] = Spi3Ctrl[4];
assign selSt[4] = Spi4Ctrl[4];
assign selSt[5] = Spi5Ctrl[4];
assign selSt[6] = Spi6Ctrl[4];

assign Assel[0] = Spi0Ctrl[3];
assign Assel[1] = Spi1Ctrl[3];
assign Assel[2] = Spi2Ctrl[3];
assign Assel[3] = Spi3Ctrl[3];
assign Assel[4] = Spi4Ctrl[3];
assign Assel[5] = Spi5Ctrl[3];
assign Assel[6] = Spi6Ctrl[3];


assign stopDelay[0] = Spi0CsDelay[7:2];
assign stopDelay[1] = Spi1CsDelay[7:2];
assign stopDelay[2] = Spi2CsDelay[7:2];
assign stopDelay[3] = Spi3CsDelay[7:2];
assign stopDelay[4] = Spi4CsDelay[7:2];
assign stopDelay[5] = Spi5CsDelay[7:2];
assign stopDelay[6] = Spi6CsDelay[7:2];

assign leadx[0] = Spi0CsDelay[1];
assign leadx[1] = Spi1CsDelay[1];
assign leadx[2] = Spi2CsDelay[1];
assign leadx[3] = Spi3CsDelay[1];
assign leadx[4] = Spi4CsDelay[1];
assign leadx[5] = Spi5CsDelay[1];
assign leadx[6] = Spi6CsDelay[1];

assign lagx[0] = Spi0CsDelay[0];
assign lagx[1] = Spi1CsDelay[0];
assign lagx[2] = Spi2CsDelay[0];
assign lagx[3] = Spi3CsDelay[0];
assign lagx[4] = Spi4CsDelay[0];
assign lagx[5] = Spi5CsDelay[0];
assign lagx[6] = Spi6CsDelay[0];

assign baudRate[0] = Spi0Clk[15:0];
assign baudRate[1] = Spi1Clk[15:0];
assign baudRate[2] = Spi2Clk[15:0];
assign baudRate[3] = Spi3Clk[15:0];
assign baudRate[4] = Spi4Clk[15:0];
assign baudRate[5] = Spi5Clk[15:0];
assign baudRate[6] = Spi6Clk[15:0];


assign SpiRst_o[0] = GPIOA[0];
assign SpiRst_o[1] = GPIOA[1];
assign SpiRst_o[2] = GPIOA[2];
assign SpiRst_o[3] = GPIOA[3];
assign SpiRst_o[4] = GPIOA[4];
assign SpiRst_o[5] = GPIOA[5];
assign SpiRst_o[6] = GPIOA[6];

assign FifoRxRst[0] = Spi0RxFifoCtrl[0];
assign FifoRxRst[1] = Spi1RxFifoCtrl[0];
assign FifoRxRst[2] = Spi2RxFifoCtrl[0];
assign FifoRxRst[3] = Spi3RxFifoCtrl[0];
assign FifoRxRst[4] = Spi4RxFifoCtrl[0];
assign FifoRxRst[5] = Spi5RxFifoCtrl[0];
assign FifoRxRst[6] = Spi6RxFifoCtrl[0];

assign FifoTxRst[0] = Spi0TxFifoCtrl[0];
assign FifoTxRst[1] = Spi1TxFifoCtrl[0];
assign FifoTxRst[2] = Spi2TxFifoCtrl[0];
assign FifoTxRst[3] = Spi3TxFifoCtrl[0];
assign FifoTxRst[4] = Spi4TxFifoCtrl[0];
assign FifoTxRst[5] = Spi5TxFifoCtrl[0];
assign FifoTxRst[6] = Spi6TxFifoCtrl[0];

assign LD_i[0] = GPIOA[16];
assign LD_i[1] = GPIOA[17];
assign LD_i[2] = GPIOA[18];
assign LD_i[3] = GPIOA[19];
assign LD_i[4] = GPIOA[20];
assign LD_i[5] = GPIOA[21];
assign LD_i[6] = GPIOA[22];
assign LD_o = LD_i[0]&LD_i[1]&LD_i[2]&LD_i[3]&LD_i[4]&LD_i[5]&LD_i[6];

assign WordCntRx[0] = Spi0RxFifoCtrl[15:8];
assign WordCntRx[1] = Spi1RxFifoCtrl[15:8];
assign WordCntRx[2] = Spi2RxFifoCtrl[15:8];
assign WordCntRx[3] = Spi3RxFifoCtrl[15:8];
assign WordCntRx[4] = Spi4RxFifoCtrl[15:8];
assign WordCntRx[5] = Spi5RxFifoCtrl[15:8];
assign WordCntRx[6] = Spi6RxFifoCtrl[15:8];

assign WordCntTx[0] = Spi0TxFifoCtrl[15:8];
assign WordCntTx[1] = Spi1TxFifoCtrl[15:8];
assign WordCntTx[2] = Spi2TxFifoCtrl[15:8];
assign WordCntTx[3] = Spi3TxFifoCtrl[15:8];
assign WordCntTx[4] = Spi4TxFifoCtrl[15:8];
assign WordCntTx[5] = Spi5TxFifoCtrl[15:8];
assign WordCntTx[6] = Spi6TxFifoCtrl[15:8];

assign CS0[0] = Spi0CsCtrl[0];
assign CS0[1] = Spi1CsCtrl[0];
assign CS0[2] = Spi2CsCtrl[0];
assign CS0[3] = Spi3CsCtrl[0];
assign CS0[4] = Spi4CsCtrl[0];
assign CS0[5] = Spi5CsCtrl[0];
assign CS0[6] = Spi6CsCtrl[0];

assign CS1[0] = Spi0CsCtrl[1];
assign CS1[1] = Spi1CsCtrl[1];
assign CS1[2] = Spi2CsCtrl[1];
assign CS1[3] = Spi3CsCtrl[1];
assign CS1[4] = Spi4CsCtrl[1];
assign CS1[5] = Spi5CsCtrl[1];
assign CS1[6] = Spi6CsCtrl[1];





//================================================================================
//  CODING
//================================================================================	

BUFG BUFG_inst (
   .O(gclk), // 1-bit output: Clock output
   .I(Clk123_i)  // 1-bit input: Clock input
);


 clk_wiz_0 ClkGen
   (
   .s_axi_aclk      (),        // input s_axi_aclk                        
   .s_axi_aresetn   (),     // input s_axi_aresetn,                                                          
   .s_axi_awaddr    (),      // input [10 : 0] s_axi_awaddr,                              
   .s_axi_awvalid   (),     // input s_axi_awvalid,                                                          
   .s_axi_awready   (),     // output s_axi_awready,                                                         
   .s_axi_wdata     (),       // input [31 : 0] s_axi_wdata,                             
   .s_axi_wstrb     (),       // input [3 : 0] s_axi_wstrb,                         
   .s_axi_wvalid    (),      // input s_axi_wvalid,                                                         
   .s_axi_wready    (),      // output s_axi_wready,                                                        
   .s_axi_bresp     (),       // output [1 : 0] s_axi_bresp,                                               
   .s_axi_bvalid    (),      // output s_axi_bvalid,                                                        
   .s_axi_bready    (),      // input s_axi_bready,                                                         
   .s_axi_araddr    (),      // input [10 : 0] s_axi_araddr,                              
   .s_axi_arvalid   (),     // input s_axi_arvalid,                                                          
   .s_axi_arready   (),     // output s_axi_arready,                                                         
   .s_axi_rdata     (),       // output [31 : 0] s_axi_rdata,                            
   .s_axi_rresp     (),       // output [1 : 0] s_axi_rresp,                                               
   .s_axi_rvalid    (),      // output s_axi_rvalid,                                                        
   .s_axi_rready    (),      // input s_axi_rready,                                                         
    // Clock out ports
    .clk_out1(Clk100_i),     // output clk_out1
    // .clk_out2(clk61),     // output clk_out2
    // Status and control signals
    .locked(),       // output locked
   // Clock in ports
    .clk_in1(gclk));      // input clk_in1

SmcDataMux SmcDataMuxer
(
    .Clk_i	(gclk),
    .Rst_i	(initRst),

	.SmcVal_i	(1'b1),
	.SmcData_i	({Data_i,Data_i}),
    .SmcAddr_i	({Addr_i,1'b0}),

	.ToRegMapVal_o	(toRegMapVal),
	.ToRegMapData_o	(toRegMapData),
    .ToRegMapAddr_o	(toRegMapAddr),
	
	.ToFifoVal_o	(toFifoVal),
	.ToFifoData_o	(toFifoData)
	
);


RegMap #(
    .CmdRegWidth(32),
    .AddrRegWidth(12)
)
RegMap_inst (
    .Clk_i(gclk),
    .Rst_i(initRst),
    .Data_i(toRegMapData),
    .Addr_i(toRegMapAddr),
    .wrEn_i(writeEn_i|toRegMapVal),
    .rdEn_i(readEn_i),
    .BE_i(BE_i),
    .Led_o(Led_o),
    .AnsDataReg_o(data),
    //Spi0
    .Spi0CtrlReg_o(Spi0Ctrl),
    .Spi0ClkReg_o(Spi0Clk),
    .Spi0CsDelayReg_o(Spi0CsDelay),
    .Spi0CsCtrlReg_o(Spi0CsCtrl),
    .Spi0TxFifoCtrlReg_o(Spi0TxFifoCtrl),
    .Spi0RxFifoCtrlReg_o(Spi0RxFifoCtrl),
    .Spi0TxFifoReg_o(Spi0TxFifo),
    .Spi0RxFifoReg_o(Spi0RxFifo),
    //Spi1
    .Spi1CtrlReg_o(Spi1Ctrl),
    .Spi1ClkReg_o(Spi1Clk),
    .Spi1CsDelayReg_o(Spi1CsDelay),
    .Spi1CsCtrlReg_o(Spi1CsCtrl),
    .Spi1TxFifoCtrlReg_o(Spi1TxFifoCtrl),
    .Spi1RxFifoCtrlReg_o(Spi1RxFifoCtrl),
    .Spi1TxFifoReg_o(Spi1TxFifo),
    .Spi1RxFifoReg_o(Spi1RxFifo),
    //Spi2
    .Spi2CtrlReg_o(Spi2Ctrl),
    .Spi2ClkReg_o(Spi2Clk),
    .Spi2CsDelayReg_o(Spi2CsDelay),
    .Spi2CsCtrlReg_o(Spi2CsCtrl),
    .Spi2TxFifoCtrlReg_o(Spi2TxFifoCtrl),
    .Spi2RxFifoCtrlReg_o(Spi2RxFifoCtrl),
    .Spi2TxFifoReg_o(Spi2TxFifo),
    .Spi2RxFifoReg_o(Spi2RxFifo),
    //Spi3
    .Spi3CtrlReg_o(Spi3Ctrl),
    .Spi3ClkReg_o(Spi3Clk),
    .Spi3CsDelayReg_o(Spi3CsDelay),
    .Spi3CsCtrlReg_o(Spi3CsCtrl),
    .Spi3TxFifoCtrlReg_o(Spi3TxFifoCtrl),
    .Spi3RxFifoCtrlReg_o(Spi3RxFifoCtrl),
    .Spi3TxFifoReg_o(Spi3TxFifo),
    .Spi3RxFifoReg_o(Spi3RxFifo),
    //Spi4
    .Spi4CtrlReg_o(Spi4Ctrl),
    .Spi4ClkReg_o(Spi4Clk),
    .Spi4CsDelayReg_o(Spi4CsDelay),
    .Spi4CsCtrlReg_o(Spi4CsCtrl),
    .Spi4TxFifoCtrlReg_o(Spi4TxFifoCtrl),
    .Spi4RxFifoCtrlReg_o(Spi4RxFifoCtrl),
    .Spi4TxFifoReg_o(Spi4TxFifo),
    .Spi4RxFifoReg_o(Spi4RxFifo),
    //Spi5
    .Spi5CtrlReg_o(Spi5Ctrl),
    .Spi5ClkReg_o(Spi5Clk),
    .Spi5CsDelayReg_o(Spi5CsDelay),
    .Spi5CsCtrlReg_o(Spi5CsCtrl),
    .Spi5TxFifoCtrlReg_o(Spi5TxFifoCtrl),
    .Spi5RxFifoCtrlReg_o(Spi5RxFifoCtrl),
    .Spi5TxFifoReg_o(Spi5TxFifo),
    .Spi5RxFifoReg_o(Spi5RxFifo),
    //Spi6
    .Spi6CtrlReg_o(Spi6Ctrl),
    .Spi6ClkReg_o(Spi6Clk),
    .Spi6CsDelayReg_o(Spi6CsDelay),
    .Spi6CsCtrlReg_o(Spi6CsCtrl),
    .Spi6TxFifoCtrlReg_o(Spi6TxFifoCtrl),
    .Spi6RxFifoCtrlReg_o(Spi6RxFifoCtrl),
    .Spi6TxFifoReg_o(Spi6TxFifo),
    .Spi6RxFifoReg_o(Spi6RxFifo),

    .SpiTxRxEnReg_o(SpiTxRxEn),
    .GPIOAReg_o(GPIOA)

);




genvar i;

generate
    for  (i = 0; i < SpiNum; i = i + 1) begin: SpiGen
	
		DataFifoWrapper DataFifoWrapepr
		(
			.WrClk_i	(gclk),
			.RdClk_i	(Clk100_i),
			.Rst_i		(initRst | FifoRxRst[i]),
            .readEn_i   (readEn_i),
	
			.ToFifoVal_i	(toFifoVal[i]),
			.ToFifoData_i	(toFifoData[32*i+:32]),
			
			.ToSpiVal_o		(toSpiVal[i]),
			.ToSpiData_o	(toSpiData[i])
		);
	
        QuadSPIm QuadSPIm_inst (
            .Clk_i(Clk100_i),
            .Start_i(ten[i]),
            .Rst_i(initRst),
			.SpiDataVal_i	(toSpiVal),
            // .SPIdata(32'h2aaa00aa),
            .SPIdata(toSpiData[i]),
            .Sck_o(Sck[i]),
            .Ss_o(Ss[i]),
            .Mosi0_i(Mosi0[i]),
            .Mosi1_i(Mosi1[i]),
            .Mosi2_i(Mosi2[i]),
            .Mosi3_i(Mosi3[i]),
            .WidthSel_i(widthSel[i]),
            .PulsePol_i(CPOL[i]),
            .CPHA_i(CPHA[i]),
            .EndianSel_i(endianSel[i]),
            .LAG_i(lagx[i]),
            .LEAD_i(leadx[i]),
            .Stop_i(stopDelay[i]),
            .SELST_i(selSt[i])
        );
    end
endgenerate


InitRst InitRst_inst (
    .clk_i(gclk),
    .signal_o(initRst)

);


endmodule