S5443_V3/SRAM/QuadSPIm.v

module QuadSPIm(
    input Clk_i,
    input Rst_i,
    input [27:0] Data_i,
    input Start_i,






    output Mosi0_i,
    output Mosi1_i,
    output Mosi2_i,
    output Mosi3_i,
    output Sck_o,
    output Ss_o

);
//================================================================================
//  REG/WIRE
//================================================================================
reg startFlag;
reg [2:0] ssCnt;
reg Ss;
reg SSr;
reg [6:0] mosiReg0;
reg [6:0] mosiReg1;
reg [6:0] mosiReg2;
reg [6:0] mosiReg3;

//================================================================================
//  ASSIGNMENTS
//================================================================================
assign Mosi0_i = (!Ss) ? (mosiReg3[6]):1'b0;
assign Mosi1_i = (!Ss) ? (mosiReg2[6]):1'b0;
assign Mosi2_i = (!Ss) ? (mosiReg1[6]):1'b0;
assign Mosi3_i = (!Ss) ? (mosiReg0[6]):1'b0;
assign Ss_o    = Ss; 
assign Sck_i   = (!Ss) ? (~Clk_i) : 1'b0;

//================================================================================
//  CODING
//================================================================================	

always @(posedge Clk_i) begin
    if (Rst_i) begin
        SSr <=1'b0;
    end
    else begin 
        SSr <= Ss;
    end
end



always @(posedge Clk_i) begin 
    if (Rst_i) begin 
        startFlag <= 1'b0;
    end
    else begin 
        if (!Start_i) begin 
            startFlag <= 1'b1;
        end
        else begin 
            startFlag <= 1'b0;
        end
    end
end


always @(negedge Clk_i) begin 
    if (Rst_i) begin 
        ssCnt <= 1'b0;
    end
    else if (ssCnt < 7 && startFlag  ) begin 
        ssCnt <= ssCnt + 1'b1;
    end
    else begin
        if (ssCnt == 6 || !startFlag) begin 
            ssCnt <= 1'b0;
        end
    end
end

always @(negedge Clk_i) begin 
    if (Rst_i) begin 
        Ss <= 1'b1;
    end
    else begin 
        if (ssCnt < 7 && startFlag ) begin 
            Ss <= 1'b0;
        end
        else begin 
            Ss <= 1'b1;
        end
    end
end

always @(negedge Clk_i) begin 
    if (Rst_i) begin 
        mosiReg0 <= Data_i[27:21];
    end
    else begin 
        if (!SSr) begin
            mosiReg0 <= { mosiReg0[5:0],1'b0 };
        end
        else begin 
            mosiReg0 <= Data_i[27:21];
        end
    end
end

always @(negedge Clk_i) begin 
    if (Rst_i) begin 
        mosiReg1 <= Data_i[20:14];
    end
    else begin 
        if (!SSr) begin
            mosiReg1 <= { mosiReg1[5:0],1'b0 };
        end
        else begin 
            mosiReg1 <= Data_i[20:14];
        end
    end
end

always @(negedge Clk_i) begin 
    if (Rst_i) begin 
        mosiReg2 <= Data_i[13:7];
    end
    else begin 
        if (!SSr) begin
            mosiReg2 <= { mosiReg2[5:0],1'b0 };
        end
        else begin 
            mosiReg2 <= Data_i[13:7];
        end
    end
end

always @(negedge Clk_i) begin 
    if (Rst_i) begin 
        mosiReg3<= Data_i[6:0];
    end
    else begin 
        if (!SSr) begin
            mosiReg3 <= { mosiReg3[5:0],1'b0 };
        end
        else begin 
            mosiReg3<= Data_i[6:0];
        end
    end
end










endmodule