S5443_V3/constrs_1/new/S5443_3.xdc

set_property PACKAGE_PIN C15 [get_ports {Addr_i[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {Addr_i[0]}]
set_property PACKAGE_PIN C13 [get_ports {Addr_i[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {Addr_i[1]}]
set_property PACKAGE_PIN D15 [get_ports {Addr_i[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {Addr_i[2]}]
set_property PACKAGE_PIN C14 [get_ports {Addr_i[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {Addr_i[3]}]
set_property PACKAGE_PIN E15 [get_ports {Addr_i[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {Addr_i[4]}]
set_property PACKAGE_PIN D13 [get_ports {Addr_i[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {Addr_i[5]}]
set_property PACKAGE_PIN F15 [get_ports {Addr_i[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {Addr_i[6]}]
set_property PACKAGE_PIN E14 [get_ports {Addr_i[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports {Addr_i[7]}]
set_property PACKAGE_PIN J15 [get_ports {Addr_i[8]}]
set_property IOSTANDARD LVCMOS33 [get_ports {Addr_i[8]}]
set_property PACKAGE_PIN F14 [get_ports {Addr_i[9]}]
set_property IOSTANDARD LVCMOS33 [get_ports {Addr_i[9]}]
set_property PACKAGE_PIN K15 [get_ports {Addr_i[10]}]
set_property IOSTANDARD LVCMOS33 [get_ports {Addr_i[10]}]



set_property PACKAGE_PIN B15 [get_ports {Data_i[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {Data_i[0]}]
set_property PACKAGE_PIN B14 [get_ports {Data_i[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {Data_i[1]}]
set_property PACKAGE_PIN B11 [get_ports {Data_i[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {Data_i[2]}]
set_property PACKAGE_PIN B12 [get_ports {Data_i[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {Data_i[3]}]
set_property PACKAGE_PIN A12 [get_ports {Data_i[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {Data_i[4]}]
set_property PACKAGE_PIN B9 [get_ports {Data_i[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {Data_i[5]}]
set_property PACKAGE_PIN K14 [get_ports {Data_i[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {Data_i[6]}]
set_property PACKAGE_PIN A11 [get_ports {Data_i[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports {Data_i[7]}]
set_property PACKAGE_PIN A6 [get_ports {Data_i[8]}]
set_property IOSTANDARD LVCMOS33 [get_ports {Data_i[8]}]
set_property PACKAGE_PIN A13 [get_ports {Data_i[9]}]
set_property IOSTANDARD LVCMOS33 [get_ports {Data_i[9]}]
set_property PACKAGE_PIN A10 [get_ports {Data_i[10]}]
set_property IOSTANDARD LVCMOS33 [get_ports {Data_i[10]}]
set_property PACKAGE_PIN B6 [get_ports {Data_i[11]}]
set_property IOSTANDARD LVCMOS33 [get_ports {Data_i[11]}]
set_property PACKAGE_PIN A5 [get_ports {Data_i[12]}]
set_property IOSTANDARD LVCMOS33 [get_ports {Data_i[12]}]
set_property PACKAGE_PIN B10 [get_ports {Data_i[13]}]
set_property IOSTANDARD LVCMOS33 [get_ports {Data_i[13]}]
set_property PACKAGE_PIN A8 [get_ports {Data_i[14]}]
set_property IOSTANDARD LVCMOS33 [get_ports {Data_i[14]}]
set_property PACKAGE_PIN A14 [get_ports {Data_i[15]}]
set_property IOSTANDARD LVCMOS33 [get_ports {Data_i[15]}]



set_property PACKAGE_PIN C6 [get_ports Led_o]
set_property IOSTANDARD LVCMOS33 [get_ports Led_o]

set_property PACKAGE_PIN A9 [get_ports writeEn_i]
set_property IOSTANDARD LVCMOS33 [get_ports writeEn_i]

set_property PACKAGE_PIN C5 [get_ports readEn_i]
set_property IOSTANDARD LVCMOS33 [get_ports readEn_i]

set_property PACKAGE_PIN C8 [get_ports outputEn_i]
set_property IOSTANDARD LVCMOS33 [get_ports outputEn_i]

set_property PACKAGE_PIN L15 [get_ports {BE_i[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {BE_i[1]}]
set_property PACKAGE_PIN L14 [get_ports {BE_i[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {BE_i[0]}]





#==========================================================================
#	INPUT CLOCKS

set_property PACKAGE_PIN M10 [get_ports Clk123_i]
set_property IOSTANDARD LVCMOS33 [get_ports Clk123_i]
create_clock -period 8.130 -name Clk123_i -waveform {0.000 4.065} -add [get_ports Clk123_i]

set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets Clk123_i_IBUF]
set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets writeEn_i_IBUF]
set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets readEn_i_IBUF]


















connect_debug_port u_ila_0/probe0 [get_nets [list {RegMap_inst/debugReg2[0]} {RegMap_inst/debugReg2[1]} {RegMap_inst/debugReg2[2]} {RegMap_inst/debugReg2[3]} {RegMap_inst/debugReg2[4]} {RegMap_inst/debugReg2[5]} {RegMap_inst/debugReg2[6]} {RegMap_inst/debugReg2[7]} {RegMap_inst/debugReg2[8]} {RegMap_inst/debugReg2[9]} {RegMap_inst/debugReg2[10]} {RegMap_inst/debugReg2[11]} {RegMap_inst/debugReg2[12]} {RegMap_inst/debugReg2[13]} {RegMap_inst/debugReg2[14]} {RegMap_inst/debugReg2[15]}]]
connect_debug_port u_ila_0/probe3 [get_nets [list {RegMap_inst/debugReg1[0]} {RegMap_inst/debugReg1[1]} {RegMap_inst/debugReg1[2]} {RegMap_inst/debugReg1[3]} {RegMap_inst/debugReg1[4]} {RegMap_inst/debugReg1[5]} {RegMap_inst/debugReg1[6]} {RegMap_inst/debugReg1[7]} {RegMap_inst/debugReg1[8]} {RegMap_inst/debugReg1[9]} {RegMap_inst/debugReg1[10]} {RegMap_inst/debugReg1[11]} {RegMap_inst/debugReg1[12]} {RegMap_inst/debugReg1[13]} {RegMap_inst/debugReg1[14]} {RegMap_inst/debugReg1[15]}]]



connect_debug_port u_ila_0/probe0 [get_nets [list {RegMap_inst/debugReg2[0]} {RegMap_inst/debugReg2[1]} {RegMap_inst/debugReg2[2]} {RegMap_inst/debugReg2[3]} {RegMap_inst/debugReg2[4]} {RegMap_inst/debugReg2[5]} {RegMap_inst/debugReg2[6]} {RegMap_inst/debugReg2[7]} {RegMap_inst/debugReg2[8]} {RegMap_inst/debugReg2[9]} {RegMap_inst/debugReg2[10]} {RegMap_inst/debugReg2[11]} {RegMap_inst/debugReg2[12]} {RegMap_inst/debugReg2[13]} {RegMap_inst/debugReg2[14]} {RegMap_inst/debugReg2[15]}]]
connect_debug_port u_ila_0/probe2 [get_nets [list {RegMap_inst/debugReg1[0]} {RegMap_inst/debugReg1[1]} {RegMap_inst/debugReg1[2]} {RegMap_inst/debugReg1[3]} {RegMap_inst/debugReg1[4]} {RegMap_inst/debugReg1[5]} {RegMap_inst/debugReg1[6]} {RegMap_inst/debugReg1[7]} {RegMap_inst/debugReg1[8]} {RegMap_inst/debugReg1[9]} {RegMap_inst/debugReg1[10]} {RegMap_inst/debugReg1[11]} {RegMap_inst/debugReg1[12]} {RegMap_inst/debugReg1[13]} {RegMap_inst/debugReg1[14]} {RegMap_inst/debugReg1[15]}]]


connect_debug_port u_ila_0/probe9 [get_nets [list {RegMap_inst/LedReg_reg[0]_i_2_n_0}]]

connect_debug_port u_ila_0/probe6 [get_nets [list {RegMap_inst/LedReg_reg[0]_i_1_n_0}]]

create_debug_core u_ila_0 ila
set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0]
set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_0]
set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0]
set_property C_DATA_DEPTH 1024 [get_debug_cores u_ila_0]
set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_0]
set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0]
set_property C_TRIGIN_EN false [get_debug_cores u_ila_0]
set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0]
set_property port_width 1 [get_debug_ports u_ila_0/clk]
connect_debug_port u_ila_0/clk [get_nets [list Clk123_i_IBUF_BUFG]]
set_property PROBE_TYPE DATA [get_debug_ports u_ila_0/probe0]
set_property port_width 2 [get_debug_ports u_ila_0/probe0]
connect_debug_port u_ila_0/probe0 [get_nets [list {BE_i_IBUF[0]} {BE_i_IBUF[1]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA [get_debug_ports u_ila_0/probe1]
set_property port_width 11 [get_debug_ports u_ila_0/probe1]
connect_debug_port u_ila_0/probe1 [get_nets [list {Addr_i_IBUF[0]} {Addr_i_IBUF[1]} {Addr_i_IBUF[2]} {Addr_i_IBUF[3]} {Addr_i_IBUF[4]} {Addr_i_IBUF[5]} {Addr_i_IBUF[6]} {Addr_i_IBUF[7]} {Addr_i_IBUF[8]} {Addr_i_IBUF[9]} {Addr_i_IBUF[10]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA [get_debug_ports u_ila_0/probe2]
set_property port_width 16 [get_debug_ports u_ila_0/probe2]
connect_debug_port u_ila_0/probe2 [get_nets [list {Data_i_IBUF[0]} {Data_i_IBUF[1]} {Data_i_IBUF[2]} {Data_i_IBUF[3]} {Data_i_IBUF[4]} {Data_i_IBUF[5]} {Data_i_IBUF[6]} {Data_i_IBUF[7]} {Data_i_IBUF[8]} {Data_i_IBUF[9]} {Data_i_IBUF[10]} {Data_i_IBUF[11]} {Data_i_IBUF[12]} {Data_i_IBUF[13]} {Data_i_IBUF[14]} {Data_i_IBUF[15]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA [get_debug_ports u_ila_0/probe3]
set_property port_width 16 [get_debug_ports u_ila_0/probe3]
connect_debug_port u_ila_0/probe3 [get_nets [list {Data_i_OBUF[0]} {Data_i_OBUF[1]} {Data_i_OBUF[2]} {Data_i_OBUF[3]} {Data_i_OBUF[4]} {Data_i_OBUF[5]} {Data_i_OBUF[6]} {Data_i_OBUF[7]} {Data_i_OBUF[8]} {Data_i_OBUF[9]} {Data_i_OBUF[10]} {Data_i_OBUF[11]} {Data_i_OBUF[12]} {Data_i_OBUF[13]} {Data_i_OBUF[14]} {Data_i_OBUF[15]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA [get_debug_ports u_ila_0/probe4]
set_property port_width 16 [get_debug_ports u_ila_0/probe4]
connect_debug_port u_ila_0/probe4 [get_nets [list {RegMap_inst/debugReg1[0]} {RegMap_inst/debugReg1[1]} {RegMap_inst/debugReg1[2]} {RegMap_inst/debugReg1[3]} {RegMap_inst/debugReg1[4]} {RegMap_inst/debugReg1[5]} {RegMap_inst/debugReg1[6]} {RegMap_inst/debugReg1[7]} {RegMap_inst/debugReg1[8]} {RegMap_inst/debugReg1[9]} {RegMap_inst/debugReg1[10]} {RegMap_inst/debugReg1[11]} {RegMap_inst/debugReg1[12]} {RegMap_inst/debugReg1[13]} {RegMap_inst/debugReg1[14]} {RegMap_inst/debugReg1[15]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA [get_debug_ports u_ila_0/probe5]
set_property port_width 16 [get_debug_ports u_ila_0/probe5]
connect_debug_port u_ila_0/probe5 [get_nets [list {RegMap_inst/debugReg2[0]} {RegMap_inst/debugReg2[1]} {RegMap_inst/debugReg2[2]} {RegMap_inst/debugReg2[3]} {RegMap_inst/debugReg2[4]} {RegMap_inst/debugReg2[5]} {RegMap_inst/debugReg2[6]} {RegMap_inst/debugReg2[7]} {RegMap_inst/debugReg2[8]} {RegMap_inst/debugReg2[9]} {RegMap_inst/debugReg2[10]} {RegMap_inst/debugReg2[11]} {RegMap_inst/debugReg2[12]} {RegMap_inst/debugReg2[13]} {RegMap_inst/debugReg2[14]} {RegMap_inst/debugReg2[15]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe6]
set_property port_width 1 [get_debug_ports u_ila_0/probe6]
connect_debug_port u_ila_0/probe6 [get_nets [list readEn_i_IBUF]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe7]
set_property port_width 1 [get_debug_ports u_ila_0/probe7]
connect_debug_port u_ila_0/probe7 [get_nets [list writeEn_i_IBUF]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe8]
set_property port_width 1 [get_debug_ports u_ila_0/probe8]
connect_debug_port u_ila_0/probe8 [get_nets [list {RegMap_inst/LedReg[31]_i_1_n_0}]]
set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub]
set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub]
set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub]
connect_debug_port dbg_hub/clk [get_nets Clk123_i_IBUF_BUFG]