S5443_V3/sources_1/new/MMCM/top_mmcme2_tb.v

//------------------------------------------------------------------------------------------
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// \   \   \/    � Copyright 2019 Xilinx, Inc. All rights reserved.
//  \   \        This file contains confidential and proprietary information of Xilinx, Inc.
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// /___/   /\    intellectual property laws.
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//
//-------------------------------------------------------------------------------------------
// Device:              7-Series
// Author:              Tatsukawa, Defossez
// Entity Name:         top_mmcme2_tb
// Purpose:            This is a basic demonstration that drives the MMCM_DRP
//                      ports to trigger two reconfiguration events, one for
//                      each state.
// Tools:               QuestaSim_10.7d or newer
// Limitations:
//
// Vendor:              Xilinx Inc.
// Version:             0.01
// Filename:            top_mmcme2_tb.v
// Date Created:        30-Jul-2014
// Date Last Modified:  26-Jun-2019
//-------------------------------------------------------------------------------------------
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//-------------------------------------------------------------------------------------------
// Revision History:
//  Rev: 30-Jul-20149 - Tatsukawa
//      Initial version of this design - source code.
//  Rev: 26-Jun-2019 - Defossez
//      Make sure the simulation works after modifications to the design.
//-------------------------------------------------------------------------------------------
//
`timescale 1ps / 1ps
//-------------------------------------------------------------------------------------------
module top_tb  ();
    reg SSTEP, RST, CLKin, STATE;
    wire SRDY, clk0out, clk1out, clk2out, clk3out, clk4out, clk5out, clk6out;
//-------------------------------------------------------------------------------------------
    top_mmcme2 U1
    (
        .SSTEP      (SSTEP),
        .STATE      (STATE),
        .RST        (RST),
        .CLKIN      (CLKin),
        .SRDY       (SRDY),
        .LOCKED_OUT (locked),
        .CLK0OUT    (clk0out),
        .CLK1OUT    (clk1out),
        .CLK2OUT    (clk2out),
        .CLK3OUT    (clk3out),
        .CLK4OUT    (clk4out),
        .CLK5OUT    (clk5out),
        .CLK6OUT    (clk6out)
    );
//-------------------------------------------------------------------------------------------
    localparam one_ns = 1000;
    localparam clock_period = 10;
    parameter [1:0]    STARTUP = 0, STATE0 = 1, STATE1 = 2, UNDEFINED = 3;
    reg [1:0] SM = STARTUP ;

always @ (posedge CLKin)
    begin
        if (RST)
               SM = STARTUP;
        else
            case (SM)
                STARTUP:
                    begin
                        SM = STATE0;
                        SSTEP=1'b0;
                        STATE=1'b0;
                    end
                STATE0:
                    begin
                        if (locked == 1 )
                            begin
                                #(1 * clock_period * one_ns) SSTEP= 1'b1;
                                #(1 * clock_period * one_ns) SSTEP=1'b0;
                                #(100 * clock_period * one_ns) SM = STATE1 ;
                                STATE=1'b1;
                            end
                    end
                STATE1:
                    begin
                        if (locked == 1 )
                            begin
                                #(1 * clock_period * one_ns) SSTEP= 1'b1;
                                #(1 * clock_period * one_ns) SSTEP=1'b0;
                                #(100 * clock_period * one_ns) SM = STATE0;
                                STATE=1'b0;
                            end
                    end
                UNDEFINED:   SM= STARTUP;
            endcase
        end
//
    initial
        begin
                CLKin = 0;
                RST = 1;
                #50000 RST = 0;
        end
    always
        # (clock_period * one_ns / 2) CLKin = ~CLKin;
//
//-------------------------------------------------------------------------------------------
endmodule
//