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S5443_3.xdc

S5443_3.xdc 43 KB
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  1. set_property PACKAGE_PIN C15 [get_ports {SmcAddr_i[0]}]
    2. 

  2. set_property IOSTANDARD LVCMOS33 [get_ports {SmcAddr_i[0]}]
    3. 

  3. set_property PACKAGE_PIN C13 [get_ports {SmcAddr_i[1]}]
    4. 

  4. set_property IOSTANDARD LVCMOS33 [get_ports {SmcAddr_i[1]}]
    5. 

  5. set_property PACKAGE_PIN D15 [get_ports {SmcAddr_i[2]}]
    6. 

  6. set_property IOSTANDARD LVCMOS33 [get_ports {SmcAddr_i[2]}]
    7. 

  7. set_property PACKAGE_PIN C14 [get_ports {SmcAddr_i[3]}]
    8. 

  8. set_property IOSTANDARD LVCMOS33 [get_ports {SmcAddr_i[3]}]
    9. 

  9. set_property PACKAGE_PIN E15 [get_ports {SmcAddr_i[4]}]
    10. 

  10. set_property IOSTANDARD LVCMOS33 [get_ports {SmcAddr_i[4]}]
    11. 

  11. set_property PACKAGE_PIN D13 [get_ports {SmcAddr_i[5]}]
    12. 

  12. set_property IOSTANDARD LVCMOS33 [get_ports {SmcAddr_i[5]}]
    13. 

  13. set_property PACKAGE_PIN F15 [get_ports {SmcAddr_i[6]}]
    14. 

  14. set_property IOSTANDARD LVCMOS33 [get_ports {SmcAddr_i[6]}]
    15. 

  15. set_property PACKAGE_PIN E14 [get_ports {SmcAddr_i[7]}]
    16. 

  16. set_property IOSTANDARD LVCMOS33 [get_ports {SmcAddr_i[7]}]
    17. 

  17. set_property PACKAGE_PIN J15 [get_ports {SmcAddr_i[8]}]
    18. 

  18. set_property IOSTANDARD LVCMOS33 [get_ports {SmcAddr_i[8]}]
    19. 

  19. set_property PACKAGE_PIN F14 [get_ports {SmcAddr_i[9]}]
    20. 

  20. set_property IOSTANDARD LVCMOS33 [get_ports {SmcAddr_i[9]}]
    21. 

  21. set_property PACKAGE_PIN K15 [get_ports {SmcAddr_i[10]}]
    22. 

  22. set_property IOSTANDARD LVCMOS33 [get_ports {SmcAddr_i[10]}]
    23. 

  23. 

  24. 

  25. 

  26. set_property PACKAGE_PIN B15 [get_ports {SmcData_io[0]}]
    27. 

  27. set_property IOSTANDARD LVCMOS33 [get_ports {SmcData_io[0]}]
    28. 

  28. set_property PACKAGE_PIN B14 [get_ports {SmcData_io[1]}]
    29. 

  29. set_property IOSTANDARD LVCMOS33 [get_ports {SmcData_io[1]}]
    30. 

  30. set_property PACKAGE_PIN B11 [get_ports {SmcData_io[2]}]
    31. 

  31. set_property IOSTANDARD LVCMOS33 [get_ports {SmcData_io[2]}]
    32. 

  32. set_property PACKAGE_PIN B12 [get_ports {SmcData_io[3]}]
    33. 

  33. set_property IOSTANDARD LVCMOS33 [get_ports {SmcData_io[3]}]
    34. 

  34. set_property PACKAGE_PIN A12 [get_ports {SmcData_io[4]}]
    35. 

  35. set_property IOSTANDARD LVCMOS33 [get_ports {SmcData_io[4]}]
    36. 

  36. set_property PACKAGE_PIN B9 [get_ports {SmcData_io[5]}]
    37. 

  37. set_property IOSTANDARD LVCMOS33 [get_ports {SmcData_io[5]}]
    38. 

  38. set_property PACKAGE_PIN K14 [get_ports {SmcData_io[6]}]
    39. 

  39. set_property IOSTANDARD LVCMOS33 [get_ports {SmcData_io[6]}]
    40. 

  40. set_property PACKAGE_PIN A11 [get_ports {SmcData_io[7]}]
    41. 

  41. set_property IOSTANDARD LVCMOS33 [get_ports {SmcData_io[7]}]
    42. 

  42. set_property PACKAGE_PIN A6 [get_ports {SmcData_io[8]}]
    43. 

  43. set_property IOSTANDARD LVCMOS33 [get_ports {SmcData_io[8]}]
    44. 

  44. set_property PACKAGE_PIN A13 [get_ports {SmcData_io[9]}]
    45. 

  45. set_property IOSTANDARD LVCMOS33 [get_ports {SmcData_io[9]}]
    46. 

  46. set_property PACKAGE_PIN A10 [get_ports {SmcData_io[10]}]
    47. 

  47. set_property IOSTANDARD LVCMOS33 [get_ports {SmcData_io[10]}]
    48. 

  48. set_property PACKAGE_PIN B6 [get_ports {SmcData_io[11]}]
    49. 

  49. set_property IOSTANDARD LVCMOS33 [get_ports {SmcData_io[11]}]
    50. 

  50. set_property PACKAGE_PIN A5 [get_ports {SmcData_io[12]}]
    51. 

  51. set_property IOSTANDARD LVCMOS33 [get_ports {SmcData_io[12]}]
    52. 

  52. set_property PACKAGE_PIN B10 [get_ports {SmcData_io[13]}]
    53. 

  53. set_property IOSTANDARD LVCMOS33 [get_ports {SmcData_io[13]}]
    54. 

  54. set_property PACKAGE_PIN A8 [get_ports {SmcData_io[14]}]
    55. 

  55. set_property IOSTANDARD LVCMOS33 [get_ports {SmcData_io[14]}]
    56. 

  56. set_property PACKAGE_PIN A14 [get_ports {SmcData_io[15]}]
    57. 

  57. set_property IOSTANDARD LVCMOS33 [get_ports {SmcData_io[15]}]
    58. 

  58. 

  59. set_property PACKAGE_PIN B13 [get_ports SmcAmsN_i]
    60. 

  60. set_property IOSTANDARD LVCMOS33 [get_ports SmcAmsN_i]
    61. 

  61. 

  62. 

  63. set_property PACKAGE_PIN C6 [get_ports Led_o]
    64. 

  64. set_property IOSTANDARD LVCMOS33 [get_ports Led_o]
    65. 

  65. 

  66. set_property PACKAGE_PIN A9 [get_ports SmcAwe_i]
    67. 

  67. set_property IOSTANDARD LVCMOS33 [get_ports SmcAwe_i]
    68. 

  68. 

  69. set_property PACKAGE_PIN C5 [get_ports SmcAre_i]
    70. 

  70. set_property IOSTANDARD LVCMOS33 [get_ports SmcAre_i]
    71. 

  71. 

  72. set_property PACKAGE_PIN C8 [get_ports SmcAoe_i]
    73. 

  73. set_property IOSTANDARD LVCMOS33 [get_ports SmcAoe_i]
    74. 

  74. 

  75. set_property PACKAGE_PIN L15 [get_ports {SmcBe_i[1]}]
    76. 

  76. set_property IOSTANDARD LVCMOS33 [get_ports {SmcBe_i[1]}]
    77. 

  77. set_property PACKAGE_PIN L14 [get_ports {SmcBe_i[0]}]
    78. 

  78. set_property IOSTANDARD LVCMOS33 [get_ports {SmcBe_i[0]}]
    79. 

  79. 

  80. 

  81. set_property PACKAGE_PIN N11 [get_ports {Ld_i[1]}]
    82. 

  82. set_property IOSTANDARD LVCMOS33 [get_ports {Ld_i[1]}]
    83. 

  83. 

  84. set_property PACKAGE_PIN N9 [get_ports {Ld_i[2]}]
    85. 

  85. set_property IOSTANDARD LVCMOS33 [get_ports {Ld_i[2]}]
    86. 

  86. 

  87. set_property PACKAGE_PIN N13 [get_ports {Ld_i[3]}]
    88. 

  88. set_property IOSTANDARD LVCMOS33 [get_ports {Ld_i[3]}]
    89. 

  89. 

  90. set_property PACKAGE_PIN P15 [get_ports {Ld_i[4]}]
    91. 

  91. set_property IOSTANDARD LVCMOS33 [get_ports {Ld_i[4]}]
    92. 

  92. 

  93. set_property PACKAGE_PIN N12 [get_ports {Ld_i[5]}]
    94. 

  94. set_property IOSTANDARD LVCMOS33 [get_ports {Ld_i[5]}]
    95. 

  95. 

  96. set_property PACKAGE_PIN M8 [get_ports {Ld_i[6]}]
    97. 

  97. set_property IOSTANDARD LVCMOS33 [get_ports {Ld_i[6]}]
    98. 

  98. 

  99. set_property PACKAGE_PIN M13 [get_ports {Ld_i[0]}]
    100. 

  100. set_property IOSTANDARD LVCMOS33 [get_ports {Ld_i[0]}]
    101. 

  101. 

  102. #==========================================================================
    103. 

  103. #	SPI INTERFACES
    104. 

  104. 

  105. #SPI0
    106. 

  106. set_property PACKAGE_PIN K1 [get_ports {Sck_o[0]}]
    107. 

  107. set_property IOSTANDARD LVCMOS33 [get_ports {Sck_o[0]}]
    108. 

  108. 

  109. set_property PACKAGE_PIN H1 [get_ports {Ss_o[0]}]
    110. 

  110. set_property IOSTANDARD LVCMOS33 [get_ports {Ss_o[0]}]
    111. 

  111. 

  112. set_property PACKAGE_PIN K2 [get_ports {SsFlash_o[0]}]
    113. 

  113. set_property IOSTANDARD LVCMOS33 [get_ports {SsFlash_o[0]}]
    114. 

  114. 

  115. set_property PACKAGE_PIN J1 [get_ports {Mosi0_o[0]}]
    116. 

  116. set_property IOSTANDARD LVCMOS33 [get_ports {Mosi0_o[0]}]
    117. 

  117. 

  118. set_property PACKAGE_PIN J3 [get_ports {Mosi1_io[0]}]
    119. 

  119. set_property IOSTANDARD LVCMOS33 [get_ports {Mosi1_io[0]}]
    120. 

  120. 

  121. set_property PACKAGE_PIN M3 [get_ports {Mosi2_o[0]}]
    122. 

  122. set_property IOSTANDARD LVCMOS33 [get_ports {Mosi2_o[0]}]
    123. 

  123. 

  124. set_property PACKAGE_PIN L1 [get_ports {Mosi3_o[0]}]
    125. 

  125. set_property IOSTANDARD LVCMOS33 [get_ports {Mosi3_o[0]}]
    126. 

  126. 

  127. set_property PACKAGE_PIN J2 [get_ports {SpiRst_o[0]}]
    128. 

  128. set_property IOSTANDARD LVCMOS33 [get_ports {SpiRst_o[0]}]
    129. 

  129. 

  130. 

  131. 

  132. set_property PACKAGE_PIN H2 [get_ports {SpiDir_o[0]}]
    133. 

  133. set_property IOSTANDARD LVCMOS33 [get_ports {SpiDir_o[0]}]
    134. 

  134. 

  135. #SPI1
    136. 

  136. set_property PACKAGE_PIN N2 [get_ports {Sck_o[1]}]
    137. 

  137. set_property IOSTANDARD LVCMOS33 [get_ports {Sck_o[1]}]
    138. 

  138. set_property PACKAGE_PIN N4 [get_ports {Ss_o[1]}]
    139. 

  139. set_property IOSTANDARD LVCMOS33 [get_ports {Ss_o[1]}]
    140. 

  140. set_property PACKAGE_PIN P1 [get_ports {SsFlash_o[1]}]
    141. 

  141. set_property IOSTANDARD LVCMOS33 [get_ports {SsFlash_o[1]}]
    142. 

  142. set_property PACKAGE_PIN N3 [get_ports {Mosi0_o[1]}]
    143. 

  143. set_property IOSTANDARD LVCMOS33 [get_ports {Mosi0_o[1]}]
    144. 

  144. set_property PACKAGE_PIN R2 [get_ports {Mosi1_io[1]}]
    145. 

  145. set_property IOSTANDARD LVCMOS33 [get_ports {Mosi1_io[1]}]
    146. 

  146. set_property PACKAGE_PIN N1 [get_ports {Mosi2_o[1]}]
    147. 

  147. set_property IOSTANDARD LVCMOS33 [get_ports {Mosi2_o[1]}]
    148. 

  148. set_property PACKAGE_PIN M2 [get_ports {Mosi3_o[1]}]
    149. 

  149. set_property IOSTANDARD LVCMOS33 [get_ports {Mosi3_o[1]}]
    150. 

  150. set_property PACKAGE_PIN P2 [get_ports {SpiRst_o[1]}]
    151. 

  151. set_property IOSTANDARD LVCMOS33 [get_ports {SpiRst_o[1]}]
    152. 

  152. 

  153. set_property PACKAGE_PIN M1 [get_ports {SpiDir_o[1]}]
    154. 

  154. set_property IOSTANDARD LVCMOS33 [get_ports {SpiDir_o[1]}]
    155. 

  155. 

  156. #SPI2
    157. 

  157. set_property PACKAGE_PIN E2 [get_ports {Sck_o[2]}]
    158. 

  158. set_property IOSTANDARD LVCMOS33 [get_ports {Sck_o[2]}]
    159. 

  159. set_property PACKAGE_PIN E1 [get_ports {Ss_o[2]}]
    160. 

  160. set_property IOSTANDARD LVCMOS33 [get_ports {Ss_o[2]}]
    161. 

  161. set_property PACKAGE_PIN F1 [get_ports {SsFlash_o[2]}]
    162. 

  162. set_property IOSTANDARD LVCMOS33 [get_ports {SsFlash_o[2]}]
    163. 

  163. set_property PACKAGE_PIN D1 [get_ports {Mosi0_o[2]}]
    164. 

  164. set_property IOSTANDARD LVCMOS33 [get_ports {Mosi0_o[2]}]
    165. 

  165. set_property PACKAGE_PIN D2 [get_ports {Mosi1_io[2]}]
    166. 

  166. set_property IOSTANDARD LVCMOS33 [get_ports {Mosi1_io[2]}]
    167. 

  167. set_property PACKAGE_PIN F2 [get_ports {Mosi2_o[2]}]
    168. 

  168. set_property IOSTANDARD LVCMOS33 [get_ports {Mosi2_o[2]}]
    169. 

  169. set_property PACKAGE_PIN G1 [get_ports {Mosi3_o[2]}]
    170. 

  170. set_property IOSTANDARD LVCMOS33 [get_ports {Mosi3_o[2]}]
    171. 

  171. set_property PACKAGE_PIN E3 [get_ports {SpiRst_o[2]}]
    172. 

  172. set_property IOSTANDARD LVCMOS33 [get_ports {SpiRst_o[2]}]
    173. 

  173. 

  174. set_property PACKAGE_PIN C1 [get_ports {SpiDir_o[2]}]
    175. 

  175. set_property IOSTANDARD LVCMOS33 [get_ports {SpiDir_o[2]}]
    176. 

  176. 

  177. #SPI3
    178. 

  178. set_property PACKAGE_PIN R10 [get_ports {Sck_o[3]}]
    179. 

  179. set_property IOSTANDARD LVCMOS33 [get_ports {Sck_o[3]}]
    180. 

  180. set_property PACKAGE_PIN P10 [get_ports {Ss_o[3]}]
    181. 

  181. set_property IOSTANDARD LVCMOS33 [get_ports {Ss_o[3]}]
    182. 

  182. set_property PACKAGE_PIN N10 [get_ports {SsFlash_o[3]}]
    183. 

  183. set_property IOSTANDARD LVCMOS33 [get_ports {SsFlash_o[3]}]
    184. 

  184. set_property PACKAGE_PIN N8 [get_ports {Mosi0_o[3]}]
    185. 

  185. set_property IOSTANDARD LVCMOS33 [get_ports {Mosi0_o[3]}]
    186. 

  186. set_property PACKAGE_PIN R8 [get_ports {Mosi1_io[3]}]
    187. 

  187. set_property IOSTANDARD LVCMOS33 [get_ports {Mosi1_io[3]}]
    188. 

  188. set_property PACKAGE_PIN R11 [get_ports {Mosi2_o[3]}]
    189. 

  189. set_property IOSTANDARD LVCMOS33 [get_ports {Mosi2_o[3]}]
    190. 

  190. set_property PACKAGE_PIN P11 [get_ports {Mosi3_o[3]}]
    191. 

  191. set_property IOSTANDARD LVCMOS33 [get_ports {Mosi3_o[3]}]
    192. 

  192. set_property PACKAGE_PIN R9 [get_ports {SpiRst_o[3]}]
    193. 

  193. set_property IOSTANDARD LVCMOS33 [get_ports {SpiRst_o[3]}]
    194. 

  194. 

  195. set_property PACKAGE_PIN P7 [get_ports {SpiDir_o[3]}]
    196. 

  196. set_property IOSTANDARD LVCMOS33 [get_ports {SpiDir_o[3]}]
    197. 

  197. 

  198. #SPI4
    199. 

  199. set_property PACKAGE_PIN R14 [get_ports {Sck_o[4]}]
    200. 

  200. set_property IOSTANDARD LVCMOS33 [get_ports {Sck_o[4]}]
    201. 

  201. set_property PACKAGE_PIN N14 [get_ports {Ss_o[4]}]
    202. 

  202. set_property IOSTANDARD LVCMOS33 [get_ports {Ss_o[4]}]
    203. 

  203. set_property PACKAGE_PIN P14 [get_ports {SsFlash_o[4]}]
    204. 

  204. set_property IOSTANDARD LVCMOS33 [get_ports {SsFlash_o[4]}]
    205. 

  205. set_property PACKAGE_PIN R13 [get_ports {Mosi0_o[4]}]
    206. 

  206. set_property IOSTANDARD LVCMOS33 [get_ports {Mosi0_o[4]}]
    207. 

  207. set_property PACKAGE_PIN P12 [get_ports {Mosi1_io[4]}]
    208. 

  208. set_property IOSTANDARD LVCMOS33 [get_ports {Mosi1_io[4]}]
    209. 

  209. set_property PACKAGE_PIN M15 [get_ports {Mosi2_o[4]}]
    210. 

  210. set_property IOSTANDARD LVCMOS33 [get_ports {Mosi2_o[4]}]
    211. 

  211. set_property PACKAGE_PIN M14 [get_ports {Mosi3_o[4]}]
    212. 

  212. set_property IOSTANDARD LVCMOS33 [get_ports {Mosi3_o[4]}]
    213. 

  213. set_property PACKAGE_PIN N15 [get_ports {SpiRst_o[4]}]
    214. 

  214. set_property IOSTANDARD LVCMOS33 [get_ports {SpiRst_o[4]}]
    215. 

  215. 

  216. 

  217. set_property PACKAGE_PIN R12 [get_ports {SpiDir_o[4]}]
    218. 

  218. set_property IOSTANDARD LVCMOS33 [get_ports {SpiDir_o[4]}]
    219. 

  219. 

  220. #SPI5
    221. 

  221. set_property PACKAGE_PIN P6 [get_ports {Sck_o[5]}]
    222. 

  222. set_property IOSTANDARD LVCMOS33 [get_ports {Sck_o[5]}]
    223. 

  223. set_property PACKAGE_PIN R5 [get_ports LoCsReg_o]
    224. 

  224. set_property IOSTANDARD LVCMOS33 [get_ports LoCsReg_o]
    225. 

  225. set_property PACKAGE_PIN R4 [get_ports {Ss_o[5]}]
    226. 

  226. set_property IOSTANDARD LVCMOS33 [get_ports {Ss_o[5]}]
    227. 

  227. set_property PACKAGE_PIN R7 [get_ports {SsFlash_o[5]}]
    228. 

  228. set_property IOSTANDARD LVCMOS33 [get_ports {SsFlash_o[5]}]
    229. 

  229. set_property PACKAGE_PIN P3 [get_ports {Mosi0_o[5]}]
    230. 

  230. set_property IOSTANDARD LVCMOS33 [get_ports {Mosi0_o[5]}]
    231. 

  231. set_property PACKAGE_PIN R6 [get_ports {Mosi1_io[5]}]
    232. 

  232. set_property IOSTANDARD LVCMOS33 [get_ports {Mosi1_io[5]}]
    233. 

  233. set_property PACKAGE_PIN N7 [get_ports {Mosi2_o[5]}]
    234. 

  234. set_property IOSTANDARD LVCMOS33 [get_ports {Mosi2_o[5]}]
    235. 

  235. # set_property PACKAGE_PIN R7 [get_ports {Mosi3_o[5]}]
    236. 

  236. # set_property IOSTANDARD LVCMOS33 [get_ports {Mosi3_o[5]}]
    237. 

  237. set_property PACKAGE_PIN N6 [get_ports {SpiRst_o[5]}]
    238. 

  238. set_property IOSTANDARD LVCMOS33 [get_ports {SpiRst_o[5]}]
    239. 

  239. 

  240. set_property PACKAGE_PIN R3 [get_ports {SpiDir_o[5]}]
    241. 

  241. set_property IOSTANDARD LVCMOS33 [get_ports {SpiDir_o[5]}]
    242. 

  242. 

  243. #SPI6
    244. 

  244. set_property PACKAGE_PIN B5 [get_ports {Sck_o[6]}]
    245. 

  245. set_property IOSTANDARD LVCMOS33 [get_ports {Sck_o[6]}]
    246. 

  246. set_property PACKAGE_PIN B3 [get_ports {Ss_o[6]}]
    247. 

  247. set_property IOSTANDARD LVCMOS33 [get_ports {Ss_o[6]}]
    248. 

  248. set_property PACKAGE_PIN A4 [get_ports {SsFlash_o[6]}]
    249. 

  249. set_property IOSTANDARD LVCMOS33 [get_ports {SsFlash_o[6]}]
    250. 

  250. set_property PACKAGE_PIN B1 [get_ports {Mosi0_o[6]}]
    251. 

  251. set_property IOSTANDARD LVCMOS33 [get_ports {Mosi0_o[6]}]
    252. 

  252. set_property PACKAGE_PIN C4 [get_ports {Mosi1_io[6]}]
    253. 

  253. set_property IOSTANDARD LVCMOS33 [get_ports {Mosi1_io[6]}]
    254. 

  254. set_property PACKAGE_PIN B4 [get_ports {Mosi2_o[6]}]
    255. 

  255. set_property IOSTANDARD LVCMOS33 [get_ports {Mosi2_o[6]}]
    256. 

  256. set_property PACKAGE_PIN A3 [get_ports {Mosi3_o[5]}]
    257. 

  257. set_property IOSTANDARD LVCMOS33 [get_ports {Mosi3_o[5]}]
    258. 

  258. set_property PACKAGE_PIN A2 [get_ports {SpiRst_o[6]}]
    259. 

  259. set_property IOSTANDARD LVCMOS33 [get_ports {SpiRst_o[6]}]
    260. 

  260. 

  261. set_property PACKAGE_PIN B2 [get_ports {SpiDir_o[6]}]
    262. 

  262. set_property IOSTANDARD LVCMOS33 [get_ports {SpiDir_o[6]}]
    263. 

  263. 

  264. 

  265. set_property PACKAGE_PIN M7 [get_ports LD_o]
    266. 

  266. set_property IOSTANDARD LVCMOS33 [get_ports LD_o]
    267. 

  267. 

  268. #==========================================================================
    269. 

  269. #	INPUT CLOCKS
    270. 

  270. 

  271. set_property PACKAGE_PIN M10 [get_ports Clk123_i]
    272. 

  272. set_property IOSTANDARD LVCMOS33 [get_ports Clk123_i]
    273. 

  273. create_clock -period 8.130 -name Clk123_i -waveform {0.000 4.065} -add [get_ports Clk123_i]
    274. 

  274. 

  275. set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets Clk123_i_IBUF]
    276. 

  276. # set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets SmcAre_i_IBUF]
    277. 

  277. 

  278. 

  279. set_false_path -from [get_clocks -of_objects [get_pins ClkManager/MMCM/inst/mmcm_adv_inst/CLKOUT1]] -to [get_clocks -of_objects [get_pins ClkManager/MMCM/inst/mmcm_adv_inst/CLKOUT0]]
    280. 

  280. set_false_path -from [get_clocks -of_objects [get_pins ClkManager/MMCM/inst/mmcm_adv_inst/CLKOUT1]] -to [get_clocks -of_objects [get_pins ClkManager/MMCM/inst/mmcm_adv_inst/CLKOUT2]]
    281. 

  281. set_false_path -from [get_clocks -of_objects [get_pins ClkManager/MMCM/inst/mmcm_adv_inst/CLKOUT1]] -to [get_clocks -of_objects [get_pins ClkManager/MMCM/inst/mmcm_adv_inst/CLKOUT3]]
    282. 

  282. set_false_path -from [get_clocks -of_objects [get_pins ClkManager/MMCM/inst/mmcm_adv_inst/CLKOUT1]] -to [get_clocks -of_objects [get_pins ClkManager/MMCM/inst/mmcm_adv_inst/CLKOUT4]]
    283. 

  283. set_false_path -from [get_clocks -of_objects [get_pins ClkManager/MMCM/inst/mmcm_adv_inst/CLKOUT1]] -to [get_clocks -of_objects [get_pins ClkManager/MMCM/inst/mmcm_adv_inst/CLKOUT5]]
    284. 

  284. set_false_path -from [get_clocks -of_objects [get_pins ClkManager/MMCM/inst/mmcm_adv_inst/CLKOUT1]] -to [get_clocks -of_objects [get_pins ClkManager/MMCM/inst/mmcm_adv_inst/CLKOUT6]]
    285. 

  285. 

  286. set_false_path -from [get_clocks -of_objects [get_pins ClkManager/MMCM/inst/mmcm_adv_inst/CLKOUT2]] -to [get_clocks -of_objects [get_pins ClkManager/MMCM/inst/mmcm_adv_inst/CLKOUT1]]
    287. 

  287. set_false_path -from [get_clocks -of_objects [get_pins ClkManager/MMCM/inst/mmcm_adv_inst/CLKOUT3]] -to [get_clocks -of_objects [get_pins ClkManager/MMCM/inst/mmcm_adv_inst/CLKOUT1]]
    288. 

  288. set_false_path -from [get_clocks -of_objects [get_pins ClkManager/MMCM/inst/mmcm_adv_inst/CLKOUT4]] -to [get_clocks -of_objects [get_pins ClkManager/MMCM/inst/mmcm_adv_inst/CLKOUT1]]
    289. 

  289. set_false_path -from [get_clocks -of_objects [get_pins ClkManager/MMCM/inst/mmcm_adv_inst/CLKOUT5]] -to [get_clocks -of_objects [get_pins ClkManager/MMCM/inst/mmcm_adv_inst/CLKOUT1]]
    290. 

  290. set_false_path -from [get_clocks -of_objects [get_pins ClkManager/MMCM/inst/mmcm_adv_inst/CLKOUT6]] -to [get_clocks -of_objects [get_pins ClkManager/MMCM/inst/mmcm_adv_inst/CLKOUT1]]
    291. 

  291. 

  292. 

  293. set_false_path -from [get_clocks Clk123_i] -to [get_clocks -of_objects [get_pins ClkManager/MMCM/inst/mmcm_adv_inst/CLKOUT6]]
    294. 

  294. set_false_path -from [get_clocks -of_objects [get_pins ClkManager/MMCM/inst/mmcm_adv_inst/CLKOUT6]] -to [get_clocks Clk123_i]
    295. 

  295. # set_false_path -from [get_clocks -of_objects [get_pins ClkManager/MMCM/inst/mmcm_adv_inst/CLKOUT6]] -to [get_clocks -of_objects [get_pins ClkManager/MMCM/inst/mmcm_adv_inst/CLKOUT6]]
    296. 

  296. 

  297. set_false_path -from [get_clocks Clk123_i] -to [get_clocks -of_objects [get_pins ClkManager/MMCM/inst/mmcm_adv_inst/CLKOUT5]]
    298. 

  298. set_false_path -from [get_clocks -of_objects [get_pins ClkManager/MMCM/inst/mmcm_adv_inst/CLKOUT5]] -to [get_clocks Clk123_i]
    299. 

  299. # set_false_path -from [get_clocks -of_objects [get_pins ClkManager/MMCM/inst/mmcm_adv_inst/CLKOUT5]] -to [get_clocks -of_objects [get_pins ClkManager/MMCM/inst/mmcm_adv_inst/CLKOUT5]]
    300. 

  300. 

  301. 

  302. set_false_path -from [get_clocks Clk123_i] -to [get_clocks -of_objects [get_pins ClkManager/MMCM/inst/mmcm_adv_inst/CLKOUT4]]
    303. 

  303. set_false_path -from [get_clocks -of_objects [get_pins ClkManager/MMCM/inst/mmcm_adv_inst/CLKOUT4]] -to [get_clocks Clk123_i]
    304. 

  304. # set_false_path -from [get_clocks -of_objects [get_pins ClkManager/MMCM/inst/mmcm_adv_inst/CLKOUT4]] -to [get_clocks -of_objects [get_pins ClkManager/MMCM/inst/mmcm_adv_inst/CLKOUT4]]
    305. 

  305. 

  306. 

  307. set_false_path -from [get_clocks Clk123_i] -to [get_clocks -of_objects [get_pins ClkManager/MMCM/inst/mmcm_adv_inst/CLKOUT3]]
    308. 

  308. set_false_path -from [get_clocks -of_objects [get_pins ClkManager/MMCM/inst/mmcm_adv_inst/CLKOUT3]] -to [get_clocks Clk123_i]
    309. 

  309. # set_false_path -from [get_clocks -of_objects [get_pins ClkManager/MMCM/inst/mmcm_adv_inst/CLKOUT3]] -to [get_clocks -of_objects [get_pins ClkManager/MMCM/inst/mmcm_adv_inst/CLKOUT3]]
    310. 

  310. 

  311. 

  312. set_false_path -from [get_clocks Clk123_i] -to [get_clocks -of_objects [get_pins ClkManager/MMCM/inst/mmcm_adv_inst/CLKOUT2]]
    313. 

  313. set_false_path -from [get_clocks -of_objects [get_pins ClkManager/MMCM/inst/mmcm_adv_inst/CLKOUT2]] -to [get_clocks Clk123_i]
    314. 

  314. # set_false_path -from [get_clocks -of_objects [get_pins ClkManager/MMCM/inst/mmcm_adv_inst/CLKOUT2]] -to [get_clocks -of_objects [get_pins ClkManager/MMCM/inst/mmcm_adv_inst/CLKOUT2]]
    315. 

  315. 

  316. 

  317. set_false_path -from [get_clocks Clk123_i] -to [get_clocks -of_objects [get_pins ClkManager/MMCM/inst/mmcm_adv_inst/CLKOUT1]]
    318. 

  318. set_false_path -from [get_clocks -of_objects [get_pins ClkManager/MMCM/inst/mmcm_adv_inst/CLKOUT1]] -to [get_clocks Clk123_i]
    319. 

  319. # set_false_path -from [get_clocks -of_objects [get_pins ClkManager/MMCM/inst/mmcm_adv_inst/CLKOUT1]] -to [get_clocks -of_objects [get_pins ClkManager/MMCM/inst/mmcm_adv_inst/CLKOUT1]]
    320. 

  320. 

  321. 

  322. set_false_path -from [get_clocks Clk123_i] -to [get_clocks -of_objects [get_pins ClkManager/MMCM/inst/mmcm_adv_inst/CLKOUT0]]
    323. 

  323. set_false_path -from [get_clocks -of_objects [get_pins ClkManager/MMCM/inst/mmcm_adv_inst/CLKOUT0]] -to [get_clocks Clk123_i]
    324. 

  324. # set_false_path -from [get_clocks -of_objects [get_pins ClkManager/MMCM/inst/mmcm_adv_inst/CLKOUT0]] -to [get_clocks -of_objects [get_pins ClkManager/MMCM/inst/mmcm_adv_inst/CLKOUT0]]
    325. 

  325. 

  326. 

  327. 

  328. 

  329. set_clock_groups -asynchronous -group [get_clocks [list Clk123_i [get_clocks -of_objects [get_pins ClkManager/MMCM/inst/mmcm_adv_inst/CLKOUT1]] [get_clocks -of_objects [get_pins ClkManager/MMCM/inst/mmcm_adv_inst/CLKOUT2]] [get_clocks -of_objects [get_pins ClkManager/MMCM/inst/mmcm_adv_inst/CLKOUT3]] [get_clocks -of_objects [get_pins ClkManager/MMCM/inst/mmcm_adv_inst/CLKOUT4]] [get_clocks -of_objects [get_pins ClkManager/MMCM/inst/mmcm_adv_inst/CLKOUT5]] [get_clocks -of_objects [get_pins ClkManager/MMCM/inst/mmcm_adv_inst/CLKOUT6]]]]
    330. 

  330. 

  331. 

  332. set_property PULLUP true [get_ports {SsFlash_o[6]}]
    333. 

  333. set_property PULLUP true [get_ports {SsFlash_o[5]}]
    334. 

  334. set_property PULLUP true [get_ports {SsFlash_o[4]}]
    335. 

  335. set_property PULLUP true [get_ports {SsFlash_o[3]}]
    336. 

  336. set_property PULLUP true [get_ports {SsFlash_o[2]}]
    337. 

  337. set_property PULLUP true [get_ports {SsFlash_o[1]}]
    338. 

  338. set_property PULLUP true [get_ports {SsFlash_o[0]}]
    339. 

  339. 

  340. set_property PULLUP true [get_ports {Ss_o[6]}]
    341. 

  341. set_property PULLUP true [get_ports {Ss_o[5]}]
    342. 

  342. set_property PULLUP true [get_ports {Ss_o[4]}]
    343. 

  343. set_property PULLUP true [get_ports {Ss_o[3]}]
    344. 

  344. set_property PULLUP true [get_ports {Ss_o[2]}]
    345. 

  345. set_property PULLUP true [get_ports {Ss_o[1]}]
    346. 

  346. set_property PULLUP true [get_ports {Ss_o[0]}]
    347. 

  347. 

  348. 

  349. # connect_debug_port u_ila_0/probe1 [get_nets [list {toRegMapAddr[1]} {toRegMapAddr[2]} {toRegMapAddr[3]} {toRegMapAddr[4]} {toRegMapAddr[5]} {toRegMapAddr[6]} {toRegMapAddr[7]} {toRegMapAddr[8]} {toRegMapAddr[9]}]]
    350. 

  350. # connect_debug_port u_ila_0/probe4 [get_nets [list {RegMap_inst/Spi0ClkReg_o[0]} {RegMap_inst/Spi0ClkReg_o[1]} {RegMap_inst/Spi0ClkReg_o[2]} {RegMap_inst/Spi0ClkReg_o[3]} {RegMap_inst/Spi0ClkReg_o[4]} {RegMap_inst/Spi0ClkReg_o[5]} {RegMap_inst/Spi0ClkReg_o[6]} {RegMap_inst/Spi0ClkReg_o[7]}]]
    351. 

  351. # connect_debug_port u_ila_0/probe5 [get_nets [list {RegMap_inst/TxFifoCtrlReg0_i[0]} {RegMap_inst/TxFifoCtrlReg0_i[1]} {RegMap_inst/TxFifoCtrlReg0_i[2]} {RegMap_inst/TxFifoCtrlReg0_i[8]} {RegMap_inst/TxFifoCtrlReg0_i[9]} {RegMap_inst/TxFifoCtrlReg0_i[10]} {RegMap_inst/TxFifoCtrlReg0_i[11]} {RegMap_inst/TxFifoCtrlReg0_i[12]} {RegMap_inst/TxFifoCtrlReg0_i[13]} {RegMap_inst/TxFifoCtrlReg0_i[14]} {RegMap_inst/TxFifoCtrlReg0_i[15]}]]
    352. 

  352. 

  353. # connect_debug_port u_ila_0/probe14 [get_nets [list {ansData[0]} {ansData[1]} {ansData[2]} {ansData[3]} {ansData[4]} {ansData[5]} {ansData[6]} {ansData[7]} {ansData[8]} {ansData[9]} {ansData[10]} {ansData[11]} {ansData[12]} {ansData[13]} {ansData[14]} {ansData[15]}]]
    354. 

  354. 

  355. 

  356. # connect_debug_port u_ila_0/probe4 [get_nets [list {Mosi1_io_OBUF[5]}]]
    357. 

  357. 

  358. # create_debug_core u_ila_0 ila
    359. 

  359. # set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0]
    360. 

  360. # set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_0]
    361. 

  361. # set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0]
    362. 

  362. # set_property C_DATA_DEPTH 1024 [get_debug_cores u_ila_0]
    363. 

  363. # set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_0]
    364. 

  364. # set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0]
    365. 

  365. # set_property C_TRIGIN_EN false [get_debug_cores u_ila_0]
    366. 

  366. # set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0]
    367. 

  367. # set_property port_width 1 [get_debug_ports u_ila_0/clk]
    368. 

  368. # connect_debug_port u_ila_0/clk [get_nets [list gclk]]
    369. 

  369. # set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0]
    370. 

  370. # set_property port_width 32 [get_debug_ports u_ila_0/probe0]
    371. 

  371. # connect_debug_port u_ila_0/probe0 [get_nets [list {SpiGen[5].SPIm_inst/txLenght[0]} {SpiGen[5].SPIm_inst/txLenght[1]} {SpiGen[5].SPIm_inst/txLenght[2]} {SpiGen[5].SPIm_inst/txLenght[3]} {SpiGen[5].SPIm_inst/txLenght[4]} {SpiGen[5].SPIm_inst/txLenght[5]} {SpiGen[5].SPIm_inst/txLenght[6]} {SpiGen[5].SPIm_inst/txLenght[7]} {SpiGen[5].SPIm_inst/txLenght[8]} {SpiGen[5].SPIm_inst/txLenght[9]} {SpiGen[5].SPIm_inst/txLenght[10]} {SpiGen[5].SPIm_inst/txLenght[11]} {SpiGen[5].SPIm_inst/txLenght[12]} {SpiGen[5].SPIm_inst/txLenght[13]} {SpiGen[5].SPIm_inst/txLenght[14]} {SpiGen[5].SPIm_inst/txLenght[15]} {SpiGen[5].SPIm_inst/txLenght[16]} {SpiGen[5].SPIm_inst/txLenght[17]} {SpiGen[5].SPIm_inst/txLenght[18]} {SpiGen[5].SPIm_inst/txLenght[19]} {SpiGen[5].SPIm_inst/txLenght[20]} {SpiGen[5].SPIm_inst/txLenght[21]} {SpiGen[5].SPIm_inst/txLenght[22]} {SpiGen[5].SPIm_inst/txLenght[23]} {SpiGen[5].SPIm_inst/txLenght[24]} {SpiGen[5].SPIm_inst/txLenght[25]} {SpiGen[5].SPIm_inst/txLenght[26]} {SpiGen[5].SPIm_inst/txLenght[27]} {SpiGen[5].SPIm_inst/txLenght[28]} {SpiGen[5].SPIm_inst/txLenght[29]} {SpiGen[5].SPIm_inst/txLenght[30]} {SpiGen[5].SPIm_inst/txLenght[31]}]]
    372. 

  372. # create_debug_port u_ila_0 probe
    373. 

  373. # set_property PROBE_TYPE DATA [get_debug_ports u_ila_0/probe1]
    374. 

  374. # set_property port_width 1 [get_debug_ports u_ila_0/probe1]
    375. 

  375. # connect_debug_port u_ila_0/probe1 [get_nets [list {Mosi3_o_OBUF[0]}]]
    376. 

  376. # create_debug_port u_ila_0 probe
    377. 

  377. # set_property PROBE_TYPE DATA [get_debug_ports u_ila_0/probe2]
    378. 

  378. # set_property port_width 16 [get_debug_ports u_ila_0/probe2]
    379. 

  379. # connect_debug_port u_ila_0/probe2 [get_nets [list {SmcData_io_IBUF[0]} {SmcData_io_IBUF[1]} {SmcData_io_IBUF[2]} {SmcData_io_IBUF[3]} {SmcData_io_IBUF[4]} {SmcData_io_IBUF[5]} {SmcData_io_IBUF[6]} {SmcData_io_IBUF[7]} {SmcData_io_IBUF[8]} {SmcData_io_IBUF[9]} {SmcData_io_IBUF[10]} {SmcData_io_IBUF[11]} {SmcData_io_IBUF[12]} {SmcData_io_IBUF[13]} {SmcData_io_IBUF[14]} {SmcData_io_IBUF[15]}]]
    380. 

  380. # create_debug_port u_ila_0 probe
    381. 

  381. # set_property PROBE_TYPE DATA [get_debug_ports u_ila_0/probe3]
    382. 

  382. # set_property port_width 1 [get_debug_ports u_ila_0/probe3]
    383. 

  383. # connect_debug_port u_ila_0/probe3 [get_nets [list {Sck_o_OBUF[0]}]]
    384. 

  384. # create_debug_port u_ila_0 probe
    385. 

  385. # set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4]
    386. 

  386. # set_property port_width 1 [get_debug_ports u_ila_0/probe4]
    387. 

  387. # connect_debug_port u_ila_0/probe4 [get_nets [list {Sck_o_OBUF[5]}]]
    388. 

  388. # create_debug_port u_ila_0 probe
    389. 

  389. # set_property PROBE_TYPE DATA [get_debug_ports u_ila_0/probe5]
    390. 

  390. # set_property port_width 1 [get_debug_ports u_ila_0/probe5]
    391. 

  391. # connect_debug_port u_ila_0/probe5 [get_nets [list {Mosi2_o_OBUF[0]}]]
    392. 

  392. # create_debug_port u_ila_0 probe
    393. 

  393. # set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe6]
    394. 

  394. # set_property port_width 1 [get_debug_ports u_ila_0/probe6]
    395. 

  395. # connect_debug_port u_ila_0/probe6 [get_nets [list {Mosi1_io_IBUF[5]}]]
    396. 

  396. # create_debug_port u_ila_0 probe
    397. 

  397. # set_property PROBE_TYPE DATA [get_debug_ports u_ila_0/probe7]
    398. 

  398. # set_property port_width 1 [get_debug_ports u_ila_0/probe7]
    399. 

  399. # connect_debug_port u_ila_0/probe7 [get_nets [list {Mosi0_o_OBUF[0]}]]
    400. 

  400. # create_debug_port u_ila_0 probe
    401. 

  401. # set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe8]
    402. 

  402. # set_property port_width 1 [get_debug_ports u_ila_0/probe8]
    403. 

  403. # connect_debug_port u_ila_0/probe8 [get_nets [list {Mosi0_o_OBUF[5]}]]
    404. 

  404. # create_debug_port u_ila_0 probe
    405. 

  405. # set_property PROBE_TYPE DATA [get_debug_ports u_ila_0/probe9]
    406. 

  406. # set_property port_width 11 [get_debug_ports u_ila_0/probe9]
    407. 

  407. # connect_debug_port u_ila_0/probe9 [get_nets [list {SmcAddr_i_IBUF[0]} {SmcAddr_i_IBUF[1]} {SmcAddr_i_IBUF[2]} {SmcAddr_i_IBUF[3]} {SmcAddr_i_IBUF[4]} {SmcAddr_i_IBUF[5]} {SmcAddr_i_IBUF[6]} {SmcAddr_i_IBUF[7]} {SmcAddr_i_IBUF[8]} {SmcAddr_i_IBUF[9]} {SmcAddr_i_IBUF[10]}]]
    408. 

  408. # create_debug_port u_ila_0 probe
    409. 

  409. # set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe10]
    410. 

  410. # set_property port_width 1 [get_debug_ports u_ila_0/probe10]
    411. 

  411. # connect_debug_port u_ila_0/probe10 [get_nets [list {Ss_o_OBUF[0]}]]
    412. 

  412. # create_debug_port u_ila_0 probe
    413. 

  413. # set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe11]
    414. 

  414. # set_property port_width 16 [get_debug_ports u_ila_0/probe11]
    415. 

  415. # connect_debug_port u_ila_0/probe11 [get_nets [list {spi0TxFifoCtrl[0]} {spi0TxFifoCtrl[1]} {spi0TxFifoCtrl[2]} {spi0TxFifoCtrl[3]} {spi0TxFifoCtrl[4]} {spi0TxFifoCtrl[5]} {spi0TxFifoCtrl[6]} {spi0TxFifoCtrl[7]} {spi0TxFifoCtrl[8]} {spi0TxFifoCtrl[9]} {spi0TxFifoCtrl[10]} {spi0TxFifoCtrl[11]} {spi0TxFifoCtrl[12]} {spi0TxFifoCtrl[13]} {spi0TxFifoCtrl[14]} {spi0TxFifoCtrl[15]}]]
    416. 

  416. # create_debug_port u_ila_0 probe
    417. 

  417. # set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe12]
    418. 

  418. # set_property port_width 1 [get_debug_ports u_ila_0/probe12]
    419. 

  419. # connect_debug_port u_ila_0/probe12 [get_nets [list {SsFlash_o_OBUF[0]}]]
    420. 

  420. # create_debug_port u_ila_0 probe
    421. 

  421. # set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe13]
    422. 

  422. # set_property port_width 16 [get_debug_ports u_ila_0/probe13]
    423. 

  423. # connect_debug_port u_ila_0/probe13 [get_nets [list {spi0CsDelay[0]} {spi0CsDelay[1]} {spi0CsDelay[2]} {spi0CsDelay[3]} {spi0CsDelay[4]} {spi0CsDelay[5]} {spi0CsDelay[6]} {spi0CsDelay[7]} {spi0CsDelay[8]} {spi0CsDelay[9]} {spi0CsDelay[10]} {spi0CsDelay[11]} {spi0CsDelay[12]} {spi0CsDelay[13]} {spi0CsDelay[14]} {spi0CsDelay[15]}]]
    424. 

  424. # create_debug_port u_ila_0 probe
    425. 

  425. # set_property PROBE_TYPE DATA [get_debug_ports u_ila_0/probe14]
    426. 

  426. # set_property port_width 16 [get_debug_ports u_ila_0/probe14]
    427. 

  427. # connect_debug_port u_ila_0/probe14 [get_nets [list {dataFromRxFifo[0][15]} {dataFromRxFifo[0][14]} {dataFromRxFifo[0][13]} {dataFromRxFifo[0][12]} {dataFromRxFifo[0][11]} {dataFromRxFifo[0][10]} {dataFromRxFifo[0][9]} {dataFromRxFifo[0][8]} {dataFromRxFifo[0][7]} {dataFromRxFifo[0][6]} {dataFromRxFifo[0][5]} {dataFromRxFifo[0][4]} {dataFromRxFifo[0][3]} {dataFromRxFifo[0][2]} {dataFromRxFifo[0][1]} {dataFromRxFifo[0][0]}]]
    428. 

  428. # create_debug_port u_ila_0 probe
    429. 

  429. # set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe15]
    430. 

  430. # set_property port_width 16 [get_debug_ports u_ila_0/probe15]
    431. 

  431. # connect_debug_port u_ila_0/probe15 [get_nets [list {spi0RxFifoCtrl[0]} {spi0RxFifoCtrl[1]} {spi0RxFifoCtrl[2]} {spi0RxFifoCtrl[3]} {spi0RxFifoCtrl[4]} {spi0RxFifoCtrl[5]} {spi0RxFifoCtrl[6]} {spi0RxFifoCtrl[7]} {spi0RxFifoCtrl[8]} {spi0RxFifoCtrl[9]} {spi0RxFifoCtrl[10]} {spi0RxFifoCtrl[11]} {spi0RxFifoCtrl[12]} {spi0RxFifoCtrl[13]} {spi0RxFifoCtrl[14]} {spi0RxFifoCtrl[15]}]]
    432. 

  432. # create_debug_port u_ila_0 probe
    433. 

  433. # set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe16]
    434. 

  434. # set_property port_width 1 [get_debug_ports u_ila_0/probe16]
    435. 

  435. # connect_debug_port u_ila_0/probe16 [get_nets [list {SpiRst_o_OBUF[0]}]]
    436. 

  436. # create_debug_port u_ila_0 probe
    437. 

  437. # set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe17]
    438. 

  438. # set_property port_width 16 [get_debug_ports u_ila_0/probe17]
    439. 

  439. # connect_debug_port u_ila_0/probe17 [get_nets [list {spi0CsCtrl[0]} {spi0CsCtrl[1]} {spi0CsCtrl[2]} {spi0CsCtrl[3]} {spi0CsCtrl[4]} {spi0CsCtrl[5]} {spi0CsCtrl[6]} {spi0CsCtrl[7]} {spi0CsCtrl[8]} {spi0CsCtrl[9]} {spi0CsCtrl[10]} {spi0CsCtrl[11]} {spi0CsCtrl[12]} {spi0CsCtrl[13]} {spi0CsCtrl[14]} {spi0CsCtrl[15]}]]
    440. 

  440. # create_debug_port u_ila_0 probe
    441. 

  441. # set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe18]
    442. 

  442. # set_property port_width 16 [get_debug_ports u_ila_0/probe18]
    443. 

  443. # connect_debug_port u_ila_0/probe18 [get_nets [list {spi0Ctrl[0]} {spi0Ctrl[1]} {spi0Ctrl[2]} {spi0Ctrl[3]} {spi0Ctrl[4]} {spi0Ctrl[5]} {spi0Ctrl[6]} {spi0Ctrl[7]} {spi0Ctrl[8]} {spi0Ctrl[9]} {spi0Ctrl[10]} {spi0Ctrl[11]} {spi0Ctrl[12]} {spi0Ctrl[13]} {spi0Ctrl[14]} {spi0Ctrl[15]}]]
    444. 

  444. # create_debug_port u_ila_0 probe
    445. 

  445. # set_property PROBE_TYPE DATA [get_debug_ports u_ila_0/probe19]
    446. 

  446. # set_property port_width 32 [get_debug_ports u_ila_0/probe19]
    447. 

  447. # connect_debug_port u_ila_0/probe19 [get_nets [list {toFifoData[0]} {toFifoData[1]} {toFifoData[2]} {toFifoData[3]} {toFifoData[4]} {toFifoData[5]} {toFifoData[6]} {toFifoData[7]} {toFifoData[8]} {toFifoData[9]} {toFifoData[10]} {toFifoData[11]} {toFifoData[12]} {toFifoData[13]} {toFifoData[14]} {toFifoData[15]} {toFifoData[16]} {toFifoData[17]} {toFifoData[18]} {toFifoData[19]} {toFifoData[20]} {toFifoData[21]} {toFifoData[22]} {toFifoData[23]} {toFifoData[24]} {toFifoData[25]} {toFifoData[26]} {toFifoData[27]} {toFifoData[28]} {toFifoData[29]} {toFifoData[30]} {toFifoData[31]}]]
    448. 

  448. # create_debug_port u_ila_0 probe
    449. 

  449. # set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe20]
    450. 

  450. # set_property port_width 1 [get_debug_ports u_ila_0/probe20]
    451. 

  451. # connect_debug_port u_ila_0/probe20 [get_nets [list SmcAre_i_IBUF]]
    452. 

  452. # create_debug_port u_ila_0 probe
    453. 

  453. # set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe21]
    454. 

  454. # set_property port_width 1 [get_debug_ports u_ila_0/probe21]
    455. 

  455. # connect_debug_port u_ila_0/probe21 [get_nets [list SmcAwe_i_IBUF]]
    456. 

  456. # set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub]
    457. 

  457. # set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub]
    458. 

  458. # set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub]
    459. 

  459. # connect_debug_port dbg_hub/clk [get_nets gclk]
    460. 

  460. 

  461. 

  462. 

  463. 

  464. create_debug_core u_ila_0 ila
    465. 

  465. set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0]
    466. 

  466. set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_0]
    467. 

  467. set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0]
    468. 

  468. set_property C_DATA_DEPTH 1024 [get_debug_cores u_ila_0]
    469. 

  469. set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_0]
    470. 

  470. set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0]
    471. 

  471. set_property C_TRIGIN_EN false [get_debug_cores u_ila_0]
    472. 

  472. set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0]
    473. 

  473. set_property port_width 1 [get_debug_ports u_ila_0/clk]
    474. 

  474. connect_debug_port u_ila_0/clk [get_nets [list gclk]]
    475. 

  475. set_property PROBE_TYPE DATA [get_debug_ports u_ila_0/probe0]
    476. 

  476. set_property port_width 8 [get_debug_ports u_ila_0/probe0]
    477. 

  477. connect_debug_port u_ila_0/probe0 [get_nets [list {spi0CtrlRR[0]} {spi0CtrlRR[1]} {spi0CtrlRR[2]} {spi0CtrlRR[3]} {spi0CtrlRR[4]} {spi0CtrlRR[5]} {spi0CtrlRR[6]} {spi0CtrlRR[8]}]]
    478. 

  478. create_debug_port u_ila_0 probe
    479. 

  479. set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1]
    480. 

  480. set_property port_width 1 [get_debug_ports u_ila_0/probe1]
    481. 

  481. connect_debug_port u_ila_0/probe1 [get_nets [list {SpiDir_o_OBUF[0]}]]
    482. 

  482. create_debug_port u_ila_0 probe
    483. 

  483. set_property PROBE_TYPE DATA [get_debug_ports u_ila_0/probe2]
    484. 

  484. set_property port_width 1 [get_debug_ports u_ila_0/probe2]
    485. 

  485. connect_debug_port u_ila_0/probe2 [get_nets [list {Mosi3_o_OBUF[0]}]]
    486. 

  486. create_debug_port u_ila_0 probe
    487. 

  487. set_property PROBE_TYPE DATA [get_debug_ports u_ila_0/probe3]
    488. 

  488. set_property port_width 1 [get_debug_ports u_ila_0/probe3]
    489. 

  489. connect_debug_port u_ila_0/probe3 [get_nets [list {Sck_o_OBUF[5]}]]
    490. 

  490. create_debug_port u_ila_0 probe
    491. 

  491. set_property PROBE_TYPE DATA [get_debug_ports u_ila_0/probe4]
    492. 

  492. set_property port_width 1 [get_debug_ports u_ila_0/probe4]
    493. 

  493. connect_debug_port u_ila_0/probe4 [get_nets [list {SmcData_io_OBUF[15]}]]
    494. 

  494. create_debug_port u_ila_0 probe
    495. 

  495. set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5]
    496. 

  496. set_property port_width 11 [get_debug_ports u_ila_0/probe5]
    497. 

  497. connect_debug_port u_ila_0/probe5 [get_nets [list {SmcAddr_i_IBUF[0]} {SmcAddr_i_IBUF[1]} {SmcAddr_i_IBUF[2]} {SmcAddr_i_IBUF[3]} {SmcAddr_i_IBUF[4]} {SmcAddr_i_IBUF[5]} {SmcAddr_i_IBUF[6]} {SmcAddr_i_IBUF[7]} {SmcAddr_i_IBUF[8]} {SmcAddr_i_IBUF[9]} {SmcAddr_i_IBUF[10]}]]
    498. 

  498. create_debug_port u_ila_0 probe
    499. 

  499. set_property PROBE_TYPE DATA [get_debug_ports u_ila_0/probe6]
    500. 

  500. set_property port_width 2 [get_debug_ports u_ila_0/probe6]
    501. 

  501. connect_debug_port u_ila_0/probe6 [get_nets [list {Mosi2_o_OBUF[0]} {Mosi2_o_OBUF[5]}]]
    502. 

  502. create_debug_port u_ila_0 probe
    503. 

  503. set_property PROBE_TYPE DATA [get_debug_ports u_ila_0/probe7]
    504. 

  504. set_property port_width 2 [get_debug_ports u_ila_0/probe7]
    505. 

  505. connect_debug_port u_ila_0/probe7 [get_nets [list {Mosi0_o_OBUF[0]} {Mosi0_o_OBUF[5]}]]
    506. 

  506. create_debug_port u_ila_0 probe
    507. 

  507. set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe8]
    508. 

  508. set_property port_width 16 [get_debug_ports u_ila_0/probe8]
    509. 

  509. connect_debug_port u_ila_0/probe8 [get_nets [list {SmcData_io_IBUF[0]} {SmcData_io_IBUF[1]} {SmcData_io_IBUF[2]} {SmcData_io_IBUF[3]} {SmcData_io_IBUF[4]} {SmcData_io_IBUF[5]} {SmcData_io_IBUF[6]} {SmcData_io_IBUF[7]} {SmcData_io_IBUF[8]} {SmcData_io_IBUF[9]} {SmcData_io_IBUF[10]} {SmcData_io_IBUF[11]} {SmcData_io_IBUF[12]} {SmcData_io_IBUF[13]} {SmcData_io_IBUF[14]} {SmcData_io_IBUF[15]}]]
    510. 

  510. create_debug_port u_ila_0 probe
    511. 

  511. set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe9]
    512. 

  512. set_property port_width 1 [get_debug_ports u_ila_0/probe9]
    513. 

  513. connect_debug_port u_ila_0/probe9 [get_nets [list {SsFlash_o_OBUF[5]}]]
    514. 

  514. create_debug_port u_ila_0 probe
    515. 

  515. set_property PROBE_TYPE DATA [get_debug_ports u_ila_0/probe10]
    516. 

  516. set_property port_width 2 [get_debug_ports u_ila_0/probe10]
    517. 

  517. connect_debug_port u_ila_0/probe10 [get_nets [list {spi0CsCtrlRR[0]} {spi0CsCtrlRR[1]}]]
    518. 

  518. create_debug_port u_ila_0 probe
    519. 

  519. set_property PROBE_TYPE DATA [get_debug_ports u_ila_0/probe11]
    520. 

  520. set_property port_width 8 [get_debug_ports u_ila_0/probe11]
    521. 

  521. connect_debug_port u_ila_0/probe11 [get_nets [list {spi0CsDelayRR[0]} {spi0CsDelayRR[1]} {spi0CsDelayRR[2]} {spi0CsDelayRR[3]} {spi0CsDelayRR[4]} {spi0CsDelayRR[5]} {spi0CsDelayRR[6]} {spi0CsDelayRR[7]}]]
    522. 

  522. create_debug_port u_ila_0 probe
    523. 

  523. set_property PROBE_TYPE DATA [get_debug_ports u_ila_0/probe12]
    524. 

  524. set_property port_width 1 [get_debug_ports u_ila_0/probe12]
    525. 

  525. connect_debug_port u_ila_0/probe12 [get_nets [list {spi5TxFifoCtrl__0[0]}]]
    526. 

  526. create_debug_port u_ila_0 probe
    527. 

  527. set_property PROBE_TYPE DATA [get_debug_ports u_ila_0/probe13]
    528. 

  528. set_property port_width 15 [get_debug_ports u_ila_0/probe13]
    529. 

  529. connect_debug_port u_ila_0/probe13 [get_nets [list {spi5RxFifoCtrl[1]} {spi5RxFifoCtrl[2]} {spi5RxFifoCtrl[3]} {spi5RxFifoCtrl[4]} {spi5RxFifoCtrl[5]} {spi5RxFifoCtrl[6]} {spi5RxFifoCtrl[7]} {spi5RxFifoCtrl[8]} {spi5RxFifoCtrl[9]} {spi5RxFifoCtrl[10]} {spi5RxFifoCtrl[11]} {spi5RxFifoCtrl[12]} {spi5RxFifoCtrl[13]} {spi5RxFifoCtrl[14]} {spi5RxFifoCtrl[15]}]]
    530. 

  530. create_debug_port u_ila_0 probe
    531. 

  531. set_property PROBE_TYPE DATA [get_debug_ports u_ila_0/probe14]
    532. 

  532. set_property port_width 16 [get_debug_ports u_ila_0/probe14]
    533. 

  533. connect_debug_port u_ila_0/probe14 [get_nets [list {spi5CsCtrl[0]} {spi5CsCtrl[1]} {spi5CsCtrl[2]} {spi5CsCtrl[3]} {spi5CsCtrl[4]} {spi5CsCtrl[5]} {spi5CsCtrl[6]} {spi5CsCtrl[7]} {spi5CsCtrl[8]} {spi5CsCtrl[9]} {spi5CsCtrl[10]} {spi5CsCtrl[11]} {spi5CsCtrl[12]} {spi5CsCtrl[13]} {spi5CsCtrl[14]} {spi5CsCtrl[15]}]]
    534. 

  534. create_debug_port u_ila_0 probe
    535. 

  535. set_property PROBE_TYPE DATA [get_debug_ports u_ila_0/probe15]
    536. 

  536. set_property port_width 16 [get_debug_ports u_ila_0/probe15]
    537. 

  537. connect_debug_port u_ila_0/probe15 [get_nets [list {spi5CsDelay[0]} {spi5CsDelay[1]} {spi5CsDelay[2]} {spi5CsDelay[3]} {spi5CsDelay[4]} {spi5CsDelay[5]} {spi5CsDelay[6]} {spi5CsDelay[7]} {spi5CsDelay[8]} {spi5CsDelay[9]} {spi5CsDelay[10]} {spi5CsDelay[11]} {spi5CsDelay[12]} {spi5CsDelay[13]} {spi5CsDelay[14]} {spi5CsDelay[15]}]]
    538. 

  538. create_debug_port u_ila_0 probe
    539. 

  539. set_property PROBE_TYPE DATA [get_debug_ports u_ila_0/probe16]
    540. 

  540. set_property port_width 16 [get_debug_ports u_ila_0/probe16]
    541. 

  541. connect_debug_port u_ila_0/probe16 [get_nets [list {spi5Ctrl[0]} {spi5Ctrl[1]} {spi5Ctrl[2]} {spi5Ctrl[3]} {spi5Ctrl[4]} {spi5Ctrl[5]} {spi5Ctrl[6]} {spi5Ctrl[7]} {spi5Ctrl[8]} {spi5Ctrl[9]} {spi5Ctrl[10]} {spi5Ctrl[11]} {spi5Ctrl[12]} {spi5Ctrl[13]} {spi5Ctrl[14]} {spi5Ctrl[15]}]]
    542. 

  542. create_debug_port u_ila_0 probe
    543. 

  543. set_property PROBE_TYPE DATA [get_debug_ports u_ila_0/probe17]
    544. 

  544. set_property port_width 1 [get_debug_ports u_ila_0/probe17]
    545. 

  545. connect_debug_port u_ila_0/probe17 [get_nets [list {spi5RxFifoCtrl__0[0]}]]
    546. 

  546. create_debug_port u_ila_0 probe
    547. 

  547. set_property PROBE_TYPE DATA [get_debug_ports u_ila_0/probe18]
    548. 

  548. set_property port_width 15 [get_debug_ports u_ila_0/probe18]
    549. 

  549. connect_debug_port u_ila_0/probe18 [get_nets [list {spi5TxFifoCtrl[1]} {spi5TxFifoCtrl[2]} {spi5TxFifoCtrl[3]} {spi5TxFifoCtrl[4]} {spi5TxFifoCtrl[5]} {spi5TxFifoCtrl[6]} {spi5TxFifoCtrl[7]} {spi5TxFifoCtrl[8]} {spi5TxFifoCtrl[9]} {spi5TxFifoCtrl[10]} {spi5TxFifoCtrl[11]} {spi5TxFifoCtrl[12]} {spi5TxFifoCtrl[13]} {spi5TxFifoCtrl[14]} {spi5TxFifoCtrl[15]}]]
    550. 

  550. create_debug_port u_ila_0 probe
    551. 

  551. set_property PROBE_TYPE DATA [get_debug_ports u_ila_0/probe19]
    552. 

  552. set_property port_width 8 [get_debug_ports u_ila_0/probe19]
    553. 

  553. connect_debug_port u_ila_0/probe19 [get_nets [list {spi5Clk[0]} {spi5Clk[1]} {spi5Clk[2]} {spi5Clk[3]} {spi5Clk[4]} {spi5Clk[5]} {spi5Clk[6]} {spi5Clk[7]}]]
    554. 

  554. create_debug_port u_ila_0 probe
    555. 

  555. set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe20]
    556. 

  556. set_property port_width 2 [get_debug_ports u_ila_0/probe20]
    557. 

  557. connect_debug_port u_ila_0/probe20 [get_nets [list {SpiSubSystem[0].SpiSubSystem/DataFifoWrapper/RxFifoCtrlReg_o[1]} {SpiSubSystem[0].SpiSubSystem/DataFifoWrapper/RxFifoCtrlReg_o[2]}]]
    558. 

  558. create_debug_port u_ila_0 probe
    559. 

  559. set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe21]
    560. 

  560. set_property port_width 1 [get_debug_ports u_ila_0/probe21]
    561. 

  561. connect_debug_port u_ila_0/probe21 [get_nets [list {SpiSubSystem[0].SpiSubSystem/DataFifoWrapper/TxFifoCtrlReg_o[1]}]]
    562. 

  562. create_debug_port u_ila_0 probe
    563. 

  563. set_property PROBE_TYPE DATA [get_debug_ports u_ila_0/probe22]
    564. 

  564. set_property port_width 32 [get_debug_ports u_ila_0/probe22]
    565. 

  565. connect_debug_port u_ila_0/probe22 [get_nets [list {SpiSubSystem[0].SpiSubSystem/toSpiData[0]} {SpiSubSystem[0].SpiSubSystem/toSpiData[1]} {SpiSubSystem[0].SpiSubSystem/toSpiData[2]} {SpiSubSystem[0].SpiSubSystem/toSpiData[3]} {SpiSubSystem[0].SpiSubSystem/toSpiData[4]} {SpiSubSystem[0].SpiSubSystem/toSpiData[5]} {SpiSubSystem[0].SpiSubSystem/toSpiData[6]} {SpiSubSystem[0].SpiSubSystem/toSpiData[7]} {SpiSubSystem[0].SpiSubSystem/toSpiData[8]} {SpiSubSystem[0].SpiSubSystem/toSpiData[9]} {SpiSubSystem[0].SpiSubSystem/toSpiData[10]} {SpiSubSystem[0].SpiSubSystem/toSpiData[11]} {SpiSubSystem[0].SpiSubSystem/toSpiData[12]} {SpiSubSystem[0].SpiSubSystem/toSpiData[13]} {SpiSubSystem[0].SpiSubSystem/toSpiData[14]} {SpiSubSystem[0].SpiSubSystem/toSpiData[15]} {SpiSubSystem[0].SpiSubSystem/toSpiData[16]} {SpiSubSystem[0].SpiSubSystem/toSpiData[17]} {SpiSubSystem[0].SpiSubSystem/toSpiData[18]} {SpiSubSystem[0].SpiSubSystem/toSpiData[19]} {SpiSubSystem[0].SpiSubSystem/toSpiData[20]} {SpiSubSystem[0].SpiSubSystem/toSpiData[21]} {SpiSubSystem[0].SpiSubSystem/toSpiData[22]} {SpiSubSystem[0].SpiSubSystem/toSpiData[23]} {SpiSubSystem[0].SpiSubSystem/toSpiData[24]} {SpiSubSystem[0].SpiSubSystem/toSpiData[25]} {SpiSubSystem[0].SpiSubSystem/toSpiData[26]} {SpiSubSystem[0].SpiSubSystem/toSpiData[27]} {SpiSubSystem[0].SpiSubSystem/toSpiData[28]} {SpiSubSystem[0].SpiSubSystem/toSpiData[29]} {SpiSubSystem[0].SpiSubSystem/toSpiData[30]} {SpiSubSystem[0].SpiSubSystem/toSpiData[31]}]]
    566. 

  566. create_debug_port u_ila_0 probe
    567. 

  567. set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe23]
    568. 

  568. set_property port_width 1 [get_debug_ports u_ila_0/probe23]
    569. 

  569. connect_debug_port u_ila_0/probe23 [get_nets [list {SpiSubSystem[0].SpiSubSystem/DataFifoWrapper/EmptyFlagTx_o}]]
    570. 

  570. create_debug_port u_ila_0 probe
    571. 

  571. set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe24]
    572. 

  572. set_property port_width 1 [get_debug_ports u_ila_0/probe24]
    573. 

  573. connect_debug_port u_ila_0/probe24 [get_nets [list {SpiSubSystem[0].SpiSubSystem/mosi0Q}]]
    574. 

  574. create_debug_port u_ila_0 probe
    575. 

  575. set_property PROBE_TYPE DATA [get_debug_ports u_ila_0/probe25]
    576. 

  576. set_property port_width 1 [get_debug_ports u_ila_0/probe25]
    577. 

  577. connect_debug_port u_ila_0/probe25 [get_nets [list {SpiSubSystem[0].SpiSubSystem/Mosi1_io_IBUF}]]
    578. 

  578. create_debug_port u_ila_0 probe
    579. 

  579. set_property PROBE_TYPE DATA [get_debug_ports u_ila_0/probe26]
    580. 

  580. set_property port_width 1 [get_debug_ports u_ila_0/probe26]
    581. 

  581. connect_debug_port u_ila_0/probe26 [get_nets [list {SpiSubSystem[0].SpiSubSystem/Mosi1_io_OBUF}]]
    582. 

  582. create_debug_port u_ila_0 probe
    583. 

  583. set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe27]
    584. 

  584. set_property port_width 1 [get_debug_ports u_ila_0/probe27]
    585. 

  585. connect_debug_port u_ila_0/probe27 [get_nets [list {SpiSubSystem[0].SpiSubSystem/DataFifoWrapper/rxFifoRdEn}]]
    586. 

  586. create_debug_port u_ila_0 probe
    587. 

  587. set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe28]
    588. 

  588. set_property port_width 1 [get_debug_ports u_ila_0/probe28]
    589. 

  589. connect_debug_port u_ila_0/probe28 [get_nets [list {SpiSubSystem[0].SpiSubSystem/DataFifoWrapper/rxFifoWrEn}]]
    590. 

  590. create_debug_port u_ila_0 probe
    591. 

  591. set_property PROBE_TYPE DATA [get_debug_ports u_ila_0/probe29]
    592. 

  592. set_property port_width 1 [get_debug_ports u_ila_0/probe29]
    593. 

  593. connect_debug_port u_ila_0/probe29 [get_nets [list SmcAre_i_IBUF]]
    594. 

  594. create_debug_port u_ila_0 probe
    595. 

  595. set_property PROBE_TYPE DATA [get_debug_ports u_ila_0/probe30]
    596. 

  596. set_property port_width 1 [get_debug_ports u_ila_0/probe30]
    597. 

  597. connect_debug_port u_ila_0/probe30 [get_nets [list SmcAwe_i_IBUF]]
    598. 

  598. create_debug_port u_ila_0 probe
    599. 

  599. set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe31]
    600. 

  600. set_property port_width 1 [get_debug_ports u_ila_0/probe31]
    601. 

  601. connect_debug_port u_ila_0/probe31 [get_nets [list {SpiSubSystem[0].SpiSubSystem/spiTxEnSync}]]
    602. 

  602. create_debug_port u_ila_0 probe
    603. 

  603. set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe32]
    604. 

  604. set_property port_width 1 [get_debug_ports u_ila_0/probe32]
    605. 

  605. connect_debug_port u_ila_0/probe32 [get_nets [list {SpiSubSystem[0].SpiSubSystem/DataFifoWrapper/txFifoRdEn}]]
    606. 

  606. create_debug_port u_ila_0 probe
    607. 

  607. set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe33]
    608. 

  608. set_property port_width 1 [get_debug_ports u_ila_0/probe33]
    609. 

  609. connect_debug_port u_ila_0/probe33 [get_nets [list {SpiSubSystem[0].SpiSubSystem/DataFifoWrapper/txFifoWrEn}]]
    610. 

  610. create_debug_port u_ila_0 probe
    611. 

  611. set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe34]
    612. 

  612. set_property port_width 1 [get_debug_ports u_ila_0/probe34]
    613. 

  613. connect_debug_port u_ila_0/probe34 [get_nets [list LoCsReg_o_OBUF]]
    614. 

  614. set_clock_groups -logically_exclusive -group [get_clocks -of_objects [get_pins ClkManager/MMCM/inst/mmcm_adv_inst/CLKOUT0]] -group [get_clocks -of_objects [get_pins ClkManager/MMCM/inst/mmcm_adv_inst/CLKOUT2]] -group [get_clocks -of_objects [get_pins ClkManager/MMCM/inst/mmcm_adv_inst/CLKOUT3]] -group [get_clocks -of_objects [get_pins ClkManager/MMCM/inst/mmcm_adv_inst/CLKOUT4]] -group [get_clocks -of_objects [get_pins ClkManager/MMCM/inst/mmcm_adv_inst/CLKOUT5]] -group [get_clocks -of_objects [get_pins ClkManager/MMCM/inst/mmcm_adv_inst/CLKOUT6]]
    615. 

  615. set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub]
    616. 

  616. set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub]
    617. 

  617. set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub]
    618. 

  618. connect_debug_port dbg_hub/clk [get_nets gclk]
    619.