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- module SpiLinesMuxer (
- input SsR_i,
- input SsQ_i,
- input SckR_i,
- input SckQ_i,
- input Mosi0R_i,
- input Mosi0Q_i,
- input ChipSelFpga_i,
- input ChipSelFlash_i,
- input Assel_i,
- input SpiMode_i,
- output Ss_o,
- output SsFlash_o,
- output Sck_o,
- output Mosi0_o
- );
- //================================================================================
- // REG/WIRE
- //================================================================================
- wire ssMuxed;
- wire sckMuxed;
- wire mosi0Muxed;
- //================================================================================
- // ASSIGNMENTS
- //================================================================================
- assign sckMuxed = (SpiMode_i) ? SckQ_i : SckR_i;
- assign ssMuxed = (SpiMode_i) ? SsQ_i : SsR_i;
- assign mosi0Muxed = (SpiMode_i) ? Mosi0Q_i : Mosi0R_i;
- assign Ss_o = (Assel_i) ? (ChipSelFpga_i ? ssMuxed : 1'b1) : ChipSelFpga_i;
- assign SsFlash_o = (Assel_i) ? (ChipSelFlash_i ? ssMuxed:1'b1) : ChipSelFlash_i;
- //================================================================================
- // CODING
- //================================================================================
- endmodule
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