S5443_V3/sources_1/new/ClkManager/MmcmClkMux.v

//////////////////////////////////////////////////////////////////////////////////
// Company:         TAIR
// Engineer:        
// 
// Create Date:     10/30/2023 11:24:31 AM
// Design Name:
// Module Name:     MmcmClkMux
// Project Name:    S5443_V3_FPGA3
// Target Devices:  BOARD: BY5443v3. FPGA: xc7s25csga225-2
// Tool Versions:
// Description:     This module determines which of the MMCM should be muxed based 
//					on a input setting
// 
// Dependencies: 
// 
// Revision:
// Revision 1.0 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////

module MmcmClkMux(
	input Rst_i,
	input [2:0] clkNum,
	input Clk0_i,
	input Clk1_i,
	input Clk2_i,
	input Clk3_i,
	input Clk4_i,
	input Clk5_i,
	input Clk6_i, 
	
	output ClkOutMMCM_o
);

//================================================================================
//	REG/WIRE
//================================================================================
reg clkOutMMCMReg;

wire clkOutMMCM;

//================================================================================
//	ASSIGNMENTS
//===============================================================================
assign clkOutMMCM = clkOutMMCMReg;

//================================================================================
//	CODING
//================================================================================ 
always @(*) begin 
	if (Rst_i) begin 
		clkOutMMCMReg = 0;
	end
	else begin 
		case (clkNum) 
			0: clkOutMMCMReg = Clk0_i;
			1: clkOutMMCMReg = Clk1_i;
			2: clkOutMMCMReg = Clk2_i;
			3: clkOutMMCMReg = Clk3_i;
			4: clkOutMMCMReg = Clk4_i;
			5: clkOutMMCMReg = Clk5_i;
			6: clkOutMMCMReg = Clk6_i;
			default: clkOutMMCMReg = 0;
		endcase
	end
end

BUFG BUFG_inst (
	.O(ClkOutMMCM_o),	// 1-bit output: Clock output
	.I(clkOutMMCM)		// 1-bit input: Clock input
);

endmodule