S5443_V3/sources_1/new/RegMap/RegMap.v

module RegMap #(
    parameter CmdRegWidth = 32,
    parameter AddrRegWidth = 12
)
(
    input [CmdRegWidth/2-1:0] Data_i,
    input [AddrRegWidth-1:0] Addr_i,
	input	Val_i,
	
    input Clk_i,
    input Rst_i,
    input [1:0] SmcBe_i,
    input [CmdRegWidth-1:0] TxFifoCtrlReg0_i,
    input [CmdRegWidth-1:0] RxFifoCtrlReg0_i,
    input [CmdRegWidth-1:0] TxFifoCtrlReg1_i,
    input [CmdRegWidth-1:0] RxFifoCtrlReg1_i,
    input [CmdRegWidth-1:0] TxFifoCtrlReg2_i,
    input [CmdRegWidth-1:0] RxFifoCtrlReg2_i,
    input [CmdRegWidth-1:0] TxFifoCtrlReg3_i,
    input [CmdRegWidth-1:0] RxFifoCtrlReg3_i,
    input [CmdRegWidth-1:0] TxFifoCtrlReg4_i,
    input [CmdRegWidth-1:0] RxFifoCtrlReg4_i,
    input [CmdRegWidth-1:0] TxFifoCtrlReg5_i,
    input [CmdRegWidth-1:0] RxFifoCtrlReg5_i,
    input [CmdRegWidth-1:0] TxFifoCtrlReg6_i,
    input [CmdRegWidth-1:0] RxFifoCtrlReg6_i,

    input [6:0] LdReg_i,




    output   [CmdRegWidth/2-1:0] Spi0CtrlReg_o,
    output   [CmdRegWidth/2-1:0] Spi0ClkReg_o,
    output   [CmdRegWidth/2-1:0] Spi0CsDelayReg_o,
    output   [CmdRegWidth/2-1:0] Spi0CsCtrlReg_o,
    output   [CmdRegWidth/2-1:0] Spi0TxFifoCtrlReg_o,
    output   [CmdRegWidth/2-1:0] Spi0RxFifoCtrlReg_o,
    output   [CmdRegWidth/2-1:0] Spi0TxFifoReg_o,
    output   [CmdRegWidth/2-1:0] Spi0RxFifoReg_o,

    output   [CmdRegWidth/2-1:0] Spi1CtrlReg_o,
    output   [CmdRegWidth/2-1:0] Spi1ClkReg_o,
    output   [CmdRegWidth/2-1:0] Spi1CsDelayReg_o,
    output   [CmdRegWidth/2-1:0] Spi1CsCtrlReg_o,
    output   [CmdRegWidth/2-1:0] Spi1TxFifoCtrlReg_o,
    output   [CmdRegWidth/2-1:0] Spi1RxFifoCtrlReg_o,
    output   [CmdRegWidth/2-1:0] Spi1TxFifoReg_o,
    output   [CmdRegWidth/2-1:0] Spi1RxFifoReg_o,

    output   [CmdRegWidth/2-1:0] Spi2CtrlReg_o,
    output   [CmdRegWidth/2-1:0] Spi2ClkReg_o,
    output   [CmdRegWidth/2-1:0] Spi2CsDelayReg_o,
    output   [CmdRegWidth/2-1:0] Spi2CsCtrlReg_o,
    output   [CmdRegWidth/2-1:0] Spi2TxFifoCtrlReg_o,
    output   [CmdRegWidth/2-1:0] Spi2RxFifoCtrlReg_o,
    output   [CmdRegWidth/2-1:0] Spi2TxFifoReg_o,
    output   [CmdRegWidth/2-1:0] Spi2RxFifoReg_o,
    
    output   [CmdRegWidth/2-1:0] Spi3CtrlReg_o,
    output   [CmdRegWidth/2-1:0] Spi3ClkReg_o,
    output   [CmdRegWidth/2-1:0] Spi3CsDelayReg_o,
    output   [CmdRegWidth/2-1:0] Spi3CsCtrlReg_o,
    output   [CmdRegWidth/2-1:0] Spi3TxFifoCtrlReg_o,
    output   [CmdRegWidth/2-1:0] Spi3RxFifoCtrlReg_o,
    output   [CmdRegWidth/2-1:0] Spi3TxFifoReg_o,
    output   [CmdRegWidth/2-1:0] Spi3RxFifoReg_o,

    output   [CmdRegWidth/2-1:0] Spi4CtrlReg_o,
    output   [CmdRegWidth/2-1:0] Spi4ClkReg_o,
    output   [CmdRegWidth/2-1:0] Spi4CsDelayReg_o,
    output   [CmdRegWidth/2-1:0] Spi4CsCtrlReg_o,
    output   [CmdRegWidth/2-1:0] Spi4TxFifoCtrlReg_o,
    output   [CmdRegWidth/2-1:0] Spi4RxFifoCtrlReg_o,
    output   [CmdRegWidth/2-1:0] Spi4TxFifoReg_o,
    output   [CmdRegWidth/2-1:0] Spi4RxFifoReg_o,
    
    output   [CmdRegWidth/2-1:0] Spi5CtrlReg_o,
    output   [CmdRegWidth/2-1:0] Spi5ClkReg_o,
    output   [CmdRegWidth/2-1:0] Spi5CsDelayReg_o,
    output   [CmdRegWidth/2-1:0] Spi5CsCtrlReg_o,
    output   [CmdRegWidth/2-1:0] Spi5TxFifoCtrlReg_o,
    output   [CmdRegWidth/2-1:0] Spi5RxFifoCtrlReg_o,
    output   [CmdRegWidth/2-1:0] Spi5TxFifoReg_o,
    output   [CmdRegWidth/2-1:0] Spi5RxFifoReg_o,

    output   [CmdRegWidth/2-1:0] Spi6CtrlReg_o,
    output   [CmdRegWidth/2-1:0] Spi6ClkReg_o,
    output   [CmdRegWidth/2-1:0] Spi6CsDelayReg_o,
    output   [CmdRegWidth/2-1:0] Spi6CsCtrlReg_o,
    output   [CmdRegWidth/2-1:0] Spi6TxFifoCtrlReg_o,
    output   [CmdRegWidth/2-1:0] Spi6RxFifoCtrlReg_o,
    output   [CmdRegWidth/2-1:0] Spi6TxFifoReg_o,
    output   [CmdRegWidth/2-1:0] Spi6RxFifoReg_o,

    output   [CmdRegWidth/2-1:0] SpiTxRxEnReg_o,
    output   [CmdRegWidth-1:0] GPIOAReg_o,

    output   [CmdRegWidth/2-1:0] AnsDataReg_o,
    output Led_o

);
//================================================================================
//	REG/WIRE
//================================================================================
    reg [CmdRegWidth/2-1:0] Spi0CtrlReg; 
    reg [CmdRegWidth/2-1:0] Spi0ClkReg;
    reg [CmdRegWidth/2-1:0] Spi0CsDelayReg;
    reg [CmdRegWidth/2-1:0] Spi0CsCtrlReg;
    reg [CmdRegWidth/2-1:0] Spi0TxFifoCtrlReg;
    reg [CmdRegWidth/2-1:0] Spi0RxFifoCtrlReg;
    
    
    reg [CmdRegWidth/2-1:0] Spi1CtrlReg;
    reg [CmdRegWidth/2-1:0] Spi1ClkReg;
    reg [CmdRegWidth/2-1:0] Spi1CsDelayReg;
    reg [CmdRegWidth/2-1:0] Spi1CsCtrlReg;
    reg [CmdRegWidth/2-1:0] Spi1TxFifoCtrlReg;
    reg [CmdRegWidth/2-1:0] Spi1RxFifoCtrlReg;
    
    
    reg [CmdRegWidth/2-1:0] Spi2CtrlReg;
    reg [CmdRegWidth/2-1:0] Spi2ClkReg;
    reg [CmdRegWidth/2-1:0] Spi2CsDelayReg;
    reg [CmdRegWidth/2-1:0] Spi2CsCtrlReg;
    reg [CmdRegWidth/2-1:0] Spi2TxFifoCtrlReg;
    reg [CmdRegWidth/2-1:0] Spi2RxFifoCtrlReg;
    
    
    reg [CmdRegWidth/2-1:0] Spi3CtrlReg;
    reg [CmdRegWidth/2-1:0] Spi3ClkReg;
    reg [CmdRegWidth/2-1:0] Spi3CsDelayReg;
    reg [CmdRegWidth/2-1:0] Spi3CsCtrlReg;
    reg [CmdRegWidth/2-1:0] Spi3TxFifoCtrlReg;
    reg [CmdRegWidth/2-1:0] Spi3RxFifoCtrlReg;
    
    
    reg [CmdRegWidth/2-1:0] Spi4CtrlReg;
    reg [CmdRegWidth/2-1:0] Spi4ClkReg;
    reg [CmdRegWidth/2-1:0] Spi4CsDelayReg;
    reg [CmdRegWidth/2-1:0] Spi4CsCtrlReg;
    reg [CmdRegWidth/2-1:0] Spi4TxFifoCtrlReg;
    reg [CmdRegWidth/2-1:0] Spi4RxFifoCtrlReg;
    
    
    
    reg [CmdRegWidth/2-1:0] Spi5CtrlReg;
    reg [CmdRegWidth/2-1:0] Spi5ClkReg;
    reg [CmdRegWidth/2-1:0] Spi5CsDelayReg;
    reg [CmdRegWidth/2-1:0] Spi5CsCtrlReg;
    reg [CmdRegWidth/2-1:0] Spi5TxFifoCtrlReg;
    reg [CmdRegWidth/2-1:0] Spi5RxFifoCtrlReg;
    
    
    reg [CmdRegWidth/2-1:0] Spi6CtrlReg;
    reg [CmdRegWidth/2-1:0] Spi6ClkReg;
    reg [CmdRegWidth/2-1:0] Spi6CsDelayReg;
    reg [CmdRegWidth/2-1:0] Spi6CsCtrlReg;
    reg [CmdRegWidth/2-1:0] Spi6TxFifoCtrlReg;
    reg [CmdRegWidth/2-1:0] Spi6RxFifoCtrlReg;
    
    (* dont_touch = "yes" *)reg [CmdRegWidth/2-1:0] spiTxRxEnReg;
    reg [CmdRegWidth/2-1:0] GPIOAReg;
    reg [CmdRegWidth/2-1:0] GPIOARegS;
    
    
    (* dont_touch = "yes" *)reg [CmdRegWidth/2-1:0] ansReg;
    (* dont_touch = "yes" *)reg [CmdRegWidth/2-1:0] ledReg;
    
    reg	[1:0]	beReg;
    //================================================================================
    //	ASSIGNMENTS
    //================================================================================
    assign Spi0CtrlReg_o = Spi0CtrlReg;
    assign Spi0ClkReg_o = Spi0ClkReg;
    assign Spi0CsDelayReg_o = Spi0CsDelayReg;
    assign Spi0CsCtrlReg_o = Spi0CsCtrlReg;
    assign Spi0TxFifoCtrlReg_o = Spi0TxFifoCtrlReg;
    assign Spi0RxFifoCtrlReg_o = Spi0RxFifoCtrlReg;
    
    assign Spi1CtrlReg_o = Spi1CtrlReg;
    assign Spi1ClkReg_o = Spi1ClkReg;
    assign Spi1CsDelayReg_o = Spi1CsDelayReg;
    assign Spi1CsCtrlReg_o = Spi1CsCtrlReg;
    assign Spi1TxFifoCtrlReg_o = Spi1TxFifoCtrlReg;
    assign Spi1RxFifoCtrlReg_o = Spi1RxFifoCtrlReg;
    
    assign Spi2CtrlReg_o = Spi2CtrlReg;
    assign Spi2ClkReg_o = Spi2ClkReg;
    assign Spi2CsDelayReg_o = Spi2CsDelayReg;
    assign Spi2CsCtrlReg_o = Spi2CsCtrlReg;
    assign Spi2TxFifoCtrlReg_o = Spi2TxFifoCtrlReg;
    assign Spi2RxFifoCtrlReg_o = Spi2RxFifoCtrlReg;
    
    assign Spi3CtrlReg_o = Spi3CtrlReg;
    assign Spi3ClkReg_o = Spi3ClkReg;
    assign Spi3CsDelayReg_o = Spi3CsDelayReg;
    assign Spi3CsCtrlReg_o = Spi3CsCtrlReg;
    assign Spi3TxFifoCtrlReg_o = Spi3TxFifoCtrlReg;
    assign Spi3RxFifoCtrlReg_o = Spi3RxFifoCtrlReg;
    
    
    assign Spi4CtrlReg_o = Spi4CtrlReg;
    assign Spi4ClkReg_o = Spi4ClkReg;
    assign Spi4CsDelayReg_o = Spi4CsDelayReg;
    assign Spi4CsCtrlReg_o = Spi4CsCtrlReg;
    assign Spi4TxFifoCtrlReg_o = Spi4TxFifoCtrlReg;
    assign Spi4RxFifoCtrlReg_o = Spi4RxFifoCtrlReg;
    
    
    assign Spi5CtrlReg_o = Spi5CtrlReg;
    assign Spi5ClkReg_o = Spi5ClkReg;
    assign Spi5CsDelayReg_o = Spi5CsDelayReg;
    assign Spi5CsCtrlReg_o = Spi5CsCtrlReg;
    assign Spi5TxFifoCtrlReg_o = Spi5TxFifoCtrlReg;
    assign Spi5RxFifoCtrlReg_o = Spi5RxFifoCtrlReg;
    
    
    assign Spi6CtrlReg_o = Spi6CtrlReg;
    assign Spi6ClkReg_o = Spi6ClkReg;
    assign Spi6CsDelayReg_o = Spi6CsDelayReg;
    assign Spi6CsCtrlReg_o = Spi6CsCtrlReg;
    assign Spi6TxFifoCtrlReg_o = Spi6TxFifoCtrlReg;
    assign Spi6RxFifoCtrlReg_o = Spi6RxFifoCtrlReg;
    
    
    assign SpiTxRxEnReg_o = spiTxRxEnReg;
    assign GPIOAReg_o = {GPIOARegS, GPIOAReg};
    
    
    
    
    
    assign AnsDataReg_o = ansReg;
    assign Led_o = ledReg[0];
    //================================================================================
    //	LOCALPARAMS
    //================================================================================
    localparam Spi0CtrlAddr = 12'h00;
    localparam Spi0ClkAddr  = 12'h04;
    localparam Spi0CsDelayAddr = 12'h08;
    localparam Spi0CsCtrlAddr = 12'h0c;
    localparam Spi0TxFifoCtrlAddrLsb = 12'h10;
    localparam Spi0TxFifoCtrlAddrMsb = 12'h12;
    localparam Spi0RxFifoCtrlAddrLsb = 12'h14;
    localparam Spi0RxFifoCtrlAddrMsb = 12'h16;
    localparam Spi0TxFifo = 12'h18;
    localparam Spi0RxFifo = 12'h1c;
    
    localparam Spi1CtrlAddr = 12'h50;
    localparam Spi1ClkAddr  = 12'h54;
    localparam Spi1CsDelayAddr = 12'h58;
    localparam Spi1CsCtrlAddr = 12'h5c;
    localparam Spi1TxFifoCtrlAddrLsb = 12'h60;
    localparam Spi1TxFifoCtrlAddrMsb = 12'h62;
    localparam Spi1RxFifoCtrlAddrLsb = 12'h64;
    localparam Spi1RxFifoCtrlAddrMsb = 12'h66;
    localparam Spi1TxFifo = 12'h68;
    localparam Spi1RxFifo = 12'h6c;
    
    localparam Spi2CtrlAddr = 12'hF0;
    localparam Spi2ClkAddr  = 12'hF4;
    localparam Spi2CsDelayAddr = 12'hF8;
    localparam Spi2CsCtrlAddr = 12'hFc;
    localparam Spi2TxFifoCtrlAddrLsb = 12'h100;
    localparam Spi2TxFifoCtrlAddrMsb = 12'h102;
    localparam Spi2RxFifoCtrlAddrLsb = 12'h104;
    localparam Spi2RxFifoCtrlAddrMsb = 12'h106;
    localparam Spi2TxFifo = 12'h108;
    localparam Spi2RxFifo = 12'h10c;
    
    localparam Spi3CtrlAddr = 12'h140;
    localparam Spi3ClkAddr  = 12'h144;
    localparam Spi3CsDelayAddr = 12'h148;
    localparam Spi3CsCtrlAddr = 12'h14c;
    localparam Spi3TxFifoCtrlAddrLsb = 12'h150;
    localparam Spi3TxFifoCtrlAddrMsb = 12'h152;
    localparam Spi3RxFifoCtrlAddrLsb = 12'h154;
    localparam Spi3RxFifoCtrlAddrMsb = 12'h156;
    localparam Spi3TxFifo = 12'h158;
    localparam Spi3RxFifo = 12'h15c;
    
    localparam Spi4CtrlAddr = 12'h190;
    localparam Spi4ClkAddr  = 12'h194;
    localparam Spi4CsDelayAddr = 12'h198;
    localparam Spi4CsCtrlAddr = 12'h19c;
    localparam Spi4TxFifoCtrlAddrLsb = 12'h1a0;
    localparam Spi4TxFifoCtrlAddrMsb = 12'h1a2;
    localparam Spi4RxFifoCtrlAddrLsb = 12'h1a4;
    localparam Spi4RxFifoCtrlAddrMsb = 12'h1a6;
    localparam Spi4TxFifo = 12'h1a8;
    localparam Spi4RxFifo = 12'h1ac;
    
    localparam Spi5CtrlAddr = 12'h1e0;
    localparam Spi5ClkAddr  = 12'h1e4;
    localparam Spi5CsDelayAddr = 12'h1e8;
    localparam Spi5CsCtrlAddr = 12'h1ec;
    localparam Spi5TxFifoCtrlAddrLsb = 12'h1f0;
    localparam Spi5TxFifoCtrlAddrMsb = 12'h1f2;
    localparam Spi5RxFifoCtrlAddrLsb = 12'h1f4;
    localparam Spi5RxFifoCtrlAddrMsb = 12'h1f6;
    localparam Spi5TxFifo = 12'h1f8;
    localparam Spi5RxFifo = 12'h1fc;
    
    localparam Spi6CtrlAddr = 12'h230;
    localparam Spi6ClkAddr  = 12'h234;
    localparam Spi6CsDelayAddr = 12'h238;
    localparam Spi6CsCtrlAddr = 12'h23c;
    localparam Spi6TxFifoCtrlAddrLsb = 12'h240;
    localparam Spi6TxFifoCtrlAddrMsb = 12'h242;
    localparam Spi6RxFifoCtrlAddrLsb = 12'h244;
    localparam Spi6RxFifoCtrlAddrMsb = 12'h246;
    localparam Spi6TxFifo = 12'h248;
    localparam Spi6RxFifo = 12'h24c;
    
    localparam SpiTxRxEn = 12'hF00;
    localparam GPIOCtrlAddr = 12'hFF0;
    localparam GPIOCtrlAddrS = 12'hFF2;
    
    localparam Debug0Addr = 12'hFF8;
    localparam Debug1Addr = 12'hFFC;
    //================================================================================
    
    
    always	@(posedge	Clk_i)	begin
    	if	(!Rst_i)	begin
    		beReg	<=	2'b0;
    	end	else	begin
    		beReg	<=	SmcBe_i;
    	end
    end
    
    
    always @(posedge Clk_i) begin 
        if (Rst_i) begin 
            Spi0ClkReg <= 0;
            Spi0CtrlReg <= 0;
            Spi0CsDelayReg <= 0;
            Spi0CsCtrlReg <= 0;
            Spi0TxFifoCtrlReg <= 0;
            Spi0RxFifoCtrlReg <= 0;
            Spi1ClkReg <= 0;
            Spi1CtrlReg <= 0;
            Spi1CsDelayReg <= 0;
            Spi1CsCtrlReg <= 0;
            Spi1TxFifoCtrlReg <= 0;
            Spi1RxFifoCtrlReg <= 0;
            Spi2ClkReg <= 0;
            Spi2CtrlReg <= 0;
            Spi2CsDelayReg <= 0;
            Spi2CsCtrlReg <= 0;
            Spi2TxFifoCtrlReg <= 0;
            Spi2RxFifoCtrlReg <= 0;
            Spi3ClkReg <= 0;
            Spi3CtrlReg <= 0;
            Spi3CsDelayReg <= 0;
            Spi3CsCtrlReg <= 0;
            Spi3TxFifoCtrlReg <= 0;
            Spi3RxFifoCtrlReg <= 0;
            Spi4ClkReg <= 0;
            Spi4CtrlReg <= 0;
            Spi4CsDelayReg <= 0;
            Spi4CsCtrlReg <= 0;
            Spi4TxFifoCtrlReg <= 0;
            Spi4RxFifoCtrlReg <= 0;
            Spi5ClkReg <= 0;
            Spi5CtrlReg <= 0;
            Spi5CsDelayReg <= 0;
            Spi5CsCtrlReg <= 0;
            Spi5TxFifoCtrlReg <= 0;
            Spi5RxFifoCtrlReg <= 0;
            Spi6ClkReg <= 0;
            Spi6CtrlReg <= 0;
            Spi6CsDelayReg <= 0;
            Spi6CsCtrlReg <= 0;
            Spi6TxFifoCtrlReg <= 0;
            Spi6RxFifoCtrlReg <= 0;
            spiTxRxEnReg <= 0;
            GPIOAReg <= 0;
            GPIOARegS <= 0;
            ledReg <= 0;
        end
        else begin 
            if (Val_i) begin 
                case (beReg)  
                    0 : begin 
                        case (Addr_i) 
                            Spi0CtrlAddr : begin 
                                Spi0CtrlReg <= Data_i;
                            end
                            Spi0ClkAddr : begin 
                                Spi0ClkReg <= Data_i;
                            end
                            Spi0CsDelayAddr : begin 
                                Spi0CsDelayReg <= Data_i;
                            end
                            Spi0CsCtrlAddr : begin 
                                Spi0CsCtrlReg <= Data_i;
                            end
                            Spi0TxFifoCtrlAddrLsb : begin 
                                Spi0TxFifoCtrlReg <= Data_i;
                            end
                            Spi0RxFifoCtrlAddrLsb : begin 
                                Spi0RxFifoCtrlReg <= Data_i;
                            end
                            Spi1CtrlAddr : begin 
                                Spi1CtrlReg <= Data_i;
                            end
                            Spi1ClkAddr : begin 
                                Spi1ClkReg <= Data_i;
                            end
                            Spi1CsDelayAddr : begin 
                                Spi1CsDelayReg <= Data_i;
                            end
                            Spi1CsCtrlAddr : begin 
                                Spi1CsCtrlReg <= Data_i;
                            end
                            Spi1TxFifoCtrlAddrLsb : begin 
                                Spi1TxFifoCtrlReg <= Data_i;
                            end
                            Spi1RxFifoCtrlAddrLsb : begin 
                                Spi1RxFifoCtrlReg <= Data_i;
                            end
                            Spi2CtrlAddr : begin 
                                Spi2CtrlReg <= Data_i;
                            end
                            Spi2ClkAddr : begin 
                                Spi2ClkReg <= Data_i;
                            end
                            Spi2CsDelayAddr : begin 
                                Spi2CsDelayReg <= Data_i;
                            end
                            Spi2CsCtrlAddr : begin 
                                Spi2CsCtrlReg <= Data_i;
                            end
                            Spi2TxFifoCtrlAddrLsb : begin 
                                Spi2TxFifoCtrlReg <= Data_i;
                            end
                            Spi2RxFifoCtrlAddrLsb : begin 
                                Spi2RxFifoCtrlReg <= Data_i;
                            end
                            Spi3CtrlAddr : begin 
                                Spi3CtrlReg <= Data_i;
                            end
                            Spi3ClkAddr : begin 
                                Spi3ClkReg <= Data_i;
                            end
                            Spi3CsDelayAddr : begin 
                                Spi3CsDelayReg <= Data_i;
                            end
                            Spi3CsCtrlAddr : begin 
                                Spi3CsCtrlReg <= Data_i;
                            end
                            Spi3TxFifoCtrlAddrLsb : begin 
                                Spi3TxFifoCtrlReg <= Data_i;
                            end
                            Spi3RxFifoCtrlAddrLsb : begin 
                                Spi3RxFifoCtrlReg <= Data_i;
                            end
                            Spi4CtrlAddr : begin 
                                Spi4CtrlReg <= Data_i;
                            end
                            Spi4ClkAddr : begin 
                                Spi4ClkReg <= Data_i;
                            end
                            Spi4CsDelayAddr : begin 
                                Spi4CsDelayReg <= Data_i;
                            end
                            Spi4CsCtrlAddr : begin 
                                Spi4CsCtrlReg <= Data_i;
                            end
                            Spi4TxFifoCtrlAddrLsb : begin 
                                Spi4TxFifoCtrlReg <= Data_i;
                            end
                            Spi4RxFifoCtrlAddrLsb : begin 
                                Spi4RxFifoCtrlReg <= Data_i;
                            end
                            Spi5CtrlAddr : begin 
                                Spi5CtrlReg <= Data_i;
                            end
                            Spi5ClkAddr : begin 
                                Spi5ClkReg <= Data_i;
                            end
                            Spi5CsDelayAddr : begin 
                                Spi5CsDelayReg <= Data_i;
                            end
                            Spi5CsCtrlAddr : begin 
                                Spi5CsCtrlReg <= Data_i;
                            end
                            Spi5TxFifoCtrlAddrLsb : begin 
                                Spi5TxFifoCtrlReg <= Data_i;
                            end
                            Spi5RxFifoCtrlAddrLsb : begin 
                                Spi5RxFifoCtrlReg <= Data_i;
                            end
                            Spi6CtrlAddr : begin 
                                Spi6CtrlReg <= Data_i;
                            end
                            Spi6ClkAddr : begin 
                                Spi6ClkReg <= Data_i;
                            end
                            Spi6CsDelayAddr : begin 
                                Spi6CsDelayReg <= Data_i;
                            end
                            Spi6CsCtrlAddr : begin 
                                Spi6CsCtrlReg <= Data_i;
                            end
                            Spi6TxFifoCtrlAddrLsb : begin 
                                Spi6TxFifoCtrlReg <= Data_i;
                            end
                            Spi6RxFifoCtrlAddrLsb : begin 
                                Spi6RxFifoCtrlReg <= Data_i;
                            end
                            SpiTxRxEn : begin 
                                spiTxRxEnReg <= Data_i;
                            end
                            GPIOCtrlAddr : begin 
                                GPIOAReg <= Data_i;
                            end
                            GPIOCtrlAddrS : begin 
                                GPIOARegS <= Data_i;
                            end
                            Debug0Addr : begin 
                                ledReg <= Data_i;
                            end
                        endcase
                    end
                    1 : begin 
                        case (Addr_i)
                            Spi0CtrlAddr : begin
                                Spi0CtrlReg[15:8] <= Data_i[15:8];
                            end
                            Spi0ClkAddr : begin 
                                Spi0ClkReg[15:8] <= Data_i[15:8];
                            end
                            Spi0CsDelayAddr : begin 
                                Spi0CsDelayReg[15:8] <= Data_i[15:8];
                            end
                            Spi0CsCtrlAddr : begin 
                                Spi0CsCtrlReg[15:8] <= Data_i[15:8];
                            end
                            Spi0TxFifoCtrlAddrLsb : begin 
                                Spi0TxFifoCtrlReg[15:8] <= Data_i[15:8];
                            end
                            Spi0RxFifoCtrlAddrLsb : begin 
                                Spi0RxFifoCtrlReg[15:8] <= Data_i[15:8];
                            end
                            Spi1CtrlAddr : begin 
                                Spi1CtrlReg[15:8] <= Data_i[15:8];
                            end
                            Spi1ClkAddr : begin 
                                Spi1ClkReg[15:8] <= Data_i[15:8];
                            end
                            Spi1CsDelayAddr : begin 
                                Spi1CsDelayReg[15:8] <= Data_i[15:8];
                            end
                            Spi1CsCtrlAddr : begin 
                                Spi1CsCtrlReg[15:8] <= Data_i[15:8];
                            end
                            Spi1TxFifoCtrlAddrLsb : begin 
                                Spi1TxFifoCtrlReg[15:8] <= Data_i[15:8];
                            end
                            Spi1RxFifoCtrlAddrLsb : begin 
                                Spi1RxFifoCtrlReg[15:8] <= Data_i[15:8];
                            end
                            Spi2CtrlAddr : begin 
                                Spi2CtrlReg[15:8] <= Data_i[15:8];
                            end
                            Spi2ClkAddr : begin 
                                Spi2ClkReg[15:8] <= Data_i[15:8];
                            end
                            Spi2CsDelayAddr : begin 
                                Spi2CsDelayReg[15:8] <= Data_i[15:8];
                            end
                            Spi2CsCtrlAddr : begin 
                                Spi2CsCtrlReg[15:8] <= Data_i[15:8];
                            end
                            Spi2TxFifoCtrlAddrLsb : begin 
                                Spi2TxFifoCtrlReg[15:8] <= Data_i[15:8];
                            end
                            Spi2RxFifoCtrlAddrLsb : begin 
                                Spi2RxFifoCtrlReg[15:8] <= Data_i[15:8];
                            end
                            Spi3CtrlAddr : begin 
                                Spi3CtrlReg[15:8] <= Data_i[15:8];
                            end
                            Spi3ClkAddr : begin 
                                Spi3ClkReg[15:8] <= Data_i[15:8];
                            end
                            Spi3CsDelayAddr : begin 
                                Spi3CsDelayReg[15:8] <= Data_i[15:8];
                            end
                            Spi3CsCtrlAddr : begin 
                                Spi3CsCtrlReg[15:8] <= Data_i[15:8];
                            end
                            Spi3TxFifoCtrlAddrLsb : begin 
                                Spi3TxFifoCtrlReg[15:8] <= Data_i[15:8];
                            end
                            Spi3RxFifoCtrlAddrLsb : begin 
                                Spi3RxFifoCtrlReg[15:8] <= Data_i[15:8];
                            end
                            Spi4CtrlAddr : begin 
                                Spi4CtrlReg[15:8] <= Data_i[15:8];
                            end
                            Spi4ClkAddr : begin 
                                Spi4ClkReg[15:8] <= Data_i[15:8];
                            end
                            Spi4CsDelayAddr : begin 
                                Spi4CsDelayReg[15:8] <= Data_i[15:8];
                            end
                            Spi4CsCtrlAddr : begin 
                                Spi4CsCtrlReg[15:8] <= Data_i[15:8];
                            end
                            Spi4TxFifoCtrlAddrLsb : begin 
                                Spi4TxFifoCtrlReg[15:8] <= Data_i[15:8];
                            end
                            Spi4RxFifoCtrlAddrLsb : begin 
                                Spi4RxFifoCtrlReg[15:8] <= Data_i[15:8];
                            end
                            Spi5CtrlAddr : begin 
                                Spi5CtrlReg[15:8] <= Data_i[15:8];
                            end
                            Spi5ClkAddr : begin 
                                Spi5ClkReg[15:8] <= Data_i[15:8];
                            end
                            Spi5CsDelayAddr : begin 
                                Spi5CsDelayReg[15:8] <= Data_i[15:8];
                            end
                            Spi5CsCtrlAddr : begin 
                                Spi5CsCtrlReg[15:8] <= Data_i[15:8];
                            end
                            Spi5TxFifoCtrlAddrLsb : begin 
                                Spi5TxFifoCtrlReg[15:8] <= Data_i[15:8];
                            end
                            Spi5RxFifoCtrlAddrLsb : begin 
                                Spi5RxFifoCtrlReg[15:8] <= Data_i[15:8];
                            end
                            Spi6CtrlAddr : begin 
                                Spi6CtrlReg[15:8] <= Data_i[15:8];
                            end
                            Spi6ClkAddr : begin 
                                Spi6ClkReg[15:8] <= Data_i[15:8];
                            end
                            Spi6CsDelayAddr : begin 
                                Spi6CsDelayReg[15:8] <= Data_i[15:8];
                            end
                            Spi6CsCtrlAddr : begin 
                                Spi6CsCtrlReg[15:8] <= Data_i[15:8];
                            end
                            Spi6TxFifoCtrlAddrLsb : begin 
                                Spi6TxFifoCtrlReg[15:8] <= Data_i[15:8];
                            end
                            Spi6RxFifoCtrlAddrLsb : begin 
                                Spi6RxFifoCtrlReg[15:8] <= Data_i[15:8];
                            end
                            SpiTxRxEn : begin 
                                spiTxRxEnReg[15:8] <= Data_i[15:8];
                            end
                            GPIOCtrlAddr : begin 
                                GPIOAReg[15:8] <= Data_i[15:8];
                            end
                            GPIOCtrlAddrS : begin 
                                GPIOARegS[15:8] <= Data_i[15:8];
                            end
                            Debug0Addr : begin 
                                ledReg[15:8] <= Data_i[15:8];
                            end
                        endcase 
                    end
                    2 : begin 
                        case (Addr_i) 
                            Spi0CtrlAddr : begin 
                                Spi0CtrlReg[7:0] <= Data_i[7:0];
                            end
                            Spi0ClkAddr : begin 
                                Spi0ClkReg[7:0] <= Data_i[7:0];
                            end
                            Spi0CsDelayAddr : begin 
                                Spi0CsDelayReg[7:0] <= Data_i[7:0];
                            end
                            Spi0CsCtrlAddr : begin 
                                Spi0CsCtrlReg[7:0] <= Data_i[7:0];
                            end
                            Spi0TxFifoCtrlAddrLsb : begin 
                                Spi0TxFifoCtrlReg[7:0] <= Data_i[7:0];
                            end
                            Spi0RxFifoCtrlAddrLsb : begin 
                                Spi0RxFifoCtrlReg[7:0] <= Data_i[7:0];
                            end
                            Spi1CtrlAddr : begin 
                                Spi1CtrlReg[7:0] <= Data_i[7:0];
                            end
                            Spi1ClkAddr : begin 
                                Spi1ClkReg[7:0] <= Data_i[7:0];
                            end
                            Spi1CsDelayAddr : begin 
                                Spi1CsDelayReg[7:0] <= Data_i[7:0];
                            end
                            Spi1CsCtrlAddr : begin 
                                Spi1CsCtrlReg[7:0] <= Data_i[7:0];
                            end
                            Spi1TxFifoCtrlAddrLsb : begin 
                                Spi1TxFifoCtrlReg[7:0] <= Data_i[7:0];
                            end
                            Spi1RxFifoCtrlAddrLsb : begin 
                                Spi1RxFifoCtrlReg[7:0] <= Data_i[7:0];
                            end
                            Spi2CtrlAddr : begin 
                                Spi2CtrlReg[7:0] <= Data_i[7:0];
                            end
                            Spi2ClkAddr : begin 
                                Spi2ClkReg[7:0] <= Data_i[7:0];
                            end
                            Spi2CsDelayAddr : begin 
                                Spi2CsDelayReg[7:0] <= Data_i[7:0];
                            end
                            Spi2CsCtrlAddr : begin 
                                Spi2CsCtrlReg[7:0] <= Data_i[7:0];
                            end
                            Spi2TxFifoCtrlAddrLsb : begin 
                                Spi2TxFifoCtrlReg[7:0] <= Data_i[7:0];
                            end
                            Spi2RxFifoCtrlAddrLsb : begin 
                                Spi2RxFifoCtrlReg[7:0] <= Data_i[7:0];
                            end
                            Spi3CtrlAddr : begin 
                                Spi3CtrlReg[7:0] <= Data_i[7:0];
                            end
                            Spi3ClkAddr : begin 
                                Spi3ClkReg[7:0] <= Data_i[7:0];
                            end
                            Spi3CsDelayAddr : begin 
                                Spi3CsDelayReg[7:0] <= Data_i[7:0];
                            end
                            Spi3CsCtrlAddr : begin 
                                Spi3CsCtrlReg[7:0] <= Data_i[7:0];
                            end
                            Spi3TxFifoCtrlAddrLsb : begin 
                                Spi3TxFifoCtrlReg[7:0] <= Data_i[7:0];
                            end
                            Spi3RxFifoCtrlAddrLsb : begin 
                                Spi3RxFifoCtrlReg[7:0] <= Data_i[7:0];
                            end
                            Spi4CtrlAddr : begin 
                                Spi4CtrlReg[7:0] <= Data_i[7:0];
                            end
                            Spi4ClkAddr : begin 
                                Spi4ClkReg[7:0] <= Data_i[7:0];
                            end
                            Spi4CsDelayAddr : begin 
                                Spi4CsDelayReg[7:0] <= Data_i[7:0];
                            end
                            Spi4CsCtrlAddr : begin 
                                Spi4CsCtrlReg[7:0] <= Data_i[7:0];
                            end
                            Spi4TxFifoCtrlAddrLsb : begin 
                                Spi4TxFifoCtrlReg[7:0] <= Data_i[7:0];
                            end
                            Spi4RxFifoCtrlAddrLsb : begin 
                                Spi4RxFifoCtrlReg[7:0] <= Data_i[7:0];
                            end
                            Spi5CtrlAddr : begin 
                                Spi5CtrlReg[7:0] <= Data_i[7:0];
                            end
                            Spi5ClkAddr : begin 
                                Spi5ClkReg[7:0] <= Data_i[7:0];
                            end
                            Spi5CsDelayAddr : begin 
                                Spi5CsDelayReg[7:0] <= Data_i[7:0];
                            end
                            Spi5CsCtrlAddr : begin 
                                Spi5CsCtrlReg[7:0] <= Data_i[7:0];
                            end
                            Spi5TxFifoCtrlAddrLsb : begin 
                                Spi5TxFifoCtrlReg[7:0] <= Data_i[7:0];
                            end
                            Spi5RxFifoCtrlAddrLsb : begin 
                                Spi5RxFifoCtrlReg[7:0] <= Data_i[7:0];
                            end
                            Spi6CtrlAddr : begin 
                                Spi6CtrlReg[7:0] <= Data_i[7:0];
                            end
                            Spi6ClkAddr : begin 
                                Spi6ClkReg[7:0] <= Data_i[7:0];
                            end
                            Spi6CsDelayAddr : begin 
                                Spi6CsDelayReg[7:0] <= Data_i[7:0];
                            end
                            Spi6CsCtrlAddr : begin 
                                Spi6CsCtrlReg[7:0] <= Data_i[7:0];
                            end
                            Spi6TxFifoCtrlAddrLsb : begin 
                                Spi6TxFifoCtrlReg[7:0] <= Data_i[7:0];
                            end
                            Spi6RxFifoCtrlAddrLsb : begin 
                                Spi6RxFifoCtrlReg[7:0] <= Data_i[7:0];
                            end
                            SpiTxRxEn : begin 
                                spiTxRxEnReg[7:0] <= Data_i[7:0];
                            end
                            GPIOCtrlAddr : begin 
                                GPIOAReg[7:0] <= Data_i[7:0];
                            end
                            GPIOCtrlAddrS : begin 
                                GPIOARegS[7:0] <= Data_i[7:0];
                            end
                            Debug0Addr : begin 
                                ledReg[7:0] <= Data_i[7:0];
                            end
                        endcase
                    end
                endcase
            end
        end
    end
    
    always @(*) begin 
        if (Rst_i) begin 
            ansReg = 0;
        end	else begin
    		case (Addr_i)
    			Spi0CtrlAddr : begin 
    				ansReg = Spi0CtrlReg;
    			end
    			Spi0ClkAddr : begin 
    				ansReg = Spi0ClkReg;
    			end
    			Spi0CsDelayAddr : begin 
    				ansReg = Spi0CsDelayReg;
    			end
    			Spi0CsCtrlAddr : begin 
    				ansReg = Spi0CsCtrlReg;
    			end
    			Spi0TxFifoCtrlAddrLsb : begin 
    				ansReg = TxFifoCtrlReg0_i[15:0];
    			end
                Spi0TxFifoCtrlAddrMsb : begin 
                    ansReg = TxFifoCtrlReg0_i[31:16];
                end
    			Spi0RxFifoCtrlAddrLsb : begin 
    				ansReg = RxFifoCtrlReg0_i[15:0];
    			end
                Spi0RxFifoCtrlAddrMsb : begin 
                    ansReg = RxFifoCtrlReg0_i[31:16];
                end
    			Spi1CtrlAddr : begin 
    				ansReg = Spi1CtrlReg;
    			end
    			Spi1ClkAddr : begin 
    				ansReg = Spi1ClkReg;
    			end
    			Spi1CsDelayAddr : begin 
    				ansReg = Spi1CsDelayReg;
    			end
    			Spi1CsCtrlAddr : begin 
    				ansReg = Spi1CsCtrlReg;
    			end
    			Spi1TxFifoCtrlAddrLsb : begin 
    				ansReg = TxFifoCtrlReg1_i[15:0];
    			end
                Spi1TxFifoCtrlAddrMsb : begin 
                    ansReg = TxFifoCtrlReg1_i[31:16];
                end
    			Spi1RxFifoCtrlAddrLsb : begin 
    				ansReg = RxFifoCtrlReg1_i[15:0];
    			end
                Spi1RxFifoCtrlAddrMsb : begin 
                    ansReg = RxFifoCtrlReg1_i[31:16];
                end
    			Spi2CtrlAddr : begin 
    				ansReg = Spi2CtrlReg;
    			end
    			Spi2ClkAddr : begin 
    				ansReg = Spi2ClkReg;
    			end
    			Spi2CsDelayAddr : begin 
    				ansReg = Spi2CsDelayReg;
    			end
    			Spi2CsCtrlAddr : begin 
    				ansReg = Spi2CsCtrlReg;
    			end
    			Spi2TxFifoCtrlAddrLsb : begin 
    				ansReg = TxFifoCtrlReg2_i[15:0];
    			end
                Spi2TxFifoCtrlAddrMsb : begin 
                    ansReg = TxFifoCtrlReg2_i[31:16];
                end
    			Spi2RxFifoCtrlAddrLsb : begin 
    				ansReg = RxFifoCtrlReg2_i[15:0];
    			end
                Spi2RxFifoCtrlAddrMsb : begin 
                    ansReg = RxFifoCtrlReg2_i[31:16];
                end
    			Spi3CtrlAddr : begin 
    				ansReg = Spi3CtrlReg;
    			end
    			Spi3ClkAddr : begin 
    				ansReg = Spi3ClkReg;
    			end
    			Spi3CsDelayAddr : begin 
    				ansReg = Spi3CsDelayReg;
    			end
    			Spi3CsCtrlAddr : begin 
    				ansReg = Spi3CsCtrlReg;
    			end
    			Spi3TxFifoCtrlAddrLsb : begin 
    				ansReg = TxFifoCtrlReg3_i[15:0];
    			end
                Spi3TxFifoCtrlAddrMsb : begin 
                    ansReg = TxFifoCtrlReg3_i[31:16];
                end
    			Spi3RxFifoCtrlAddrLsb : begin 
    				ansReg = RxFifoCtrlReg3_i[15:0];
    			end
                Spi3RxFifoCtrlAddrMsb : begin 
                    ansReg = RxFifoCtrlReg3_i[31:16];
                end
    			Spi4CtrlAddr : begin 
    				ansReg = Spi4CtrlReg;
    			end
    			Spi4ClkAddr : begin 
    				ansReg = Spi4ClkReg;
    			end
    			Spi4CsDelayAddr : begin 
    				ansReg = Spi4CsDelayReg;
    			end
    			Spi4CsCtrlAddr : begin 
    				ansReg = Spi4CsCtrlReg;
    			end
    			Spi4TxFifoCtrlAddrLsb : begin 
    				ansReg = TxFifoCtrlReg4_i[15:0];
    			end
                Spi4TxFifoCtrlAddrMsb : begin 
                    ansReg = TxFifoCtrlReg4_i[31:16];
                end
    			Spi4RxFifoCtrlAddrLsb : begin 
    				ansReg = RxFifoCtrlReg4_i[15:0];
    			end
                Spi4RxFifoCtrlAddrMsb : begin 
                    ansReg = RxFifoCtrlReg4_i[31:16];
                end
    			Spi5CtrlAddr : begin 
    				ansReg = Spi5CtrlReg;
    			end
    			Spi5ClkAddr : begin 
    				ansReg = Spi5ClkReg;
    			end
    			Spi5CsDelayAddr : begin 
    				ansReg = Spi5CsDelayReg;
    			end
    			Spi5CsCtrlAddr : begin 
    				ansReg = Spi5CsCtrlReg;
    			end
    			Spi5TxFifoCtrlAddrLsb : begin 
    				ansReg = TxFifoCtrlReg5_i[15:0];
    			end
                Spi5TxFifoCtrlAddrMsb : begin 
                    ansReg = TxFifoCtrlReg5_i[31:16];
                end
    			Spi5RxFifoCtrlAddrLsb : begin 
    				ansReg = RxFifoCtrlReg5_i[15:0];
    			end
                Spi5RxFifoCtrlAddrMsb : begin 
                    ansReg = RxFifoCtrlReg5_i[31:16];
                end
    			Spi6CtrlAddr : begin 
    				ansReg = Spi6CtrlReg;
    			end
    			Spi6ClkAddr : begin 
    				ansReg = Spi6ClkReg;
    			end
    			Spi6CsDelayAddr : begin 
    				ansReg = Spi6CsDelayReg;
    			end
    			Spi6CsCtrlAddr : begin 
    				ansReg = Spi6CsCtrlReg;
    			end
    			Spi6TxFifoCtrlAddrLsb : begin 
    				ansReg = TxFifoCtrlReg6_i[15:0];
    			end
                Spi6TxFifoCtrlAddrMsb : begin 
                    ansReg = TxFifoCtrlReg6_i[31:16];
                end
    			Spi6RxFifoCtrlAddrLsb : begin 
    				ansReg = RxFifoCtrlReg6_i[15:0];
    			end
                Spi6RxFifoCtrlAddrMsb : begin 
                    ansReg = RxFifoCtrlReg6_i[31:16];
                end
    			SpiTxRxEn : begin 
    				ansReg = spiTxRxEnReg;
    			end
    			GPIOCtrlAddr : begin 
    				ansReg = GPIOAReg;
    			end
                GPIOCtrlAddrS : begin 
                    ansReg = {9'd0,LdReg_i};
                end
    			Debug0Addr : begin 
    				ansReg = ledReg;
    			end
                default : begin 
                    ansReg = 0;
                end
            endcase
        end
    end
    
    
    
    endmodule