Запущен приём 1 канала на FPGA_M на 125МГц.

S5444_M/src/src/AdcDataRx/AdcDataInterface.v

@@ -74,6 +74,9 @@ module	AdcDataInterface
     wire    [ChNum-1:0]    	adc2P;
     wire    [ChNum-1:0]    	adc2N;
 	
+	wire    [1:0]    	adc1PTest;
+    wire    [1:0]    	adc1NTest;
+
 	reg	[AdcDataWidth*2-1:0]	adc1DataSyncPipe	[2:0];
 	reg	[AdcDataWidth*2-1:0]	adc2DataSyncPipe	[2:0];
 
@@ -100,6 +103,9 @@ module	AdcDataInterface
 	assign  adc1P	= {Adc1DataDb1P_i, Adc1DataDb0P_i, Adc1DataDa1P_i, Adc1DataDa0P_i};
 	assign  adc1N	= {Adc1DataDb1N_i, Adc1DataDb0N_i, Adc1DataDa1N_i, Adc1DataDa0N_i};
 	
+	assign  adc1PTest	= {Adc1DataDa1P_i, Adc1DataDa0P_i};
+	assign  adc1NTest	= {Adc1DataDa1N_i, Adc1DataDa0N_i};
+
 	assign  adc2P	= {Adc2DataDb1P_i, Adc2DataDb0P_i, Adc2DataDa1P_i, Adc2DataDa0P_i};
 	assign  adc2N	= {Adc2DataDb1N_i, Adc2DataDb0N_i, Adc2DataDa1N_i, Adc2DataDa0N_i};
 	
@@ -166,8 +172,8 @@ top5x2_7to1_ddr_rx	Adc1Rx
 	.Locked_i	(Locked_i),
 	.clkin1_p	(Adc1FclkP_i),
 	.clkin1_n	(Adc1FclkN_i),	
-	.datain1_p	(adc1P),	
-	.datain1_n	(adc1N),	
+	.datain1_p	(adc1PTest),	
+	.datain1_n	(adc1NTest),	
 	.clkin2_p	(),	
 	.clkin2_n	(),	
 	.datain2_p	(),	
@@ -177,23 +183,23 @@ top5x2_7to1_ddr_rx	Adc1Rx
 	.DivClk_o	(Adc1RxClk)
 );
 
-top5x2_7to1_ddr_rx	Adc2Rx
-(                  
-	.reset		(Rst_i),
-	.refclkin	(RefClk_i),
-	.Locked_i	(Locked_i),
-	.clkin1_p	(Adc2FclkP_i),
-	.clkin1_n	(Adc2FclkN_i),	
-	.datain1_p	(adc2P),	
-	.datain1_n	(adc2N),	
-	.clkin2_p	(),	
-	.clkin2_n	(),	
-	.datain2_p	(),	
-	.datain2_n	(),	
-	.dummy		(),
-	.dout		(adc2Dout),
-	.DivClk_o	(Adc2RxClk)
-);
+// top5x2_7to1_ddr_rx	Adc2Rx
+// (                  
+// 	.reset		(Rst_i),
+// 	.refclkin	(RefClk_i),
+// 	.Locked_i	(Locked_i),
+// 	.clkin1_p	(Adc2FclkP_i),
+// 	.clkin1_n	(Adc2FclkN_i),	
+// 	.datain1_p	(adc2P),	
+// 	.datain1_n	(adc2N),	
+// 	.clkin2_p	(),	
+// 	.clkin2_n	(),	
+// 	.datain2_p	(),	
+// 	.datain2_n	(),	
+// 	.dummy		(),
+// 	.dout		(adc2Dout),
+// 	.DivClk_o	(Adc2RxClk)
+// );
 
 // AdcSync Adc1_1Sync
 // (
@@ -215,15 +221,15 @@ AdcSync Adc1Sync
 	.Data_o	({adc1ChT1DataSync, adc1ChR1DataSync})
 );
 
-AdcSync Adc2Sync
-(
-    .Clk_i	(Clk_i),
-	.Rst_i	(Rst_i),
+// AdcSync Adc2Sync
+// (
+//     .Clk_i	(Clk_i),
+// 	.Rst_i	(Rst_i),
 	
-    .Data_i	(adc2Dout),
+//     .Data_i	(adc2Dout),
 	
-	.Data_o	({adc2ChR2DataSync, adc2ChT2DataSync})
-);
+// 	.Data_o	({adc2ChR2DataSync, adc2ChT2DataSync})
+// );
 
 endmodule
 

S5444_M/src/src/AdcDataRx/DDR/serdes_1_to_7_mmcm_idelay_ddr.v

@@ -242,8 +242,11 @@ else begin
    	bslip_ack_dom_ch <= bslip_ack ;
 	enable <= 1'b1 ;
    	if (enable == 1'b1) begin
-   		if (clk_iserdes_data != 7'b1100001) begin flag1 <= 1'b1 ; end else begin flag1 <= 1'b0 ; end 
-   		if (clk_iserdes_data != 7'b1100011) begin flag2 <= 1'b1 ; end else begin flag2 <= 1'b0 ; end
+   		// if (clk_iserdes_data != 7'b1100001) begin flag1 <= 1'b1 ; end else begin flag1 <= 1'b0 ; end 
+   		// if (clk_iserdes_data != 7'b1100011) begin flag2 <= 1'b1 ; end else begin flag2 <= 1'b0 ; end
+   		if (clk_iserdes_data != 7'b1111111) begin flag1 <= 1'b1 ; end else begin flag1 <= 1'b0 ; end
+   		if (clk_iserdes_data != 7'b0000000) begin flag2 <= 1'b1 ; end else begin flag2 <= 1'b0 ; end
+
      		if (bsstate == 0) begin
    			if (flag1 == 1'b1 && flag2 == 1'b1) begin
      		   		bslipreq <= 1'b1 ;					// bitslip needed
@@ -397,6 +400,7 @@ assign status[6] = 1'b1 ;
 MMCME2_ADV #(
       	.BANDWIDTH		("OPTIMIZED"),  		
       	.CLKFBOUT_MULT_F	(14),       			
+      	// .CLKFBOUT_MULT_F	(28),       			
       	.CLKFBOUT_PHASE		(0.0),     			
       	.CLKIN1_PERIOD		(CLKIN_PERIOD),  		
       	.CLKIN2_PERIOD		(CLKIN_PERIOD),  		

S5444_M/src/src/AdcDataRx/DDR/top5x2_7to1_ddr_rx.v

@@ -58,7 +58,7 @@
 
 module top5x2_7to1_ddr_rx 
 #(
-	parameter	integer	D	=	4,		// Set the number of outputs per channel to be 5 in this example
+	parameter	integer	D	=	2,		// Set the number of outputs per channel to be 5 in this example
 	parameter	integer	N	=	1,       // Set the number of channels to be 2 in this example
 	parameter	DataWidth	=	14
 )
@@ -136,7 +136,8 @@ n_x_serdes_1_to_7_mmcm_idelay_ddr #(
  	.HIGH_PERFORMANCE_MODE 	("FALSE"),
     .D			(D),				// Number of data lines
     .REF_FREQ		(200.0),			// Set idelay control reference frequency
-    .CLKIN_PERIOD		(16.600),			// Set input clock period
+    .CLKIN_PERIOD		(16.000),			// Set input clock period
+    // .CLKIN_PERIOD		(40.000),			// Set input clock period
     .MMCM_MODE		(1),				// Parameter to set multiplier for MMCM to get VCO in correct operating range. 1 multiplies input clock by 7, 2 multiplies clock by 14, etc
 	.DIFF_TERM		("TRUE"),
 	.DATA_FORMAT 		("PER_CHANL"))  		// PER_CLOCK or PER_CHANL data formatting
@@ -145,7 +146,7 @@ rx0 (
 	.clkin_n   		(clkin_n),
 	.datain_p     		(datain_p),
 	.datain_n     		(datain_n),
-	.enable_phase_detector	(1'b1),				// enable phase detector operation
+	.enable_phase_detector	(1'b0),				// enable phase detector operation
 	.enable_monitor		(1'b0),				// enables data eye monitoring
 	.dcd_correct		(1'b0),				// enables clock duty cycle correction
 	.rxclk    		(),