Актуализирован проект для FPGA_S.

S5444_M/src/src/Sim/S5443TopPulseProfileTb.v

@@ -548,9 +548,7 @@ always	@(posedge	Clk41)	begin
 			DspSpiData		<=	AdcCtrl;
 		end	else	if	(cmdCnt	==	99)	begin
 			DspSpiData		<=	{8'h58,24'd100};
-		end	else	if	(cmdCnt	==	100)	begin
-			DspSpiData		<=	MeasCmdFft;
-		end else	begin
+		end	else begin
 			DspSpiData	<=	32'hfffffff;
 		end
 	end	else	if	(txCurrState	==	TX)	begin

S5444_S/src/src/InternalDsp/CordicNco.v

@@ -90,10 +90,10 @@ module CordicNco
 	assign precompAngle[11] = 32'd333772;
 	assign precompAngle[12] = 32'd166886;
 	assign precompAngle[13] = 32'd83443;
-	assign precompAngle[14] = 32'd41722;
-	assign precompAngle[15] = 32'd20861;
-	assign precompAngle[16] = 32'd10430;
-	assign precompAngle[17] = 32'd5215;
+	// assign precompAngle[14] = 32'd41722;
+	// assign precompAngle[15] = 32'd20861;
+	// assign precompAngle[16] = 32'd10430;
+	// assign precompAngle[17] = 32'd5215;
 	//assign precompAngle[18] = 32'd2608;
 
 	assign	Sin_o	=	WindVal_i	?	sin_o	:	14'h0;

S5444_S/src/src/InternalDsp/Description.txt

@@ -0,0 +1,53 @@
+1. Модуль InternalDsp обертка в котором подключатся модули ЦОС системы.
+   Структура модуля следующая:
+		InternalDsp
+			MeasCtrlModule
+			WinParameters
+			Win_Calc
+			CordicNco
+				CordicRotation
+			ComplPrng
+			DspPipeline
+				SimpleMult
+				SummAcc
+				MyIntToFp
+				FpCustomMultipliter
+			AdcDataCalibration	
+
+2. Модуль ComplPrng генерирует случайную составляющую для подмешивания к полезному сигналу.
+3. Модуль CordicNco генерирует отсчеты Sin и Cos для реализации квадратурного демодулятора. Модуль реализован по алгоритму Cordic (см. в интернете).
+4. Модуль CordicRotation осуществляет поворот фазы при работе модуля CordicNco. 
+
+5. Модуль DspPipeline обертка для основных модулей ЦОС.
+   Модуль реализован в соответствии с документом Блок схема DSP S5435v4port.vsd.
+
+6. Модуль MeasCtrlModule - осуществляет контроль за запуском и остановкой измерений. Определяет режим работы системы из пришедших настроек.
+   
+7. Модуль NcoRstGen генерирует сигнал сброса для CordicNco. Каждый раз когда происходит переключение частоты ПЧ и приходит новое FreuencyTuningWord (FTW) для CordicNco, модуль отслеживает это, и послее переключеня ПЧ генерирует сброс NCO.
+8. Модуль Win_Calc генерирует цифровой фильтр для ЦОСа.
+   
+   Расчет фильтра реализован на основе приближения функции синуса полиномом 4 степени (про приближение полиномом искать в интернете).
+   Модуль может генерировать 3 вида фильтров:
+		1. Прямоугольное окно.
+		2. Sin^2 окно.
+		3. Окно Тьюки.
+   Исходя из выбранного фильтра определяется какое окно будет использоваться ЦОСом.
+   Фильтры 1Гц-300Кгц - окно Тьюки.
+   Фильтры 500КГц-2МГц - Sin^2 окно.
+   Фильтры 3МГц - 10МГц - прямоугольные окна. Прямоугольные окна подобраны по колличеству точек так, чтобы удвоенная составляющая сигнала, попадала строго в полосу подавления фильтра.
+   
+
+      
+9. Модуль WinParameters содержит таблицу с набором фильтров от 1Гц до 10МГц. Модуль выставляет на выходные линии параметры для расчета цифрового фильтра исходя из пришедшей команды.
+   Модуль выдает следующие параметры:
+		1. Фазовый инкремент.
+		2. Стартовый аргумент.
+		3. Колличество точек фильтра.
+		4. Нормировочный коэффициент фильтра.
+		5. Средний шум трассы цифрового фильтра.
+		
+10. Модуль AdcDataCalibration расчитывает постоянную составляющую в пришедшем сигнале. 
+	Алгоритм работы модуля:
+		1. Модуль накапливает в аккумуляторе выборку данных с АЦП.
+		2. Как только выборка накоплена, берется среднее значение по выборке. 
+		3. Значение выдается на выход модуля, чтобы в последствии вычесть её из полезного сигнала от АЦП.

S5444_S/src/src/InternalDsp/DspPipeline.v

@@ -11,12 +11,14 @@ module DspPipeline
 	parameter	WindNormCoefWidth	=	32,
 	parameter	WindCorrCoefWidth	=	32,
 	parameter	IntermediateWidth	=	14,
-	parameter	FracWidth			=	51
+	// parameter	FracWidth			=	51
+	parameter	FracWidth			=	32
 )
 (
     input	Clk_i,
     input	Rst_i,
     input	Val_i,
+    input	MeasWindEnd_i,
     input	StartFpConv_i,
 	
 	input	[WindCorrCoefWidth-1:0]	FilterCorrCoef_i,
@@ -35,7 +37,7 @@ module DspPipeline
 //================================================================================
 //  LOCALPARAMS
 	localparam	NormResultWidth	=	AccWidth+WindNormCoefWidth;
-	localparam	AdcWindWidth	=	37;
+	localparam	AdcWindWidth	=	18;
 //================================================================================
 //  REG/WIRE 
 	wire	[AdcWindWidth-1:0]	adcWindResult;
@@ -47,7 +49,9 @@ module DspPipeline
 	wire	adcWindCosResultVal;
 	
 	wire	[AccWidth-1:0]	AccResultI;
+	wire	resultIVal;
 	wire	[AccWidth-1:0]	AccResultQ;
+	wire	resultQVal;
 	
 	wire	[ResultWidth-1:0]	NormResultI;
 	wire	NormResultIVal;
@@ -92,7 +96,7 @@ AdcWindMult
 (
 	.Rst_i		(Rst_i),
 	.Clk_i		(Clk_i),
-	.Val_i		(valRegReg),
+	.Val_i		(Val_i),
 	.FactorA_i	(AdcData_i),
 	.FactorB_i	(Wind_i),
 	.Result_o	(adcWindResult),
@@ -143,10 +147,12 @@ SummAccQ
 (
     .Clk_i		(Clk_i),
     .Rst_i		(Rst_i),
+	.AccZeroing_i		(MeasWindEnd_i),
     .Val_i		(adcWindSinResultVal),
 	
 	.Data_i		(adcWindSinResult[53:0]),
-	.Result_o	(AccResultQ)
+	.Result_o	(AccResultQ),
+	.ResultVal_o	(resultQVal)
 );
 
 SumAcc
@@ -158,10 +164,12 @@ SummAccI
 (
     .Clk_i		(Clk_i),
     .Rst_i		(Rst_i),
+    .AccZeroing_i		(MeasWindEnd_i),
     .Val_i		(adcWindCosResultVal),
 	
 	.Data_i		(adcWindCosResult[53:0]),
-	.Result_o	(AccResultI)
+	.Result_o	(AccResultI),
+	.ResultVal_o	(resultIVal)
 );
 
 //===============================InToFpConv=======================================
@@ -178,7 +186,7 @@ QToFp32
 	.Rst_i				(Rst_i),
 	.InData_i			(AccResultQ),
 	.AverageNoizeLvl_i	(AverageNoizeLvl_i),
-	.InDataVal_i		(StartFpConv_i),
+	.InDataVal_i		(resultQVal),
 	.OutData_o			(qFp32Result),
 	.OutDataVal_o		(qFp32ResultVal)
 );
@@ -196,7 +204,7 @@ IToFp32
 	.Rst_i				(Rst_i),
 	.InData_i			(AccResultI),
 	.AverageNoizeLvl_i	(AverageNoizeLvl_i),
-	.InDataVal_i		(StartFpConv_i),
+	.InDataVal_i		(resultIVal),
 	.OutData_o			(iFp32Result),
 	.OutDataVal_o		(iFp32ResultVal)
 );

S5444_S/src/src/InternalDsp/InternalDsp.v

@@ -35,7 +35,7 @@ module InternalDsp
 	parameter	CmdDataRegWith		=	24,
 	parameter	IntermediateWidth	=	18,
 	parameter	CorrAdcDataWidth	=	20,
-	parameter	AccWidth			=	80
+	parameter	AccWidth			=	61
 )
 (
 	input	wire	Clk_i,
@@ -117,7 +117,7 @@ module InternalDsp
 	wire	[ChNum-1:0]	resultValBus;
 	
 	wire	measWind;
-	wire	measWindDelayed;
+	wire	measWindEnd;
 	wire	stopMeas;
 	wire	[1:0]	tukeyCtrl;
 	
@@ -228,9 +228,9 @@ MeasCtrlModule
 	.WindPhIncStart_i		(winPhIncStart),
 	.WindArg_o				(windArg),
 		
-	.StartFpConv_o			(StartFpConv),
+	.StartFpConv_o			(),
 	.MeasWind_o				(measWind),
-	.MeasWindDel_o			(measWindDelayed),
+	.MeasWindEnd_o			(measWindEnd),
 	.StopMeas_o				(stopMeas),
 	.MeasEnd_o				(MeasEnd_o),
 	.WinCtrl_o				(winCtrl),
@@ -264,7 +264,6 @@ WinParameters
 Win_calc	WinCalcInst
 (
 	.clk_i			(Clk_i),
-	.wind_clk		(WindCalcClk_i),
 	.filterCmd_i	(measCtrlReg[15-:8]),
 	.reset_i		(Rst_i),
 	.WinCtrl_i		(winCtrl),
@@ -294,7 +293,7 @@ CordicNco
 #(	
 	.ODatWidth	(NcoWidth),
 	.PhIncWidth	(WindNcoPhIncWidth),
-	.IterNum	(15),
+	.IterNum	(13),
 	.EnSinN		(0)
 )
 ncoInst
@@ -368,7 +367,8 @@ generate
 			.Clk_i				(Clk_i),
 			.Rst_i				(Rst_i),
 			.Val_i				(measWind),
-			.StartFpConv_i		(StartFpConv),
+			.MeasWindEnd_i		(measWindEnd),
+			.StartFpConv_i		(measWindEnd),
 			
 			.FilterCorrCoef_i	({filterCorrCoefHReg[0+:WindNcoPhIncWidth-CmdDataRegWith],filterCorrCoefLReg}),
 			// .FilterCorrCoef_i	(32'h3f800000),

S5444_S/src/src/InternalDsp/MeasCtrlModule.v

@@ -44,7 +44,7 @@ module MeasCtrlModule
 	
 	output	StartFpConv_o,
 	output	MeasWind_o,
-	output	MeasWindDel_o,
+	output	MeasWindEnd_o,
 	output	StopMeas_o,
 	output	MeasEnd_o,
 	output	WinCtrl_o,
@@ -105,11 +105,14 @@ module MeasCtrlModule
 	wire	wideFilterFlag	=	(FilterCmd_i>=8'h54	&	FilterCmd_i!=8'h70);
 	
 	reg		sampleStrobeGenRst;
+	
+	wire	measWindOr	=	(measWind|measWindR);
 //================================================================================
 //  ASSIGNMENTS
 	assign	StartFpConv_o			=	startFpConvPipe	[2];
-	assign	MeasWind_o				=	measWind;
-	assign	MeasWindDel_o			=	measWindR;
+	// assign	MeasWind_o				=	measWind;
+	assign	MeasWind_o				=	measWindOr;
+	assign	MeasWindEnd_o			=	measWindEnd;
 	assign	StopMeas_o				=	pMeasEnd;
 	assign	MeasEnd_o				=	stopMeasCmd;
 	assign	WindArg_o				=	windArg;
@@ -173,7 +176,7 @@ module MeasCtrlModule
 	always	@(posedge	Clk_i)	begin
 		if	(!Rst_i)	begin
 			if	(measWindR)	begin
-				if	(pNumCnt	==	WindPointsNum_i-1)	begin
+				if	(pNumCnt	==	WindPointsNum_i-2)	begin
 					measWindEnd	<=	1'b1;
 				end	else	begin
 					measWindEnd	<=	1'b0;

S5444_S/src/src/InternalDsp/Win_calc.v

@@ -21,7 +21,6 @@
 //////////////////////////////////////////////////////////////////////////////////
 module Win_calc	(
 	input			clk_i,
-	input			wind_clk,
 	input	[7:0]	filterCmd_i,
 	input			reset_i,
 	input			WinCtrl_i,
@@ -29,20 +28,32 @@ module Win_calc	(
 	input	[1:0]	TukeyCtrl_i,
 	input	[31:0]	win_value_i,
 	input	[2:0]	win_type_i,	
-	output	signed [17:0]	win_o
+	output	signed [17:0]	win_o,
+	output	reg	signed [17:0]	sinWin_o
 );
+
 //================================================================================
-//  REG/WIRE
+//  PARAMETERS
 //================================================================================
+	localparam	signed	A3_1	=	18'h15584;
+// ????????? ??? ?????????? SIN
+	localparam signed	[17:0]	A1	=	18'h12400;			// a-1
+	localparam signed	[17:0]	A2	=	18'h002C0;			// b
+	localparam signed	[17:0]	A3	=	~A3_1	+	1'b1;	// c
+	localparam signed	[17:0]	A4	=	18'h0126C;			// d
+	localparam signed	[17:0]	A5	=	18'h01C5C;			// e
 	
-	reg			[3:0]	calc_cycle;
-	reg	signed	[17:0]	a1;		
-	reg signed	[17:0]	b; 	
-	reg signed	[17:0]	c1;
-	reg signed	[17:0]	c2;	
-	wire 		[47:0]	p2;
-	wire 		[47:0]	p1;	
+	localparam	CalcWidth			=	10;
+	localparam	CalcWidthR			=	18;
+	localparam	b2Width				=	CalcWidth*2;
+	localparam	b3Width				=	CalcWidth*3;
+	localparam	b4Width				=	CalcWidth*4;
+	localparam	b5Width				=	CalcWidth*5;
 	
+	localparam [31:0]	testArg	=	32'h12492492;
+//================================================================================
+//  REG/WIRE
+//================================================================================
 	reg			signed	[17:0]	sinWind;
 	reg			signed	[17:0]	tukeyWind;	
 		
@@ -52,13 +63,11 @@ module Win_calc	(
 	reg	[35:0]	sinWindPow2;
 	
 	wire	sinFilterFlag	=	(filterCmd_i>=8'h54	&	filterCmd_i<=8'h62);
-	// wire	rectFilterFlag	=	(filterCmd_i>=8'h63	&	filterCmd_i!=8'h70)|filterCmd_i==8'h30;
 	wire	rectFilterFlag	=	(filterCmd_i>=8'h63	&	filterCmd_i!=8'h70);
 	
-	wire	[17:0]	bSin	=	win_value_i[31]	?	18'h3FFFF	-	win_value_i[31:14]	:	win_value_i	[31:14];
-	wire	[17:0]	bTukey	=	win_value_i[31]	?	18'h3FFFF	-	win_value_i[31:14]	:	win_value_i	[31:14];
+	wire	[CalcWidth-1:0]	bCurr	=	win_value_i[31]	?	10'h3FF	-	win_value_i[31-:CalcWidth]	:	win_value_i	[31-:CalcWidth];
 	
-	wire	[17:0]	bCurr	=	sinFilterFlag	?	bSin:bTukey;
+	wire	[CalcWidthR-1:0]	bNew	=	win_value_i[31]	?	18'h3FFFF	-	win_value_i[31:14]	:	win_value_i	[31:14];
 	
 	wire	signed	[17:0]	constOne	=	18'b011111111111111111;
 	
@@ -68,32 +77,63 @@ module Win_calc	(
 	
 	wire	signed [17:0]	windMux1;
 	wire	signed [17:0]	windMux2;
-//================================================================================
-//  PARAMETERS
-//================================================================================
-	localparam	signed	A3_1	=	18'h15584;
-// ????????? ??? ?????????? SIN
-	localparam signed	[17:0]	A1	=	18'h12400;			// a-1
-	localparam signed	[17:0]	A2	=	18'h002C0;			// b
-	localparam signed	[17:0]	A3	=	~A3_1	+	1'b1;	// c
-	localparam signed	[17:0]	A4	=	18'h0126C;			// d
-	localparam signed	[17:0]	A5	=	18'h01C5C;			// e
 	
+	wire	signed	[b2Width-1:0]	b2	=	bCurr**2;
+	wire	signed	[b3Width-1:0]	b3	=	bCurr**3;
+	wire	signed	[b4Width-1:0]	b4	=	bCurr**4;
+	wire	signed	[b5Width-1:0]	b5	=	bCurr**5;
+	
+	wire	signed	[CalcWidthR-1:0]	b2Cut	=	b2[b2Width-2-:CalcWidthR];
+	wire	signed	[CalcWidthR-1:0]	b3Cut	=	b3[b3Width-3-:CalcWidthR];
+	wire	signed	[CalcWidthR-1:0]	b4Cut	=	b4[b4Width-4-:CalcWidthR];
+	wire	signed	[CalcWidthR-1:0]	b5Cut	=	b5[b5Width-5-:CalcWidthR];
+	
+	reg		signed	[CalcWidthR*2-1:0]	a1b;
+	reg		signed	[CalcWidthR*2-1:0]	a2b2;
+	reg		signed	[CalcWidthR*2-1:0]	a3b3;
+	reg		signed	[CalcWidthR*2-1:0]	a4b4;
+	reg		signed	[CalcWidthR*2-1:0]	a5b5;
+	
+	wire	signed	[CalcWidthR-1:0]	a1bCut	=	a1b	[CalcWidthR*2-2-:CalcWidthR];
+	wire	signed	[CalcWidthR-1:0]	a2b2Cut	=	a2b2[CalcWidthR*2-2-:CalcWidthR];
+	wire	signed	[CalcWidthR-1:0]	a3b3Cut	=	a3b3[CalcWidthR*2-2-:CalcWidthR];
+	wire	signed	[CalcWidthR-1:0]	a4b4Cut	=	a4b4[CalcWidthR*2-2-:CalcWidthR];
+	wire	signed	[CalcWidthR-1:0]	a5b5Cut	=	a5b5[CalcWidthR*2-2-:CalcWidthR];
+	
+	reg		signed	[CalcWidthR-1:0]	bPrevSh;
+		
+	wire	signed	[CalcWidthR-1:0]	approxSin	=	a5b5Cut+a4b4Cut+a3b3Cut+a2b2Cut+a1bCut+bPrevSh;	
+	
+	wire	signed	[CalcWidthR-1:0]	resultSin	=	approxSin[17]?	18'h1ffff:approxSin;
 //================================================================================
 //  ASSIGNMENTS
 // ================================================================================	
-
-	// assign	win_o	=	(sinFilterFlag)	?	sinWindPow2[34-:18]:tukeyWindOut;
-	
-	assign	win_o		=	windMux2;
 	
 	assign	windMux1	=	(sinFilterFlag)	?	sinWindPow2[34-:18]:tukeyWindOut;
 	assign	windMux2	=	(rectFilterFlag)?	18'h1ffff:windMux1;
 
+	assign	win_o		=	windMux2;
 // ================================================================================
 //  CODING
 //================================================================================	
 
+always	@(posedge	clk_i)	begin
+	if	(!reset_i)	begin
+		a5b5	<=	A5*b5Cut;
+		a4b4	<=	A4*b4Cut;
+		a3b3	<=	A3*b3Cut;
+		a2b2	<=	A2*b2Cut;
+		a1b		<=	A1*bNew;
+		bPrevSh	<=	bNew;
+	end	else	begin
+		a5b5	<=	0;
+		a4b4	<=	0;
+		a3b3	<=	0;
+		a2b2	<=	0;
+		a1b		<=	0;
+		bPrevSh	<=	0;
+	end
+end
 
 always	@(posedge	clk_i)	begin
 	if	(!reset_i)	begin
@@ -105,19 +145,19 @@ always	@(posedge	clk_i)	begin
 	end
 end
 
-always	@(posedge	clk_i)	begin
+always	@(*)	begin
 	if	(!reset_i)	begin
-		tukeyCorr	<=	(tukeyWind+constOne);
-		sinWindPow2	<=	sinWind**2;
+		tukeyCorr	=	(tukeyWind+constOne);
+		sinWindPow2	=	resultSin**2;
 	end	else	begin
-		tukeyCorr	<=	18'h0;
-		sinWindPow2	<=	18'h0;
+		tukeyCorr	=	18'h0;
+		sinWindPow2	=	18'h0;
 	end
 end
 
 always	@(*)	begin
 	if	(!reset_i)	begin
-		case(tukeyCtrlRR)
+		case(tukeyCtrlR)
 			2'h0:		begin
 							tukeyWindOut	=	0;
 						end
@@ -136,304 +176,20 @@ always	@(*)	begin
 	end
 end
 
-always	@(negedge	wind_clk)	begin
-	if	(!reset_i)	begin
-		// if	(MeasWind_i)	begin
-			case	(calc_cycle)
-				4'd1: 	
-						begin
-							a1	<=	A5;
-							c1	<=	A4;
-							c2	<=	A3;
-							b	<=	bCurr;
-						end
-						
-				4'd2:	
-						begin
-							a1	<=	p2[34:17];
-							c1	<=	A2;
-							c2	<=	A1;
-						end
-				4'd3:	
-						begin
-							a1	<=	p2[34:17];
-							c1	<=	b;
-						end
-			endcase
-		// end	else	begin
-			// a1	<=	18'b0;
-			// c1	<=	18'b0;
-			// c2	<=	18'b0;
-			// b	<=	18'b0;
-		// end
-	end	else	begin
-		a1	<=	18'b0;
-		c1	<=	18'b0;
-		c2	<=	18'b0;
-		b	<=	18'b0;
-	end
-end
-
-// always	@(*)	begin
-	// if	(!reset_i)	begin
-		// if	(MeasWind_i)	begin
-			// case	(calc_cycle)
-				// 3'd1: 	
-						// begin
-							// a1	=	A5;
-							// c1	=	A4;
-							// c2	=	A3;
-							// b	=	bCurr;
-						// end
-			// endcase
-		// end	else	begin
-			// a1	=	18'b0;
-			// c1	=	18'b0;
-			// c2	=	18'b0;
-			// b	=	18'b0;
-		// end
-	// end	else	begin
-		// a1	=	18'b0;
-		// c1	=	18'b0;
-		// c2	=	18'b0;
-		// b	=	18'b0;
-	// end
-// end
 
-		
-always	@(posedge	wind_clk)	begin
-	if	(!reset_i)	begin
-		if	(!win_type_i)	begin 
-			if (calc_cycle	==	3'd0) begin
-				if	(p1[47:34]	==	0)	begin
-					sinWind	<=	p1[34-:18];//1.0.17	
-				end	else	begin
-					sinWind	<=	18'h1FFFF;
-				end
-				
-			end 
-		end	else	begin
-			sinWind		<=	18'h0;
-		end
-	end	else	begin
-		sinWind		<=	18'h0;
-	end
-end
-
-always	@(posedge	wind_clk)	begin
+always	@(*)	begin
 	if	(!reset_i)	begin
 		if	(!win_type_i)	begin 
-			if (calc_cycle	==	3'd0) begin
-				if	(!WinCtrl_i)	begin
-					tukeyWind	<=	p1[34-:18];
-				end	else	begin
-					tukeyWind	<=	0-p1[34-:18];
-				end
-			end 
-		end	else	begin
-			tukeyWind	<=	18'h0;
-		end
-	end	else	begin
-		tukeyWind	<=	18'h0;
-	end
-end
-
-//??????? "????? ??????? ????????". ????????  [(b*A5+A4) = p1 ? ????????????? ?????? (b*p1+A3)=p2] == 1 ????.
-
-always	@(posedge	wind_clk)	begin
-	if	(!reset_i)	begin
-		if	(MeasWind_i)	begin
-			if	(calc_cycle	!=	4'd3)	begin
-				calc_cycle	<=	calc_cycle	+	4'd1;
+			if	(!WinCtrl_i)	begin
+				tukeyWind	=	resultSin;
 			end	else	begin
-				calc_cycle	<=	4'd0;
+				tukeyWind	=	0-resultSin;
 			end
 		end	else	begin
-			calc_cycle	<=	4'd0;
+			tukeyWind	=	18'h0;
 		end
 	end	else	begin
-		calc_cycle	<=	4'd0;
+		tukeyWind	=	18'h0;
 	end
 end
-
-DSP48E1 #(
-      // Feature Control Attributes: Data Path Selection
-      .A_INPUT("DIRECT"),               // Selects A input source, "DIRECT" (A port) or "CASCADE" (ACIN port)
-      .B_INPUT("DIRECT"),               // Selects B input source, "DIRECT" (B port) or "CASCADE" (BCIN port)
-      .USE_DPORT("FALSE"),              // Select D port usage (TRUE or FALSE)
-      .USE_MULT("MULTIPLY"),            // Select multiplier usage ("MULTIPLY", "DYNAMIC", or "NONE")
-      .USE_SIMD("ONE48"),               // SIMD selection ("ONE48", "TWO24", "FOUR12")
-      // Pattern Detector Attributes: Pattern Detection Configuration
-      .AUTORESET_PATDET("NO_RESET"),    // "NO_RESET", "RESET_MATCH", "RESET_NOT_MATCH" 
-      .MASK(48'h3fffffffffff),          // 48-bit mask value for pattern detect (1=ignore)
-      .PATTERN(48'h000000000000),       // 48-bit pattern match for pattern detect
-      .SEL_MASK("MASK"),                // "C", "MASK", "ROUNDING_MODE1", "ROUNDING_MODE2" 
-      .SEL_PATTERN("PATTERN"),          // Select pattern value ("PATTERN" or "C")
-      .USE_PATTERN_DETECT("NO_PATDET"), // Enable pattern detect ("PATDET" or "NO_PATDET")
-      // Register Control Attributes: Pipeline Register Configuration
-      .ACASCREG(0),                     // Number of pipeline stages between A/ACIN and ACOUT (0, 1 or 2)
-      .ADREG(0),                        // Number of pipeline stages for pre-adder (0 or 1)
-      .ALUMODEREG(0),                   // Number of pipeline stages for ALUMODE (0 or 1)
-      .AREG(0),                         // Number of pipeline stages for A (0, 1 or 2)
-      .BCASCREG(0),                     // Number of pipeline stages between B/BCIN and BCOUT (0, 1 or 2)
-      .BREG(0),                         // Number of pipeline stages for B (0, 1 or 2)
-      .CARRYINREG(0),                   // Number of pipeline stages for CARRYIN (0 or 1)
-      .CARRYINSELREG(0),                // Number of pipeline stages for CARRYINSEL (0 or 1)
-      .CREG(0),                         // Number of pipeline stages for C (0 or 1)
-      .DREG(0),                         // Number of pipeline stages for D (0 or 1)
-      .INMODEREG(0),                    // Number of pipeline stages for INMODE (0 or 1)
-      .MREG(0),                         // Number of multiplier pipeline stages (0 or 1)
-      .OPMODEREG(0),                    // Number of pipeline stages for OPMODE (0 or 1)
-      .PREG(1)                          // Number of pipeline stages for P (0 or 1)
-   )
-FirstStage (
-      // Cascade: 30-bit (each) output: Cascade Ports
-      .ACOUT(),                   // 30-bit output: A port cascade output
-      .BCOUT(),                   // 18-bit output: B port cascade output
-      .CARRYCASCOUT(),     // 1-bit output: Cascade carry output
-      .MULTSIGNOUT(),       // 1-bit output: Multiplier sign cascade output
-      .PCOUT(),                   // 48-bit output: Cascade output
-      // Control: 1-bit (each) output: Control Inputs/Status Bits
-      .OVERFLOW(),             // 1-bit output: Overflow in add/acc output
-      .PATTERNBDETECT(), // 1-bit output: Pattern bar detect output
-      .PATTERNDETECT(),   // 1-bit output: Pattern detect output
-      .UNDERFLOW(),           // 1-bit output: Underflow in add/acc output
-      // Data: 4-bit (each) output: Data Ports
-      .CARRYOUT(),             // 4-bit output: Carry output
-      .P(p1),                           // 48-bit output: Primary data output
-      // Cascade: 30-bit (each) input: Cascade Ports
-      .ACIN(),                     // 30-bit input: A cascade data input
-      .BCIN(),                     // 18-bit input: B cascade input
-      .CARRYCASCIN(),       // 1-bit input: Cascade carry input
-      .MULTSIGNIN(),         // 1-bit input: Multiplier sign input
-      .PCIN(48'b0),                     // 48-bit input: P cascade input
-      // Control: 4-bit (each) input: Control Inputs/Status Bits
-      .ALUMODE(4'b0000),               // 4-bit input: ALU control input
-      .CARRYINSEL(3'b000),         // 3-bit input: Carry select input
-      // .CLK(1'b0),                       // 1-bit input: Clock input
-      .CLK(wind_clk),                       // 1-bit input: Clock input
-      .INMODE(5'b00000),                 // 5-bit input: INMODE control input
-      .OPMODE(7'b0110101),                 // 7-bit input: Operation mode input
-      // Data: 30-bit (each) input: Data Ports
-      .A({{12{a1[17]}},a1}),                           // 30-bit input: A data input
-      .B(b),                           // 18-bit input: B data input
-      .C({ {13{c1[17]}}, c1[17:0],17'b0 }),                           // 48-bit input: C data input
-      .CARRYIN(1'b0),               // 1-bit input: Carry input signal
-      .D(25'b0),                           // 25-bit input: D data input
-      // Reset/Clock Enable: 1-bit (each) input: Reset/Clock Enable Inputs
-      .CEA1(1'b1),                     // 1-bit input: Clock enable input for 1st stage AREG
-      .CEA2(1'b1),                     // 1-bit input: Clock enable input for 2nd stage AREG
-      .CEAD(1'b1),                     // 1-bit input: Clock enable input for ADREG
-      .CEALUMODE(1'b1),           // 1-bit input: Clock enable input for ALUMODE
-      .CEB1(1'b1),                     // 1-bit input: Clock enable input for 1st stage BREG
-      .CEB2(1'b1),                     // 1-bit input: Clock enable input for 2nd stage BREG
-      .CEC(1'b1),                       // 1-bit input: Clock enable input for CREG
-      .CECARRYIN(1'b1),           // 1-bit input: Clock enable input for CARRYINREG
-      .CECTRL(1'b1),                 // 1-bit input: Clock enable input for OPMODEREG and CARRYINSELREG
-      .CED(1'b1),                       // 1-bit input: Clock enable input for DREG
-      .CEINMODE(1'b1),             // 1-bit input: Clock enable input for INMODEREG
-      .CEM(1'b0),                       // 1-bit input: Clock enable input for MREG
-      .CEP(1'b1),                       // 1-bit input: Clock enable input for PREG
-      .RSTA(1'b0),                     // 1-bit input: Reset input for AREG
-      .RSTALLCARRYIN(1'b0),   // 1-bit input: Reset input for CARRYINREG
-      .RSTALUMODE(1'b0),         // 1-bit input: Reset input for ALUMODEREG
-      .RSTB(1'b0),                     // 1-bit input: Reset input for BREG
-      .RSTC(1'b0),                     // 1-bit input: Reset input for CREG
-      .RSTCTRL(1'b0),               // 1-bit input: Reset input for OPMODEREG and CARRYINSELREG
-      .RSTD(1'b0),                     // 1-bit input: Reset input for DREG and ADREG
-      .RSTINMODE(1'b0),           // 1-bit input: Reset input for INMODEREG
-      .RSTM(reset_i),                     // 1-bit input: Reset input for MREG
-      .RSTP(reset_i)                      // 1-bit input: Reset input for PREG
-);
-   
-DSP48E1 #(
-      // Feature Control Attributes: Data Path Selection
-      .A_INPUT("DIRECT"),               // Selects A input source, "DIRECT" (A port) or "CASCADE" (ACIN port)
-      .B_INPUT("DIRECT"),               // Selects B input source, "DIRECT" (B port) or "CASCADE" (BCIN port)
-      .USE_DPORT("FALSE"),              // Select D port usage (TRUE or FALSE)
-      .USE_MULT("MULTIPLY"),            // Select multiplier usage ("MULTIPLY", "DYNAMIC", or "NONE")
-      .USE_SIMD("ONE48"),               // SIMD selection ("ONE48", "TWO24", "FOUR12")
-      // Pattern Detector Attributes: Pattern Detection Configuration
-      .AUTORESET_PATDET("NO_RESET"),    // "NO_RESET", "RESET_MATCH", "RESET_NOT_MATCH" 
-      .MASK(48'h1),          // 48-bit mask value for pattern detect (1=ignore)
-      .PATTERN(48'h000000000000),       // 48-bit pattern match for pattern detect
-      .SEL_MASK("MASK"),                // "C", "MASK", "ROUNDING_MODE1", "ROUNDING_MODE2" 
-      .SEL_PATTERN("PATTERN"),          // Select pattern value ("PATTERN" or "C")
-      .USE_PATTERN_DETECT("NO_PATDET"), // Enable pattern detect ("PATDET" or "NO_PATDET")
-      // Register Control Attributes: Pipeline Register Configuration
-      .ACASCREG(0),                     // Number of pipeline stages between A/ACIN and ACOUT (0, 1 or 2)
-      .ADREG(0),                        // Number of pipeline stages for pre-adder (0 or 1)
-      .ALUMODEREG(0),                   // Number of pipeline stages for ALUMODE (0 or 1)
-      .AREG(0),                         // Number of pipeline stages for A (0, 1 or 2)
-      .BCASCREG(0),                     // Number of pipeline stages between B/BCIN and BCOUT (0, 1 or 2)
-      .BREG(0),                         // Number of pipeline stages for B (0, 1 or 2)
-      .CARRYINREG(0),                   // Number of pipeline stages for CARRYIN (0 or 1)
-      .CARRYINSELREG(0),                // Number of pipeline stages for CARRYINSEL (0 or 1)
-      .CREG(0),                         // Number of pipeline stages for C (0 or 1)
-      .DREG(0),                         // Number of pipeline stages for D (0 or 1)
-      .INMODEREG(0),                    // Number of pipeline stages for INMODE (0 or 1)
-      .MREG(0),                         // Number of multiplier pipeline stages (0 or 1)
-      .OPMODEREG(0),                    // Number of pipeline stages for OPMODE (0 or 1)
-      .PREG(0)                          // Number of pipeline stages for P (0 or 1)
-   )
-SecondStage (
-      // Cascade: 30-bit (each) output: Cascade Ports
-      .ACOUT(),                   // 30-bit output: A port cascade output
-      .BCOUT(),                   // 18-bit output: B port cascade output
-      .CARRYCASCOUT(),     // 1-bit output: Cascade carry output
-      .MULTSIGNOUT(),       // 1-bit output: Multiplier sign cascade output
-      .PCOUT(),                   // 48-bit output: Cascade output
-      // Control: 1-bit (each) output: Control Inputs/Status Bits
-      .OVERFLOW(),             // 1-bit output: Overflow in add/acc output
-      .PATTERNBDETECT(), // 1-bit output: Pattern bar detect output
-      .PATTERNDETECT(),   // 1-bit output: Pattern detect output
-      .UNDERFLOW(),           // 1-bit output: Underflow in add/acc output
-      // Data: 4-bit (each) output: Data Ports
-      .CARRYOUT(),             // 4-bit output: Carry output
-      .P(p2),                           // 48-bit output: Primary data output
-      // Cascade: 30-bit (each) input: Cascade Ports
-      .ACIN(),                     // 30-bit input: A cascade data input
-      .BCIN(),                     // 18-bit input: B cascade input
-      .CARRYCASCIN(),       // 1-bit input: Cascade carry input
-      .MULTSIGNIN(),         // 1-bit input: Multiplier sign input
-      .PCIN(48'b0),                     // 48-bit input: P cascade input
-      // Control: 4-bit (each) input: Control Inputs/Status Bits
-      .ALUMODE(4'b0000),               // 4-bit input: ALU control input
-      .CARRYINSEL(3'b000),         // 3-bit input: Carry select input
-      .CLK(1'b0),                       // 1-bit input: Clock input
-      // .CLK(wind_clk),                       // 1-bit input: Clock input
-      .INMODE(5'b00000),                 // 5-bit input: INMODE control input
-      .OPMODE(7'b0110101),                 // 7-bit input: Operation mode input
-      // Data: 30-bit (each) input: Data Ports
-      .A({{12{p1[47]}},p1[34:17]}),                           // 30-bit input: A data input
-      .B(b),                           // 18-bit input: B data input
-      .C({ {13{c2[17]}}, c2[17:0],17'b0 }),                           // 48-bit input: C data input
-      .CARRYIN(1'b0),               // 1-bit input: Carry input signal
-      .D(25'b0),                           // 25-bit input: D data input
-      // Reset/Clock Enable: 1-bit (each) input: Reset/Clock Enable Inputs
-      .CEA1(1'b1),                     // 1-bit input: Clock enable input for 1st stage AREG
-      .CEA2(1'b1),                     // 1-bit input: Clock enable input for 2nd stage AREG
-      .CEAD(1'b1),                     // 1-bit input: Clock enable input for ADREG
-      .CEALUMODE(1'b1),           // 1-bit input: Clock enable input for ALUMODE
-      .CEB1(1'b1),                     // 1-bit input: Clock enable input for 1st stage BREG
-      .CEB2(1'b1),                     // 1-bit input: Clock enable input for 2nd stage BREG
-      .CEC(1'b1),                       // 1-bit input: Clock enable input for CREG
-      .CECARRYIN(1'b1),           // 1-bit input: Clock enable input for CARRYINREG
-      .CECTRL(1'b1),                 // 1-bit input: Clock enable input for OPMODEREG and CARRYINSELREG
-      .CED(1'b1),                       // 1-bit input: Clock enable input for DREG
-      .CEINMODE(1'b1),             // 1-bit input: Clock enable input for INMODEREG
-      .CEM(1'b0),                       // 1-bit input: Clock enable input for MREG
-      .CEP(1'b0),                       // 1-bit input: Clock enable input for PREG
-      .RSTA(1'b0),                     // 1-bit input: Reset input for AREG
-      .RSTALLCARRYIN(1'b0),   // 1-bit input: Reset input for CARRYINREG
-      .RSTALUMODE(1'b0),         // 1-bit input: Reset input for ALUMODEREG
-      .RSTB(1'b0),                     // 1-bit input: Reset input for BREG
-      .RSTC(1'b0),                     // 1-bit input: Reset input for CREG
-      .RSTCTRL(1'b0),               // 1-bit input: Reset input for OPMODEREG and CARRYINSELREG
-      .RSTD(1'b0),                     // 1-bit input: Reset input for DREG and ADREG
-      .RSTINMODE(1'b0),           // 1-bit input: Reset input for INMODEREG
-      .RSTM(reset_i),                     // 1-bit input: Reset input for MREG
-      .RSTP(reset_i)                      // 1-bit input: Reset input for PREG
-);
-
 endmodule

S5444_S/src/src/Math/SumAcc.v

@@ -7,6 +7,7 @@ module SumAcc
     input	Clk_i,
     input	Rst_i,
     input	Val_i,
+    input	AccZeroing_i,
 	input	[IDataWidth-1:0]	Data_i,
 	
 	output	[ODataWidth-1:0]	Result_o,
@@ -22,22 +23,41 @@ module SumAcc
 	reg		resultVal;
 	wire	[ODataWidth-1:0]	extData	=	{{(ODataWidth - IDataWidth){Data_i[IDataWidth-1]}}, Data_i};	//sign extension
 	
+	reg		accZeroing;
+	reg		accZeroingR;
+	reg		accZeroingRR;
 //================================================================================
 //  ASSIGNMENTS
 	assign	Result_o	=	dataAcc;
 	assign	ResultVal_o	=	resultVal;
 //================================================================================
 //  CODING
+
+	always	@(posedge	Clk_i)	begin
+		if	(Rst_i)	begin
+			accZeroing		<=	0;
+			accZeroingR		<=	0;
+			accZeroingRR		<=	0;
+		end	else	begin
+			accZeroing		<=	AccZeroing_i;
+			accZeroingR		<=	accZeroing;
+			accZeroingRR	<=	accZeroingR;
+		end
+	end
+	
 	always	@(posedge	Clk_i)	begin
 		if	(Rst_i)	begin
 			dataAcc		<=	{ODataWidth{1'b0}};
-			resultVal	<=	1'b0;
 		end	else	if	(Val_i)	begin
-			dataAcc		<=	dataAcc+extData;
-			resultVal	<=	Val_i;
+			if	(!accZeroingRR)	begin
+				dataAcc		<=	dataAcc+extData;
+			end	else	begin
+				dataAcc		<=	0+extData;
+			end
+		resultVal	<=	accZeroingR;
 		end	else	begin
 			dataAcc		<=	0;
-			resultVal	<=	1'b0;
+			resultVal	<=	0;
 		end
 	end
 

S5444_S/src/src/PulseMeas/PulseGenNew.v

@@ -0,0 +1,340 @@
+//`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    10:02:35 04/20/2020 
+// Design Name: 
+// Module Name:    PulseGen 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module	PulseGenNew	
+#(	
+	parameter	CmdRegWidth	=	32
+)
+(
+	input	Rst_i,
+	input	Clk_i,
+	input	EnPulse_i,
+	
+	input	PulsePol_i,
+	input	EnEdge_i,
+	input	[CmdRegWidth-29:0]	Mode_i,
+	input	[CmdRegWidth-1:0]	P1Del_i,
+	input	[CmdRegWidth-1:0]	P2Del_i,
+	input	[CmdRegWidth-1:0]	P3Del_i,
+	input	[CmdRegWidth-1:0]	P1Width_i,
+	input	[CmdRegWidth-1:0]	P2Width_i,
+	input	[CmdRegWidth-1:0]	P3Width_i,
+	
+	output	Pulse_o
+);	
+
+//================================================================================
+//  LOCALPARAM
+
+	localparam	IDLE	=	2'h0;
+	localparam	DELAY	=	2'h1;
+	localparam	PULSE	=	2'h2;
+	
+	localparam	DISABLED	=	8'd0;
+	localparam	SINGLE		=	8'd1;
+	localparam	DOUBLE		=	8'd2;
+	localparam	TRIPPLE		=	8'd3;
+	localparam	BURST		=	8'd4;
+	localparam	CONTINIOUS	=	8'd5;
+	
+//================================================================================
+	reg		pulse;
+	wire	[31:0]	delArray	[2:0];
+	wire	[31:0]	widthArray	[2:0];
+	
+	reg	[31:0]	pulseCnt;
+	reg	[31:0]	delayCnt;
+	reg	[31:0]	widthCnt;
+	
+	reg	[31:0]	currWidthValue;
+	reg	[31:0]	currDelValue;
+
+	reg	[1:0]	currState;
+	reg	[1:0]	nextState;
+	
+	reg		pulseDone;	
+	reg		delayDone;	
+	// wire	delayDone	=	(currState	==	DELAY)?	delayCnt==currDelValue-1:1'b0;	
+	
+	// wire	zeroDelay	=	(P1Del_i==0||P1Del_i==1);
+	wire	zeroDelay	=	(P1Del_i==0);
+	wire	singleDelay	=	(P1Del_i==1);
+	
+	reg	patternDone;
+
+	reg	enPulseR;
+	
+	wire	enPulsePos	=	(!enPulseR&EnPulse_i);
+	wire	enPulseNeg	=	(enPulseR&!EnPulse_i);
+	
+	wire	enPulse		=	(EnEdge_i)?	enPulseNeg:enPulsePos;
+	wire	enPulseEn	=	(Mode_i	!=	0)?	enPulse:1'b0;
+//================================================================================
+//  ASSIGNMENTS
+	assign	delArray	[0]	=	P1Del_i;
+	assign	delArray	[1]	=	P2Del_i;
+	assign	delArray	[2]	=	P3Del_i;
+	
+	assign	widthArray	[0]	=	P1Width_i;
+	assign	widthArray	[1]	=	P2Width_i;
+	assign	widthArray	[2]	=	P3Width_i;
+	
+	assign	Pulse_o	=	(PulsePol_i)?	~pulse:pulse;
+
+//================================================================================
+//  CODING
+
+always	@(*)	begin
+	if	(!Rst_i)	begin
+		if	(Mode_i==0)	begin
+			delayDone=1'b0;
+		end	else	if	(Mode_i	>=1 & Mode_i<=3)	begin
+			delayDone=(delayCnt==currDelValue-2);
+		end	else	begin
+			delayDone=(delayCnt==currDelValue-1);
+		end
+	end	else	begin
+		delayDone=1'b0;
+	end
+end
+always	@(posedge	Clk_i)	begin
+	if	(!Rst_i)	begin
+		enPulseR	<=	EnPulse_i;
+	end	else	begin
+		enPulseR	<=	1'b0;
+	end
+end
+
+always	@(posedge	Clk_i)	begin
+	if	(!Rst_i)	begin
+		if	(Mode_i	>=1 & Mode_i<=3)	begin	
+			if	(currState	!=	IDLE)	begin
+				delayCnt	<=	delayCnt+1;
+			end	else	begin
+				delayCnt	<=	0;
+			end
+		end	else	begin
+			if	(currState	==	DELAY)	begin
+				delayCnt	<=	delayCnt+1;
+			end	else	begin
+				delayCnt	<=	0;
+			end
+		end
+	end	else	begin
+		delayCnt	<=	0;
+	end
+end
+
+always	@(posedge	Clk_i)	begin
+	if	(!Rst_i)	begin
+		if	(pulse)	begin
+			widthCnt	<=	widthCnt+1;
+		end	else	begin
+			widthCnt	<=	0;
+		end
+	end	else	begin
+		widthCnt	<=	0;
+	end
+end
+
+always	@(*)	begin
+	if	(!Rst_i)	begin
+		if	(pulse)	begin
+			if	(widthCnt==currWidthValue-1)	begin
+				pulseDone	=	1'b1;
+			end	else	begin
+				pulseDone	=	1'b0;
+			end
+		end	else	begin
+			pulseDone	=	1'b0;
+		end
+	end	else	begin
+		pulseDone	=	1'b0;
+	end
+end
+
+always	@(posedge	Clk_i)	begin
+	if	(!Rst_i)	begin
+		if	(pulseDone)	begin
+			if	(!patternDone)	begin
+				pulseCnt	<=	pulseCnt+1;
+			end	else	begin
+				pulseCnt	<=	0;
+			end
+		end
+	end	else	begin
+		pulseCnt	<=	0;
+	end
+end
+
+always	@(*)	begin
+	if	(!Rst_i)	begin
+		if	(Mode_i	==	0)	begin
+				currDelValue	=	0;
+				currWidthValue	=	0;
+		end	else	begin
+			if	(Mode_i	>=1 & Mode_i<=3)	begin
+				currDelValue	=	delArray[pulseCnt];
+				currWidthValue	=	widthArray[pulseCnt];
+			end	else	begin
+				if	(Mode_i	==	4|Mode_i	==	5)	begin
+					if	(pulseCnt==0)	begin
+						currDelValue	=	delArray[0];
+						currWidthValue	=	widthArray[0];
+					end	else	begin
+						currDelValue	=	delArray[1];
+						currWidthValue	=	widthArray[0];
+					end	
+				end
+			end
+		end
+	end	else	begin
+		currDelValue	=	0;
+		currWidthValue	=	0;
+	end
+end
+
+always	@(*)	begin
+	if	(!Rst_i)	begin
+		// if	(currState	!=	IDLE)	begin
+			case(Mode_i)
+				8'd0:	begin
+							patternDone	=	0;
+						end
+				8'd1:	begin
+							patternDone	=	((pulseCnt==Mode_i-1)&pulseDone);
+						end
+				8'd2:	begin
+							patternDone	=	((pulseCnt==Mode_i-1)&pulseDone);
+						end
+				8'd3:	begin
+							patternDone	=	((pulseCnt==Mode_i-1)&pulseDone);
+						end
+				8'd4:	begin
+							patternDone	=	((pulseCnt==P2Width_i-1)&pulseDone);
+						end
+				8'd5:	begin
+							patternDone	=	0;
+						end
+				default	:begin
+							patternDone	=	0;
+						end
+			endcase
+		// end	else	begin
+			// patternDone	=	0;
+		// end
+	end	else	begin
+		patternDone	=	0;
+	end
+end
+
+	
+always	@(posedge	Clk_i)	begin
+	if	(!Rst_i)	begin
+		currState	<=	nextState;
+	end	else	begin
+		currState	<=	IDLE;
+	end
+end
+
+always	@(*)	begin
+	nextState	=	IDLE;
+	case(currState)
+	IDLE	:	begin
+					if (enPulseEn)	begin
+						if	(zeroDelay)	begin
+							if	(currWidthValue==1)	begin
+								nextState = DELAY;
+							end	else begin
+								nextState = PULSE;
+							end
+						end	else	if	(singleDelay)	begin
+							nextState	=	PULSE;
+						end	else	begin
+							nextState	=	DELAY;
+						end
+					end	else	begin
+						nextState = IDLE;
+					end
+				end
+				
+	DELAY	:	begin
+					if	(delayDone)	begin
+						nextState = PULSE;
+					end	else begin
+						nextState = DELAY;
+					end
+				end
+
+	PULSE	:	begin
+					if	(pulseDone)	begin
+						if	(!patternDone)	begin
+							nextState  = DELAY;
+						end	else begin
+							nextState  = IDLE;
+						end
+					end	else	begin
+						nextState  = PULSE;
+					end
+				end
+	endcase
+end
+
+always	@(*)	begin
+	if	(!Rst_i)	begin
+		if	(Mode_i	!=	0)	begin
+			case(currState)
+				IDLE:	begin
+							if	(zeroDelay&enPulseEn)	begin
+								pulse	=	1'b1;
+							end	else	begin
+								pulse	=	1'b0;
+							end
+						end
+				DELAY:	begin
+							pulse	=	1'b0;
+						end
+				PULSE:	begin
+							pulse	=	1'b1;
+						end
+				default:begin
+							pulse	=	1'b0;
+						end
+			endcase
+		end	else	begin
+			pulse	=	1'b0;
+		end	
+	end	else	begin
+		pulse	=	1'b0;
+	end
+end
+
+endmodule
+
+
+
+
+
+
+
+
+
+
+

S5444_S/src/src/Top/S5443Top.v

@@ -1061,14 +1061,14 @@ PulseGenMux
 	.MuxOut_o		(pgMuxedOut[j])
 );	
 
-PulseGen
+PulseGenNew
 #(	
 	.CmdRegWidth	(CmdRegWidth)
 )
 PulseGenerator
 (
-	//.Rst_i			(initRst|pGenRst[j]|pGenMeasRst[j]),
-	.Rst_i			(initRst|pGenMeasRst[j]),
+	.Rst_i			(initRst|pGenRst[j]|pGenMeasRst[j]),
+	// .Rst_i			(initRst|pGenMeasRst[j]),
 	.Clk_i			(gclk),
 	.EnPulse_i		(pgMuxedOut[j]),