Запущен приём на 125МГц на всех каналах FPGA_M. Добавлен модуль реализации окна Блэкмана.

S5444_M/src/src/AdcDataRx/AdcDataInterface.v

@@ -81,8 +81,7 @@ module	AdcDataInterface
 	reg	[AdcDataWidth*2-1:0]	adc2DataSyncPipe	[2:0];
 
 	wire	[(ChNum-2)*AdcDataWidth-1:0]	adc1Dout;
-	wire	[(ChNum-2)*AdcDataWidth-1:0]	adc1_1Dout;
-	wire	[(ChNum-2)*AdcDataWidth-1:0]	adc1_1DoutS;
+	wire	[(ChNum)*AdcDataWidth-1:0]	adcDataDout;
 	wire	[(ChNum-2)*AdcDataWidth-1:0]	adc2Dout;
 	
 	wire	[AdcDataWidth-1:0]	adc1ChAData;
@@ -102,9 +101,6 @@ module	AdcDataInterface
 	
 	assign  adc1P	= {Adc1DataDb1P_i, Adc1DataDb0P_i, Adc1DataDa1P_i, Adc1DataDa0P_i};
 	assign  adc1N	= {Adc1DataDb1N_i, Adc1DataDb0N_i, Adc1DataDa1N_i, Adc1DataDa0N_i};
-	
-	assign  adc1PTest	= {Adc1DataDa1P_i, Adc1DataDa0P_i};
-	assign  adc1NTest	= {Adc1DataDa1N_i, Adc1DataDa0N_i};
 
 	assign  adc2P	= {Adc2DataDb1P_i, Adc2DataDb0P_i, Adc2DataDa1P_i, Adc2DataDa0P_i};
 	assign  adc2N	= {Adc2DataDb1N_i, Adc2DataDb0N_i, Adc2DataDa1N_i, Adc2DataDa0N_i};
@@ -172,8 +168,8 @@ top5x2_7to1_ddr_rx	Adc1Rx
 	.Locked_i	(Locked_i),
 	.clkin1_p	(Adc1FclkP_i),
 	.clkin1_n	(Adc1FclkN_i),	
-	.datain1_p	(adc1PTest),	
-	.datain1_n	(adc1NTest),	
+	.datain1_p	(adc1P),	
+	.datain1_n	(adc1N),	
 	.clkin2_p	(),	
 	.clkin2_n	(),	
 	.datain2_p	(),	
@@ -183,33 +179,25 @@ top5x2_7to1_ddr_rx	Adc1Rx
 	.DivClk_o	(Adc1RxClk)
 );
 
-// top5x2_7to1_ddr_rx	Adc2Rx
-// (                  
-// 	.reset		(Rst_i),
-// 	.refclkin	(RefClk_i),
-// 	.Locked_i	(Locked_i),
-// 	.clkin1_p	(Adc2FclkP_i),
-// 	.clkin1_n	(Adc2FclkN_i),	
-// 	.datain1_p	(adc2P),	
-// 	.datain1_n	(adc2N),	
-// 	.clkin2_p	(),	
-// 	.clkin2_n	(),	
-// 	.datain2_p	(),	
-// 	.datain2_n	(),	
-// 	.dummy		(),
-// 	.dout		(adc2Dout),
-// 	.DivClk_o	(Adc2RxClk)
-// );
+top5x2_7to1_ddr_rx	Adc2Rx
+(                  
+	.reset		(Rst_i),
+	.refclkin	(RefClk_i),
+	.Locked_i	(Locked_i),
+	.clkin1_p	(Adc2FclkP_i),
+	.clkin1_n	(Adc2FclkN_i),	
+	.datain1_p	(adc2P),	
+	.datain1_n	(adc2N),	
+	.clkin2_p	(),	
+	.clkin2_n	(),	
+	.datain2_p	(),	
+	.datain2_n	(),	
+	.dummy		(),
+	.dout		(adc2Dout),
+	.DivClk_o	(Adc2RxClk)
+);
+
 
-// AdcSync Adc1_1Sync
-// (
-//     .Clk_i	(Clk_i),
-// 	.Rst_i	(Rst_i),
-	
-//     .Data_i	(adc1_1Dout),
-	
-// 	.Data_o	(adc1_1DoutS)
-// );
 
 AdcSync Adc1Sync
 (
@@ -221,15 +209,15 @@ AdcSync Adc1Sync
 	.Data_o	({adc1ChT1DataSync, adc1ChR1DataSync})
 );
 
-// AdcSync Adc2Sync
-// (
-//     .Clk_i	(Clk_i),
-// 	.Rst_i	(Rst_i),
+AdcSync Adc2Sync
+(
+    .Clk_i	(Clk_i),
+	.Rst_i	(Rst_i),
 	
-//     .Data_i	(adc2Dout),
+    .Data_i	(adc2Dout),
 	
-// 	.Data_o	({adc2ChR2DataSync, adc2ChT2DataSync})
-// );
+	.Data_o	({adc2ChR2DataSync, adc2ChT2DataSync})
+);
 
 endmodule
 

S5444_M/src/src/AdcDataRx/AdcSync.v

@@ -1,21 +1,22 @@
 module AdcSync 
 #(	
+	parameter	ChNum	=	2,
 	parameter	AdcDataWidth	=	14
 )
 (
     input	Clk_i,
 	input	Rst_i,
 	
-    input	[AdcDataWidth*2-1:0]	Data_i,
+    input	[AdcDataWidth*ChNum-1:0]	Data_i,
 	
-	output	[AdcDataWidth*2-1:0]	Data_o
+	output	[AdcDataWidth*ChNum-1:0]	Data_o
 );
 
 //================================================================================
 //  REG/WIRE
 //================================================================================
 
-	reg	[AdcDataWidth*2-1:0]	adcDataSyncPipe	[2:0];
+	reg	[AdcDataWidth*ChNum-1:0]	adcDataSyncPipe	[2:0];
 	integer i;
 
 //================================================================================

S5444_M/src/src/AdcDataRx/DDR/serdes_1_to_7_slave_idelay_ddr.v

@@ -188,8 +188,12 @@ else begin
    	bslip_ack_dom_ch <= bslip_ack ;
 	enable <= 1'b1 ;
    	if (enable == 1'b1) begin
-   		if (clk_iserdes_data != 7'b1100001) begin flag1 <= 1'b1 ; end else begin flag1 <= 1'b0 ; end
-   		if (clk_iserdes_data != 7'b1100011) begin flag2 <= 1'b1 ; end else begin flag2 <= 1'b0 ; end
+   		// if (clk_iserdes_data != 7'b1100001) begin flag1 <= 1'b1 ; end else begin flag1 <= 1'b0 ; end
+   		// if (clk_iserdes_data != 7'b1100011) begin flag2 <= 1'b1 ; end else begin flag2 <= 1'b0 ; end
+
+   		if (clk_iserdes_data != 7'b1111111) begin flag1 <= 1'b1 ; end else begin flag1 <= 1'b0 ; end
+   		if (clk_iserdes_data != 7'b0000000) begin flag2 <= 1'b1 ; end else begin flag2 <= 1'b0 ; end
+
      		if (bsstate == 0) begin
    			if (flag1 == 1'b1 && flag2 == 1'b1) begin
      		   		bslipreq <= 1'b1 ;					// bitslip needed

S5444_M/src/src/AdcDataRx/DDR/top5x2_7to1_ddr_rx.v

@@ -58,7 +58,7 @@
 
 module top5x2_7to1_ddr_rx 
 #(
-	parameter	integer	D	=	2,		// Set the number of outputs per channel to be 5 in this example
+	parameter	integer	D	=	4,		// Set the number of outputs per channel to be 5 in this example
 	parameter	integer	N	=	1,       // Set the number of channels to be 2 in this example
 	parameter	DataWidth	=	14
 )
@@ -75,7 +75,7 @@ module top5x2_7to1_ddr_rx
 	input	[D-1:0]	datain2_p,	
 	input	[D-1:0]	datain2_n,			// lvds channel 2 data inputs
 	output	reg	dummy,
-	output	[27:0]	dout,
+	output	[7*D*N-1:0]	dout,
 	output	DivClk_o
 	// output	[DataWidth-1:0]	dout
 );// Dummy output for test
@@ -84,14 +84,14 @@ module top5x2_7to1_ddr_rx
 
 wire	refclkint; 		
 wire	rx_mmcm_lckdps;		
-wire	[1:0]	rx_mmcm_lckdpsbs;	
+wire	[N-1:0]	rx_mmcm_lckdpsbs;	
 wire	rxclk_div;		
-wire	clkin_p;			
-wire	clkin_n;			
+wire	[N-1:0]	clkin_p ;			
+wire	[N-1:0]	clkin_n ;			
 wire	[D*N-1:0]	datain_p;		
 wire	[D*N-1:0]	datain_n;		
 // wire	[N*DataWidth-1:0]	rxdall;			
-wire	[27:0]	rxdall;			
+wire	[7*D*N-1:0]	rxdall;			
 wire	delay_ready;		
 wire	rx_mmcm_lckd;	
 
@@ -127,6 +127,11 @@ assign	datain_n	=	datain1_n;
 assign	dout		=	rxdall;
 assign	DivClk_o	=	rxclk_div;
 
+// assign clkin_p  = {clkin2_p, clkin1_p} ;
+// assign clkin_n  = {clkin2_n, clkin1_n} ;
+// assign datain_p = {datain2_p, datain1_p} ;
+// assign datain_n = {datain2_n, datain1_n} ;
+
 n_x_serdes_1_to_7_mmcm_idelay_ddr #(
 	.N			(N),
 	.SAMPL_CLOCK		("BUF_G"),
@@ -159,7 +164,7 @@ rx0 (
 	.rx_mmcm_lckdpsbs	(rx_mmcm_lckdpsbs),
 	.clk_data  		(),
 	.rx_data		(rxdall),
-	.bit_rate_value		(16'h840),			// required bit rate value in BCD
+	.bit_rate_value		(16'h875),			// required bit rate value in BCD
 	.bit_time_value		(),
 	.status			(),
 	.eye_info		(),				// data eye monitor per line

S5444_M/src/src/ClkGen/Clk200Gen.v

@@ -14,17 +14,17 @@ wire	rxFb;
 
 PLLE2_ADV #(
       	.BANDWIDTH		("OPTIMIZED"),
-      	.CLKFBOUT_MULT		(24),
+      	.CLKFBOUT_MULT		(8),
       	.CLKFBOUT_PHASE		(0.0),
-      	.CLKIN1_PERIOD		(20),
+      	.CLKIN1_PERIOD		(8),
       	.CLKIN2_PERIOD		(),
-      	.CLKOUT0_DIVIDE		(6),
+      	.CLKOUT0_DIVIDE		(5),
       	.CLKOUT0_DUTY_CYCLE	(0.5),
       	.CLKOUT0_PHASE		(0.0),
-      	.CLKOUT1_DIVIDE		(120),
+      	.CLKOUT1_DIVIDE		(100),
       	.CLKOUT1_DUTY_CYCLE	(0.5),
       	.CLKOUT1_PHASE		(0.0),
-      	.CLKOUT2_DIVIDE		(12),
+      	.CLKOUT2_DIVIDE		(10),
       	.CLKOUT2_DUTY_CYCLE	(0.5),
       	.CLKOUT2_PHASE		(0.0),
       	.CLKOUT3_DIVIDE		(120),

S5444_M/src/src/InternalDsp/BlackmanWindCalc.sv

@@ -0,0 +1,115 @@
+`timescale 1ns / 1ps
+
+module BlackmanWindCalc 
+#(
+    parameter CALC_WIDTH = 16,
+    parameter PH_INC_WIDTH = 32
+)
+(
+    input Clk_i,
+    input [7:0] FilterCmd_i,
+    input RstN_i,
+    input MeasWind_i,
+    input [PH_INC_WIDTH-1:0] PhaseInc_i,
+    output signed [CALC_WIDTH+1:0] WinSample_o
+);
+
+
+//================================================================================
+//  PARAMETERS
+//================================================================================
+
+parameter signed [CALC_WIDTH-1:0] A0_COEFF_SCALED = 13978;
+parameter signed [CALC_WIDTH-1:0] A1_COEFF_SCALED = 16270;
+parameter signed [CALC_WIDTH-1:0] A2_COEFF_SCALED = 2518;
+
+//================================================================================
+//  REG/WIRE
+//================================================================================
+
+logic signed [CALC_WIDTH-1:0] cosValue2pi;
+logic signed [CALC_WIDTH-1:0] cosValue4pi;
+
+logic signed [CALC_WIDTH*2-1:0] a1CosMultProd;
+logic signed [CALC_WIDTH-1:0] a1CosMultProdCut;
+
+logic signed [CALC_WIDTH*2-1:0] a2CosMultProd;
+logic signed [CALC_WIDTH-1:0] a2CosMultProdCut;
+
+logic signed [CALC_WIDTH-1:0] a0a1Diff;
+
+logic signed [CALC_WIDTH-1:0] winSample;
+
+reg [PH_INC_WIDTH-1:0] phaseInc;
+
+// Адрес в таблице (верхние разряды фазы)
+wire [8:0] addr = phaseInc[31:23];
+//================================================================================
+//  ASSIGNMENTS
+//================================================================================
+
+assign WinSample_o = {{2{winSample[CALC_WIDTH-1]}},winSample};
+assign a1CosMultProd = A1_COEFF_SCALED*cosValue2pi;
+assign a1CosMultProdCut = a1CosMultProd[CALC_WIDTH*2-2-:CALC_WIDTH];
+assign a2CosMultProd = A2_COEFF_SCALED*cosValue4pi;
+assign a2CosMultProdCut = a2CosMultProd[CALC_WIDTH*2-2-:CALC_WIDTH];
+assign a0a1Diff = A0_COEFF_SCALED - a1CosMultProdCut;
+
+//================================================================================
+//  CODING 
+//================================================================================
+
+// Win sample calc
+always_ff @(posedge Clk_i or negedge RstN_i) begin
+    if(~RstN_i) begin
+       winSample <= 0;
+    end else begin
+        if (MeasWind_i) begin
+            winSample <= a0a1Diff + a2CosMultProdCut;
+        end else begin
+            winSample <= 0;
+        end
+    end
+end
+
+// phase increment regs
+always @(posedge Clk_i or negedge RstN_i) begin
+    if(~RstN_i) begin
+        phaseInc <= {PH_INC_WIDTH{1'b0}};
+    end else begin
+        if (MeasWind_i) begin
+            phaseInc <= phaseInc + PhaseInc_i;
+        end else begin
+            phaseInc <= 0;
+        end
+    end
+end
+
+SinPeriodMem SinPeriodMem (
+  .a(addr),      // input wire [8 : 0] a
+  .spo(cosValue2pi)  // output wire [15 : 0] spo
+);
+
+SinPeriodMem4pi SinPeriodMem4pi (
+  .a(addr),      // input wire [8 : 0] a
+  .spo(cosValue4pi)  // output wire [15 : 0] spo
+);
+
+endmodule
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+

S5444_M/src/src/InternalDsp/InternalDsp.v

@@ -278,6 +278,16 @@ Win_calc	WinCalcInst
 	.win_o			(wind)
 );
 
+// BlackmanWindCalc BlackmanWindCalc
+// (
+//     .Clk_i(Clk_i),
+//     .FilterCmd_i(measCtrlReg[15-:8]),
+//     .RstN_i(~Rst_i),
+//     .MeasWind_i(measWind),
+//     .PhaseInc_i(windPhInc),
+//     .WinSample_o(wind)
+// );
+
 //----------------------------------------------
 //Module generates Sin and Cos for measurement
 
@@ -293,7 +303,8 @@ ncoInst
 	.Clk_i		(Clk_i),
 	.Rst_i		(Rst_i|NcoRst_i),
 	.Val_i		(1'b1),
-	.PhaseInc_i	({ifFtwHReg[0+:WindNcoPhIncWidth-CmdDataRegWith],ifFtwLReg}),
+	// .PhaseInc_i	({ifFtwHReg[0+:WindNcoPhIncWidth-CmdDataRegWith],ifFtwLReg}),
+	.PhaseInc_i	(32'h19999999),
 	.WindVal_i	(1'b1),
 	.WinType_i	(),
 	.Wind_o		(),

S5444_M/src/src/InternalDsp/SinPeriod2pi.coe

@@ -0,0 +1,514 @@
+memory_initialization_radix = 16;
+memory_initialization_vector = 
+7fff,
+7ffd,
+7ff5,
+7fe9,
+7fd8,
+7fc1,
+7fa6,
+7f86,
+7f61,
+7f37,
+7f09,
+7ed5,
+7e9c,
+7e5f,
+7e1d,
+7dd5,
+7d89,
+7d39,
+7ce3,
+7c88,
+7c29,
+7bc5,
+7b5c,
+7aee,
+7a7c,
+7a05,
+7989,
+7909,
+7884,
+77fa,
+776b,
+76d8,
+7641,
+75a5,
+7504,
+745f,
+73b5,
+7307,
+7254,
+719d,
+70e2,
+7022,
+6f5e,
+6e96,
+6dc9,
+6cf8,
+6c23,
+6b4a,
+6a6d,
+698b,
+68a6,
+67bc,
+66cf,
+65dd,
+64e8,
+63ee,
+62f1,
+61f0,
+60eb,
+5fe3,
+5ed7,
+5dc7,
+5cb3,
+5b9c,
+5a82,
+5964,
+5842,
+571d,
+55f5,
+54c9,
+539b,
+5268,
+5133,
+4ffb,
+4ebf,
+4d81,
+4c3f,
+4afb,
+49b4,
+4869,
+471c,
+45cd,
+447a,
+4325,
+41ce,
+4073,
+3f17,
+3db8,
+3c56,
+3af2,
+398c,
+3824,
+36ba,
+354d,
+33df,
+326e,
+30fb,
+2f87,
+2e11,
+2c99,
+2b1f,
+29a3,
+2826,
+26a8,
+2528,
+23a6,
+2223,
+209f,
+1f1a,
+1d93,
+1c0b,
+1a82,
+18f9,
+176e,
+15e2,
+1455,
+12c8,
+113a,
+0fab,
+0e1c,
+0c8c,
+0afb,
+096b,
+07d9,
+0648,
+04b6,
+0324,
+0192,
+0000,
+fe6e,
+fcdc,
+fb4a,
+f9b8,
+f827,
+f696,
+f505,
+f374,
+f1e4,
+f055,
+eec6,
+ed38,
+ebab,
+ea1e,
+e892,
+e708,
+e57e,
+e3f5,
+e26d,
+e0e6,
+df61,
+dddd,
+dc5a,
+dad8,
+d958,
+d7da,
+d65d,
+d4e1,
+d367,
+d1ef,
+d079,
+cf05,
+cd92,
+cc22,
+cab3,
+c946,
+c7dc,
+c674,
+c50e,
+c3aa,
+c248,
+c0e9,
+bf8d,
+be32,
+bcdb,
+bb86,
+ba33,
+b8e4,
+b797,
+b64d,
+b505,
+b3c1,
+b27f,
+b141,
+b005,
+aecd,
+ad98,
+ac66,
+ab37,
+aa0b,
+a8e3,
+a7be,
+a69c,
+a57e,
+a464,
+a34d,
+a239,
+a129,
+a01d,
+9f15,
+9e10,
+9d0f,
+9c12,
+9b18,
+9a23,
+9931,
+9844,
+975a,
+9675,
+9593,
+94b6,
+93dd,
+9308,
+9237,
+916a,
+90a2,
+8fde,
+8f1e,
+8e63,
+8dac,
+8cf9,
+8c4b,
+8ba1,
+8afc,
+8a5b,
+89bf,
+8928,
+8895,
+8806,
+877c,
+86f7,
+8677,
+85fb,
+8584,
+8512,
+84a4,
+843b,
+83d7,
+8378,
+831d,
+82c7,
+8277,
+822b,
+81e3,
+81a1,
+8164,
+812b,
+80f7,
+80c9,
+809f,
+807a,
+805a,
+803f,
+8028,
+8017,
+800b,
+8003,
+8001,
+8003,
+800b,
+8017,
+8028,
+803f,
+805a,
+807a,
+809f,
+80c9,
+80f7,
+812b,
+8164,
+81a1,
+81e3,
+822b,
+8277,
+82c7,
+831d,
+8378,
+83d7,
+843b,
+84a4,
+8512,
+8584,
+85fb,
+8677,
+86f7,
+877c,
+8806,
+8895,
+8928,
+89bf,
+8a5b,
+8afc,
+8ba1,
+8c4b,
+8cf9,
+8dac,
+8e63,
+8f1e,
+8fde,
+90a2,
+916a,
+9237,
+9308,
+93dd,
+94b6,
+9593,
+9675,
+975a,
+9844,
+9931,
+9a23,
+9b18,
+9c12,
+9d0f,
+9e10,
+9f14,
+a01d,
+a129,
+a239,
+a34d,
+a464,
+a57e,
+a69c,
+a7be,
+a8e3,
+aa0b,
+ab37,
+ac65,
+ad97,
+aecd,
+b005,
+b141,
+b27f,
+b3c1,
+b505,
+b64c,
+b797,
+b8e4,
+ba33,
+bb86,
+bcdb,
+be32,
+bf8c,
+c0e9,
+c248,
+c3aa,
+c50d,
+c673,
+c7dc,
+c946,
+cab3,
+cc21,
+cd92,
+cf05,
+d079,
+d1ef,
+d367,
+d4e1,
+d65c,
+d7d9,
+d958,
+dad8,
+dc5a,
+dddd,
+df61,
+e0e6,
+e26d,
+e3f5,
+e57d,
+e707,
+e892,
+ea1e,
+ebab,
+ed38,
+eec6,
+f055,
+f1e4,
+f374,
+f505,
+f695,
+f827,
+f9b8,
+fb4a,
+fcdc,
+fe6e,
+0000,
+0192,
+0324,
+04b6,
+0648,
+07d9,
+096a,
+0afb,
+0c8c,
+0e1c,
+0fab,
+113a,
+12c8,
+1455,
+15e2,
+176e,
+18f8,
+1a82,
+1c0b,
+1d93,
+1f1a,
+209f,
+2223,
+23a6,
+2528,
+26a8,
+2826,
+29a3,
+2b1f,
+2c99,
+2e11,
+2f87,
+30fb,
+326e,
+33de,
+354d,
+36ba,
+3824,
+398c,
+3af2,
+3c56,
+3db8,
+3f17,
+4073,
+41cd,
+4325,
+447a,
+45cd,
+471c,
+4869,
+49b3,
+4afb,
+4c3f,
+4d81,
+4ebf,
+4ffb,
+5133,
+5268,
+539a,
+54c9,
+55f5,
+571d,
+5842,
+5964,
+5a82,
+5b9c,
+5cb3,
+5dc7,
+5ed7,
+5fe3,
+60eb,
+61f0,
+62f1,
+63ee,
+64e8,
+65dd,
+66cf,
+67bc,
+68a6,
+698b,
+6a6d,
+6b4a,
+6c23,
+6cf8,
+6dc9,
+6e96,
+6f5e,
+7022,
+70e2,
+719d,
+7254,
+7307,
+73b5,
+745f,
+7504,
+75a5,
+7641,
+76d8,
+776b,
+77fa,
+7884,
+7909,
+7989,
+7a05,
+7a7c,
+7aee,
+7b5c,
+7bc5,
+7c29,
+7c88,
+7ce3,
+7d38,
+7d89,
+7dd5,
+7e1d,
+7e5f,
+7e9c,
+7ed5,
+7f09,
+7f37,
+7f61,
+7f86,
+7fa6,
+7fc1,
+7fd8,
+7fe9,
+7ff5,
+7ffd;

S5444_M/src/src/InternalDsp/SinPeriod4pi.coe

@@ -0,0 +1,514 @@
+memory_initialization_radix = 16;
+memory_initialization_vector = 
+7fff,
+7ff5,
+7fd8,
+7fa6,
+7f61,
+7f09,
+7e9c,
+7e1d,
+7d89,
+7ce3,
+7c29,
+7b5c,
+7a7c,
+7989,
+7884,
+776b,
+7641,
+7504,
+73b5,
+7254,
+70e2,
+6f5e,
+6dc9,
+6c23,
+6a6d,
+68a6,
+66cf,
+64e8,
+62f1,
+60eb,
+5ed7,
+5cb3,
+5a82,
+5842,
+55f5,
+539b,
+5133,
+4ebf,
+4c3f,
+49b4,
+471c,
+447a,
+41ce,
+3f17,
+3c56,
+398c,
+36ba,
+33df,
+30fb,
+2e11,
+2b1f,
+2826,
+2528,
+2223,
+1f1a,
+1c0b,
+18f9,
+15e2,
+12c8,
+0fab,
+0c8c,
+096b,
+0648,
+0324,
+0000,
+fcdc,
+f9b8,
+f696,
+f374,
+f055,
+ed38,
+ea1e,
+e708,
+e3f5,
+e0e6,
+dddd,
+dad8,
+d7da,
+d4e1,
+d1ef,
+cf05,
+cc22,
+c946,
+c674,
+c3aa,
+c0e9,
+be32,
+bb86,
+b8e4,
+b64d,
+b3c1,
+b141,
+aecd,
+ac66,
+aa0b,
+a7be,
+a57e,
+a34d,
+a129,
+9f15,
+9d0f,
+9b18,
+9931,
+975a,
+9593,
+93dd,
+9237,
+90a2,
+8f1e,
+8dac,
+8c4b,
+8afc,
+89bf,
+8895,
+877c,
+8677,
+8584,
+84a4,
+83d7,
+831d,
+8277,
+81e3,
+8164,
+80f7,
+809f,
+805a,
+8028,
+800b,
+8001,
+800b,
+8028,
+805a,
+809f,
+80f7,
+8164,
+81e3,
+8277,
+831d,
+83d7,
+84a4,
+8584,
+8677,
+877c,
+8895,
+89bf,
+8afc,
+8c4b,
+8dac,
+8f1e,
+90a2,
+9237,
+93dd,
+9593,
+975a,
+9931,
+9b18,
+9d0f,
+9f14,
+a129,
+a34d,
+a57e,
+a7be,
+aa0b,
+ac65,
+aecd,
+b141,
+b3c1,
+b64c,
+b8e4,
+bb86,
+be32,
+c0e9,
+c3aa,
+c673,
+c946,
+cc21,
+cf05,
+d1ef,
+d4e1,
+d7d9,
+dad8,
+dddd,
+e0e6,
+e3f5,
+e707,
+ea1e,
+ed38,
+f055,
+f374,
+f695,
+f9b8,
+fcdc,
+0000,
+0324,
+0648,
+096a,
+0c8c,
+0fab,
+12c8,
+15e2,
+18f8,
+1c0b,
+1f1a,
+2223,
+2528,
+2826,
+2b1f,
+2e11,
+30fb,
+33de,
+36ba,
+398c,
+3c56,
+3f17,
+41cd,
+447a,
+471c,
+49b3,
+4c3f,
+4ebf,
+5133,
+539a,
+55f5,
+5842,
+5a82,
+5cb3,
+5ed7,
+60eb,
+62f1,
+64e8,
+66cf,
+68a6,
+6a6d,
+6c23,
+6dc9,
+6f5e,
+70e2,
+7254,
+73b5,
+7504,
+7641,
+776b,
+7884,
+7989,
+7a7c,
+7b5c,
+7c29,
+7ce3,
+7d89,
+7e1d,
+7e9c,
+7f09,
+7f61,
+7fa6,
+7fd8,
+7ff5,
+7fff,
+7ff5,
+7fd8,
+7fa6,
+7f61,
+7f09,
+7e9c,
+7e1d,
+7d89,
+7ce3,
+7c29,
+7b5c,
+7a7c,
+7989,
+7884,
+776b,
+7641,
+7504,
+73b5,
+7254,
+70e2,
+6f5e,
+6dc9,
+6c23,
+6a6d,
+68a6,
+66cf,
+64e8,
+62f1,
+60ec,
+5ed7,
+5cb4,
+5a82,
+5842,
+55f5,
+539b,
+5133,
+4ebf,
+4c3f,
+49b4,
+471d,
+447a,
+41ce,
+3f17,
+3c56,
+398d,
+36ba,
+33df,
+30fc,
+2e11,
+2b1f,
+2827,
+2528,
+2224,
+1f1a,
+1c0b,
+18f9,
+15e2,
+12c8,
+0fab,
+0c8c,
+096b,
+0648,
+0324,
+0000,
+fcdc,
+f9b8,
+f696,
+f374,
+f055,
+ed38,
+ea1e,
+e708,
+e3f5,
+e0e6,
+dddd,
+dad8,
+d7da,
+d4e1,
+d1f0,
+cf05,
+cc22,
+c947,
+c674,
+c3aa,
+c0e9,
+be33,
+bb86,
+b8e4,
+b64d,
+b3c1,
+b141,
+aecd,
+ac66,
+aa0b,
+a7be,
+a57e,
+a34d,
+a129,
+9f15,
+9d0f,
+9b18,
+9931,
+975a,
+9593,
+93dd,
+9237,
+90a2,
+8f1e,
+8dac,
+8c4b,
+8afc,
+89bf,
+8895,
+877d,
+8677,
+8584,
+84a4,
+83d7,
+831d,
+8277,
+81e3,
+8164,
+80f7,
+809f,
+805a,
+8028,
+800b,
+8001,
+800b,
+8028,
+805a,
+809f,
+80f7,
+8164,
+81e3,
+8277,
+831d,
+83d7,
+84a4,
+8584,
+8677,
+877c,
+8895,
+89bf,
+8afc,
+8c4b,
+8dac,
+8f1e,
+90a2,
+9237,
+93dd,
+9593,
+975a,
+9931,
+9b18,
+9d0f,
+9f14,
+a129,
+a34c,
+a57e,
+a7be,
+aa0b,
+ac65,
+aecd,
+b140,
+b3c0,
+b64c,
+b8e3,
+bb85,
+be32,
+c0e9,
+c3a9,
+c673,
+c946,
+cc21,
+cf04,
+d1ef,
+d4e1,
+d7d9,
+dad8,
+dddc,
+e0e6,
+e3f4,
+e707,
+ea1e,
+ed38,
+f055,
+f374,
+f695,
+f9b8,
+fcdc,
+0000,
+0324,
+0647,
+096a,
+0c8b,
+0fab,
+12c8,
+15e2,
+18f8,
+1c0b,
+1f19,
+2223,
+2527,
+2826,
+2b1f,
+2e10,
+30fb,
+33de,
+36b9,
+398c,
+3c56,
+3f17,
+41cd,
+447a,
+471c,
+49b3,
+4c3f,
+4ebf,
+5133,
+539a,
+55f5,
+5842,
+5a82,
+5cb3,
+5ed7,
+60eb,
+62f1,
+64e8,
+66cf,
+68a6,
+6a6d,
+6c23,
+6dc9,
+6f5e,
+70e2,
+7254,
+73b5,
+7504,
+7641,
+776b,
+7883,
+7989,
+7a7c,
+7b5c,
+7c29,
+7ce3,
+7d89,
+7e1d,
+7e9c,
+7f09,
+7f61,
+7fa6,
+7fd8,
+7ff5;

S5444_M/src/src/InternalDsp/TableSinGen.sv

@@ -0,0 +1,135 @@
+`timescale 1ns / 1ps
+
+module TableSinGen #(
+    parameter PHASE_WIDTH = 32,
+    parameter AMPLITUDE_BITS = 16,
+    parameter TABLE_SIZE = 512
+) (
+    input wire Clk_i,
+    input wire RstN_i,
+    input wire Val_i,
+    input wire [PHASE_WIDTH-1:0] PointsNum_i,
+    input wire [PHASE_WIDTH-1:0] PhaseIncr_i,
+    output reg signed [AMPLITUDE_BITS+1:0] WindSamplesOut_o,
+    output WindVal_o,
+    output FilterEnd_o
+);
+
+assign WindVal_o = winVal;
+assign FilterEnd_o = filterEnd;
+// assign WindSamplesOut_o = (WindVal_o)? winSample:0;
+assign WindSamplesOut_o = (WindVal_o)? {{2{winSample[AMPLITUDE_BITS-1]}},winSample}:0;
+
+logic signed [AMPLITUDE_BITS-1:0] cosValue2pi;
+logic signed [AMPLITUDE_BITS-1:0] cosValue4pi;
+
+parameter [AMPLITUDE_BITS-1:0] A0_COEFF_SCALED = 13978;
+parameter signed [AMPLITUDE_BITS-1:0] A1_COEFF_SCALED = 16270;
+parameter signed [AMPLITUDE_BITS-1:0] A2_COEFF_SCALED = 2518;
+
+logic signed [AMPLITUDE_BITS*2-1:0] a1CosMultProd;
+assign a1CosMultProd = A1_COEFF_SCALED*cosValue2pi;
+logic signed [AMPLITUDE_BITS-1:0] a1CosMultProdCut;
+assign a1CosMultProdCut = a1CosMultProd[AMPLITUDE_BITS*2-2-:AMPLITUDE_BITS];
+
+logic signed [AMPLITUDE_BITS*2-1:0] a2CosMultProd;
+assign a2CosMultProd = A2_COEFF_SCALED*cosValue4pi;
+logic signed [AMPLITUDE_BITS-1:0] a2CosMultProdCut;
+assign a2CosMultProdCut = a2CosMultProd[AMPLITUDE_BITS*2-2-:AMPLITUDE_BITS];
+
+logic signed [AMPLITUDE_BITS-1:0] a0a1Diff;
+assign a0a1Diff = A0_COEFF_SCALED - a1CosMultProdCut;
+
+logic signed [AMPLITUDE_BITS-1:0] winSample;
+// assign winSample = a0a1Diff + a2CosMultProdCut;
+
+// logic signed [AMPLITUDE_BITS-1:0] winSampleCorr;
+// assign winSampleCorr = winSample[AMPLITUDE_BITS-:AMPLITUDE_BITS];
+
+
+logic [31:0] pNumCnt;
+logic filterEnd;
+assign filterEnd = (pNumCnt==PointsNum_i);
+
+logic winVal;
+logic valR;
+assign winVal = (valR & !filterEnd);
+
+always_ff @(posedge Clk_i or negedge RstN_i) begin
+    if(~RstN_i) begin
+        valR <= 0;
+    end else begin
+        valR <= Val_i;
+    end
+end
+
+always_ff @(posedge Clk_i or negedge RstN_i) begin
+    if(~RstN_i) begin
+       winSample <= 0;
+    end else begin
+        if (Val_i) begin
+            winSample <= a0a1Diff + a2CosMultProdCut;
+        end else begin
+            winSample <= 0;
+        end
+    end
+end
+
+always_ff @(posedge Clk_i or negedge RstN_i) begin
+    if(~RstN_i) begin
+       pNumCnt <= 0;
+    end else begin
+        if (valR) begin
+            if (pNumCnt != PointsNum_i) begin
+                pNumCnt <= pNumCnt+1;
+            end
+        end else begin
+            pNumCnt <= 0;
+        end
+    end
+end
+// Регистры накопителей фазы
+reg [PHASE_WIDTH-1:0] phaseInc;
+always @(posedge Clk_i or negedge RstN_i) begin
+    if(~RstN_i) begin
+        phaseInc <= {PHASE_WIDTH{1'b0}};
+    end else begin
+        if (Val_i) begin
+            phaseInc <= phaseInc + PhaseIncr_i;
+        end else begin
+            phaseInc <= 0;
+        end
+    end
+end
+
+// Адрес в таблице (верхние разряды фазы)
+wire [8:0] lutAddrUpper = phaseInc[31:23];
+
+SinPeriodMem SinPeriodMem (
+  .a(lutAddrUpper),      // input wire [8 : 0] a
+  .spo(cosValue2pi)  // output wire [15 : 0] spo
+);
+
+SinPeriodMem4pi SinPeriodMem4pi (
+  .a(lutAddrUpper),      // input wire [8 : 0] a
+  .spo(cosValue4pi)  // output wire [15 : 0] spo
+);
+
+endmodule
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+

S5444_M/src/src/InternalDsp/WinParameters.v

@@ -336,6 +336,22 @@ always	@	(posedge	Clk_i)	begin
 						winPointsNum	<=	32'h19;
 						averageNoiseLvl	<=	32'h0;
 					end	
+
+			// 8'h62 : begin//	2	MHzTestFilter
+			// 			windPhInc 		<=	32'h24924924;
+			// 			winNormCoef		<=	32'h3d14f209;
+			// 			winPointsNum	<=	32'h3f;
+			// 			averageNoiseLvl	<=	32'h0;
+			// 		end	
+
+			// 8'h62 : begin//	2	MHzTestBlackmanFilter
+			// 			windPhInc 		<=	32'h2b1da46;
+			// 			// windPhInc 		<=	32'h2B1DA460;
+			// 			winNormCoef		<=	32'h3d14f209;
+			// 			winPointsNum	<=	32'h5f;
+			// 			averageNoiseLvl	<=	32'h0;
+			// 		end	
+
 			8'h63 : begin
 						windPhInc 		<=	32'h0;
 						// winNormCoef		<=	32'h3e124925;

S5444_M/src/src/Sim/S5443TopPulseProfileTb.v

@@ -74,7 +74,7 @@ module S5443TopPulseProfileTb;
 	parameter	[31:0]	MeasCmdBypass	=	{8'h11,8'h0,8'h63,8'h1};
 	parameter	[31:0]	MeasCmdFft 		=	{8'h11,8'h0,8'h55,7'h5,1'b1};
 	// parameter	[31:0]	MeasCmd 		=	{8'h11,8'h0,8'h53,8'h0};
-	parameter	[31:0]	MeasCmd =	{8'h11,8'h0,8'h55,8'h0};
+	parameter	[31:0]	MeasCmd =	{8'h11,8'h0,8'h62,8'h0};
 	parameter	[31:0]	AdcCtrl =	{8'h12,24'h2};
 	parameter	[31:0]	SensCtrlCmd =	{1'b0,27'h0,4'b1};
 	// parameter	[31:0]	DitherCmd 	= {8'h0E,24'h100192};
@@ -213,7 +213,7 @@ module S5443TopPulseProfileTb;
 	wire [5:0] trig6to1 = (!trig6to1Dir) ? trig6to1Test:6'bz;
 //==========================================================================================
 //clocks gen
-	always	#10 Clk50	=	~Clk50;
+	always	#4 Clk50	=	~Clk50;
 	always	#(14.285714285714/2) Clk70	=	~Clk70;
 	always	#10 clk_i	=	~clk_i;
 	always	#(24.390243902439/2)	Clk41	=	~Clk41;