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@@ -7,6 +7,7 @@ module SumAcc
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input Clk_i,
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input Rst_i,
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input Val_i,
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+ input AccZeroing_i,
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input [IDataWidth-1:0] Data_i,
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output [ODataWidth-1:0] Result_o,
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@@ -22,22 +23,41 @@ module SumAcc
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reg resultVal;
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wire [ODataWidth-1:0] extData = {{(ODataWidth - IDataWidth){Data_i[IDataWidth-1]}}, Data_i}; //sign extension
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+ reg accZeroing;
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+ reg accZeroingR;
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+ reg accZeroingRR;
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//================================================================================
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// ASSIGNMENTS
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assign Result_o = dataAcc;
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assign ResultVal_o = resultVal;
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//================================================================================
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// CODING
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+
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+ always @(posedge Clk_i) begin
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+ if (Rst_i) begin
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+ accZeroing <= 0;
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+ accZeroingR <= 0;
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+ accZeroingRR <= 0;
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+ end else begin
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+ accZeroing <= AccZeroing_i;
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+ accZeroingR <= accZeroing;
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+ accZeroingRR <= accZeroingR;
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+ end
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+ end
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+
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always @(posedge Clk_i) begin
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if (Rst_i) begin
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dataAcc <= {ODataWidth{1'b0}};
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- resultVal <= 1'b0;
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end else if (Val_i) begin
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- dataAcc <= dataAcc+extData;
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- resultVal <= Val_i;
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+ if (!accZeroingRR) begin
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+ dataAcc <= dataAcc+extData;
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+ end else begin
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+ dataAcc <= 0+extData;
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+ end
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+ resultVal <= accZeroingR;
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end else begin
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dataAcc <= 0;
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- resultVal <= 1'b0;
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+ resultVal <= 0;
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end
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end
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