Добавляются мультиплексоры для сигналов модуляторов, для каждого из AM.

S5444_M/src/constrs/S5443Top.xdc

@@ -125,7 +125,7 @@ set_property PACKAGE_PIN C14 [get_ports Adc1InitCs_o]
 set_property IOSTANDARD LVCMOS25 [get_ports Adc1InitCs_o]
 set_property PACKAGE_PIN A14 [get_ports AdcInitRst_o]
 set_property IOSTANDARD LVCMOS25 [get_ports AdcInitRst_o]
-#
+
 #==========================================================================
 #  OTHER
 
@@ -186,9 +186,14 @@ set_property IOSTANDARD LVCMOS33 [get_ports DspReadyForRx_i]
 set_property PACKAGE_PIN P7 [get_ports StartMeasDsp_o]
 set_property IOSTANDARD LVCMOS33 [get_ports StartMeasDsp_o]
 
-set_property PACKAGE_PIN E14 [get_ports Mod_o]
-set_property IOSTANDARD LVCMOS25 [get_ports Mod_o]
-
+set_property PACKAGE_PIN A6 [get_ports {Mod_o[0]}]
+set_property IOSTANDARD LVCMOS25 [get_ports {Mod_o[0]}]
+set_property PACKAGE_PIN B5 [get_ports {Mod_o[1]}]
+set_property IOSTANDARD LVCMOS25 [get_ports {Mod_o[1]}]
+set_property PACKAGE_PIN B6 [get_ports {Mod_o[2]}]
+set_property IOSTANDARD LVCMOS25 [get_ports {Mod_o[2]}]
+set_property PACKAGE_PIN A7 [get_ports {Mod_o[3]}]
+set_property IOSTANDARD LVCMOS25 [get_ports {Mod_o[3]}]
 
 set_property PACKAGE_PIN K15 [get_ports DspTrigOut_i]
 set_property IOSTANDARD LVCMOS33 [get_ports DspTrigOut_i]

S5444_M/src/src/PulseMeas/Mux.v

@@ -35,6 +35,8 @@ module	Mux
 	input	IntTrig2_i,
 	input	[PGenNum-1:0]		PulseBus_i,
 	input	[TrigPortsNum-1:0]	ExtPortsBus_i,
+	input	SlowMod_i,
+	input	FastMod_i,
 	
 	output	MuxOut_o
 );	
@@ -45,7 +47,7 @@ module	Mux
 //================================================================================
 //	REG/WIRE
 	reg		muxOut;
-	wire	[PGenNum+TrigPortsNum+5:0]	inputBus	=	{IntTrig2_i,1'b1,1'b0,DspStartCmd_i,DspTrigOut_i,IntTrig_i,ExtPortsBus_i,PulseBus_i};
+	wire	[PGenNum+TrigPortsNum+7:0]	inputBus	=	{FastMod_i,SlowMod_i,IntTrig2_i,1'b1,1'b0,DspStartCmd_i,DspTrigOut_i,IntTrig_i,ExtPortsBus_i,PulseBus_i};
 //================================================================================
 //  ASSIGNMENTS
 	assign	MuxOut_o	=	muxOut;

S5444_M/src/src/RegMap/RegMap.v

@@ -57,8 +57,7 @@ module	RegMap
 	output	[CmdDataRegWith-1:0]	IfFtwRegH_o,
 	output	[CmdDataRegWith-1:0]	FilterCorrCoefRegL_o,
 	output	[CmdDataRegWith-1:0]	FilterCorrCoefRegH_o,
-	output	[CmdDataRegWith-1:0]	DspTrigInReg_o,		
-	output	[CmdDataRegWith-1:0]	DspTrigOutReg_o,
+	output	[CmdDataRegWith-1:0]	ActivePortSel_o,		
 	output	[CmdDataRegWith-1:0]	DspTrigIn1Reg_o,		
 	output	[CmdDataRegWith-1:0]	DspTrigIn2Reg_o,
 	output	[CmdDataRegWith-1:0]	DspTrigOut1Reg_o,		
@@ -142,7 +141,9 @@ module	RegMap
 	output	[CmdDataRegWith-1:0]	MuxCtrl1Reg_o,
 	output	[CmdDataRegWith-1:0]	MuxCtrl2Reg_o,
 	output	[CmdDataRegWith-1:0]	MuxCtrl3Reg_o,
-	output	[CmdDataRegWith-1:0]	MuxCtrl4Reg_o
+	output	[CmdDataRegWith-1:0]	MuxCtrl4Reg_o,
+	output	[CmdDataRegWith-1:0]	MuxCtrl5Reg_o,
+	output	[CmdDataRegWith-1:0]	MuxCtrl6Reg_o
 );
 //================================================================================
 //	LOCALPARAMS
@@ -167,8 +168,7 @@ module	RegMap
 	localparam	IfFtwRegLAddr			=	7'h16;
 	localparam	FilterCorrCoefHAddr		=	7'h17;
 	localparam	FilterCorrCoefLAddr		=	7'h18;
-	localparam	DspTrigInAddr			=	7'h19;	
-	localparam	DspTrigOutAddr			=	7'h1a;	
+	localparam	ActivePortSelAddr		=	7'h19;	
 	localparam	DspTrigIn1Addr			=	7'h5a;	
 	localparam	DspTrigIn2Addr			=	7'h5b;	
 	localparam	DspTrigOut1Addr			=	7'h5c;	
@@ -255,6 +255,8 @@ module	RegMap
 	localparam	MuxCtrl2RegAddr			=	7'h1d;
 	localparam	MuxCtrl3RegAddr			=	7'h1e;
 	localparam	MuxCtrl4RegAddr			=	7'h1f;
+	localparam	MuxCtrl5RegAddr			=	7'h1a;	
+	localparam	MuxCtrl6RegAddr			=	7'h5a;
 
 //================================================================================
 //	REG/WIRE
@@ -280,12 +282,12 @@ module	RegMap
 	reg	[CmdDataRegWith-1:0]	ifFtwRegH;
 	reg	[CmdDataRegWith-1:0]	filterCorrCoefRegL;
 	reg	[CmdDataRegWith-1:0]	filterCorrCoefRegH;
-	reg	[CmdDataRegWith-1:0]	dspTrigInReg;
-	reg	[CmdDataRegWith-1:0]	dspTrigOutReg;
+	reg	[CmdDataRegWith-1:0]	activePortSelReg;
 	reg	[CmdDataRegWith-1:0]	dspTrigIn1Reg;
 	reg	[CmdDataRegWith-1:0]	dspTrigIn2Reg;
 	reg	[CmdDataRegWith-1:0]	dspTrigOut1Reg;
 	reg	[CmdDataRegWith-1:0]	dspTrigOut2Reg;
+	
 	//pulse meas regs
 	reg	[CmdDataRegWith-1:0]	pGMode0Reg;
 	reg	[CmdDataRegWith-1:0]	pGMode1Reg;
@@ -295,6 +297,8 @@ module	RegMap
 	reg	[CmdDataRegWith-1:0]	muxCtrl2Reg;
 	reg	[CmdDataRegWith-1:0]	muxCtrl3Reg;
 	reg	[CmdDataRegWith-1:0]	muxCtrl4Reg;
+	reg	[CmdDataRegWith-1:0]	muxCtrl5Reg;
+	reg	[CmdDataRegWith-1:0]	muxCtrl6Reg;
 	
 	//PG1 Regs
 	reg	[CmdDataRegWith-1:0]	pG1P1DelayReg;
@@ -390,8 +394,7 @@ module	RegMap
 	assign	IfFtwRegH_o				=	ifFtwRegH;
 	assign	FilterCorrCoefRegL_o	=	filterCorrCoefRegL;
 	assign	FilterCorrCoefRegH_o	=	filterCorrCoefRegH;	
-	assign	DspTrigInReg_o			=	dspTrigInReg;		
-	assign	DspTrigOutReg_o			=	dspTrigOutReg;
+	assign	ActivePortSel_o			=	activePortSelReg;		
 	assign	DspTrigIn1Reg_o			=	dspTrigIn1Reg;		
 	assign	DspTrigIn2Reg_o			=	dspTrigIn2Reg;
 	assign	DspTrigOut1Reg_o		=	dspTrigOut1Reg;		
@@ -477,6 +480,8 @@ module	RegMap
 	assign	MuxCtrl2Reg_o		=	muxCtrl2Reg;
 	assign	MuxCtrl3Reg_o		=	muxCtrl3Reg;
 	assign	MuxCtrl4Reg_o		=	muxCtrl4Reg;
+	assign	MuxCtrl5Reg_o		=	muxCtrl5Reg;
+	assign	MuxCtrl6Reg_o		=	muxCtrl6Reg;
 	
 	assign	AnsDataReg_o		=	ansReg;
 //================================================================================
@@ -540,11 +545,8 @@ module	RegMap
 					FilterCorrCoefHAddr:	begin
 												filterCorrCoefRegH	<=	Data_i	[CmdDataRegWith-1:0];
 											end
-					DspTrigInAddr:			begin
-												dspTrigInReg	<=	Data_i	[CmdDataRegWith-1:0];
-											end
-					DspTrigOutAddr:			begin
-												dspTrigOutReg	<=	Data_i	[CmdDataRegWith-1:0];
+					ActivePortSelAddr:			begin
+												activePortSelReg	<=	Data_i	[CmdDataRegWith-1:0];
 											end
 					PG1P1DelayRegAddr:		begin
 												pG1P1DelayReg	<=	Data_i	[CmdDataRegWith-1:0];
@@ -738,6 +740,12 @@ module	RegMap
 					MuxCtrl4RegAddr:		begin
 												muxCtrl4Reg	<=	Data_i	[CmdDataRegWith-1:0];
 											end
+					MuxCtrl5RegAddr:		begin
+												muxCtrl5Reg	<=	Data_i	[CmdDataRegWith-1:0];
+											end
+					MuxCtrl6RegAddr:		begin
+												muxCtrl6Reg	<=	Data_i	[CmdDataRegWith-1:0];
+											end
 					DspTrigIn1Addr:			begin
 												dspTrigIn1Reg	<=	Data_i	[CmdDataRegWith-1:0];
 											end
@@ -771,8 +779,7 @@ module	RegMap
 			ifFtwRegH			<=	{CmdDataRegWith{1'b0}};
 			filterCorrCoefRegL	<=	{CmdDataRegWith{1'b0}};
 			filterCorrCoefRegH	<=	{CmdDataRegWith{1'b0}};
-			dspTrigInReg		<=	{CmdDataRegWith{1'b0}};
-			dspTrigOutReg		<=	{CmdDataRegWith{1'b0}};
+			activePortSelReg	<=	{CmdDataRegWith{1'b0}};
 			dspTrigIn1Reg		<=	{CmdDataRegWith{1'b0}};
 			dspTrigIn2Reg		<=	{CmdDataRegWith{1'b0}};
 			dspTrigOut1Reg		<=	{CmdDataRegWith{1'b0}};
@@ -848,7 +855,9 @@ module	RegMap
 			muxCtrl1Reg			<=	{CmdDataRegWith{1'b0}};	
 			muxCtrl2Reg			<=	{CmdDataRegWith{1'b0}};	
 			muxCtrl3Reg			<=	{CmdDataRegWith{1'b0}};	
-			muxCtrl4Reg			<=	{CmdDataRegWith{1'b0}};	
+			muxCtrl4Reg			<=	{CmdDataRegWith{1'b0}};
+			muxCtrl6Reg			<=	{CmdDataRegWith{1'b0}};
+			muxCtrl5Reg			<=	{CmdDataRegWith{1'b0}};			
 		end
 	end
 	
@@ -954,11 +963,11 @@ module	RegMap
 					FilterCorrCoefHAddr:	begin
 												ansReg	=	filterCorrCoefRegH;
 											end
-					DspTrigInAddr:			begin
-												ansReg	=	dspTrigInReg;
+					ActivePortSelAddr:		begin
+												ansReg	=	activePortSelReg;
 											end
-					DspTrigOutAddr:			begin
-												ansReg	=	dspTrigOutReg;
+					MuxCtrl5RegAddr:		begin
+												ansReg	=	muxCtrl5Reg;
 											end
 					DspTrigIn1Addr:			begin
 												ansReg	=	dspTrigIn1Reg;

S5444_M/src/src/Top/S5443Top.v

@@ -134,7 +134,7 @@ module	S5443Top
 	output	[3:0]	PortSelDir_o,	//управление направлением двунаправленного буффера
 	
 	//mod out line
-	output	Mod_o,
+	output	[ChNum-1:0]	Mod_o,
 	
 	//gain lines
 	input	DspReadyForRx_i,
@@ -225,8 +225,7 @@ module	S5443Top
 	wire	[CmdDataRegWith-1:0]	ifFtwH;
 	wire	[CmdDataRegWith-1:0]	measCtrl;
 	wire	[CmdDataRegWith-1:0]	amplitudeMod;
-	wire	[CmdDataRegWith-1:0]	dspTrigIn;
-	wire	[CmdDataRegWith-1:0]	dspTrigOut;
+	wire	[CmdDataRegWith-1:0]	activePortSel;
 	wire	[CmdDataRegWith-1:0]	dspTrigIn1;
 	wire	[CmdDataRegWith-1:0]	dspTrigIn2;
 	wire	[CmdDataRegWith-1:0]	dspTrigOut1;
@@ -363,6 +362,8 @@ module	S5443Top
 	wire	[CmdDataRegWith-1:0]	muxCtrl2;
 	wire	[CmdDataRegWith-1:0]	muxCtrl3;
 	wire	[CmdDataRegWith-1:0]	muxCtrl4;
+	wire	[CmdDataRegWith-1:0]	muxCtrl5;
+	wire	[CmdDataRegWith-1:0]	muxCtrl6;
 
 	wire	[CmdRegWidth-29:0]	pgModeArray		[PGenNum-1:0];
 	wire	pgPulsePolArray		[PGenNum-1:0];
@@ -388,8 +389,13 @@ module	S5443Top
 	wire	[TrigPortsNum-1:0]	extPortsMuxedOut;
 	
 	wire	measEnd;
+	
 	wire	slowMod;
 	wire	fastMod;
+	
+	wire	[ChNum-1:0] slowModOut;
+	wire	[ChNum-1:0] fastModOut;
+	
 	wire	[3:0]	modKeyCtrl;
 	wire	tirgToDspEvent;
 	wire	trigFromDspEvent;
@@ -401,10 +407,23 @@ module	S5443Top
 	reg		dspReadyForRxRegRR;
 	
 	wire	sampleStrobeGenRst;
+	
+	wire	[ChNum:0] fastModCtrl [ChNum-1:0]; 
+	wire	[ChNum:0] slowModCtrl [ChNum-1:0]; 
 //================================================================================
 //  assignments
 //================================================================================	
 	
+	assign	fastModCtrl [ChNum-1] = muxCtrl5[18:15]; 
+	assign	fastModCtrl [ChNum-2] = muxCtrl5[14:10]; 
+	assign	fastModCtrl [ChNum-3] = muxCtrl5[9:5]; 
+	assign	fastModCtrl [ChNum-4] = muxCtrl5[4:0];
+	
+	assign	slowModCtrl [ChNum-1] = muxCtrl6[18:15]; 
+	assign	slowModCtrl [ChNum-2] = muxCtrl6[14:10]; 
+	assign	slowModCtrl [ChNum-3] = muxCtrl6[9:5]; 
+	assign	slowModCtrl [ChNum-4] = muxCtrl6[4:0];
+	
 	assign	pgModeArray	[PGenNum-1]	=	pgMode0[21:18];	
 	assign	pgModeArray	[PGenNum-2]	=	pgMode0[17:15];	
 	assign	pgModeArray	[PGenNum-3]	=	pgMode0[14:12];	
@@ -544,9 +563,9 @@ module	S5443Top
 	
 	assign	Overload_o	=	overCtrlR||OverloadS_i;
 
-	assign	Mod_o	=	fastMod;
+	assign	Mod_o	[ChNum-1:0] =	fastModOut;
 	
-	assign	PortSel_o		=	~modKeyCtrl;
+	assign	PortSel_o	[ChNum-1:0] 	=	~modKeyCtrl;
 	assign	PortSelDir_o	=	4'd15;
 	
 	assign	Trig6to1Dir_o	[0]	=	!measCtrl[16];
@@ -565,10 +584,10 @@ module	S5443Top
 	
 	assign	DspReadyForRxToFpgaS_o	=	dspReadyForRxRegR;
 	assign	StartMeasDsp_o	=	startMeasSyncR;
+	
 //================================================================================
 //  CODING
 //================================================================================
-integer m;
 
 always	@(posedge	gclk)	begin	//stretching pulse
 	stopMeasR	<=	stopMeas;
@@ -853,8 +872,7 @@ RegMapInst
 	.IfFtwRegH_o			(ifFtwH),
 	.FilterCorrCoefRegL_o	(filterCorrCoefL),
 	.FilterCorrCoefRegH_o	(filterCorrCoefH),
-	.DspTrigInReg_o			(dspTrigIn),		
-	.DspTrigOutReg_o		(dspTrigOut),
+	.ActivePortSel_o		(activePortSel),
 	.DspTrigIn1Reg_o		(dspTrigIn1),
 	.DspTrigIn2Reg_o		(dspTrigIn2),
 	.DspTrigOut1Reg_o		(dspTrigOut1),	
@@ -938,7 +956,9 @@ RegMapInst
 	.MuxCtrl1Reg_o			(muxCtrl1),
 	.MuxCtrl2Reg_o			(muxCtrl2),
 	.MuxCtrl3Reg_o			(muxCtrl3),
-	.MuxCtrl4Reg_o			(muxCtrl4)
+	.MuxCtrl4Reg_o			(muxCtrl4),
+	.MuxCtrl5Reg_o			(muxCtrl5),
+	.MuxCtrl6Reg_o			(muxCtrl6)
 );
 
 //--------------------------------------------------------------------------------
@@ -1044,6 +1064,8 @@ DspTrigMux
 	.IntTrig2_i		(1'b0),
 	.PulseBus_i		(7'd0),
 	.ExtPortsBus_i	(Trig6to1_io),
+	.SlowMod_i		(1'b0),
+	.FastMod_i		(1'b0),
 	
 	.MuxOut_o		(DspTrigIn_o)
 );
@@ -1082,6 +1104,8 @@ MeasTrigMux
 	.IntTrig2_i		(1'b0),
 	.PulseBus_i		(7'b0),
 	.ExtPortsBus_i	(Trig6to1_io),
+	.SlowMod_i		(1'b0),
+	.FastMod_i		(1'b0),
 	
 	.MuxOut_o		(measTrig)
 );
@@ -1173,6 +1197,8 @@ PulseGenMux
 	.IntTrig2_i		(intTrig2),
 	.PulseBus_i		(pulseBus),
 	.ExtPortsBus_i	(Trig6to1_io),
+	.SlowMod_i		(1'b0),
+	.FastMod_i		(1'b0),
 	
 	.MuxOut_o		(pgMuxedOut[j])
 );	
@@ -1254,6 +1280,8 @@ ExtPortsMux
 	.IntTrig2_i		(intTrig2),
 	.PulseBus_i		(pulseBus),
 	.ExtPortsBus_i	(Trig6to1_io),
+	.SlowMod_i		(1'b0),
+	.FastMod_i		(1'b0),
 	
 	.MuxOut_o		(extPortsMuxedOut[l])
 );	
@@ -1282,6 +1310,8 @@ SlowModMux
 	.IntTrig2_i		(1'b0),
 	.PulseBus_i		(pulseBus),
 	.ExtPortsBus_i	(Trig6to1_io),
+	.SlowMod_i		(1'b0),
+	.FastMod_i		(1'b0),
 	
 	.MuxOut_o		(slowMod)
 );
@@ -1307,10 +1337,64 @@ FastModMux
 	.IntTrig2_i		(1'b0),
 	.PulseBus_i		(pulseBus),
 	.ExtPortsBus_i	(Trig6to1_io),
+	.SlowMod_i		(1'b0),
+	.FastMod_i		(1'b0),
 	
 	.MuxOut_o		(fastMod)
 );
 
+genvar m;
+generate
+	for	(m=0;	m<ChNum;	m=m+1)	begin	:ModulationMuxes
+		// Mux	
+		// #(	
+			// .CmdRegWidth	(CmdRegWidth),
+			// .PGenNum		(PGenNum),
+			// .TrigPortsNum	(TrigPortsNum)
+		// )
+		// SlowModMuxOut
+		// (
+			// .Rst_i			(initRst),
+
+			// .MuxCtrl_i		(slowModCtrl[m]),
+
+			// .DspTrigOut_i	(1'b0),
+			// .DspStartCmd_i	(1'b0),
+			// .IntTrig_i		(1'b0),
+			// .IntTrig2_i		(1'b0),
+			// .PulseBus_i		(7'h0),
+			// .ExtPortsBus_i	(6'h0),
+			// .SlowMod_i		(slowMod),
+			// .FastMod_i		(1'b0),
+			
+			// .MuxOut_o		(slowModOut[m])
+		// );
+
+		Mux	
+		#(	
+			.CmdRegWidth	(CmdRegWidth),
+			.PGenNum		(PGenNum),
+			.TrigPortsNum	(TrigPortsNum)
+		)
+		FastModMuxOut
+		(
+			.Rst_i			(initRst),
+
+			.MuxCtrl_i		(fastModCtrl[m]),
+
+			.DspTrigOut_i	(1'b0),
+			.DspStartCmd_i	(1'b0),
+			.IntTrig_i		(1'b0),
+			.IntTrig2_i		(1'b0),
+			.PulseBus_i		(7'h0),
+			.ExtPortsBus_i	(6'h0),
+			.SlowMod_i		(1'b0),
+			.FastMod_i		(fastMod),
+			
+			.MuxOut_o		(fastModOut[m])
+		);
+	end
+endgenerate
 //--------------------------------------------------------------------------------
 //	Software Gating
 //--------------------------------------------------------------------------------	
@@ -1332,6 +1416,8 @@ GatingMux
 	.IntTrig2_i		(1'b0),
 	.PulseBus_i		(pulseBus),
 	.ExtPortsBus_i	(Trig6to1_io),
+	.SlowMod_i		(1'b0),
+	.FastMod_i		(1'b0),
 	
 	.MuxOut_o		(gatingPulse)
 );
@@ -1357,6 +1443,8 @@ SampleStrobeMux
 	.IntTrig2_i		(1'b0),
 	.PulseBus_i		(pulseBus),
 	.ExtPortsBus_i	(Trig6to1_io),
+	.SlowMod_i		(1'b0),
+	.FastMod_i		(1'b0),
 	
 	.MuxOut_o		(sampleStrobe)
 );