Изменения для улучшения таймингов. Доработаны модулия приёма по SPI. Добавлена синхронная логика в некоторые модули.

S5444_M/src/constrs/S5443Top.xdc

@@ -254,7 +254,7 @@ set_property IOSTANDARD LVCMOS25 [get_ports DitherCtrlCh1_o]
 set_property PACKAGE_PIN G14 [get_ports DitherCtrlCh2_o]
 set_property IOSTANDARD LVCMOS25 [get_ports DitherCtrlCh2_o]
 
-set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets Ss_i_IBUF]
+#set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets Ss_i_IBUF]
 set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets Sck_i_IBUF]
 
 #set_false_path -from [get_clocks -of_objects [get_pins Clk200Gen/rx_plle2_adv_inst/CLKOUT0]] -to [get_clocks -of_objects [get_pins Clk200Gen/rx_plle2_adv_inst/CLKOUT0]]
@@ -267,3 +267,32 @@ set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets Sck_i_IBUF]
 
 
 
+
+
+
+
+
+
+
+
+
+
+
+create_debug_core u_ila_0 ila
+set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0]
+set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_0]
+set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0]
+set_property C_DATA_DEPTH 1024 [get_debug_cores u_ila_0]
+set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_0]
+set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0]
+set_property C_TRIGIN_EN false [get_debug_cores u_ila_0]
+set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0]
+set_property port_width 1 [get_debug_ports u_ila_0/clk]
+connect_debug_port u_ila_0/clk [get_nets [list gclk_BUFG]]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0]
+set_property port_width 1 [get_debug_ports u_ila_0/probe0]
+connect_debug_port u_ila_0/probe0 [get_nets [list OverloadS_i_IBUF]]
+set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub]
+set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub]
+set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub]
+connect_debug_port dbg_hub/clk [get_nets gclk_BUFG]

S5444_M/src/src/AdcDataRx/AdcDataInterface.v

@@ -106,7 +106,7 @@ module	AdcDataInterface
 	assign	Adc1ChT1Data_o	=	adc1ChT1DataSync;
 	assign	Adc1ChR1Data_o	=	adc1ChR1DataSync;
 	assign	Adc2ChR2Data_o	=	adc2ChR2DataSync;
-	assign	Adc2ChT2Data_o	=	adc2ChT2DataSync;
+	assign	Adc2ChT2Data_o	=	~adc2ChT2DataSync;
 	
 	wire	idly_reset_int;
 	wire	rx_reset;

S5444_M/src/src/ExtDspInterface/QuadSlaveSpi.v

@@ -60,6 +60,10 @@ module	QuadSlaveSpi
 	
 	reg	[CmdRegWidth-1:0] singleCaptReg;
 	
+	reg	[CmdRegWidth-1:0] outDataReg;
+	reg	[CmdRegWidth-1:0] outDataReg1;
+	reg	[CmdRegWidth-1:0] outDataReg2;
+	
 	reg [QuadSpiRegWidth-1:0] quadCaptReg0;
 	reg [QuadSpiRegWidth-1:0] quadCaptReg1;
 	reg [QuadSpiRegWidth-1:0] quadCaptReg2;
@@ -70,7 +74,6 @@ module	QuadSlaveSpi
 	reg	spiMode;
 	wire directTransit	=	(ansAddr	==	Adc0DirAccessAddr)|(ansAddr	==	Adc1DirAccessAddr);
 
-	
 	reg	txWind;
 	reg	[4:0]	txCnt;
 
@@ -84,48 +87,49 @@ module	QuadSlaveSpi
 	
 	assign	AnsAddr_o	=	ansAddr;
 	assign	Miso0_Mosi2_io		=	txWind?	AnsReg_i[txCnt]:1'bz;
+	assign	Miso1_Mosi3_io		=	txWind?	AnsReg_i[txCnt]:1'bz;
 //================================================================================
 //	CODING
 //================================================================================
 	
-	always @(posedge Rst_i or posedge Sck_i) begin
-		if (Rst_i) begin
+	always @(posedge Ss_i or posedge Sck_i) begin
+		if (Ss_i) begin
 			singleCaptReg <= 0;
 			quadCaptReg0 <= 0;
 			quadCaptReg1 <= 0;
 			quadCaptReg2 <= 0;
 			quadCaptReg3 <= 0;
 		end else begin
-			if (!Ss_i) begin
-				if (SpiRst_i) begin
-					singleCaptReg <= {singleCaptReg[CmdRegWidth-2:0],Mosi0_i};
-					quadCaptReg0 <= 0;
-					quadCaptReg1 <= 0;
-					quadCaptReg2 <= 0;
-					quadCaptReg3 <= 0;
-				end else begin
-					singleCaptReg <= 0;
-					quadCaptReg0 <= {quadCaptReg0[QuadSpiRegWidth-2:0],Mosi0_i};
-					quadCaptReg1 <= {quadCaptReg1[QuadSpiRegWidth-2:0],Mosi1_i};
-					quadCaptReg2 <= {quadCaptReg2[QuadSpiRegWidth-2:0],Miso0_Mosi2_io};
-					quadCaptReg3 <= {quadCaptReg3[QuadSpiRegWidth-2:0],Miso1_Mosi3_io};
-				end
-			end
+			singleCaptReg <= {singleCaptReg[CmdRegWidth-2:0],Mosi0_i};
+			quadCaptReg0 <= {quadCaptReg0[QuadSpiRegWidth-2:0],Mosi0_i};
+			quadCaptReg1 <= {quadCaptReg1[QuadSpiRegWidth-2:0],Mosi1_i};
+			quadCaptReg2 <= {quadCaptReg2[QuadSpiRegWidth-2:0],Miso0_Mosi2_io};
+			quadCaptReg3 <= {quadCaptReg3[QuadSpiRegWidth-2:0],Miso1_Mosi3_io};
 		end 
 	end
 	
-	always @(posedge Rst_i or posedge Sck_i)	begin
-		if	(Rst_i)	begin
-			dataCnt	<=	0;
+	always @(posedge Sck_i) begin
+		if (SpiRst_i) begin
+			if (dataCnt == 5'd31) begin
+				outDataReg <= {singleCaptReg[CmdRegWidth-2:0], Mosi0_i};
+			end
 		end else begin
-			if	(~Ss_i)	begin
-				dataCnt	<=	dataCnt	+	5'd1;
+			if (dataCnt == 5'd7) begin
+				outDataReg <= {{quadCaptReg3[QuadSpiRegWidth-2:0],Miso1_Mosi3_io},{quadCaptReg2[QuadSpiRegWidth-2:0],Miso0_Mosi2_io},{quadCaptReg1[QuadSpiRegWidth-2:0],Mosi1_i},{quadCaptReg0[QuadSpiRegWidth-2:0],Mosi0_i}};
 			end
 		end
 	end
+	
+	always @(posedge Ss_i or posedge Sck_i)	begin
+		if	(Ss_i)	begin
+			dataCnt	<=	0;
+		end else begin
+			dataCnt	<=	dataCnt	+	5'd1;
+		end
+	end
 
-	always @(posedge Rst_i or posedge Sck_i)	begin
-		if	(Rst_i)	begin
+	always @(posedge Ss_i or posedge Sck_i)	begin
+		if	(Ss_i)	begin
 			spiMode	<=	1'b0;
 		end else begin
 			if	(dataCnt	==	5'd1)	begin
@@ -146,20 +150,16 @@ module	QuadSlaveSpi
 		end
 	end
 
-	always @(posedge Rst_i or negedge Sck_i)	begin
-		if	(Rst_i)	begin
+	always @(posedge Ss_i or negedge Sck_i)	begin
+		if	(Ss_i)	begin
 			ansAddr	<=	7'h7F;	
 		end else begin
-			if	(~Ss_i)	begin
-				if	(dataCnt	==	5'd8)	begin
-					if (SpiRst_i) begin
-						ansAddr	<=	singleCaptReg[QuadSpiRegWidth-1:0];
-					end	else	begin
-						ansAddr	<=	quadCaptReg3[QuadSpiRegWidth-1:0];
-					end 
-				end
-			end	else	begin
-				ansAddr	<=	7'h7F;	
+			if	(dataCnt	==	5'd8)	begin
+				if (SpiRst_i) begin
+					ansAddr	<=	singleCaptReg[QuadSpiRegWidth-1:0];
+				end	else	begin
+					ansAddr	<=	quadCaptReg3[QuadSpiRegWidth-1:0];
+				end 
 			end
 		end
 	end
@@ -212,18 +212,18 @@ module	QuadSlaveSpi
 		end
 	end
 
-	always @(posedge Rst_i or posedge Clk_i)	begin
-		if (Rst_i) 	begin
+	always	@(posedge	Clk_i)	begin
+		if (Rst_i) begin
+			outDataReg1 <= 0;
+			outDataReg2 <= 0;
 			Data_o <= 0;
 		end else begin
-			if (SpiRst_i) begin
-				Data_o <= singleCaptReg;
-			end else begin
-				Data_o <= {quadCaptReg3,quadCaptReg2,quadCaptReg1,quadCaptReg0};
-			end
+			outDataReg1 <= outDataReg;
+			outDataReg2 <= outDataReg1;
+			Data_o <= outDataReg2;
 		end
 	end
-
+	
 	always	@(*)	begin
 		if	(spiMode	&	!Ss_i)	begin
 			if	(dataCnt	>=5'd8|dataCnt	==	0)	begin

S5444_M/src/src/InternalDsp/InternalDsp.v

@@ -103,19 +103,16 @@ module InternalDsp
 
 	wire	[NcoWidth-1:0]	ncoCosFirstTone;
 	wire	[NcoWidth-1:0]	ncoSinFirstTone;
-	
 	wire	[NcoWidth-1:0]	ncoCosSecondTone;
 	wire	[NcoWidth-1:0]	ncoSinSecondTone;
 	
-	wire	[NcoWidth-1:0]	ncoCosMuxedTone	[ChNum-1:0];
-	wire	[NcoWidth-1:0]	ncoSinMuxedTone	[ChNum-1:0];
+	reg		[NcoWidth-1:0]	currNcoSinTone [ChNum-1:0];
+	reg		[NcoWidth-1:0]	currNcoCosTone [ChNum-1:0];
 	
 	wire	[CorrAdcDataWidth-1:0]	adcDataBus	[ChNum-1:0];
 	wire	[CorrAdcDataWidth-1:0]	adcDataBusExt	[ChNum-1:0];
 	wire	[CorrAdcDataWidth-1:0]	gatedAdcDataBus	[ChNum-1:0];
 	
-	wire	[CorrAdcDataWidth-1:0]	AdcDataBusMuxed	[ChNum-1:0];
-	
 	wire	[CorrAdcDataWidth-1:0]	calAdcData		[ChNum-1:0];
 	wire	[CorrAdcDataWidth-1:0]	prngData;
 	reg		[CorrAdcDataWidth-1:0]	prngDataBus		[ChNum-1:0];
@@ -153,15 +150,24 @@ module InternalDsp
 	wire	[CorrAdcDataWidth-1:0]	adc2ChR2DataGated	=	(GatingPulse_i)?	adcDataBusExt[ChNum-2]:{CorrAdcDataWidth{1'b0}};
 	wire	[CorrAdcDataWidth-1:0]	adc2ChT2DataGated	=	(GatingPulse_i)?	adcDataBusExt[ChNum-1]:{CorrAdcDataWidth{1'b0}};	
 	
-	wire	grDelayMeasFlag = (measCtrlReg[1:0] == 2'h2);
+	reg	grDelayMeasFlag;
 	
+	reg	[AdcDataWidth-1:0]	adc1ChT1DataR;
+	reg	[AdcDataWidth-1:0]	adc1ChR1DataR;
+	reg	[AdcDataWidth-1:0]	adc2ChR2DataR;
+	reg	[AdcDataWidth-1:0]	adc2ChT2DataR;
 //================================================================================
 //  ASSIGNMENTS
 
-	assign	adcDataBus	[ChNum-1]	=	{{2{Adc2ChT2Data_i[AdcDataWidth-1]}},Adc2ChT2Data_i,4'b0};
-	assign	adcDataBus	[ChNum-2]	=	{{2{Adc2ChR2Data_i[AdcDataWidth-1]}},Adc2ChR2Data_i,4'b0};
-	assign	adcDataBus	[ChNum-3]	=	{{2{Adc1ChR1Data_i[AdcDataWidth-1]}},Adc1ChR1Data_i,4'b0};
-	assign	adcDataBus	[ChNum-4]	=	{{2{Adc1ChT1Data_i[AdcDataWidth-1]}},Adc1ChT1Data_i,4'b0};
+	// assign	adcDataBus	[ChNum-1]	=	{{2{Adc2ChT2Data_i[AdcDataWidth-1]}},Adc2ChT2Data_i,4'b0};
+	// assign	adcDataBus	[ChNum-2]	=	{{2{Adc2ChR2Data_i[AdcDataWidth-1]}},Adc2ChR2Data_i,4'b0};
+	// assign	adcDataBus	[ChNum-3]	=	{{2{Adc1ChR1Data_i[AdcDataWidth-1]}},Adc1ChR1Data_i,4'b0};
+	// assign	adcDataBus	[ChNum-4]	=	{{2{Adc1ChT1Data_i[AdcDataWidth-1]}},Adc1ChT1Data_i,4'b0};	
+	
+	assign	adcDataBus	[ChNum-1]	=	{{2{adc2ChT2DataR[AdcDataWidth-1]}},adc2ChT2DataR,4'b0};
+	assign	adcDataBus	[ChNum-2]	=	{{2{adc2ChR2DataR[AdcDataWidth-1]}},adc2ChR2DataR,4'b0};
+	assign	adcDataBus	[ChNum-3]	=	{{2{adc1ChR1DataR[AdcDataWidth-1]}},adc1ChR1DataR,4'b0};
+	assign	adcDataBus	[ChNum-4]	=	{{2{adc1ChT1DataR[AdcDataWidth-1]}},adc1ChT1DataR,4'b0};
 	
 	assign	adcDataBusExt	[ChNum-1]	=	calAdcData	[ChNum-1]+prngDataBus[ChNum-1];
 	assign	adcDataBusExt	[ChNum-2]	=	calAdcData	[ChNum-2]+prngDataBus[ChNum-2];
@@ -177,12 +183,22 @@ module InternalDsp
 	assign	Adc1ReT1Data_o	=	resultReBus	[ChNum-4];
 	assign	Adc1ImR1Data_o	=	resultImBus	[ChNum-3];
 	assign	Adc1ReR1Data_o	=	resultReBus	[ChNum-3];
-	//adc2                 
+               
 	assign	Adc2ImR2Data_o	=	resultImBus	[ChNum-2];
 	assign	Adc2ReR2Data_o	=	resultReBus	[ChNum-2];
 	assign	Adc2ImT2Data_o	=	resultImBus	[ChNum-1];
 	assign	Adc2ReT2Data_o	=	resultReBus	[ChNum-1];
 	
+	// assign	Adc1ImT1Data_o	=	32'h3f800000;
+	// assign	Adc1ReT1Data_o	=	32'h3f800000;
+	// assign	Adc1ImR1Data_o	=	32'h3f800000;
+	// assign	Adc1ReR1Data_o	=	32'h3f800000;
+                
+	// assign	Adc2ImR2Data_o	=	32'h3f800000;
+	// assign	Adc2ReR2Data_o	=	32'h3f800000;
+	// assign	Adc2ImT2Data_o	=	32'h3f800000;
+	// assign	Adc2ReT2Data_o	=	32'h3f800000;
+	
 	
 	assign	MeasDataRdy_o	=	&resultValBus;
 	assign	EndMeas_o		=	stopMeas;
@@ -199,6 +215,43 @@ module InternalDsp
 //----------------------------------------------
 //Module generates event signals for measurement
 
+always	@(posedge	Clk_i)	begin
+	if	(Rst_i)	begin
+		adc1ChT1DataR	<= 0;
+		adc1ChR1DataR	<= 0;
+		adc2ChR2DataR	<= 0;
+		adc2ChT2DataR	<= 0;
+	end	else	begin
+		if (grDelayMeasFlag) begin
+			adc1ChT1DataR	<= Adc1ChT1Data_i;
+			adc1ChR1DataR	<= Adc1ChT1Data_i;
+			adc2ChR2DataR	<= Adc2ChT2Data_i;
+			adc2ChT2DataR	<= Adc2ChT2Data_i;
+			currNcoSinTone [0] <= ncoSinFirstTone;
+			currNcoSinTone [1] <= ncoSinSecondTone;
+			currNcoSinTone [2] <= ncoCosFirstTone;
+			currNcoSinTone [3] <= ncoCosSecondTone;
+			currNcoCosTone [0] <= ncoCosFirstTone;
+			currNcoCosTone [1] <= ncoCosSecondTone;
+			currNcoCosTone [2] <= ncoCosFirstTone;
+			currNcoCosTone [3] <= ncoCosSecondTone;
+		end else begin
+			adc1ChT1DataR	<= Adc1ChT1Data_i;
+			adc1ChR1DataR	<= Adc1ChR1Data_i;
+			adc2ChR2DataR	<= Adc2ChR2Data_i;
+			adc2ChT2DataR	<= Adc2ChT2Data_i;
+			currNcoSinTone [0] <= ncoSinFirstTone;
+			currNcoSinTone [1] <= ncoSinFirstTone;
+			currNcoSinTone [2] <= ncoSinFirstTone;
+			currNcoSinTone [3] <= ncoSinFirstTone;
+			currNcoCosTone [0] <= ncoCosFirstTone;
+			currNcoCosTone [1] <= ncoCosFirstTone;
+			currNcoCosTone [2] <= ncoCosFirstTone;
+			currNcoCosTone [3] <= ncoCosFirstTone;
+		end
+	end 
+end
+
 always	@(posedge	Clk_i)	begin
 	if	(!Rst_i)	begin
 		if	(!StartMeas_i)	begin
@@ -211,6 +264,7 @@ always	@(posedge	Clk_i)	begin
 			filterCorrCoefHReg	<=	FilterCorrCoefH_i;
 			measNumReg			<=	MeasNum_i;
 			windPointsNumReg	<=	windPointsNum;
+			grDelayMeasFlag		<=	(measCtrlReg[1:0] == 2'h2);
 		end 
 	end	else	begin
 		measCtrlReg			<=	0;
@@ -222,6 +276,7 @@ always	@(posedge	Clk_i)	begin
 		filterCorrCoefHReg	<=	0;
 		measNumReg			<=	0;
 		windPointsNumReg	<=	0;
+		grDelayMeasFlag		<=	0;
 	end 
 end
 
@@ -294,18 +349,6 @@ Win_calc	WinCalcInst
 	.win_o			(wind)
 );
 
-// Approximation3 WindCalc2
-// (
-    // .Clk_i			(Clk_i), 
-    // .Rst_i			(Rst_i),
-    // .Clk100_i		(WindCalcClk_i),
-    // .WinCtrl_i		(winCtrl),
-    // .Win_value_i	(windArg),
-    // .filterCmd_i	(measCtrlReg[15-:8]), 
-	// .Win_o			(wind)
-// );
-
-
 //----------------------------------------------
 //Module generates Sin and Cos for measurement
 
@@ -392,133 +435,44 @@ generate
 			.CalibratedAdcData_o	(calAdcData[g])
 		);
 		
-		if	(g==1)	begin
-			GrDelModeMux	
-			#(	
-				.AdcDataWidth	(CorrAdcDataWidth),
-				.NcoDataWidth	(NcoWidth)
-			)
-			GrDelModeMux
-			(
-				.Rst_i	(Rst_i),
-				
-				.MuxCtrl_i	(grDelayMeasFlag),
-	
-				.AdcDataOrig_i	(gatedAdcDataBus[g]),
-				.AdcDataGrDel_i	(gatedAdcDataBus[g-1]),
-				
-				.NcoSinOrig_i	(ncoSinFirstTone),
-				.NcoCosOrig_i	(ncoCosFirstTone),
-				.NcoSinGrDel_i	(ncoSinSecondTone),
-				.NcoCosGrDel_i	(ncoCosSecondTone),
-				
-				.MuxAdcData_o	(AdcDataBusMuxed[g]),
-				.MuxNcoSin_o	(ncoSinMuxedTone[g]),
-				.MuxNcoCos_o	(ncoCosMuxedTone[g])
-			);	
-		end
-		
-		if	(g==3)	begin
-			GrDelModeMux	
-			#(	
-				.AdcDataWidth	(CorrAdcDataWidth),
-				.NcoDataWidth	(NcoWidth)
-			)
-			GrDelModeMux
-			(
-				.Rst_i	(Rst_i),
-				
-				.MuxCtrl_i	(grDelayMeasFlag),
-	
-				.AdcDataOrig_i	(gatedAdcDataBus[g]),
-				.AdcDataGrDel_i	(gatedAdcDataBus[g-1]),
-				
-				.NcoSinOrig_i	(ncoSinFirstTone),
-				.NcoCosOrig_i	(ncoCosFirstTone),
-				.NcoSinGrDel_i	(ncoSinSecondTone),
-				.NcoCosGrDel_i	(ncoCosSecondTone),
-				
-				.MuxAdcData_o	(AdcDataBusMuxed[g]),
-				.MuxNcoSin_o	(ncoSinMuxedTone[g]),
-				.MuxNcoCos_o	(ncoCosMuxedTone[g])
-			);	
-		end
-		
-		if (g==1||g==3) begin
-			DspPipeline	
-			#(	
-				.AdcDataWidth		(AdcDataWidth),
-				.AccWidth			(AccWidth),
-				.WindWidth			(WindWidth),
-				.NcoWidth			(NcoWidth),
-				.ResultWidth		(ResultWidth),
-				.WindCorrCoefWidth	(WindCorrCoefWidth),
-				.WindNormCoefWidth	(WindNormCoefWidth),
-				.IntermediateWidth	(IntermediateWidth)
-			)
-			DspPipelineInst
-			(
-				.Clk_i				(Clk_i),
-				.Rst_i				(Rst_i),
-				.Val_i				(measWind),
-				.MeasWindEnd_i		(measWindEnd),
-				.StartFpConv_i		(measWindEnd),
-				
-				.FilterCorrCoef_i	({filterCorrCoefHReg[0+:WindNcoPhIncWidth-CmdDataRegWith],filterCorrCoefLReg}),
-				// .FilterCorrCoef_i	(32'h3f800000),
-				.AverageNoizeLvl_i	(averageNoizeLvl),
-				// .AdcData_i			(gatedAdcDataBus[g]),
-				.AdcData_i			(AdcDataBusMuxed[g]),
-				// .AdcData_i			({{2{ncoCosFirstTone[17]}},ncoCosFirstTone}),
-				.Wind_i				(wind),
-				.NcoSin_i			(ncoSinMuxedTone[g]),
-				.NcoCos_i			(ncoCosMuxedTone[g]),	
-				.NormCoef_i			(windNormCoef),
-				// .NormCoef_i			(32'h3f800000),
-				// .NormCoef_i			(32'h3f03993a),
-	
-				.CorrResultIm_o		(resultImBus[g]),
-				.CorrResultRe_o		(resultReBus[g]),
-				.CorrResultVal_o	(resultValBus[g])
-			);
-		end else begin
-			DspPipeline	
-			#(	
-				.AdcDataWidth		(AdcDataWidth),
-				.AccWidth			(AccWidth),
-				.WindWidth			(WindWidth),
-				.NcoWidth			(NcoWidth),
-				.ResultWidth		(ResultWidth),
-				.WindCorrCoefWidth	(WindCorrCoefWidth),
-				.WindNormCoefWidth	(WindNormCoefWidth),
-				.IntermediateWidth	(IntermediateWidth)
-			)
-			DspPipelineInst
-			(
-				.Clk_i				(Clk_i),
-				.Rst_i				(Rst_i),
-				.Val_i				(measWind),
-				.MeasWindEnd_i		(measWindEnd),
-				.StartFpConv_i		(measWindEnd),
-				
-				.FilterCorrCoef_i	({filterCorrCoefHReg[0+:WindNcoPhIncWidth-CmdDataRegWith],filterCorrCoefLReg}),
-				// .FilterCorrCoef_i	(32'h3f800000),
-				.AverageNoizeLvl_i	(averageNoizeLvl),
-				.AdcData_i			(gatedAdcDataBus[g]),
-				// .AdcData_i			(AdcDataBusMuxed[g]),
-				// .AdcData_i			({{2{ncoCosFirstTone[17]}},ncoCosFirstTone}),
-				.Wind_i				(wind),
-				.NcoSin_i			(ncoSinFirstTone),
-				.NcoCos_i			(ncoCosFirstTone),	
-				.NormCoef_i			(windNormCoef),
-				// .NormCoef_i			(32'h3f800000),
-				// .NormCoef_i			(32'h3f03993a),
-	
-				.CorrResultIm_o		(resultImBus[g]),
-				.CorrResultRe_o		(resultReBus[g]),
-				.CorrResultVal_o	(resultValBus[g])
-			);
-		end
+		DspPipeline	
+		#(	
+			.AdcDataWidth		(AdcDataWidth),
+			.AccWidth			(AccWidth),
+			.WindWidth			(WindWidth),
+			.NcoWidth			(NcoWidth),
+			.ResultWidth		(ResultWidth),
+			.WindCorrCoefWidth	(WindCorrCoefWidth),
+			.WindNormCoefWidth	(WindNormCoefWidth),
+			.IntermediateWidth	(IntermediateWidth)
+		)
+		DspPipelineInst
+		(
+			.Clk_i				(Clk_i),
+			.Rst_i				(Rst_i),
+			.Val_i				(measWind),
+			.MeasWindEnd_i		(measWindEnd),
+			.StartFpConv_i		(measWindEnd),
+			
+			.FilterCorrCoef_i	({filterCorrCoefHReg[0+:WindNcoPhIncWidth-CmdDataRegWith],filterCorrCoefLReg}),
+			// .FilterCorrCoef_i	(32'h3f800000),
+			.AverageNoizeLvl_i	(averageNoizeLvl),
+			.AdcData_i			(gatedAdcDataBus[g]),
+			// .AdcData_i			({{2{ncoCosFirstTone[17]}},ncoCosFirstTone}),
+			.Wind_i				(wind),
+			// .NcoSin_i			(ncoSinFirstTone),
+			// .NcoCos_i			(ncoCosFirstTone),
+			
+			.NcoSin_i			(currNcoSinTone[g]),
+			.NcoCos_i			(currNcoCosTone[g]),	
+			.NormCoef_i			(windNormCoef),
+			// .NormCoef_i			(32'h3f800000),
+			// .NormCoef_i			(32'h3f03993a),
+
+			.CorrResultIm_o		(resultImBus[g]),
+			.CorrResultRe_o		(resultReBus[g]),
+			.CorrResultVal_o	(resultValBus[g])
+		);
 	end
 endgenerate
 

S5444_M/src/src/PulseMeas/StartAfterGainSel.v

@@ -24,6 +24,8 @@ module StartAfterGainSel
 )	
 (
 	input	Rst_i,	
+	input	Clk_i,	
+	
 	input	[ChNum-1:0]	MeasStart_i,
 	input	[ChNum-1:0]	GainCtrl_i,
 	
@@ -42,59 +44,61 @@ module StartAfterGainSel
 //================================================================================
 //  CODING
 
-always	@(*)	begin
-	if	(!Rst_i)	begin
+always	@(posedge Rst_i or posedge Clk_i)	begin
+	if	(Rst_i)	begin
+		measStart <= 0;
+	end else begin
 		case(GainCtrl_i)
 			4'd0:	begin
-						measStart	=	&MeasStart_i;
+						measStart	<=	&MeasStart_i;
 					end
 			4'd1:	begin
-						measStart	=	MeasStart_i[0];
+						measStart	<=	MeasStart_i[0];
 					end
 			4'd2:	begin
-						measStart	=	MeasStart_i[1];
+						measStart	<=	MeasStart_i[1];
 					end
 			4'd3:	begin
-						measStart	=	MeasStart_i[0]&MeasStart_i[1];
+						measStart	<=	MeasStart_i[0]&MeasStart_i[1];
 					end
 			4'd4:	begin
-						measStart	=	&MeasStart_i[2];
+						measStart	<=	&MeasStart_i[2];
 					end
 			4'd5:	begin
-						measStart	=	MeasStart_i[0]&MeasStart_i[2];
+						measStart	<=	MeasStart_i[0]&MeasStart_i[2];
 					end
 			4'd6:	begin
-						measStart	=	MeasStart_i[1]&MeasStart_i[2];
+						measStart	<=	MeasStart_i[1]&MeasStart_i[2];
 					end
 			4'd7:	begin
-						measStart	=	MeasStart_i[0]&MeasStart_i[1]&MeasStart_i[2];
+						measStart	<=	MeasStart_i[0]&MeasStart_i[1]&MeasStart_i[2];
 					end
 			4'd8:	begin
-						measStart	=	MeasStart_i[3];
+						measStart	<=	MeasStart_i[3];
 					end
 			4'd9:	begin
-						measStart	=	MeasStart_i[0]&MeasStart_i[3];
+						measStart	<=	MeasStart_i[0]&MeasStart_i[3];
 					end
 			4'd10:	begin
-						measStart	=	MeasStart_i[1]&MeasStart_i[3];
+						measStart	<=	MeasStart_i[1]&MeasStart_i[3];
 					end
 			4'd11:	begin
-						measStart	=	MeasStart_i[0]&MeasStart_i[1]&MeasStart_i[3];
+						measStart	<=	MeasStart_i[0]&MeasStart_i[1]&MeasStart_i[3];
 					end
 			4'd12:	begin
-						measStart	=	MeasStart_i[2]&MeasStart_i[3];
+						measStart	<=	MeasStart_i[2]&MeasStart_i[3];
 					end
 			4'd13:	begin
-						measStart	=	MeasStart_i[0]&MeasStart_i[2]&MeasStart_i[3];
+						measStart	<=	MeasStart_i[0]&MeasStart_i[2]&MeasStart_i[3];
 					end
 			4'd14:	begin
-						measStart	=	MeasStart_i[1]&MeasStart_i[2]&MeasStart_i[3];
+						measStart	<=	MeasStart_i[1]&MeasStart_i[2]&MeasStart_i[3];
 					end
 			4'd15:	begin
-						measStart	=	&MeasStart_i;
+						measStart	<=	&MeasStart_i;
 					end		
 			default:	begin
-							measStart	=	&MeasStart_i;
+							measStart	<=	&MeasStart_i;
 						end
 		endcase
 	end

S5444_M/src/src/Sim/S5443TopPulseProfileTb.v

@@ -31,6 +31,7 @@
 //=============================================================================================================
 module S5443TopPulseProfileTb;
 	
+	parameter	IsSim	=	1'b1;
 	localparam	[4:0]	EP1MUXCMD	=	5'd14;
 	localparam	[4:0]	EP2MUXCMD	=	5'd1;
 	localparam	[4:0]	EP3MUXCMD	=	5'd1;
@@ -72,8 +73,8 @@ module S5443TopPulseProfileTb;
 	//COMMANDS	FOR REG_MAP
 	parameter	[31:0]	MeasCmdBypass	=	{8'h11,8'h0,8'h63,8'h1};
 	parameter	[31:0]	MeasCmdFft 		=	{8'h11,8'h0,8'h63,7'h5,1'b1};
-	// parameter	[31:0]	MeasCmd 		=	{8'h11,8'h0,8'h53,8'h0};
-	parameter	[31:0]	MeasCmd =	{8'h11,6'h0,8'h63,4'h0,4'h0,2'h2};
+	parameter	[31:0]	MeasCmd 		=	{8'h11,8'h0,8'h63,8'h0};
+	// parameter	[31:0]	MeasCmd =	{8'h11,6'h0,8'h63,4'h0,4'h0,2'h2};
 	parameter	[23:0]	testCmd = {6'h0,8'h63,4'h0,4'h0,2'h2};
 	parameter	[31:0]	AdcCtrl =	{8'h12,24'h2};
 	parameter	[31:0]	SensCtrlCmd =	{1'b0,27'h0,4'b1};
@@ -305,7 +306,9 @@ ncoInst
 );
 
 
-S5443Top MasterFpga 
+S5443Top  
+#(.IsSim (IsSim))
+MasterFpga
 (
 	.ClkP_i				(Clk50),
 	.ClkN_i				(~Clk50),
@@ -352,7 +355,7 @@ S5443Top MasterFpga
 	.Miso0_Mosi2_io		(miso0_mosi2),
 	.Miso1_Mosi3_io		(miso1_mosi3),
 	.SpiRst_i			(spiRst),
-	.Sck_i				(Clk41),
+	.Sck_i				(~Clk41),
 	.Ss_i				(ss),
 
 	.LpOutClk_o			(),
@@ -402,7 +405,7 @@ reg	[2:0]	txNextState;
 
 wire	txWork	=	tb_cnt	>=	23;
 // wire	txStop	=	(cmdCnt	>=	90)	&	(cmdCnt	>=	70)	&	(cmdCnt	>=	71);
-wire	txStop	=	(cmdCnt	>=	251);
+wire	txStop	=	(cmdCnt	>=	150);
 
 
 reg	[6:0]	txCnt;

S5444_M/src/src/Top/S5443Top.v

@@ -51,7 +51,8 @@ module	S5443Top
 	parameter	Divparam			=	4,
 	parameter	MeasPeriod			=	44,
 	parameter	PhIncWidth			=	32,
-	parameter	NcoWidth			=	18
+	parameter	NcoWidth			=	18,
+	parameter	IsSim				=	1'b0
 )
 (
 	//common ports
@@ -525,10 +526,10 @@ module	S5443Top
 	assign	pgP3WidthArray[PGenNum-6]	=	{pG2P123Width[23:16],pG2P3Width};
 	assign	pgP3WidthArray[PGenNum-7]	=	{pG1P123Width[23:16],pG1P3Width};
 
-	assign	adcDataBus	[ChNum-4]	=	adc1ChT1Data;
-	assign	adcDataBus	[ChNum-3]	=	adc1ChR1Data;
-	assign	adcDataBus	[ChNum-2]	=	adc2ChR2Data;
-	assign	adcDataBus	[ChNum-1]	=	adc2ChT2Data;
+	assign	adcDataBus	[ChNum-4]	=	(IsSim)?AdcData_i:adc1ChT1Data;
+	assign	adcDataBus	[ChNum-3]	=	(IsSim)?AdcData_i:adc1ChR1Data;
+	assign	adcDataBus	[ChNum-2]	=	(IsSim)?AdcData_i:adc2ChR2Data;
+	assign	adcDataBus	[ChNum-1]	=	(IsSim)?AdcData_i:adc2ChT2Data;
 	
 	assign	gainManual	[ChNum-4]	=	gainCtrl[5];
 	assign	gainManual	[ChNum-3]	=	gainCtrl[4];
@@ -733,10 +734,10 @@ ExternalDspInterface
 	
 	.OscDataRdFlag_o	(oscDataRdFlag),
 	
-	.Adc1ChT1Data_i		(adc1ChT1Data),	
-	.Adc1ChR1Data_i		(adc1ChR1Data),	
-	.Adc2ChR2Data_i		(adc2ChR2Data),	
-	.Adc2ChT2Data_i		(adc2ChT2Data),		
+	.Adc1ChT1Data_i		(adcDataBus[ChNum-4]),	
+	.Adc1ChR1Data_i		(adcDataBus[ChNum-3]),	
+	.Adc2ChR2Data_i		(adcDataBus[ChNum-2]),	
+	.Adc2ChT2Data_i		(adcDataBus[ChNum-1]),		
 	
 	.Mosi_o				(adcInitMosi),
 	.Sck_o				(adcInitSck),
@@ -797,15 +798,10 @@ InternalDsp
 	.NcoRst_i				(ncoRst),
 	.OscWind_o				(oscWind),
 
-	.Adc1ChT1Data_i			(adc1ChT1Data),	//T1
-	.Adc1ChR1Data_i			(adc1ChR1Data),	//R1
-	.Adc2ChR2Data_i			(adc2ChR2Data),	//R2
-	.Adc2ChT2Data_i			(adc2ChT2Data),	//T2
-
-	// .Adc1ChT1Data_i			(AdcData_i),	//T1
-	// .Adc1ChR1Data_i			(AdcData_i),	//R1
-	// .Adc2ChR2Data_i			(AdcData_i),	//R2
-	// .Adc2ChT2Data_i			(AdcData_i),	//T2
+	.Adc1ChT1Data_i			(adcDataBus[ChNum-4]),	//T1
+	.Adc1ChR1Data_i			(adcDataBus[ChNum-3]),	//R1
+	.Adc2ChR2Data_i			(adcDataBus[ChNum-2]),	//R2
+	.Adc2ChT2Data_i			(adcDataBus[ChNum-1]),	//T2
 
 	.GatingPulse_i			(gatingPulse),
 
@@ -1060,6 +1056,8 @@ StartAfterGainSel
 StartAfterGainSelInst
 (
 	.Rst_i			(initRst),
+	.Clk_i			(gclk),
+	
 	.GainCtrl_i		(gainAutoEn),
 	.MeasStart_i	(measStartBus),
 	
@@ -1234,7 +1232,6 @@ PulseGen
 PulseGenerator
 (
 	.Rst_i			(initRst|pGenRst[j]|pGenMeasRst[j]),
-	// .Rst_i			(initRst|pGenMeasRst[j]),
 	.Clk_i			(gclk),
 	.EnPulse_i		(pgMuxedOut[j]),
 	
@@ -1492,19 +1489,6 @@ SampleStrobeGenRstDemux
 	.RstDemuxOut_o	(pGenMeasRst)
 );	
 
-// --------------------------------------------------------------------------------
-	// Active Port Selection
-// --------------------------------------------------------------------------------	
-// ActivePortSelector	ActivePortSel
-// (
-	// .Rst_i		(initRst),
-	
-	// .Mod_i		(slowMod),
-	// .Ctrl_i		(measCtrl[7:4]),
-	
-	// .Ctrl_o		(modKeyCtrl)
-// );
-
 //--------------------------------------------------------------------------------
 //	Debug led
 //--------------------------------------------------------------------------------	

S5444_S/src/src/AdcDataRx/AdcDataInterface.v

@@ -1,4 +1,5 @@
 `timescale 1ns / 1ps
+(* keep_hierarchy = "yes" *)
 //////////////////////////////////////////////////////////////////////////////////
 // company: 
 // engineer: 
@@ -29,8 +30,6 @@ module	AdcDataInterface
 	input	RefClk_i,
 	input	Locked_i,
 	input	Rst_i,
-	
-	input	[AdcDataWidth-1:0]	testAdc,
 		
 	input	Adc1FclkP_i,		
     input	Adc1FclkN_i,		

S5444_S/src/src/ExtDspInterface/QuadSlaveSpi.v

@@ -60,6 +60,10 @@ module	QuadSlaveSpi
 	
 	reg	[CmdRegWidth-1:0] singleCaptReg;
 	
+	reg	[CmdRegWidth-1:0] outDataReg;
+	reg	[CmdRegWidth-1:0] outDataReg1;
+	reg	[CmdRegWidth-1:0] outDataReg2;
+	
 	reg [QuadSpiRegWidth-1:0] quadCaptReg0;
 	reg [QuadSpiRegWidth-1:0] quadCaptReg1;
 	reg [QuadSpiRegWidth-1:0] quadCaptReg2;
@@ -70,7 +74,6 @@ module	QuadSlaveSpi
 	reg	spiMode;
 	wire directTransit	=	(ansAddr	==	Adc0DirAccessAddr)|(ansAddr	==	Adc1DirAccessAddr);
 
-	
 	reg	txWind;
 	reg	[4:0]	txCnt;
 
@@ -84,48 +87,49 @@ module	QuadSlaveSpi
 	
 	assign	AnsAddr_o	=	ansAddr;
 	assign	Miso0_Mosi2_io		=	txWind?	AnsReg_i[txCnt]:1'bz;
+	assign	Miso1_Mosi3_io		=	txWind?	AnsReg_i[txCnt]:1'bz;
 //================================================================================
 //	CODING
 //================================================================================
 	
-	always @(posedge Rst_i or posedge Sck_i) begin
-		if (Rst_i) begin
+	always @(posedge Ss_i or posedge Sck_i) begin
+		if (Ss_i) begin
 			singleCaptReg <= 0;
 			quadCaptReg0 <= 0;
 			quadCaptReg1 <= 0;
 			quadCaptReg2 <= 0;
 			quadCaptReg3 <= 0;
 		end else begin
-			if (!Ss_i) begin
-				if (SpiRst_i) begin
-					singleCaptReg <= {singleCaptReg[CmdRegWidth-2:0],Mosi0_i};
-					quadCaptReg0 <= 0;
-					quadCaptReg1 <= 0;
-					quadCaptReg2 <= 0;
-					quadCaptReg3 <= 0;
-				end else begin
-					singleCaptReg <= 0;
-					quadCaptReg0 <= {quadCaptReg0[QuadSpiRegWidth-2:0],Mosi0_i};
-					quadCaptReg1 <= {quadCaptReg1[QuadSpiRegWidth-2:0],Mosi1_i};
-					quadCaptReg2 <= {quadCaptReg2[QuadSpiRegWidth-2:0],Miso0_Mosi2_io};
-					quadCaptReg3 <= {quadCaptReg3[QuadSpiRegWidth-2:0],Miso1_Mosi3_io};
-				end
-			end
+			singleCaptReg <= {singleCaptReg[CmdRegWidth-2:0],Mosi0_i};
+			quadCaptReg0 <= {quadCaptReg0[QuadSpiRegWidth-2:0],Mosi0_i};
+			quadCaptReg1 <= {quadCaptReg1[QuadSpiRegWidth-2:0],Mosi1_i};
+			quadCaptReg2 <= {quadCaptReg2[QuadSpiRegWidth-2:0],Miso0_Mosi2_io};
+			quadCaptReg3 <= {quadCaptReg3[QuadSpiRegWidth-2:0],Miso1_Mosi3_io};
 		end 
 	end
 	
-	always @(posedge Rst_i or posedge Sck_i)	begin
-		if	(Rst_i)	begin
-			dataCnt	<=	0;
+	always @(posedge Sck_i) begin
+		if (SpiRst_i) begin
+			if (dataCnt == 5'd31) begin
+				outDataReg <= {singleCaptReg[CmdRegWidth-2:0], Mosi0_i};
+			end
 		end else begin
-			if	(~Ss_i)	begin
-				dataCnt	<=	dataCnt	+	5'd1;
+			if (dataCnt == 5'd7) begin
+				outDataReg <= {{quadCaptReg3[QuadSpiRegWidth-2:0],Miso1_Mosi3_io},{quadCaptReg2[QuadSpiRegWidth-2:0],Miso0_Mosi2_io},{quadCaptReg1[QuadSpiRegWidth-2:0],Mosi1_i},{quadCaptReg0[QuadSpiRegWidth-2:0],Mosi0_i}};
 			end
 		end
 	end
+	
+	always @(posedge Ss_i or posedge Sck_i)	begin
+		if	(Ss_i)	begin
+			dataCnt	<=	0;
+		end else begin
+			dataCnt	<=	dataCnt	+	5'd1;
+		end
+	end
 
-	always @(posedge Rst_i or posedge Sck_i)	begin
-		if	(Rst_i)	begin
+	always @(posedge Ss_i or posedge Sck_i)	begin
+		if	(Ss_i)	begin
 			spiMode	<=	1'b0;
 		end else begin
 			if	(dataCnt	==	5'd1)	begin
@@ -146,20 +150,16 @@ module	QuadSlaveSpi
 		end
 	end
 
-	always @(posedge Rst_i or negedge Sck_i)	begin
-		if	(Rst_i)	begin
+	always @(posedge Ss_i or negedge Sck_i)	begin
+		if	(Ss_i)	begin
 			ansAddr	<=	7'h7F;	
 		end else begin
-			if	(~Ss_i)	begin
-				if	(dataCnt	==	5'd8)	begin
-					if (SpiRst_i) begin
-						ansAddr	<=	singleCaptReg[QuadSpiRegWidth-1:0];
-					end	else	begin
-						ansAddr	<=	quadCaptReg3[QuadSpiRegWidth-1:0];
-					end 
-				end
-			end	else	begin
-				ansAddr	<=	7'h7F;	
+			if	(dataCnt	==	5'd8)	begin
+				if (SpiRst_i) begin
+					ansAddr	<=	singleCaptReg[QuadSpiRegWidth-1:0];
+				end	else	begin
+					ansAddr	<=	quadCaptReg3[QuadSpiRegWidth-1:0];
+				end 
 			end
 		end
 	end
@@ -212,18 +212,18 @@ module	QuadSlaveSpi
 		end
 	end
 
-	always @(posedge Rst_i or posedge Clk_i)	begin
-		if (Rst_i) 	begin
+	always	@(posedge	Clk_i)	begin
+		if (Rst_i) begin
+			outDataReg1 <= 0;
+			outDataReg2 <= 0;
 			Data_o <= 0;
 		end else begin
-			if (SpiRst_i) begin
-				Data_o <= singleCaptReg;
-			end else begin
-				Data_o <= {quadCaptReg3,quadCaptReg2,quadCaptReg1,quadCaptReg0};
-			end
+			outDataReg1 <= outDataReg;
+			outDataReg2 <= outDataReg1;
+			Data_o <= outDataReg2;
 		end
 	end
-
+	
 	always	@(*)	begin
 		if	(spiMode	&	!Ss_i)	begin
 			if	(dataCnt	>=5'd8|dataCnt	==	0)	begin

S5444_S/src/src/InternalDsp/InternalDsp.v

@@ -1,5 +1,5 @@
 `timescale 1ns / 1ps
-(* keep_hierarchy = "yes" *)
+// (* keep_hierarchy = "yes" *)
 //////////////////////////////////////////////////////////////////////////////////
 // Company: 
 // Engineer: 
@@ -103,19 +103,16 @@ module InternalDsp
 
 	wire	[NcoWidth-1:0]	ncoCosFirstTone;
 	wire	[NcoWidth-1:0]	ncoSinFirstTone;
-	
 	wire	[NcoWidth-1:0]	ncoCosSecondTone;
 	wire	[NcoWidth-1:0]	ncoSinSecondTone;
 	
-	wire	[NcoWidth-1:0]	ncoCosMuxedTone	[ChNum-1:0];
-	wire	[NcoWidth-1:0]	ncoSinMuxedTone	[ChNum-1:0];
+	reg		[NcoWidth-1:0]	currNcoSinTone [ChNum-1:0];
+	reg		[NcoWidth-1:0]	currNcoCosTone [ChNum-1:0];
 	
 	wire	[CorrAdcDataWidth-1:0]	adcDataBus	[ChNum-1:0];
 	wire	[CorrAdcDataWidth-1:0]	adcDataBusExt	[ChNum-1:0];
 	wire	[CorrAdcDataWidth-1:0]	gatedAdcDataBus	[ChNum-1:0];
 	
-	wire	[CorrAdcDataWidth-1:0]	AdcDataBusMuxed	[ChNum-1:0];
-	
 	wire	[CorrAdcDataWidth-1:0]	calAdcData		[ChNum-1:0];
 	wire	[CorrAdcDataWidth-1:0]	prngData;
 	reg		[CorrAdcDataWidth-1:0]	prngDataBus		[ChNum-1:0];
@@ -153,15 +150,24 @@ module InternalDsp
 	wire	[CorrAdcDataWidth-1:0]	adc2ChR2DataGated	=	(GatingPulse_i)?	adcDataBusExt[ChNum-2]:{CorrAdcDataWidth{1'b0}};
 	wire	[CorrAdcDataWidth-1:0]	adc2ChT2DataGated	=	(GatingPulse_i)?	adcDataBusExt[ChNum-1]:{CorrAdcDataWidth{1'b0}};	
 	
-	wire	grDelayMeasFlag = (measCtrlReg[1:0] == 2'h2);
+	reg	grDelayMeasFlag;
 	
+	reg	[AdcDataWidth-1:0]	adc1ChT1DataR;
+	reg	[AdcDataWidth-1:0]	adc1ChR1DataR;
+	reg	[AdcDataWidth-1:0]	adc2ChR2DataR;
+	reg	[AdcDataWidth-1:0]	adc2ChT2DataR;
 //================================================================================
 //  ASSIGNMENTS
+	
+	assign	adcDataBus	[ChNum-1]	=	{{2{adc2ChT2DataR[AdcDataWidth-1]}},adc2ChT2DataR,4'b0};
+	assign	adcDataBus	[ChNum-2]	=	{{2{adc2ChR2DataR[AdcDataWidth-1]}},adc2ChR2DataR,4'b0};
+	assign	adcDataBus	[ChNum-3]	=	{{2{adc1ChR1DataR[AdcDataWidth-1]}},adc1ChR1DataR,4'b0};
+	assign	adcDataBus	[ChNum-4]	=	{{2{adc1ChT1DataR[AdcDataWidth-1]}},adc1ChT1DataR,4'b0};
 
-	assign	adcDataBus	[ChNum-1]	=	{{2{Adc2ChT2Data_i[AdcDataWidth-1]}},Adc2ChT2Data_i,4'b0};
-	assign	adcDataBus	[ChNum-2]	=	{{2{Adc2ChR2Data_i[AdcDataWidth-1]}},Adc2ChR2Data_i,4'b0};
-	assign	adcDataBus	[ChNum-3]	=	{{2{Adc1ChR1Data_i[AdcDataWidth-1]}},Adc1ChR1Data_i,4'b0};
-	assign	adcDataBus	[ChNum-4]	=	{{2{Adc1ChT1Data_i[AdcDataWidth-1]}},Adc1ChT1Data_i,4'b0};
+	// assign	adcDataBus	[ChNum-1]	=	{{2{ncoSinFirstTone[NcoWidth-1]}},ncoSinFirstTone[NcoWidth-1-:14],4'b0};
+	// assign	adcDataBus	[ChNum-2]	=	{{2{ncoSinFirstTone[NcoWidth-1]}},ncoSinFirstTone[NcoWidth-1-:14],4'b0};
+	// assign	adcDataBus	[ChNum-3]	=	{{2{ncoSinFirstTone[NcoWidth-1]}},ncoSinFirstTone[NcoWidth-1-:14],4'b0};
+	// assign	adcDataBus	[ChNum-4]	=	{{2{ncoSinFirstTone[NcoWidth-1]}},ncoSinFirstTone[NcoWidth-1-:14],4'b0};	
 	
 	assign	adcDataBusExt	[ChNum-1]	=	calAdcData	[ChNum-1]+prngDataBus[ChNum-1];
 	assign	adcDataBusExt	[ChNum-2]	=	calAdcData	[ChNum-2]+prngDataBus[ChNum-2];
@@ -177,13 +183,12 @@ module InternalDsp
 	assign	Adc1ReT1Data_o	=	resultReBus	[ChNum-4];
 	assign	Adc1ImR1Data_o	=	resultImBus	[ChNum-3];
 	assign	Adc1ReR1Data_o	=	resultReBus	[ChNum-3];
-	//adc2                 
+              
 	assign	Adc2ImR2Data_o	=	resultImBus	[ChNum-2];
 	assign	Adc2ReR2Data_o	=	resultReBus	[ChNum-2];
 	assign	Adc2ImT2Data_o	=	resultImBus	[ChNum-1];
 	assign	Adc2ReT2Data_o	=	resultReBus	[ChNum-1];
 	
-	
 	assign	MeasDataRdy_o	=	&resultValBus;
 	assign	EndMeas_o		=	stopMeas;
 	
@@ -199,6 +204,43 @@ module InternalDsp
 //----------------------------------------------
 //Module generates event signals for measurement
 
+always	@(posedge	Clk_i)	begin
+	if	(Rst_i)	begin
+		adc1ChT1DataR	<= 0;
+		adc1ChR1DataR	<= 0;
+		adc2ChR2DataR	<= 0;
+		adc2ChT2DataR	<= 0;
+	end	else	begin
+		if (grDelayMeasFlag) begin
+			adc1ChT1DataR	<= Adc1ChT1Data_i;
+			adc1ChR1DataR	<= Adc1ChT1Data_i;
+			adc2ChR2DataR	<= Adc2ChT2Data_i;
+			adc2ChT2DataR	<= Adc2ChT2Data_i;
+			currNcoSinTone [0] <= ncoSinFirstTone;
+			currNcoSinTone [1] <= ncoSinSecondTone;
+			currNcoSinTone [2] <= ncoCosFirstTone;
+			currNcoSinTone [3] <= ncoCosSecondTone;
+			currNcoCosTone [0] <= ncoCosFirstTone;
+			currNcoCosTone [1] <= ncoCosSecondTone;
+			currNcoCosTone [2] <= ncoCosFirstTone;
+			currNcoCosTone [3] <= ncoCosSecondTone;
+		end else begin
+			adc1ChT1DataR	<= Adc1ChT1Data_i;
+			adc1ChR1DataR	<= Adc1ChR1Data_i;
+			adc2ChR2DataR	<= Adc2ChR2Data_i;
+			adc2ChT2DataR	<= Adc2ChT2Data_i;
+			currNcoSinTone [0] <= ncoSinFirstTone;
+			currNcoSinTone [1] <= ncoSinFirstTone;
+			currNcoSinTone [2] <= ncoSinFirstTone;
+			currNcoSinTone [3] <= ncoSinFirstTone;
+			currNcoCosTone [0] <= ncoCosFirstTone;
+			currNcoCosTone [1] <= ncoCosFirstTone;
+			currNcoCosTone [2] <= ncoCosFirstTone;
+			currNcoCosTone [3] <= ncoCosFirstTone;
+		end
+	end 
+end
+
 always	@(posedge	Clk_i)	begin
 	if	(!Rst_i)	begin
 		if	(!StartMeas_i)	begin
@@ -211,6 +253,7 @@ always	@(posedge	Clk_i)	begin
 			filterCorrCoefHReg	<=	FilterCorrCoefH_i;
 			measNumReg			<=	MeasNum_i;
 			windPointsNumReg	<=	windPointsNum;
+			grDelayMeasFlag		<=	(measCtrlReg[1:0] == 2'h2);
 		end 
 	end	else	begin
 		measCtrlReg			<=	0;
@@ -222,6 +265,7 @@ always	@(posedge	Clk_i)	begin
 		filterCorrCoefHReg	<=	0;
 		measNumReg			<=	0;
 		windPointsNumReg	<=	0;
+		grDelayMeasFlag		<=	0;
 	end 
 end
 
@@ -294,18 +338,6 @@ Win_calc	WinCalcInst
 	.win_o			(wind)
 );
 
-// Approximation3 WindCalc2
-// (
-    // .Clk_i			(Clk_i), 
-    // .Rst_i			(Rst_i),
-    // .Clk100_i		(WindCalcClk_i),
-    // .WinCtrl_i		(winCtrl),
-    // .Win_value_i	(windArg),
-    // .filterCmd_i	(measCtrlReg[15-:8]), 
-	// .Win_o			(wind)
-// );
-
-
 //----------------------------------------------
 //Module generates Sin and Cos for measurement
 
@@ -392,133 +424,41 @@ generate
 			.CalibratedAdcData_o	(calAdcData[g])
 		);
 		
-		if	(g==1)	begin
-			GrDelModeMux	
-			#(	
-				.AdcDataWidth	(CorrAdcDataWidth),
-				.NcoDataWidth	(NcoWidth)
-			)
-			GrDelModeMux
-			(
-				.Rst_i	(Rst_i),
-				
-				.MuxCtrl_i	(grDelayMeasFlag),
-	
-				.AdcDataOrig_i	(gatedAdcDataBus[g]),
-				.AdcDataGrDel_i	(gatedAdcDataBus[g-1]),
-				
-				.NcoSinOrig_i	(ncoSinFirstTone),
-				.NcoCosOrig_i	(ncoCosFirstTone),
-				.NcoSinGrDel_i	(ncoSinSecondTone),
-				.NcoCosGrDel_i	(ncoCosSecondTone),
-				
-				.MuxAdcData_o	(AdcDataBusMuxed[g]),
-				.MuxNcoSin_o	(ncoSinMuxedTone[g]),
-				.MuxNcoCos_o	(ncoCosMuxedTone[g])
-			);	
-		end
-		
-		if	(g==3)	begin
-			GrDelModeMux	
-			#(	
-				.AdcDataWidth	(CorrAdcDataWidth),
-				.NcoDataWidth	(NcoWidth)
-			)
-			GrDelModeMux
-			(
-				.Rst_i	(Rst_i),
-				
-				.MuxCtrl_i	(grDelayMeasFlag),
-	
-				.AdcDataOrig_i	(gatedAdcDataBus[g]),
-				.AdcDataGrDel_i	(gatedAdcDataBus[g-1]),
-				
-				.NcoSinOrig_i	(ncoSinFirstTone),
-				.NcoCosOrig_i	(ncoCosFirstTone),
-				.NcoSinGrDel_i	(ncoSinSecondTone),
-				.NcoCosGrDel_i	(ncoCosSecondTone),
-				
-				.MuxAdcData_o	(AdcDataBusMuxed[g]),
-				.MuxNcoSin_o	(ncoSinMuxedTone[g]),
-				.MuxNcoCos_o	(ncoCosMuxedTone[g])
-			);	
-		end
-		
-		if (g==1||g==3) begin
-			DspPipeline	
-			#(	
-				.AdcDataWidth		(AdcDataWidth),
-				.AccWidth			(AccWidth),
-				.WindWidth			(WindWidth),
-				.NcoWidth			(NcoWidth),
-				.ResultWidth		(ResultWidth),
-				.WindCorrCoefWidth	(WindCorrCoefWidth),
-				.WindNormCoefWidth	(WindNormCoefWidth),
-				.IntermediateWidth	(IntermediateWidth)
-			)
-			DspPipelineInst
-			(
-				.Clk_i				(Clk_i),
-				.Rst_i				(Rst_i),
-				.Val_i				(measWind),
-				.MeasWindEnd_i		(measWindEnd),
-				.StartFpConv_i		(measWindEnd),
-				
-				.FilterCorrCoef_i	({filterCorrCoefHReg[0+:WindNcoPhIncWidth-CmdDataRegWith],filterCorrCoefLReg}),
-				// .FilterCorrCoef_i	(32'h3f800000),
-				.AverageNoizeLvl_i	(averageNoizeLvl),
-				// .AdcData_i			(gatedAdcDataBus[g]),
-				.AdcData_i			(AdcDataBusMuxed[g]),
-				// .AdcData_i			({{2{ncoCosFirstTone[17]}},ncoCosFirstTone}),
-				.Wind_i				(wind),
-				.NcoSin_i			(ncoSinMuxedTone[g]),
-				.NcoCos_i			(ncoCosMuxedTone[g]),	
-				.NormCoef_i			(windNormCoef),
-				// .NormCoef_i			(32'h3f800000),
-				// .NormCoef_i			(32'h3f03993a),
-	
-				.CorrResultIm_o		(resultImBus[g]),
-				.CorrResultRe_o		(resultReBus[g]),
-				.CorrResultVal_o	(resultValBus[g])
-			);
-		end else begin
-			DspPipeline	
-			#(	
-				.AdcDataWidth		(AdcDataWidth),
-				.AccWidth			(AccWidth),
-				.WindWidth			(WindWidth),
-				.NcoWidth			(NcoWidth),
-				.ResultWidth		(ResultWidth),
-				.WindCorrCoefWidth	(WindCorrCoefWidth),
-				.WindNormCoefWidth	(WindNormCoefWidth),
-				.IntermediateWidth	(IntermediateWidth)
-			)
-			DspPipelineInst
-			(
-				.Clk_i				(Clk_i),
-				.Rst_i				(Rst_i),
-				.Val_i				(measWind),
-				.MeasWindEnd_i		(measWindEnd),
-				.StartFpConv_i		(measWindEnd),
-				
-				.FilterCorrCoef_i	({filterCorrCoefHReg[0+:WindNcoPhIncWidth-CmdDataRegWith],filterCorrCoefLReg}),
-				// .FilterCorrCoef_i	(32'h3f800000),
-				.AverageNoizeLvl_i	(averageNoizeLvl),
-				.AdcData_i			(gatedAdcDataBus[g]),
-				// .AdcData_i			(AdcDataBusMuxed[g]),
-				// .AdcData_i			({{2{ncoCosFirstTone[17]}},ncoCosFirstTone}),
-				.Wind_i				(wind),
-				.NcoSin_i			(ncoSinFirstTone),
-				.NcoCos_i			(ncoCosFirstTone),	
-				.NormCoef_i			(windNormCoef),
-				// .NormCoef_i			(32'h3f800000),
-				// .NormCoef_i			(32'h3f03993a),
-	
-				.CorrResultIm_o		(resultImBus[g]),
-				.CorrResultRe_o		(resultReBus[g]),
-				.CorrResultVal_o	(resultValBus[g])
-			);
-		end
+		DspPipeline	
+		#(	
+			.AdcDataWidth		(AdcDataWidth),
+			.AccWidth			(AccWidth),
+			.WindWidth			(WindWidth),
+			.NcoWidth			(NcoWidth),
+			.ResultWidth		(ResultWidth),
+			.WindCorrCoefWidth	(WindCorrCoefWidth),
+			.WindNormCoefWidth	(WindNormCoefWidth),
+			.IntermediateWidth	(IntermediateWidth)
+		)
+		DspPipelineInst
+		(
+			.Clk_i				(Clk_i),
+			.Rst_i				(Rst_i),
+			.Val_i				(measWind),
+			.MeasWindEnd_i		(measWindEnd),
+			.StartFpConv_i		(measWindEnd),
+			
+			.FilterCorrCoef_i	({filterCorrCoefHReg[0+:WindNcoPhIncWidth-CmdDataRegWith],filterCorrCoefLReg}),
+			// .FilterCorrCoef_i	(32'h3f800000),
+			.AverageNoizeLvl_i	(averageNoizeLvl),
+			.AdcData_i			(gatedAdcDataBus[g]),
+			.Wind_i				(wind),
+			// .NcoSin_i			(ncoSinFirstTone),
+			// .NcoCos_i			(ncoCosFirstTone),
+			
+			.NcoSin_i			(currNcoSinTone[g]),
+			.NcoCos_i			(currNcoCosTone[g]),	
+			.NormCoef_i			(windNormCoef),
+
+			.CorrResultIm_o		(resultImBus[g]),
+			.CorrResultRe_o		(resultReBus[g]),
+			.CorrResultVal_o	(resultValBus[g])
+		);
 	end
 endgenerate
 

S5444_S/src/src/PulseMeas/StartAfterGainSel.v

@@ -24,6 +24,8 @@ module StartAfterGainSel
 )	
 (
 	input	Rst_i,	
+	input	Clk_i,	
+	
 	input	[ChNum-1:0]	MeasStart_i,
 	input	[ChNum-1:0]	GainCtrl_i,
 	
@@ -42,59 +44,61 @@ module StartAfterGainSel
 //================================================================================
 //  CODING
 
-always	@(*)	begin
-	if	(!Rst_i)	begin
+always	@(posedge Rst_i or posedge Clk_i)	begin
+	if	(Rst_i)	begin
+		measStart <= 0;
+	end else begin
 		case(GainCtrl_i)
 			4'd0:	begin
-						measStart	=	&MeasStart_i;
+						measStart	<=	&MeasStart_i;
 					end
 			4'd1:	begin
-						measStart	=	MeasStart_i[0];
+						measStart	<=	MeasStart_i[0];
 					end
 			4'd2:	begin
-						measStart	=	MeasStart_i[1];
+						measStart	<=	MeasStart_i[1];
 					end
 			4'd3:	begin
-						measStart	=	MeasStart_i[0]&MeasStart_i[1];
+						measStart	<=	MeasStart_i[0]&MeasStart_i[1];
 					end
 			4'd4:	begin
-						measStart	=	&MeasStart_i[2];
+						measStart	<=	&MeasStart_i[2];
 					end
 			4'd5:	begin
-						measStart	=	MeasStart_i[0]&MeasStart_i[2];
+						measStart	<=	MeasStart_i[0]&MeasStart_i[2];
 					end
 			4'd6:	begin
-						measStart	=	MeasStart_i[1]&MeasStart_i[2];
+						measStart	<=	MeasStart_i[1]&MeasStart_i[2];
 					end
 			4'd7:	begin
-						measStart	=	MeasStart_i[0]&MeasStart_i[1]&MeasStart_i[2];
+						measStart	<=	MeasStart_i[0]&MeasStart_i[1]&MeasStart_i[2];
 					end
 			4'd8:	begin
-						measStart	=	MeasStart_i[3];
+						measStart	<=	MeasStart_i[3];
 					end
 			4'd9:	begin
-						measStart	=	MeasStart_i[0]&MeasStart_i[3];
+						measStart	<=	MeasStart_i[0]&MeasStart_i[3];
 					end
 			4'd10:	begin
-						measStart	=	MeasStart_i[1]&MeasStart_i[3];
+						measStart	<=	MeasStart_i[1]&MeasStart_i[3];
 					end
 			4'd11:	begin
-						measStart	=	MeasStart_i[0]&MeasStart_i[1]&MeasStart_i[3];
+						measStart	<=	MeasStart_i[0]&MeasStart_i[1]&MeasStart_i[3];
 					end
 			4'd12:	begin
-						measStart	=	MeasStart_i[2]&MeasStart_i[3];
+						measStart	<=	MeasStart_i[2]&MeasStart_i[3];
 					end
 			4'd13:	begin
-						measStart	=	MeasStart_i[0]&MeasStart_i[2]&MeasStart_i[3];
+						measStart	<=	MeasStart_i[0]&MeasStart_i[2]&MeasStart_i[3];
 					end
 			4'd14:	begin
-						measStart	=	MeasStart_i[1]&MeasStart_i[2]&MeasStart_i[3];
+						measStart	<=	MeasStart_i[1]&MeasStart_i[2]&MeasStart_i[3];
 					end
 			4'd15:	begin
-						measStart	=	&MeasStart_i;
+						measStart	<=	&MeasStart_i;
 					end		
 			default:	begin
-							measStart	=	&MeasStart_i;
+							measStart	<=	&MeasStart_i;
 						end
 		endcase
 	end

S5444_S/src/src/Sim/S5443TopPulseProfileTb.v

@@ -1,4 +1,4 @@
-`timescale 1ns / 1ps
+`timescale 10ns / 10ps
 
 //=============================================================================================================
 
@@ -31,64 +31,73 @@
 //=============================================================================================================
 module S5443TopPulseProfileTb;
 	
-	localparam	[3:0]	EP1MUXCMD	=	4'd1;
-	localparam	[3:0]	EP2MUXCMD	=	4'd1;
-	localparam	[3:0]	EP3MUXCMD	=	4'd1;
-	localparam	[3:0]	EP4MUXCMD	=	4'd1;
-	localparam	[3:0]	EP5MUXCMD	=	4'd1;
-	localparam	[3:0]	EP6MUXCMD	=	4'd1;
-	
-	localparam	[3:0]	PG1MUXCMD	=	4'd13;
-	localparam	[3:0]	PG2MUXCMD	=	4'd0;
-	localparam	[3:0]	PG3MUXCMD	=	4'd0;
-	localparam	[3:0]	PG4MUXCMD	=	4'd0;
-	localparam	[3:0]	PG5MUXCMD	=	4'd0;
-	localparam	[3:0]	PG6MUXCMD	=	4'd0;
-	localparam	[3:0]	PG7MUXCMD	=	4'd0;
-	
-	localparam	[2:0]	PG1MODE	=	3'd1;
+	parameter	IsSim	=	1'b1;
+	localparam	[4:0]	EP1MUXCMD	=	5'd14;
+	localparam	[4:0]	EP2MUXCMD	=	5'd1;
+	localparam	[4:0]	EP3MUXCMD	=	5'd1;
+	localparam	[4:0]	EP4MUXCMD	=	5'd1;
+	localparam	[4:0]	EP5MUXCMD	=	5'd1;
+	localparam	[4:0]	EP6MUXCMD	=	5'd1;
+	
+	localparam	[4:0]	PG1MUXCMD	=	5'd13;
+	localparam	[4:0]	PG2MUXCMD	=	5'd0;
+	localparam	[4:0]	PG3MUXCMD	=	5'd18;
+	localparam	[4:0]	PG4MUXCMD	=	5'd18;
+	localparam	[4:0]	PG5MUXCMD	=	5'd0;
+	localparam	[4:0]	PG6MUXCMD	=	5'd0;
+	localparam	[4:0]	PG7MUXCMD	=	5'd0;
+	
+	localparam	[2:0]	PG1MODE	=	3'd5;
 	localparam	[2:0]	PG2MODE	=	3'd1;
-	localparam	[2:0]	PG3MODE	=	3'd0;
+	localparam	[2:0]	PG3MODE	=	3'd3;
 	localparam	[2:0]	PG4MODE	=	3'd4;
 	localparam	[2:0]	PG5MODE	=	3'd0;
-	localparam	[2:0]	PG6MODE	=	3'd3;
-	localparam	[2:0]	PG7MODE	=	3'd0;
+	localparam	[2:0]	PG6MODE	=	3'd0;
+	localparam	[2:0]	PG7MODE	=	3'd3;
 	
 	localparam	PG1POL	=	1'b0;
 	localparam	PG2POL	=	1'b0;
-	localparam	PG3POL	=	1'b1;
+	localparam	PG3POL	=	1'b0;
 	localparam	PG4POL	=	1'b0;
 	localparam	PG5POL	=	1'b0;
 	localparam	PG6POL	=	1'b0;
 	localparam	PG7POL	=	1'b0;
 	
-	localparam	[3:0]	EXTTRIGMUXCMD	=	4'd15;
-	localparam	[3:0]	MODMUXCMD		=	4'd1;
-	localparam	[3:0]	GATINGMUXCMD	=	4'd2;
-	localparam	[3:0]	SMPLSTRBMUXCMD	=	4'd3;
+	localparam	[4:0]	EXTTRIGMUXCMD	=	5'd15;
+	localparam	[4:0]	DSPTRIGINCMD	=	5'h8;
+	localparam	[4:0]	MUXSLOWMODCMD	=	5'd1;
+	localparam	[4:0]	MUXFASTMODCMD	=	5'd1;
+	localparam	[4:0]	GATINGMUXCMD	=	5'd2;
+	localparam	[4:0]	SMPLSTRBMUXCMD	=	5'd3;
 	
 	//COMMANDS	FOR REG_MAP
-	parameter	[31:0]	MeasCmd =	{8'h11,8'h0,8'h55,8'h0};
-	// parameter	[31:0]	MeasCmd =	{8'h11,8'h0,8'h64,8'h0};
+	parameter	[31:0]	MeasCmdBypass	=	{8'h11,8'h0,8'h63,8'h1};
+	parameter	[31:0]	MeasCmdFft 		=	{8'h11,8'h0,8'h63,7'h5,1'b1};
+	// parameter	[31:0]	MeasCmd 		=	{8'h11,8'h0,8'h53,8'h0};
+	parameter	[31:0]	MeasCmd =	{8'h11,6'h0,8'h63,4'h0,4'h0,2'h2};
+	parameter	[23:0]	testCmd = {6'h0,8'h63,4'h0,4'h0,2'h2};
 	parameter	[31:0]	AdcCtrl =	{8'h12,24'h2};
-	parameter	[31:0]	IfFtwH 	=	{8'h15,16'h0,8'h38};
-	parameter	[31:0]	IfFtwL 	=	{8'h16,24'h51eb85};
+	parameter	[31:0]	SensCtrlCmd =	{1'b0,27'h0,4'b1};
+	// parameter	[31:0]	DitherCmd 	= {8'h0E,24'h100192};
+	parameter	[31:0]	DitherCmd 	= {8'h0E,8'd9,4'h0,4'h1,4'd11,4'h3};
+	parameter	[31:0]	IfFtwH 	=	{8'h15,16'h0,8'h40};
+	parameter	[31:0]	IfFtwL 	=	{8'h16,24'h000000};
 	parameter	[31:0]	FilterCorrCmdH 		=	{8'h17,24'hD70A3D};
 	parameter	[31:0]	FilterCorrCmdL 		=	{8'h18,24'hD70A3D};
 	
 	//PG7 Cmd
 	parameter	[31:0]	PG7P1DelayRegCmd	=	{8'h20,24'd0};
-	parameter	[31:0]	PG7P2DelayRegCmd	=	{8'h21,24'd0};
-	parameter	[31:0]	PG7P3DelayRegCmd	=	{8'h22,24'd0};
-	parameter	[31:0]	PG7P123DelayRegCmd	=	{8'h23,24'd0};
+	parameter	[31:0]	PG7P2DelayRegCmd	=	{8'h21,24'd1};
+	parameter	[31:0]	PG7P3DelayRegCmd	=	{8'h22,24'd5};
+	parameter	[31:0]	PG7P123DelayRegCmd	=	{8'h23,24'd15};
 	parameter	[31:0]	PG7P1WidthRegCmd	=	{8'h24,24'd1};
-	parameter	[31:0]	PG7P2WidthRegCmd	=	{8'h25,24'd0};
-	parameter	[31:0]	PG7P3WidthRegCmd	=	{8'h26,24'd0};
+	parameter	[31:0]	PG7P2WidthRegCmd	=	{8'h25,24'd3};
+	parameter	[31:0]	PG7P3WidthRegCmd	=	{8'h26,24'd5};
 	parameter	[31:0]	PG7P123WidthRegCmd	=	{8'h27,24'd0};
 
 	//PG1 Cmd
-	parameter	[31:0]	PG1P1DelayRegCmd	=	{8'h28,24'd1};
-	parameter	[31:0]	PG1P2DelayRegCmd	=	{8'h29,24'd0};
+	parameter	[31:0]	PG1P1DelayRegCmd	=	{8'h28,24'd0};
+	parameter	[31:0]	PG1P2DelayRegCmd	=	{8'h29,24'd400};
 	parameter	[31:0]	PG1P3DelayRegCmd	=	{8'h2a,24'd0};
 	parameter	[31:0]	PG1P123DelayRegCmd	=	{8'h2b,24'd0};
 	parameter	[31:0]	PG1P1WidthRegCmd	=	{8'h2c,24'd1};
@@ -97,80 +106,105 @@ module S5443TopPulseProfileTb;
 	parameter	[31:0]	PG1P123WidthRegCmd	=	{8'h2f,24'd0};
 	
 	//PG2 Cmd
-	parameter	[31:0]	PG2P1DelayRegCmd	=	{8'h30,24'd1500};
-	parameter	[31:0]	PG2P2DelayRegCmd	=	{8'h31,24'd0};
-	parameter	[31:0]	PG2P3DelayRegCmd	=	{8'h32,24'd0};
-	parameter	[31:0]	PG2P123DelayRegCmd	=	{8'h33,24'd0};
-	parameter	[31:0]	PG2P1WidthRegCmd	=	{8'h34,24'd3000};
-	parameter	[31:0]	PG2P2WidthRegCmd	=	{8'h35,24'd0};
-	parameter	[31:0]	PG2P3WidthRegCmd	=	{8'h36,24'd0};
-	parameter	[31:0]	PG2P123WidthRegCmd	=	{8'h37,24'd0};
+	parameter	[31:0]	PG2P1DelayRegCmd	=	{8'h20,24'd0};
+	parameter	[31:0]	PG2P2DelayRegCmd	=	{8'h21,24'd1};
+	parameter	[31:0]	PG2P3DelayRegCmd	=	{8'h22,24'd5};
+	parameter	[31:0]	PG2P123DelayRegCmd	=	{8'h23,24'd15};
+	parameter	[31:0]	PG2P1WidthRegCmd	=	{8'h24,24'd1};
+	parameter	[31:0]	PG2P2WidthRegCmd	=	{8'h25,24'd3};
+	parameter	[31:0]	PG2P3WidthRegCmd	=	{8'h26,24'd5};
+	parameter	[31:0]	PG2P123WidthRegCmd	=	{8'h27,24'd0};
 	
 	//PG3 Cmd
-	parameter	[31:0]	PG3P1DelayRegCmd	=	{8'h38,24'd6};
-	parameter	[31:0]	PG3P2DelayRegCmd	=	{8'h39,24'd0};
-	parameter	[31:0]	PG3P3DelayRegCmd	=	{8'h3a,24'd0};
-	parameter	[31:0]	PG3P123DelayRegCmd	=	{8'h3b,24'd0};
-	parameter	[31:0]	PG3P1WidthRegCmd	=	{8'h3c,24'd31};
-	parameter	[31:0]	PG3P2WidthRegCmd	=	{8'h3d,24'd0};
-	parameter	[31:0]	PG3P3WidthRegCmd	=	{8'h3e,24'd0};
-	parameter	[31:0]	PG3P123WidthRegCmd	=	{8'h3f,24'd0};
+	parameter	[31:0]	PG3P1DelayRegCmd	=	{8'h20,24'd0};
+	parameter	[31:0]	PG3P2DelayRegCmd	=	{8'h21,24'd1};
+	parameter	[31:0]	PG3P3DelayRegCmd	=	{8'h22,24'd5};
+	parameter	[31:0]	PG3P123DelayRegCmd	=	{8'h23,24'd15};
+	parameter	[31:0]	PG3P1WidthRegCmd	=	{8'h24,24'd1};
+	parameter	[31:0]	PG3P2WidthRegCmd	=	{8'h25,24'd3};
+	parameter	[31:0]	PG3P3WidthRegCmd	=	{8'h26,24'd5};
+	parameter	[31:0]	PG3P123WidthRegCmd	=	{8'h27,24'd0};
 	
 	//PG4 Cmd
-	parameter	[31:0]	PG4P1DelayRegCmd	=	{8'h40,24'd1};
-	parameter	[31:0]	PG4P2DelayRegCmd	=	{8'h41,24'd65};
+	parameter	[31:0]	PG4P1DelayRegCmd	=	{8'h40,24'd0};
+	parameter	[31:0]	PG4P2DelayRegCmd	=	{8'h41,24'd3};
 	parameter	[31:0]	PG4P3DelayRegCmd	=	{8'h42,24'd0};
 	parameter	[31:0]	PG4P123DelayRegCmd	=	{8'h43,24'd0};
-	parameter	[31:0]	PG4P1WidthRegCmd	=	{8'h44,24'd4};
-	parameter	[31:0]	PG4P2WidthRegCmd	=	{8'h45,24'd100};
+	parameter	[31:0]	PG4P1WidthRegCmd	=	{8'h44,24'd1};
+	parameter	[31:0]	PG4P2WidthRegCmd	=	{8'h45,24'd10};
 	parameter	[31:0]	PG4P3WidthRegCmd	=	{8'h46,24'd7};
 	parameter	[31:0]	PG4P123WidthRegCmd	=	{8'h47,24'd0};
 	
 	//PG5 Cmd
-	parameter	[31:0]	PG5P1DelayRegCmd	=	{8'h48,24'd5};
-	parameter	[31:0]	PG5P2DelayRegCmd	=	{8'h49,24'd15};
-	parameter	[31:0]	PG5P3DelayRegCmd	=	{8'h4a,24'd30};
+	parameter	[31:0]	PG5P1DelayRegCmd	=	{8'h48,24'd0};
+	parameter	[31:0]	PG5P2DelayRegCmd	=	{8'h49,24'd0};
+	parameter	[31:0]	PG5P3DelayRegCmd	=	{8'h4a,24'd0};
 	parameter	[31:0]	PG5P123DelayRegCmd	=	{8'h4b,24'd0};
-	parameter	[31:0]	PG5P1WidthRegCmd	=	{8'h4c,24'd5};
-	parameter	[31:0]	PG5P2WidthRegCmd	=	{8'h4d,24'd6};
-	parameter	[31:0]	PG5P3WidthRegCmd	=	{8'h4e,24'd7};
+	parameter	[31:0]	PG5P1WidthRegCmd	=	{8'h4c,24'd0};
+	parameter	[31:0]	PG5P2WidthRegCmd	=	{8'h4d,24'd0};
+	parameter	[31:0]	PG5P3WidthRegCmd	=	{8'h4e,24'd0};
 	parameter	[31:0]	PG5P123WidthRegCmd	=	{8'h4f,24'd0};
 	
 	//PG6 Cmd
-	parameter	[31:0]	PG6P1DelayRegCmd	=	{8'h50,24'd5};
-	parameter	[31:0]	PG6P2DelayRegCmd	=	{8'h51,24'd15};
-	parameter	[31:0]	PG6P3DelayRegCmd	=	{8'h52,24'd30};
+	parameter	[31:0]	PG6P1DelayRegCmd	=	{8'h50,24'd0};
+	parameter	[31:0]	PG6P2DelayRegCmd	=	{8'h51,24'd5};
+	parameter	[31:0]	PG6P3DelayRegCmd	=	{8'h52,24'd15};
 	parameter	[31:0]	PG6P123DelayRegCmd	=	{8'h53,24'd0};
-	parameter	[31:0]	PG6P1WidthRegCmd	=	{8'h54,24'd5};
-	parameter	[31:0]	PG6P2WidthRegCmd	=	{8'h55,24'd6};
-	parameter	[31:0]	PG6P3WidthRegCmd	=	{8'h56,24'd7};
+	parameter	[31:0]	PG6P1WidthRegCmd	=	{8'h54,24'd1};
+	parameter	[31:0]	PG6P2WidthRegCmd	=	{8'h55,24'd3};
+	parameter	[31:0]	PG6P3WidthRegCmd	=	{8'h56,24'd5};
 	parameter	[31:0]	PG6P123WidthRegCmd	=	{8'h57,24'd0};
 	
-	parameter	[31:0]	MeasNum0RegCmd		=	{8'h58,24'd30};
-	parameter	[31:0]	MeasNum1RegCmd		=	{8'h59,24'd0};
+	parameter	[31:0]	MeasNum0RegCmd		=	{8'h58,24'd10};
+	parameter	[31:0]	MeasNum1RegCmd		=	{8'h59,MUXSLOWMODCMD,MUXFASTMODCMD,DSPTRIGINCMD,25'd0};
 	parameter	[31:0]	PGMode0RegCmd		=	{8'h0b,3'b0,PG7MODE,PG6MODE,PG5MODE,PG4MODE,PG3MODE,PG2MODE,PG1MODE};
-	parameter	[31:0]	PGMode1RegCmd		=	{8'h1b,7'b0000000,PG7POL,PG6POL,PG5POL,PG4POL,PG3POL,PG2POL,PG1POL,10'b0};
+	parameter	[31:0]	PGMode1RegCmd		=	{8'h1b,7'b0000000,PG7POL,PG6POL,PG5POL,PG4POL,PG3POL,PG2POL,PG1POL,10'h0};
 	
-	parameter	[31:0]	MuxCtrl1RegCmd	=	{8'h1c,PG6MUXCMD,PG5MUXCMD,PG4MUXCMD,PG3MUXCMD,PG2MUXCMD,PG1MUXCMD};
-	parameter	[31:0]	MuxCtrl2RegCmd	=	{8'h1d,4'b0,SMPLSTRBMUXCMD,GATINGMUXCMD,MODMUXCMD,EXTTRIGMUXCMD,PG7MUXCMD};
-	parameter	[31:0]	MuxCtrl3RegCmd	=	{8'h1e,EP6MUXCMD,EP5MUXCMD,EP4MUXCMD,EP3MUXCMD,EP2MUXCMD,EP1MUXCMD};
+	parameter	[31:0]	MuxCtrl1RegCmd	=	{8'h1c,4'h0,PG7MUXCMD,PG6MUXCMD,PG5MUXCMD,PG4MUXCMD};
+	parameter	[31:0]	MuxCtrl2RegCmd	=	{8'h1d,4'h0,PG3MUXCMD,PG2MUXCMD,PG1MUXCMD,SMPLSTRBMUXCMD};
+	parameter	[31:0]	MuxCtrl3RegCmd	=	{8'h1e,4'h0,GATINGMUXCMD,EXTTRIGMUXCMD,EP2MUXCMD,EP1MUXCMD};
+	parameter	[31:0]	MuxCtrl4RegCmd	=	{8'h1f,4'h0,EP6MUXCMD,EP5MUXCMD,EP4MUXCMD,EP3MUXCMD};
 	
+	
+	parameter	[31:0]	DirectAdc1Access	=	{8'h13,24'hA};
+	parameter	[31:0]	DirectAdc2Access	=	{8'h14,24'hA};
+	
+	parameter	[31:0]	PortSelRegCmd	=	{8'h19,8'h0,4'h3,4'h3,4'h3,4'h3};
+	parameter	[31:0]	MuxCtrl6RegCmd	=	{8'h1a,4'h0,5'd17,5'd17,5'd17,5'd17};
+	parameter	[31:0]	MuxCtrl7RegCmd	=	{8'h5a,4'h0,5'd17,5'd17,5'd17,5'd17};
 	//=================================================================================================================================================================================================================
 	
+	wire spiRst = 1'b1;
+	// wire spiRst = 1'b0;
+	
 	reg		Clk41;
 	reg		Clk50;
 	reg		Clk70;
 	
 	reg	[31:0]	tb_cnt=4'd0;
 	reg	rst;
-	reg	mosi_i	=	1'b0;
+	
+	reg mosi0;
+	reg mosi1;
+	
+	wire miso0_mosi2;
+	wire miso1_mosi3;
+	
+	reg mosi2;
+	reg mosi3;
+	
+	assign miso0_mosi2 = (spiRst)? 1'bz:mosi2;
+	assign miso1_mosi3 = (spiRst)? 1'bz:mosi3;
+	
 	reg	Miso_i	=	1'b0;
-	reg	ss_i;
+	reg	ss;
 	reg	clk_i	=	1'b0;
 	
-	
 	reg	[31:0]	DspSpiData;
 	reg		startCalcCmdReg;
+	wire	startCalcSlaveFpga;
+	wire	startMeasS;
+	wire	dspReadySlaveFpga;
 						
 	wire	[17:0]	cos_value;	
 	wire	[17:0]	sin_value;				
@@ -193,6 +227,8 @@ module S5443TopPulseProfileTb;
 	assign	trig0R	=	trig0;
     assign	trig1R	=	trig1;
 	
+	
+	
 //==========================================================================================
 //clocks gen
 	always	#10 Clk50	=	~Clk50;
@@ -201,6 +237,7 @@ module S5443TopPulseProfileTb;
 	always	#(24.390243902439/2)	Clk41	=	~Clk41;
 	
 	wire	sck_i;	
+	
 //==========================================================================================
 initial begin
 	Clk50	=	1'b1;
@@ -224,12 +261,9 @@ wire	endMeasNeg	=	!endMeas&endMeasReg;
 
 always	@(posedge	Clk70)	begin
 	if	(!rst)	begin
-		if	(!endMeas)	begin
-			if	(tb_cnt	==	3501)	begin
-				startCalcCmdReg	<=	1'b1;
-			end	
-		end	else	begin
-			startCalcCmdReg	<=	1'b0;
+			// if	(tb_cnt	==	3550	|	tb_cnt	==	3950	|tb_cnt	==	4505)	begin
+		if	(tb_cnt	==	3550)	begin
+			startCalcCmdReg	<=	1'b1;
 		end
 	end	else	begin
 		startCalcCmdReg	<=	1'b0;
@@ -247,8 +281,8 @@ end
 wire	Adc1DataDa0P;
 wire	Adc1DataDa1P;
 
-// wire	[31:0]	test	=	32'h2351eb85;
-wire	[31:0]	test	=	32'h3851eb85;
+wire	[31:0]	test	=	32'h2351eb85;
+// wire	[31:0]	test	=	32'h40000000;
 CordicNco		
 #(	.ODatWidth	(18),
 	.PhIncWidth	(32),
@@ -269,10 +303,12 @@ ncoInst
 );
 
 
-S5443Top 
-uut (
-	.Clk_i				(Clk50),
-	.Led_o				(),
+S5443Top  
+#(.IsSim (IsSim))
+MasterFpga
+(
+	.ClkP_i				(Clk50),
+	.ClkN_i				(~Clk50),
 //------------------------------------------	
     .Adc1FclkP_i		(),		
     .Adc1FclkN_i		(),		
@@ -305,125 +341,48 @@ uut (
 	.Adc1InitCs_o		(),
 	.Adc2InitCs_o		(),
 	.AdcInitRst_o		(),
+	
+	.DitherCtrlCh1_o	(),
+	.DitherCtrlCh2_o	(),
 //------------------------------------------	
 	
-	.Mosi_i				(mosi_i),
-	.Sck_i				(~sck_i),
-	.Ss_i				(ss_i),
+	.Mosi0_i			(mosi0),
+	.Mosi1_i			(mosi1),
+	.Miso0_Mosi2_io		(miso0_mosi2),
+	.Miso1_Mosi3_io		(miso1_mosi3),
+	.SpiRst_i			(spiRst),
+	.Sck_i				(~Clk41),
+	.Ss_i				(ss),
 
 	.LpOutClk_o			(),
 	.LpOutFs_o			(),			
 	.LpOutData_o		(),
 	
 	//fpga-dsp signals
-	.StartMeas_i		(startCalcCmdReg),
-	.StartMeas_o		(startMeasS),
-	.EndMeas_o			(endMeas),
-	.TimersClk_o		(),
-	
-	.Trig6to1_io		(),	
-	.Trig6to1Dir_o		(trigDir),	
-	
-	.DspTrigOut_i		(dspTrigOut),				//Trig from DSP
-	.DspTrigIn_o		(),				//Trig To DSP
-	
-	.OverloadS_i		(1'b0),
-	.Overload_o			(),
-	
-	.PortSel_o			(),
-	.PortSelDir_o		(),
-	
-	//mod out line
-	
-	.Mod_o				(),	
-	
-	//gain lines
-	.SensEnM_io			(sensEn),
-	.AmpEn_o			(),	//	0-adc1ChA 1-adc1ChB 2-adc2ChA 3-adc2ChB
-	.AdcData_i			(sin_value[17-:14])
-);
+	.StartMeasDsp_i		(startCalcCmdReg),
+	.StartMeasEvent_i	(startCalcCmdReg),
 
+	.Overload_o			(),
 
-//comment for stupid vivado
-S5443TopS SlaveFpga
-(
-	//common ports
-	.Clk_i					(Clk50),
-	
-	//fpga-adc1 data interface
-    .Adc1FclkP_i			(),
-    .Adc1FclkN_i			(),
-
-    .Adc1DataDa0P_i			(),
-	.Adc1DataDa0N_i			(),
-    .Adc1DataDa1P_i			(),
-    .Adc1DataDa1N_i			(),
-
-	.Adc1DataDb0P_i			(),
-    .Adc1DataDb0N_i			(),
-    .Adc1DataDb1P_i			(),
-    .Adc1DataDb1N_i			(),
-	
-	//fpga-adc2 data interface
-    .Adc2FclkP_i			(),
-    .Adc2FclkN_i			(),
-	
-    .Adc2DataDa0P_i			(),
-    .Adc2DataDa0N_i			(),
-    .Adc2DataDa1P_i			(),
-    .Adc2DataDa1N_i			(),
-	
-	.Adc2DataDb0P_i			(),
-    .Adc2DataDb0N_i			(),
-    .Adc2DataDb1P_i			(),
-    .Adc2DataDb1N_i			(),
-	
-	//fpga-adc's initialization interface
-	.AdcInitMosi_o			(),
-	.AdcInitClk_o			(),
-	.Adc1InitCs_o			(),
-	.Adc2InitCs_o			(),
-	.AdcInitRst_o			(),
-
-	//ditherCtrl
-	.DitherCtrlCh1_o		(),
-	.DitherCtrlCh2_o		(),
-	
-	//fpga-dsp cmd interface
-	.Mosi_i					(mosi_i),
-	.Sck_i					(~sck_i),
-	.Ss_i					(ss_i),
-	// .Miso_i,
-	.Miso_o					(),
-	
-	//fpga-dsp data interface
-	.LpOutClk_o				(),
-	.LpOutFs_o				(),
-	.LpOutData_o			(),
-	
-	//fpga-dsp signals
-	.StartMeasEvent_i		(startMeasS),		//"high"- start meas, "low"-stop meas
-	//overload lines
-	.Overload_o				(),
-	
-	//gain lines
-	.SensEnS_io				(sensEn),	
+	.DspReadyForRx_i		(1'b0),
 	.AmpEn_o				(),	//	0-adc1ChA 1-adc1ChB 2-adc2ChA 3-adc2ChB
-	
-	///test port for testbench
 	.AdcData_i				(sin_value[17-:14])
+	// .AdcData_i			(Data_i)
 );
 
-parameter	IDLE	=	2'h0;
-parameter	CMD		=	2'h1;
-parameter	TX		=	2'h2;
-parameter	PAUSE	=	2'h3;
 
-reg	[1:0]	txCurrState;
-reg	[1:0]	txNextState;
+parameter	IDLE	=	3'h0;
+parameter	CMD		=	3'h1;
+parameter	STX		=	3'h2;
+parameter	QTX		=	3'h3;
+parameter	PAUSE	=	3'h4;
+
+reg	[2:0]	txCurrState;
+reg	[2:0]	txNextState;
 
 wire	txWork	=	tb_cnt	>=	23;
-wire	txStop	=	cmdCnt	>=	70;
+// wire	txStop	=	(cmdCnt	>=	90)	&	(cmdCnt	>=	70)	&	(cmdCnt	>=	71);
+wire	txStop	=	(cmdCnt	>=	150);
 
 
 reg	[6:0]	txCnt;
@@ -443,7 +402,7 @@ end
 
 always	@(posedge	Clk41)	begin
 	if	(!rst)	begin
-		if	(txCurrState	==	TX)	begin
+		if	(txCurrState	==	STX || txCurrState	==	QTX)	begin
 			txCnt	<=	txCnt+1;
 		end	else	begin
 			txCnt	<=	0;
@@ -589,7 +548,7 @@ always	@(posedge	Clk41)	begin
 		end	else	if	(cmdCnt	==	59)	begin
 			DspSpiData		<=	PG7P3WidthRegCmd;
 		end	else	if	(cmdCnt	==	60)	begin
-			DspSpiData		<=	PG7P123WidthRegCmd;
+			DspSpiData		<=	PortSelRegCmd;
 		end	else	if	(cmdCnt	==	61)	begin
 			DspSpiData		<=	MeasNum0RegCmd;
 		end else	if	(cmdCnt	==	62)	begin
@@ -606,34 +565,53 @@ always	@(posedge	Clk41)	begin
 			DspSpiData		<=	MuxCtrl3RegCmd;
 		end	else	if	(cmdCnt	==	68)	begin
 			DspSpiData		<=	AdcCtrl;
-		end	
-	end	else	if	(txCurrState	==	TX)	begin
+		end	else	if	(cmdCnt	==	99)	begin
+			DspSpiData		<=	MuxCtrl6RegCmd;
+		end	else	if	(cmdCnt	==	100)	begin
+			DspSpiData		<=	MuxCtrl7RegCmd;
+		end else	begin
+			DspSpiData	<=	32'hfffffff;
+		end
+	end	else	if	(txCurrState	==	STX||txCurrState	==	QTX)	begin
 		DspSpiData	<=	DspSpiData<<1;
 	end
 end
 
 always	@(posedge Clk41)	begin
-	if	(txCurrState	==	TX)	begin
+	if	(txCurrState	==	STX)	begin
 		if	(txCnt	>=	7'd0)	begin
-			mosi_i	<=	DspSpiData[31];
+			mosi0	<=	DspSpiData[31];
 		end	else	begin
-			mosi_i	<=	1'b1;
+			mosi0	<=	1'b1;
 		end
-	end	else	begin
-		mosi_i	<=	1'b1;
+	end else if (txCurrState == QTX) begin
+		if	(txCnt	>=	7'd0)	begin
+			mosi0	<=	DspSpiData[7];
+			mosi1	<=	DspSpiData[15];
+			mosi2	<=	DspSpiData[23];
+			mosi3	<=	DspSpiData[31];
+		end	else	begin
+			mosi0	<=	1'b1;
+			mosi1	<=	1'b1;
+			mosi2	<=	1'b1;
+			mosi3	<=	1'b1;
+		end
+	end else begin
+		mosi0	<=	1'b1;
+		mosi1	<=	1'b1;
+		mosi2	<=	1'b1;
+		mosi3	<=	1'b1;
 	end
 end
 
 always	@(posedge	Clk41)	begin
-	if	(txCurrState	==	TX)	begin
-		ss_i	<=	1'b0;
+	if	(txCurrState	==	STX || txCurrState	==	QTX)	begin
+		ss	<=	1'b0;
 	end	else	begin
-		ss_i	<=	1'b1;
+		ss	<=	1'b1;
 	end
 end
 
-assign	sck_i	=	Clk41;
-
 always	@(posedge	Clk41)	begin
 	if	(rst)	begin
 		txCurrState	<=	IDLE;
@@ -649,24 +627,36 @@ always @(*) begin
 	IDLE	:	begin
 					if (txWork)	begin
 						txNextState = CMD;
-					end	else begin
+					end else begin
 						txNextState = IDLE;
 					end
 				end
 				
 	CMD	:		begin
 					if (!txStop)	begin
-						txNextState = TX;
-					end	else begin
+						if (spiRst) begin
+							txNextState = STX;
+						end	else begin
+							txNextState = QTX;
+						end
+					end else begin
 						txNextState = IDLE;
 					end
 				end
 
-	TX		:	begin
+	STX		:	begin
 					if (txCnt==6'd31) begin
 						txNextState  = PAUSE;
 					end	else begin
-						txNextState  = TX;
+						txNextState  = STX;
+					end
+				end
+	
+	QTX		:	begin
+					if (txCnt==6'd7) begin
+						txNextState  = PAUSE;
+					end	else begin
+						txNextState  = QTX;
 					end
 				end
         
@@ -680,28 +670,24 @@ always @(*) begin
 	endcase
 end
 
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
+	reg [13:0] Data_i;
+	real pi = 3.14159265358;
+	real phase = 0;
+	real phaseInc = 0.001;
+	real signal;
+	always @ (posedge Clk50)
+		begin
+			if (tb_cnt >= 4505)
+				begin
+					phase = phase + phaseInc;
+					phaseInc <= phaseInc + 0.0005;
+					signal = $sin(2*pi*phase);
+					Data_i = 2**12 * signal;
+				end
+			else
+				Data_i = 0;
+		end
+		
 endmodule
 
 

S5444_S/src/src/Top/S5443Top.v

@@ -49,7 +49,8 @@ module	S5443Top
 	parameter	Divparam			=	4,
 	parameter	MeasPeriod			=	44,
 	parameter	PhIncWidth			=	32,
-	parameter	NcoWidth			=	18
+	parameter	NcoWidth			=	18,
+	parameter	IsSim				=	1'b0
 )
 (
 	//common ports
@@ -131,6 +132,8 @@ module	S5443Top
 	wire	[AdcDataWidth-1:0]	adc2ChR2Data;
 	wire	[AdcDataWidth-1:0]	adc2ChT2Data;
 	
+	wire	testAdc;
+	
 	reg		startMeasSync;
 	wire	intTrig1;
 	
@@ -241,7 +244,7 @@ module	S5443Top
 	wire	[AdcDataWidth-1:0]	adcDataBus	[ChNum-1:0];
 	wire	overCtrlR	=	|overCtrlChannels[ChNum-1:0];
 	
-	localparam TESTCNTPARAM	=	32'd100000000;
+	localparam TESTCNTPARAM	=	32'd100;
 	reg	[31:0]	testCnt;
 
 	wire	refClk;
@@ -509,13 +512,19 @@ module	S5443Top
 	assign	gainHighThresholdBus	[ChNum-2]	=	gainHighThreshR2;
 	assign	gainHighThresholdBus	[ChNum-1]	=	gainHighThreshT2;
 	
-	assign	AmpEn_o	[3]	=	~ampEnNewStates[3];	
+	
+	// assign	testAdc = (adc1ChT1Data == 14'h3fff);
+	assign	testAdc = (adc1ChR1Data == 14'h3fff);
+	// assign	testAdc = (adc2ChR2Data == 14'h3fff);
+	// assign	testAdc = (adc2ChT2Data == 14'h3fff);
+	
+	assign	AmpEn_o	[3]	=	~ampEnNewStates[3];		
 	assign	AmpEn_o	[2]	=	~ampEnNewStates[2];	
 	assign	AmpEn_o	[1]	=	~ampEnNewStates[0];	
 	assign	AmpEn_o	[0]	=	~ampEnNewStates[1];	
 	
-	assign	Overload_o	=	overCtrlR;
-	// assign	Overload_o	=	intTrig2;
+	// assign	Overload_o	=	overCtrlR;
+	assign	Overload_o	=	testAdc;
 //================================================================================
 //  CODING
 //================================================================================
@@ -574,9 +583,7 @@ AdcDataInterface
 	.Rst_i			(initRst),
 	
 	.Adc1FclkP_i	(Adc1FclkP_i),		
-	.Adc1FclkN_i	(Adc1FclkN_i),
-	
-	.testAdc		(AdcData_i),		
+	.Adc1FclkN_i	(Adc1FclkN_i),	
 	
 	.Adc1DataDa0P_i	(Adc1DataDa0P_i),
 	.Adc1DataDa0N_i	(Adc1DataDa0N_i),
@@ -646,10 +653,10 @@ ExternalDspInterface
 	
 	.OscDataRdFlag_o	(oscDataRdFlag),
 	
-	.Adc1ChT1Data_i		(adc1ChT1Data),	
-	.Adc1ChR1Data_i		(adc1ChR1Data),	
-	.Adc2ChR2Data_i		(adc2ChR2Data),	
-	.Adc2ChT2Data_i		(adc2ChT2Data),		
+	.Adc1ChT1Data_i		(adcDataBus[ChNum-4]),	
+	.Adc1ChR1Data_i		(adcDataBus[ChNum-3]),	
+	.Adc2ChR2Data_i		(adcDataBus[ChNum-2]),	
+	.Adc2ChT2Data_i		(adcDataBus[ChNum-1]),		
 	
 	.Mosi_o				(adcInitMosi),
 	.Sck_o				(adcInitSck),
@@ -750,11 +757,11 @@ InternalDsp
 	.NcoRst_i				(ncoRst),
 	.OscWind_o				(oscWind),
 
-	.Adc1ChT1Data_i			(adc1ChT1Data),	//T1
-	.Adc1ChR1Data_i			(adc1ChR1Data),	//R1
-	.Adc2ChR2Data_i			(adc2ChR2Data),	//R2
-	.Adc2ChT2Data_i			(adc2ChT2Data),	//T2
-
+	.Adc1ChT1Data_i			(adcDataBus[ChNum-4]),	//T1
+	.Adc1ChR1Data_i			(adcDataBus[ChNum-3]),	//R1
+	.Adc2ChR2Data_i			(adcDataBus[ChNum-2]),	//R2
+	.Adc2ChT2Data_i			(adcDataBus[ChNum-1]),	//T2
+	
 	// .Adc1ChT1Data_i			(AdcData_i),	//T1
 	// .Adc1ChR1Data_i			(AdcData_i),	//R1
 	// .Adc2ChR2Data_i			(AdcData_i),	//R2
@@ -1009,6 +1016,8 @@ StartAfterGainSel
 StartAfterGainSelInst
 (
 	.Rst_i			(initRst),
+	.Clk_i			(gclk),
+	
 	.GainCtrl_i		(gainAutoEn),
 	.MeasStart_i	(measStartBus),
 	
@@ -1081,7 +1090,6 @@ PulseGen
 PulseGenerator
 (
 	.Rst_i			(initRst|pGenRst[j]|pGenMeasRst[j]),
-	// .Rst_i			(initRst|pGenMeasRst[j]),
 	.Clk_i			(gclk),
 	.EnPulse_i		(pgMuxedOut[j]),