Обновлены назначения пинов. Добавлены мультиплексоры для управления быстрыми и медленными модуляторами.

S5444_M/src/constrs/S5443Top.xdc

@@ -1,11 +1,11 @@
-set_property PACKAGE_PIN C1 [get_ports Adc1DataDa0P_i]
-set_property PACKAGE_PIN D2 [get_ports Adc1DataDa1P_i]
-set_property PACKAGE_PIN E2 [get_ports Adc1DataDb0P_i]
-set_property PACKAGE_PIN F2 [get_ports Adc1DataDb1P_i]
-set_property PACKAGE_PIN B9 [get_ports Adc2DataDa0P_i]
-set_property PACKAGE_PIN A8 [get_ports Adc2DataDa1P_i]
-set_property PACKAGE_PIN B6 [get_ports Adc2DataDb0P_i]
-set_property PACKAGE_PIN A5 [get_ports Adc2DataDb1P_i]
+set_property PACKAGE_PIN D2 [get_ports Adc1DataDa0P_i]
+set_property PACKAGE_PIN E2 [get_ports Adc1DataDa1P_i]
+set_property PACKAGE_PIN K1 [get_ports Adc1DataDb0P_i]
+set_property PACKAGE_PIN M1 [get_ports Adc1DataDb1P_i]
+set_property PACKAGE_PIN F15 [get_ports Adc2DataDa0P_i]
+set_property PACKAGE_PIN D15 [get_ports Adc2DataDa1P_i]
+set_property PACKAGE_PIN A13 [get_ports Adc2DataDb0P_i]
+set_property PACKAGE_PIN A11 [get_ports Adc2DataDb1P_i]
 
 
 #==========================================================================
@@ -14,8 +14,9 @@ set_property PACKAGE_PIN A5 [get_ports Adc2DataDb1P_i]
 
 #==========================================================================
 #	INPUT CLOCKS
-set_property PACKAGE_PIN C15 [get_ports Clk_i]
-set_property IOSTANDARD LVCMOS25 [get_ports Clk_i]
+set_property PACKAGE_PIN H3 [get_ports ClkP_i]
+set_property IOSTANDARD LVDS_25 [get_ports ClkP_i]
+set_property IOSTANDARD LVDS_25 [get_ports ClkN_i]
 create_clock -period 20.000 [get_ports Clk_i]
 
 #==========================================================================
@@ -40,7 +41,7 @@ set_property IOSTANDARD LVDS_25 [get_ports Adc1DataDb1N_i]
 #==========================================================================
 #	ADC2
 
-set_property PACKAGE_PIN A11 [get_ports Adc2FclkP_i]
+set_property PACKAGE_PIN B15 [get_ports Adc2FclkP_i]
 set_property IOSTANDARD LVDS_25 [get_ports Adc2FclkP_i]
 set_property IOSTANDARD LVDS_25 [get_ports Adc2FclkN_i]
 
@@ -59,177 +60,185 @@ set_property IOSTANDARD LVDS_25 [get_ports Adc2DataDb1N_i]
 #==========================================================================
 # DSP interface
 
-set_property PACKAGE_PIN H14 [get_ports Miso_o]
-set_property IOSTANDARD LVCMOS33 [get_ports Miso_o]
+set_property PACKAGE_PIN N6 [get_ports Mosi0_i]
+set_property IOSTANDARD LVCMOS33 [get_ports Mosi0_i]
+set_property PACKAGE_PIN N8 [get_ports Mosi1_i]
+set_property IOSTANDARD LVCMOS33 [get_ports Mosi1_i]
 
-set_property PACKAGE_PIN H15 [get_ports Mosi_i]
-set_property IOSTANDARD LVCMOS33 [get_ports Mosi_i]
+set_property PACKAGE_PIN R8 [get_ports Miso0_Mosi2_io]
+set_property IOSTANDARD LVCMOS33 [get_ports Miso0_Mosi2_io]
+set_property PACKAGE_PIN P6 [get_ports Miso1_Mosi3_io]
+set_property IOSTANDARD LVCMOS33 [get_ports Miso1_Mosi3_io]
 
-set_property PACKAGE_PIN J12 [get_ports Ss_i]
+set_property PACKAGE_PIN N7 [get_ports Ss_i]
 set_property IOSTANDARD LVCMOS33 [get_ports Ss_i]
 
-set_property PACKAGE_PIN M9 [get_ports Sck_i]
+set_property PACKAGE_PIN R7 [get_ports SpiRst_i]
+set_property IOSTANDARD LVCMOS33 [get_ports SpiRst_i]
+
+set_property PACKAGE_PIN R5 [get_ports Sck_i]
 set_property IOSTANDARD LVCMOS33 [get_ports Sck_i]
-#create_clock -period 24.000 [get_ports Sck_i]
 create_clock -period 16.000 [get_ports Sck_i]
 
-set_property PACKAGE_PIN N12 [get_ports LpOutClk_o]
+set_property PACKAGE_PIN R9 [get_ports LpOutClk_o]
 set_property IOSTANDARD LVCMOS33 [get_ports LpOutClk_o]
 
-set_property PACKAGE_PIN P12 [get_ports LpOutFs_o]
+set_property PACKAGE_PIN J15 [get_ports LpOutFs_o]
 set_property IOSTANDARD LVCMOS33 [get_ports LpOutFs_o]
 
-set_property PACKAGE_PIN L15 [get_ports {LpOutData_o[0]}]
+set_property PACKAGE_PIN P10 [get_ports {LpOutData_o[0]}]
 set_property IOSTANDARD LVCMOS33 [get_ports {LpOutData_o[0]}]
-set_property PACKAGE_PIN L14 [get_ports {LpOutData_o[1]}]
+set_property PACKAGE_PIN R10 [get_ports {LpOutData_o[1]}]
 set_property IOSTANDARD LVCMOS33 [get_ports {LpOutData_o[1]}]
-set_property PACKAGE_PIN M15 [get_ports {LpOutData_o[2]}]
+set_property PACKAGE_PIN P11 [get_ports {LpOutData_o[2]}]
 set_property IOSTANDARD LVCMOS33 [get_ports {LpOutData_o[2]}]
-set_property PACKAGE_PIN M13 [get_ports {LpOutData_o[3]}]
+set_property PACKAGE_PIN R11 [get_ports {LpOutData_o[3]}]
 set_property IOSTANDARD LVCMOS33 [get_ports {LpOutData_o[3]}]
-set_property PACKAGE_PIN N15 [get_ports {LpOutData_o[4]}]
+set_property PACKAGE_PIN P12 [get_ports {LpOutData_o[4]}]
 set_property IOSTANDARD LVCMOS33 [get_ports {LpOutData_o[4]}]
-set_property PACKAGE_PIN M14 [get_ports {LpOutData_o[5]}]
+set_property PACKAGE_PIN R12 [get_ports {LpOutData_o[5]}]
 set_property IOSTANDARD LVCMOS33 [get_ports {LpOutData_o[5]}]
-set_property PACKAGE_PIN P15 [get_ports {LpOutData_o[6]}]
+set_property PACKAGE_PIN R13 [get_ports {LpOutData_o[6]}]
 set_property IOSTANDARD LVCMOS33 [get_ports {LpOutData_o[6]}]
-set_property PACKAGE_PIN N14 [get_ports {LpOutData_o[7]}]
+set_property PACKAGE_PIN P14 [get_ports {LpOutData_o[7]}]
 set_property IOSTANDARD LVCMOS33 [get_ports {LpOutData_o[7]}]
-set_property PACKAGE_PIN P14 [get_ports {LpOutData_o[8]}]
+set_property PACKAGE_PIN R14 [get_ports {LpOutData_o[8]}]
 set_property IOSTANDARD LVCMOS33 [get_ports {LpOutData_o[8]}]
-set_property PACKAGE_PIN R14 [get_ports {LpOutData_o[9]}]
+set_property PACKAGE_PIN P15 [get_ports {LpOutData_o[9]}]
 set_property IOSTANDARD LVCMOS33 [get_ports {LpOutData_o[9]}]
-set_property PACKAGE_PIN N13 [get_ports {LpOutData_o[10]}]
+set_property PACKAGE_PIN N15 [get_ports {LpOutData_o[10]}]
 set_property IOSTANDARD LVCMOS33 [get_ports {LpOutData_o[10]}]
-set_property PACKAGE_PIN R13 [get_ports {LpOutData_o[11]}]
+set_property PACKAGE_PIN M15 [get_ports {LpOutData_o[11]}]
 set_property IOSTANDARD LVCMOS33 [get_ports {LpOutData_o[11]}]
-set_property PACKAGE_PIN R11 [get_ports {LpOutData_o[12]}]
+set_property PACKAGE_PIN L14 [get_ports {LpOutData_o[12]}]
 set_property IOSTANDARD LVCMOS33 [get_ports {LpOutData_o[12]}]
-set_property PACKAGE_PIN P11 [get_ports {LpOutData_o[13]}]
+set_property PACKAGE_PIN L15 [get_ports {LpOutData_o[13]}]
 set_property IOSTANDARD LVCMOS33 [get_ports {LpOutData_o[13]}]
-set_property PACKAGE_PIN R10 [get_ports {LpOutData_o[14]}]
+set_property PACKAGE_PIN K14 [get_ports {LpOutData_o[14]}]
 set_property IOSTANDARD LVCMOS33 [get_ports {LpOutData_o[14]}]
-set_property PACKAGE_PIN P10 [get_ports {LpOutData_o[15]}]
+set_property PACKAGE_PIN K15 [get_ports {LpOutData_o[15]}]
 set_property IOSTANDARD LVCMOS33 [get_ports {LpOutData_o[15]}]
 
 #==========================================================================
 #  ADC SPI
 
-set_property PACKAGE_PIN B15 [get_ports AdcInitMosi_o]
+set_property PACKAGE_PIN H12 [get_ports AdcInitMosi_o]
 set_property IOSTANDARD LVCMOS25 [get_ports AdcInitMosi_o]
-set_property PACKAGE_PIN A13 [get_ports AdcInitClk_o]
+
+set_property PACKAGE_PIN H11 [get_ports AdcInitClk_o]
 set_property IOSTANDARD LVCMOS25 [get_ports AdcInitClk_o]
-set_property PACKAGE_PIN B14 [get_ports Adc2InitCs_o]
-set_property IOSTANDARD LVCMOS25 [get_ports Adc2InitCs_o]
-set_property PACKAGE_PIN C14 [get_ports Adc1InitCs_o]
+
+set_property PACKAGE_PIN J2 [get_ports Adc1InitCs_o]
 set_property IOSTANDARD LVCMOS25 [get_ports Adc1InitCs_o]
-set_property PACKAGE_PIN A14 [get_ports AdcInitRst_o]
+set_property PACKAGE_PIN H2 [get_ports Adc2InitCs_o]
+set_property IOSTANDARD LVCMOS25 [get_ports Adc2InitCs_o]
+
+set_property PACKAGE_PIN C1 [get_ports AdcInitRst_o]
 set_property IOSTANDARD LVCMOS25 [get_ports AdcInitRst_o]
 
 #==========================================================================
 #  OTHER
 
-set_property PACKAGE_PIN R6 [get_ports Led_o]
+set_property PACKAGE_PIN J12 [get_ports Led_o]
 set_property IOSTANDARD LVCMOS33 [get_ports Led_o]
 
-set_property PACKAGE_PIN N11 [get_ports Overload_o]
+set_property PACKAGE_PIN M7 [get_ports Overload_o]
 set_property IOSTANDARD LVCMOS33 [get_ports Overload_o]
 
-set_property PACKAGE_PIN R8 [get_ports OverloadS_i]
+set_property PACKAGE_PIN M14 [get_ports OverloadS_i]
 set_property IOSTANDARD LVCMOS33 [get_ports OverloadS_i]
 
-set_property PACKAGE_PIN M10 [get_ports StartMeas_i]
+set_property PACKAGE_PIN R6 [get_ports StartMeas_i]
 set_property IOSTANDARD LVCMOS33 [get_ports StartMeas_i]
 
-set_property PACKAGE_PIN M8 [get_ports EndMeas_o]
+set_property PACKAGE_PIN N9 [get_ports EndMeas_o]
 set_property IOSTANDARD LVCMOS33 [get_ports EndMeas_o]
 
-set_property PACKAGE_PIN R9 [get_ports StartMeasEvent_o]
+set_property PACKAGE_PIN R3 [get_ports StartMeasEvent_o]
 set_property IOSTANDARD LVCMOS33 [get_ports StartMeasEvent_o]
 
-set_property PACKAGE_PIN L13 [get_ports TimersClk_o]
+set_property PACKAGE_PIN P7 [get_ports TimersClk_o]
 set_property IOSTANDARD LVCMOS33 [get_ports TimersClk_o]
 
-set_property PACKAGE_PIN A2 [get_ports {AmpEn_o[0]}]
+set_property PACKAGE_PIN B2 [get_ports {AmpEn_o[0]}]
 set_property IOSTANDARD LVCMOS25 [get_ports {AmpEn_o[0]}]
-set_property PACKAGE_PIN B2 [get_ports {AmpEn_o[1]}]
+set_property PACKAGE_PIN A3 [get_ports {AmpEn_o[1]}]
 set_property IOSTANDARD LVCMOS25 [get_ports {AmpEn_o[1]}]
-set_property PACKAGE_PIN A3 [get_ports {AmpEn_o[2]}]
+set_property PACKAGE_PIN F3 [get_ports {AmpEn_o[2]}]
 set_property IOSTANDARD LVCMOS25 [get_ports {AmpEn_o[2]}]
-set_property PACKAGE_PIN A4 [get_ports {AmpEn_o[3]}]
+set_property PACKAGE_PIN F14 [get_ports {AmpEn_o[3]}]
 set_property IOSTANDARD LVCMOS25 [get_ports {AmpEn_o[3]}]
 
-set_property PACKAGE_PIN J1 [get_ports {PortSel_o[0]}]
+set_property PACKAGE_PIN C6 [get_ports {PortSel_o[0]}]
 set_property IOSTANDARD LVCMOS25 [get_ports {PortSel_o[0]}]
-set_property PACKAGE_PIN J2 [get_ports {PortSel_o[1]}]
+set_property PACKAGE_PIN B3 [get_ports {PortSel_o[1]}]
 set_property IOSTANDARD LVCMOS25 [get_ports {PortSel_o[1]}]
-set_property PACKAGE_PIN R3 [get_ports {PortSel_o[2]}]
+set_property PACKAGE_PIN A8 [get_ports {PortSel_o[2]}]
 set_property IOSTANDARD LVCMOS25 [get_ports {PortSel_o[2]}]
-set_property PACKAGE_PIN P3 [get_ports {PortSel_o[3]}]
+set_property PACKAGE_PIN B13 [get_ports {PortSel_o[3]}]
 set_property IOSTANDARD LVCMOS25 [get_ports {PortSel_o[3]}]
-
-set_property PACKAGE_PIN F14 [get_ports {PortSelDir_o[0]}]
-set_property IOSTANDARD LVCMOS25 [get_ports {PortSelDir_o[0]}]
-set_property PACKAGE_PIN F15 [get_ports {PortSelDir_o[1]}]
-set_property IOSTANDARD LVCMOS25 [get_ports {PortSelDir_o[1]}]
-set_property PACKAGE_PIN R4 [get_ports {PortSelDir_o[2]}]
-set_property IOSTANDARD LVCMOS25 [get_ports {PortSelDir_o[2]}]
-set_property PACKAGE_PIN M4 [get_ports {PortSelDir_o[3]}]
-set_property IOSTANDARD LVCMOS25 [get_ports {PortSelDir_o[3]}]
-
-set_property PACKAGE_PIN R7 [get_ports DspReadyForRxToFpgaS_o]
+set_property PACKAGE_PIN A9 [get_ports {PortSel_o[4]}]
+set_property IOSTANDARD LVCMOS25 [get_ports {PortSel_o[4]}]
+set_property PACKAGE_PIN B14 [get_ports {PortSel_o[5]}]
+set_property IOSTANDARD LVCMOS25 [get_ports {PortSel_o[5]}]
+set_property PACKAGE_PIN B9 [get_ports {PortSel_o[6]}]
+set_property IOSTANDARD LVCMOS25 [get_ports {PortSel_o[6]}]
+set_property PACKAGE_PIN B10 [get_ports {PortSel_o[7]}]
+set_property IOSTANDARD LVCMOS25 [get_ports {PortSel_o[7]}]
+
+set_property PACKAGE_PIN C5 [get_ports DspReadyForRxToFpgaS_o]
 set_property IOSTANDARD LVCMOS33 [get_ports DspReadyForRxToFpgaS_o]
 
-set_property PACKAGE_PIN R5 [get_ports DspReadyForRx_i]
+set_property PACKAGE_PIN H14 [get_ports DspReadyForRx_i]
 set_property IOSTANDARD LVCMOS33 [get_ports DspReadyForRx_i]
 
 set_property PACKAGE_PIN P7 [get_ports StartMeasDsp_o]
 set_property IOSTANDARD LVCMOS33 [get_ports StartMeasDsp_o]
 
-set_property PACKAGE_PIN A6 [get_ports {Mod_o[0]}]
-set_property IOSTANDARD LVCMOS25 [get_ports {Mod_o[0]}]
-set_property PACKAGE_PIN B5 [get_ports {Mod_o[1]}]
-set_property IOSTANDARD LVCMOS25 [get_ports {Mod_o[1]}]
-set_property PACKAGE_PIN B6 [get_ports {Mod_o[2]}]
-set_property IOSTANDARD LVCMOS25 [get_ports {Mod_o[2]}]
-set_property PACKAGE_PIN A7 [get_ports {Mod_o[3]}]
-set_property IOSTANDARD LVCMOS25 [get_ports {Mod_o[3]}]
+set_property PACKAGE_PIN A6 [get_ports {FastMod_o[0]}]
+set_property IOSTANDARD LVCMOS25 [get_ports {FastMod_o[0]}]
+set_property PACKAGE_PIN B5 [get_ports {FastMod_o[1]}]
+set_property IOSTANDARD LVCMOS25 [get_ports {FastMod_o[1]}]
+set_property PACKAGE_PIN B6 [get_ports {FastMod_o[2]}]
+set_property IOSTANDARD LVCMOS25 [get_ports {FastMod_o[2]}]
+set_property PACKAGE_PIN A7 [get_ports {FastMod_o[3]}]
+set_property IOSTANDARD LVCMOS25 [get_ports {FastMod_o[3]}]
 
-set_property PACKAGE_PIN K15 [get_ports DspTrigOut_i]
+set_property PACKAGE_PIN N10 [get_ports DspTrigOut_i]
 set_property IOSTANDARD LVCMOS33 [get_ports DspTrigOut_i]
-set_property PACKAGE_PIN K14 [get_ports DspTrigIn_o]
+set_property PACKAGE_PIN M8 [get_ports DspTrigIn_o]
 set_property IOSTANDARD LVCMOS33 [get_ports DspTrigIn_o]
 
-set_property PACKAGE_PIN D15 [get_ports {Trig6to1_io[0]}]
+set_property PACKAGE_PIN P3 [get_ports {Trig6to1_io[0]}]
 set_property IOSTANDARD LVCMOS25 [get_ports {Trig6to1_io[0]}]
-set_property PACKAGE_PIN E15 [get_ports {Trig6to1_io[1]}]
+set_property PACKAGE_PIN N4 [get_ports {Trig6to1_io[1]}]
 set_property IOSTANDARD LVCMOS25 [get_ports {Trig6to1_io[1]}]
-set_property PACKAGE_PIN P2 [get_ports {Trig6to1_io[2]}]
+set_property PACKAGE_PIN P1 [get_ports {Trig6to1_io[2]}]
 set_property IOSTANDARD LVCMOS25 [get_ports {Trig6to1_io[2]}]
-set_property PACKAGE_PIN N4 [get_ports {Trig6to1_io[3]}]
+set_property PACKAGE_PIN N1 [get_ports {Trig6to1_io[3]}]
 set_property IOSTANDARD LVCMOS25 [get_ports {Trig6to1_io[3]}]
-set_property PACKAGE_PIN P1 [get_ports {Trig6to1_io[4]}]
+set_property PACKAGE_PIN B1 [get_ports {Trig6to1_io[4]}]
 set_property IOSTANDARD LVCMOS25 [get_ports {Trig6to1_io[4]}]
-set_property PACKAGE_PIN N2 [get_ports {Trig6to1_io[5]}]
+set_property PACKAGE_PIN M2 [get_ports {Trig6to1_io[5]}]
 set_property IOSTANDARD LVCMOS25 [get_ports {Trig6to1_io[5]}]
 
-set_property PACKAGE_PIN C13 [get_ports {Trig6to1Dir_o[0]}]
+set_property PACKAGE_PIN R2 [get_ports {Trig6to1Dir_o[0]}]
 set_property IOSTANDARD LVCMOS25 [get_ports {Trig6to1Dir_o[0]}]
-set_property PACKAGE_PIN B13 [get_ports {Trig6to1Dir_o[1]}]
+set_property PACKAGE_PIN R4 [get_ports {Trig6to1Dir_o[1]}]
 set_property IOSTANDARD LVCMOS25 [get_ports {Trig6to1Dir_o[1]}]
-set_property PACKAGE_PIN N3 [get_ports {Trig6to1Dir_o[2]}]
+set_property PACKAGE_PIN B4 [get_ports {Trig6to1Dir_o[2]}]
 set_property IOSTANDARD LVCMOS25 [get_ports {Trig6to1Dir_o[2]}]
-set_property PACKAGE_PIN R2 [get_ports {Trig6to1Dir_o[3]}]
+set_property PACKAGE_PIN A5 [get_ports {Trig6to1Dir_o[3]}]
 set_property IOSTANDARD LVCMOS25 [get_ports {Trig6to1Dir_o[3]}]
-set_property PACKAGE_PIN N1 [get_ports {Trig6to1Dir_o[4]}]
+set_property PACKAGE_PIN A2 [get_ports {Trig6to1Dir_o[4]}]
 set_property IOSTANDARD LVCMOS25 [get_ports {Trig6to1Dir_o[4]}]
-set_property PACKAGE_PIN M3 [get_ports {Trig6to1Dir_o[5]}]
+set_property PACKAGE_PIN A4 [get_ports {Trig6to1Dir_o[5]}]
 set_property IOSTANDARD LVCMOS25 [get_ports {Trig6to1Dir_o[5]}]
 
-set_property PACKAGE_PIN M1 [get_ports DitherCtrlCh1_o]
+set_property PACKAGE_PIN C10 [get_ports DitherCtrlCh1_o]
 set_property IOSTANDARD LVCMOS25 [get_ports DitherCtrlCh1_o]
 
-set_property PACKAGE_PIN M2 [get_ports DitherCtrlCh2_o]
+set_property PACKAGE_PIN G14 [get_ports DitherCtrlCh2_o]
 set_property IOSTANDARD LVCMOS25 [get_ports DitherCtrlCh2_o]
 
 set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets Ss_i_IBUF]

S5444_M/src/src/RegMap/RegMap.v

@@ -560,7 +560,7 @@ module	RegMap
 					FilterCorrCoefHAddr:	begin
 												filterCorrCoefRegH	<=	Data_i	[CmdDataRegWith-1:0];
 											end
-					ActivePortSelAddr:			begin
+					ActivePortSelAddr:		begin
 												activePortSelReg	<=	Data_i	[CmdDataRegWith-1:0];
 											end
 					PG1P1DelayRegAddr:		begin

S5444_M/src/src/Top/S5443Top.v

@@ -55,7 +55,8 @@ module	S5443Top
 )
 (
 	//common ports
-	input	Clk_i,
+	input	ClkP_i,
+	input	ClkN_i,
 	output	Led_o,
 	
 	//fpga-adc1 data interface
@@ -99,11 +100,14 @@ module	S5443Top
 	output	DitherCtrlCh2_o,
 	
 	//fpga-dsp cmd interface
-	input	Mosi_i,
+	
+	input	Mosi0_i,
+	input	Mosi1_i,
+	inout	Miso0_Mosi2_io,
+	inout	Miso1_Mosi3_io,
+	input	SpiRst_i,
 	input	Sck_i,
 	input	Ss_i,
-	input	Miso_i,
-	output	Miso_o,
 	
 	//fpga-dsp data interface
 	output	LpOutClk_o,
@@ -130,11 +134,11 @@ module	S5443Top
 	
 	//modulation & active port selection
 	
-	output	[3:0]	PortSel_o,		//управление модулятором через ключ 
-	output	[3:0]	PortSelDir_o,	//управление направлением двунаправленного буффера
+	output	[ChNum*2-1:0]	PortSel_o,		//управление модулятором через ключ 
+	// output	[3:0]	PortSelDir_o,	//управление направлением двунаправленного буффера
 	
 	//mod out line
-	output	[ChNum-1:0]	Mod_o,
+	output	[ChNum-1:0]	FastMod_o,
 	
 	//gain lines
 	input	DspReadyForRx_i,
@@ -565,10 +569,14 @@ module	S5443Top
 	
 	assign	Overload_o	=	overCtrlR||OverloadS_i;
 
-	assign	Mod_o	[ChNum-1:0] =	fastModOut;
+	assign	FastMod_o =	fastModOut;
+	
+	assign	PortSel_o	[7:6] 	=	slowModOut[ChNum-1]	? activePortSel[13:12]:2'b0;
+	assign	PortSel_o	[5:4] 	=	slowModOut[ChNum-2]	? activePortSel[9:8]:2'b0;
+	assign	PortSel_o	[3:2] 	=	slowModOut[ChNum-3]	? activePortSel[5:4]:2'b0;
+	assign	PortSel_o	[1:0] 	=	slowModOut[ChNum-4]	? activePortSel[1:0]:2'b0;
 	
-	assign	PortSel_o	[ChNum-1:0] 	=	~modKeyCtrl;
-	assign	PortSelDir_o	=	4'd15;
+	// assign	PortSelDir_o	=	4'd15;
 	
 	assign	Trig6to1Dir_o	[0]	=	!measCtrl[16];
 	assign	Trig6to1Dir_o	[1]	=	!measCtrl[17];
@@ -619,12 +627,25 @@ end
 //	Data Receiving Interface
 //--------------------------------------------------------------------------------
 
-IBUF iob_50m_in
+// IBUF iob_50m_in
+// (
+	// .I    			(Clk_i),
+	// .O         		(gclk)
+// );
+	
+IBUFDS 
+#(
+	.DIFF_TERM("TRUE"),       
+	.IBUF_LOW_PWR("FALSE"),     
+	.IOSTANDARD("DEFAULT")    
+) 
+ClkBuf 
 (
-	.I    			(Clk_i),
-	.O         		(gclk)
+	.O	(gclk),  
+	.I	(ClkP_i),  
+	.IB	(ClkN_i) 
 );
-	
+   
 Clk200Gen	ClocksGenerator 
 (
     .Clk_i			(gclk),
@@ -1352,29 +1373,29 @@ FastModMux
 genvar m;
 generate
 	for	(m=0;	m<ChNum;	m=m+1)	begin	:ModulationMuxes
-		// Mux	
-		// #(	
-			// .CmdRegWidth	(CmdRegWidth),
-			// .PGenNum		(PGenNum),
-			// .TrigPortsNum	(TrigPortsNum)
-		// )
-		// SlowModMuxOut
-		// (
-			// .Rst_i			(initRst),
-
-			// .MuxCtrl_i		(slowModCtrl[m]),
-
-			// .DspTrigOut_i	(1'b0),
-			// .DspStartCmd_i	(1'b0),
-			// .IntTrig_i		(1'b0),
-			// .IntTrig2_i		(1'b0),
-			// .PulseBus_i		(7'h0),
-			// .ExtPortsBus_i	(6'h0),
-			// .SlowMod_i		(slowMod),
-			// .FastMod_i		(1'b0),
+		Mux	
+		#(	
+			.CmdRegWidth	(CmdRegWidth),
+			.PGenNum		(PGenNum),
+			.TrigPortsNum	(TrigPortsNum)
+		)
+		SlowModSourceMux
+		(
+			.Rst_i			(initRst),
+
+			.MuxCtrl_i		(slowModCtrl[m]),
+
+			.DspTrigOut_i	(1'b0),
+			.DspStartCmd_i	(1'b0),
+			.IntTrig_i		(1'b0),
+			.IntTrig2_i		(1'b0),
+			.PulseBus_i		(7'h0),
+			.ExtPortsBus_i	(6'h0),
+			.SlowMod_i		(slowMod),
+			.FastMod_i		(1'b0),
 			
-			// .MuxOut_o		(slowModOut[m])
-		// );
+			.MuxOut_o		(slowModOut[m])
+		);
 
 		Mux	
 		#(	
@@ -1474,18 +1495,18 @@ SampleStrobeGenRstDemux
 	.RstDemuxOut_o	(pGenMeasRst)
 );	
 
-//--------------------------------------------------------------------------------
-//	Active Port Selection
-//--------------------------------------------------------------------------------	
-ActivePortSelector	ActivePortSel
-(
-	.Rst_i		(initRst),
+// --------------------------------------------------------------------------------
+	// Active Port Selection
+// --------------------------------------------------------------------------------	
+// ActivePortSelector	ActivePortSel
+// (
+	// .Rst_i		(initRst),
 	
-	.Mod_i		(slowMod),
-	.Ctrl_i		(measCtrl[7:4]),
+	// .Mod_i		(slowMod),
+	// .Ctrl_i		(measCtrl[7:4]),
 	
-	.Ctrl_o		(modKeyCtrl)
-);
+	// .Ctrl_o		(modKeyCtrl)
+// );
 
 //--------------------------------------------------------------------------------
 //	Debug led