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@@ -250,3 +250,50 @@ connect_debug_port dbg_hub/clk [get_nets gclk_BUFG]
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+
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+create_debug_core u_ila_0 ila
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+set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0]
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+set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_0]
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+set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0]
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+set_property C_DATA_DEPTH 1024 [get_debug_cores u_ila_0]
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+set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_0]
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+set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0]
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+set_property C_TRIGIN_EN false [get_debug_cores u_ila_0]
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+set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0]
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+set_property port_width 1 [get_debug_ports u_ila_0/clk]
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+connect_debug_port u_ila_0/clk [get_nets [list gclk_BUFG]]
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+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0]
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+set_property port_width 18 [get_debug_ports u_ila_0/probe0]
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+connect_debug_port u_ila_0/probe0 [get_nets [list {InternalDsp/wind[0]} {InternalDsp/wind[1]} {InternalDsp/wind[2]} {InternalDsp/wind[3]} {InternalDsp/wind[4]} {InternalDsp/wind[5]} {InternalDsp/wind[6]} {InternalDsp/wind[7]} {InternalDsp/wind[8]} {InternalDsp/wind[9]} {InternalDsp/wind[10]} {InternalDsp/wind[11]} {InternalDsp/wind[12]} {InternalDsp/wind[13]} {InternalDsp/wind[14]} {InternalDsp/wind[15]} {InternalDsp/wind[16]} {InternalDsp/wind[17]}]]
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+create_debug_port u_ila_0 probe
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+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1]
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+set_property port_width 7 [get_debug_ports u_ila_0/probe1]
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+connect_debug_port u_ila_0/probe1 [get_nets [list {pulseBus[0]} {pulseBus[1]} {pulseBus[2]} {pulseBus[3]} {pulseBus[4]} {pulseBus[5]} {pulseBus[6]}]]
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+create_debug_port u_ila_0 probe
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+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2]
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+set_property port_width 1 [get_debug_ports u_ila_0/probe2]
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+connect_debug_port u_ila_0/probe2 [get_nets [list InternalDsp/EndMeas_o]]
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+create_debug_port u_ila_0 probe
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+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3]
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+set_property port_width 1 [get_debug_ports u_ila_0/probe3]
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+connect_debug_port u_ila_0/probe3 [get_nets [list measStart]]
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+create_debug_port u_ila_0 probe
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+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4]
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+set_property port_width 1 [get_debug_ports u_ila_0/probe4]
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+connect_debug_port u_ila_0/probe4 [get_nets [list InternalDsp/MeasWind_o]]
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+create_debug_port u_ila_0 probe
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+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5]
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+set_property port_width 1 [get_debug_ports u_ila_0/probe5]
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+connect_debug_port u_ila_0/probe5 [get_nets [list startMeasSyncRR]]
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+create_debug_port u_ila_0 probe
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+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe6]
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+set_property port_width 1 [get_debug_ports u_ila_0/probe6]
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+connect_debug_port u_ila_0/probe6 [get_nets [list StartMeas_i_IBUF]]
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+create_debug_port u_ila_0 probe
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+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe7]
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+set_property port_width 1 [get_debug_ports u_ila_0/probe7]
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+connect_debug_port u_ila_0/probe7 [get_nets [list EndMeas_o_OBUF]]
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+set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub]
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+set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub]
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+set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub]
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+connect_debug_port dbg_hub/clk [get_nets gclk_BUFG]
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