Добавил констрейны. Добавил логику обработки CsFlash в InterfaceArbiter.

src/constr/BochV3.cst

@@ -0,0 +1,66 @@
+//Copyright (C)2014-2024 Gowin Semiconductor Corporation.
+//All rights reserved. 
+//File Title: Physical Constraints file
+//Tool Version: V1.9.9.03 (64-bit)
+//Part Number: GW1N-UV9QN88C6/I5
+//Device: GW1N-9
+//Created Time: Tue 11 26 09:47:17 2024
+
+IO_LOC "TfeCs_o" 39;
+IO_PORT "TfeCs_o" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;
+IO_LOC "TfeMosi_o" 41;
+IO_PORT "TfeMosi_o" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;
+IO_LOC "TfeClk_o" 42;
+IO_PORT "TfeClk_o" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;
+IO_LOC "CtrlCp2444v1Rst_o" 34;
+IO_PORT "CtrlCp2444v1Rst_o" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;
+IO_LOC "CtrlCp2444v1Sck_o" 37;
+IO_PORT "CtrlCp2444v1Sck_o" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;
+IO_LOC "CtrlCp2444v1CsFlash_o" 35;
+IO_PORT "CtrlCp2444v1CsFlash_o" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;
+IO_LOC "CtrlCp2444v1Cs_o" 36;
+IO_PORT "CtrlCp2444v1Cs_o" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;
+IO_LOC "CtrlCp2444v1Mosi3_o" 29;
+IO_PORT "CtrlCp2444v1Mosi3_o" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;
+IO_LOC "CtrlCp2444v1Mosi2_o" 30;
+IO_PORT "CtrlCp2444v1Mosi2_o" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;
+IO_LOC "CtrlCp2444v1Mosi1_o" 31;
+IO_PORT "CtrlCp2444v1Mosi1_o" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;
+IO_LOC "CtrlCp2444v1Mosi0_o" 32;
+IO_PORT "CtrlCp2444v1Mosi0_o" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;
+IO_LOC "LmkBSck_o" 76;
+IO_PORT "LmkBSck_o" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;
+IO_LOC "LmkBCs_o" 75;
+IO_PORT "LmkBCs_o" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;
+IO_LOC "LmkBMosi_o" 77;
+IO_PORT "LmkBMosi_o" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;
+IO_LOC "LmkASck_o" 50;
+IO_PORT "LmkASck_o" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;
+IO_LOC "LmkACs_o" 49;
+IO_PORT "LmkACs_o" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;
+IO_LOC "LmkAMosi_o" 51;
+IO_PORT "LmkAMosi_o" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;
+IO_LOC "Mosi3_i" 83;
+IO_PORT "Mosi3_i" IO_TYPE=LVCMOS33 PULL_MODE=UP BANK_VCCIO=3.3;
+IO_LOC "Mosi2_i" 82;
+IO_PORT "Mosi2_i" IO_TYPE=LVCMOS33 PULL_MODE=UP BANK_VCCIO=3.3;
+IO_LOC "Mosi1_io" 81;
+IO_PORT "Mosi1_io" IO_TYPE=LVCMOS33 PULL_MODE=UP BANK_VCCIO=3.3;
+IO_LOC "Mosi0_i" 80;
+IO_PORT "Mosi0_i" IO_TYPE=LVCMOS33 PULL_MODE=UP BANK_VCCIO=3.3;
+IO_LOC "SsFlash_i" 15;
+IO_PORT "SsFlash_i" IO_TYPE=LVCMOS33 PULL_MODE=UP BANK_VCCIO=3.3;
+IO_LOC "Ss_i" 14;
+IO_PORT "Ss_i" IO_TYPE=LVCMOS33 PULL_MODE=UP BANK_VCCIO=3.3;
+IO_LOC "Sck_i" 13;
+IO_PORT "Sck_i" IO_TYPE=LVCMOS33 PULL_MODE=UP BANK_VCCIO=3.3;
+IO_LOC "Rst_i" 16;
+IO_PORT "Rst_i" IO_TYPE=LVCMOS33 PULL_MODE=UP BANK_VCCIO=3.3;
+IO_LOC "TfeMiso_i" 40;
+IO_PORT "TfeMiso_i" IO_TYPE=LVCMOS33 PULL_MODE=UP BANK_VCCIO=3.3;
+IO_LOC "CtrlCp2444v1Ld_i" 33;
+IO_PORT "CtrlCp2444v1Ld_i" IO_TYPE=LVCMOS33 PULL_MODE=UP BANK_VCCIO=3.3;
+IO_LOC "LmkBMiso_i" 74;
+IO_PORT "LmkBMiso_i" IO_TYPE=LVCMOS33 PULL_MODE=UP BANK_VCCIO=3.3;
+IO_LOC "LmkAMiso_i" 48;
+IO_PORT "LmkAMiso_i" IO_TYPE=LVCMOS33 PULL_MODE=UP BANK_VCCIO=3.3;

src/constr/BochV3.sdc

@@ -0,0 +1,11 @@
+//Copyright (C)2014-2024 GOWIN Semiconductor Corporation.
+//All rights reserved.
+//File Title: Timing Constraints file
+//Tool Version: V1.9.9.03 (64-bit) 
+//Created Time: 2024-11-26 10:09:40
+create_clock -name Sck_i -period 10 -waveform {0 8.334} [get_ports {Sck_i}]
+create_clock -name clk25 -period 40 -waveform {0 20} [get_nets {clk25}]
+create_clock -name clk40 -period 25 -waveform {0 12.5} [get_nets {clk40}]
+create_clock -name clk60 -period 16.667 -waveform {0 8.334} [get_nets {clk60}]
+set_clock_groups -asynchronous -group [get_clocks {Sck_i}] -group [get_clocks {clk60 clk40 clk25}]
+report_timing -setup -to_clock [get_clocks {clk60}]

src/src/InterfaceArbiter/InterfaceArbiter.v

@@ -105,9 +105,17 @@ module InterfaceArbiter
 	reg plsToggleSyncC;
 	reg plsToggleSyncSignalR;
 
+
 	/*Flash signals*/
 	reg 	plsToggleFlash;
 	wire 	plsToggleMux;
+	reg 	plsToggleSyncAFlash;
+	reg 	plsToggleSyncBFlash;
+	reg 	plsToggleSyncSignalRFlash;
+	wire 	plsToggleSyncSignalFlash;
+
+	/* Mux */
+	wire plsToggleSyncSignalMux;
 
 //================================================================================
 //  ASSIGNMENTS
@@ -118,6 +126,8 @@ module InterfaceArbiter
 	assign Data_o = (spiMode)? dataRegQSpi:dataRegSSpi;
 
 	assign plsToggleSyncSignal = plsToggleSyncA^plsToggle;
+	assign plsToggleSyncSignalFlash = plsToggleSyncAFlash^plsToggleFlash;
+	assign plsToggleSyncSignalMux = (DirectFlagFlash_i) ? plsToggleSyncSignalFlash:plsToggleSyncSignal;
 
 	//assign ssCntRstThresh = (spiMode) ? QSPIWORDWIDTH-1:SSPIWORDWIDTH-1;
 	
@@ -135,6 +145,18 @@ module InterfaceArbiter
     	end
 	end
 
+	always @(posedge Clk_i) begin 
+		if (Rst_i) begin 
+			plsToggleSyncAFlash <= 1'b0;
+			plsToggleSyncBFlash <= 1'b0;
+		end
+		else begin 
+			plsToggleSyncAFlash <= plsToggleFlash;
+			plsToggleSyncBFlash <= plsToggleSyncAFlash;
+		end
+	end
+
+
 	always @(posedge Clk_i) begin 
 	    if (Rst_i) begin 
 	        plsToggleSyncC <= 1'b0;
@@ -177,7 +199,7 @@ module InterfaceArbiter
 			plsToggleSyncSignalR <= 1'b0;
 		end
 		else begin 
-			plsToggleSyncSignalR <= plsToggleSyncSignal;
+			plsToggleSyncSignalR <= plsToggleSyncSignalMux;
 		end
 	end
 
@@ -254,7 +276,7 @@ module InterfaceArbiter
 	always @(posedge Clk_i) begin
 		if (!Rst_i) begin
 			if (currState == DATARX) begin
-				if (plsToggleSyncSignal) begin
+				if (plsToggleSyncSignalMux) begin
 					if (wordsCnt == wordsNum-1) begin
 						wordsCnt <= 0;
 						rxDone <= 1'b1;
@@ -321,7 +343,7 @@ module InterfaceArbiter
 	
 	always @(posedge Clk_i) begin
 		if (!Rst_i) begin
-			if (plsToggleSyncSignal) begin
+			if (plsToggleSyncSignalMux) begin
 				dataRegSSpi <= captRegSspi;
 				dataRegQSpi <= {captReg0,captReg1,captReg2,captReg3};
 				dataValReg <= 1'b1;