Init commit

src/src/ClkGen/ClkGen.v

@@ -0,0 +1,57 @@
+////////////////////////////////////////////////////////////////////////////////////////////
+// Company:			TAIR
+// Engineer:		Zaytsev Mikhail
+// 
+// Create Date:		23/04/2024 
+// Design Name: 
+// Module Name:		ClkGen 
+// Project Name:	BOCHV3_FPGA
+// Target Devices:	Board: BOCHV3. FPGA: GW1N-UV9QN88C6/I5
+// Tool versions:					
+// Dependencies:	
+// Revision: 
+// Revision 1.0 - File Created
+// Additional Comments: 
+//
+////////////////////////////////////////////////////////////////////////////////////////////
+module ClkGen (
+	output Clk60Mhz_o,
+	output Clk25Mhz_o
+);
+
+//==========================================
+// Wires
+//==========================================
+wire clk25Mhz;
+wire clk210Mhz;
+wire clk60Mhz;
+
+wire lockFirstPll;
+
+//==========================================
+// Assignments
+//==========================================
+assign Clk25Mhz_o = clk25Mhz;
+//==========================================================================//
+//									CODING									//
+//==========================================================================//
+GowinInternalOsc25MHZ GowinInternalOsc25MHZ
+(
+	.oscout(clk25Mhz)
+); 
+
+GowinPllFirst GowinPllFirst
+(
+	.clkin(clk25Mhz),
+	.lock(lockFirstPll),
+	.clkout(clk210Mhz)
+);
+
+GowinClkDiv3dot5 GowinClkDiv210MhzTo60Mhz
+(
+	.hclkin(clk210Mhz),
+	.clkout(Clk60Mhz_o),
+	.resetn(lockFirstPll)
+);
+
+endmodule

src/src/ClkGen/GowinClkDiv3dot5/GowinClkDiv3dot5.ipc

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+[General]
+ipc_version=4
+file=GowinClkDiv3dot5
+module=GowinClkDiv3dot5
+target_device=gw1n9-022
+type=clock_clkdiv
+version=1.0
+
+[Config]
+Calibration=false
+Division_Factor=3.5
+Language=0

src/src/ClkGen/GowinClkDiv3dot5/GowinClkDiv3dot5.mod

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+-series GW1N
+-device GW1N-9
+-device_version 
+-package QFN88
+-part_number GW1N-UV9QN88C6/I5
+
+
+-mod_name GowinClkDiv3dot5
+-file_name GowinClkDiv3dot5
+-path C:/Gowin/Projects/BOCHv3_FPGA/src/src/ClkGen/GowinClkDiv3dot5/
+-type CLKDIV
+-file_type vlg
+-division_factor 3.5
+-calib false

src/src/ClkGen/GowinClkDiv3dot5/GowinClkDiv3dot5.v

@@ -0,0 +1,29 @@
+//Copyright (C)2014-2024 Gowin Semiconductor Corporation.
+//All rights reserved.
+//File Title: IP file
+//Tool Version: V1.9.9.03 (64-bit)
+//Part Number: GW1N-UV9QN88C6/I5
+//Device: GW1N-9
+//Created Time: Fri Nov 22 15:18:20 2024
+
+module GowinClkDiv3dot5 (clkout, hclkin, resetn);
+
+output clkout;
+input hclkin;
+input resetn;
+
+wire gw_gnd;
+
+assign gw_gnd = 1'b0;
+
+CLKDIV clkdiv_inst (
+    .CLKOUT(clkout),
+    .HCLKIN(hclkin),
+    .RESETN(resetn),
+    .CALIB(gw_gnd)
+);
+
+defparam clkdiv_inst.DIV_MODE = "3.5";
+defparam clkdiv_inst.GSREN = "false";
+
+endmodule //GowinClkDiv3dot5

src/src/ClkGen/GowinClkDiv3dot5/GowinClkDiv3dot5_tmp.v

@@ -0,0 +1,18 @@
+//Copyright (C)2014-2024 Gowin Semiconductor Corporation.
+//All rights reserved.
+//File Title: Template file for instantiation
+//Tool Version: V1.9.9.03 (64-bit)
+//Part Number: GW1N-UV9QN88C6/I5
+//Device: GW1N-9
+//Created Time: Fri Nov 22 15:18:20 2024
+
+//Change the instance name and port connections to the signal names
+//--------Copy here to design--------
+
+    GowinClkDiv3dot5 your_instance_name(
+        .clkout(clkout), //output clkout
+        .hclkin(hclkin), //input hclkin
+        .resetn(resetn) //input resetn
+    );
+
+//--------Copy end-------------------

src/src/ClkGen/GowinInternalOsc25MHz/GowinInternalOsc25MHz.ipc

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+[General]
+ipc_version=4
+file=GowinInternalOsc25MHz
+module=GowinInternalOsc25MHz
+target_device=gw1n9-022
+type=clock_osc
+version=3.0
+
+[Config]
+FREQ=10
+LANG=0
+OSCILLATOR_FREQUENCY_210MHz=false
+OSCILLATOR_FREQUENCY_25MHz=false
+REGULATOR_ENABLE=false

src/src/ClkGen/GowinInternalOsc25MHz/GowinInternalOsc25MHz.mod

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+-series GW1N
+-device GW1N-9
+-device_version 
+-package QFN88
+-part_number GW1N-UV9QN88C6/I5
+
+
+-mod_name GowinInternalOsc25MHz
+-file_name GowinInternalOsc25MHz
+-path C:/Gowin/Projects/BOCHv3_FPGA/src/src/ClkGen/GowinInternalOsc25MHz/
+-type OSC
+-file_type vlg
+-dev_type GW1N-9
+-freq_div 10

src/src/ClkGen/GowinInternalOsc25MHz/GowinInternalOsc25MHz.v

@@ -0,0 +1,20 @@
+//Copyright (C)2014-2024 Gowin Semiconductor Corporation.
+//All rights reserved.
+//File Title: IP file
+//Tool Version: V1.9.9.03 (64-bit)
+//Part Number: GW1N-UV9QN88C6/I5
+//Device: GW1N-9
+//Created Time: Fri Nov 22 17:38:07 2024
+
+module GowinInternalOsc25MHz (oscout);
+
+output oscout;
+
+OSC osc_inst (
+    .OSCOUT(oscout)
+);
+
+defparam osc_inst.FREQ_DIV = 10;
+defparam osc_inst.DEVICE = "GW1N-9";
+
+endmodule //GowinInternalOsc25MHz

src/src/ClkGen/GowinInternalOsc25MHz/GowinInternalOsc25MHz_tmp.v

@@ -0,0 +1,16 @@
+//Copyright (C)2014-2024 Gowin Semiconductor Corporation.
+//All rights reserved.
+//File Title: Template file for instantiation
+//Tool Version: V1.9.9.03 (64-bit)
+//Part Number: GW1N-UV9QN88C6/I5
+//Device: GW1N-9
+//Created Time: Fri Nov 22 17:38:07 2024
+
+//Change the instance name and port connections to the signal names
+//--------Copy here to design--------
+
+    GowinInternalOsc25MHz your_instance_name(
+        .oscout(oscout) //output oscout
+    );
+
+//--------Copy end-------------------

src/src/ClkGen/GowinPllFirst/GowinPllFirst.ipc

@@ -0,0 +1,24 @@
+[General]
+ipc_version=4
+file=GowinPllFirst
+module=GowinPllFirst
+target_device=gw1n9-022
+type=clock_rpll
+version=1.0
+
+[Config]
+CKLOUTD3=false
+CLKFB_SOURCE=0
+CLKIN_FREQ=25
+CLKOUTD=false
+CLKOUTP=false
+CLKOUT_BYPASS=false
+CLKOUT_DIVIDE_DYN=true
+CLKOUT_FREQ=210
+CLKOUT_TOLERANCE=0
+DYNAMIC=true
+LANG=0
+LOCK_EN=true
+MODE_GENERAL=true
+PLL_PWD=false
+RESET_PLL=false

src/src/ClkGen/GowinPllFirst/GowinPllFirst.mod

@@ -0,0 +1,33 @@
+-series GW1N
+-device GW1N-9
+-device_version 
+-package QFN88
+-part_number GW1N-UV9QN88C6/I5
+
+
+-mod_name GowinPllFirst
+-file_name GowinPllFirst
+-path C:/Gowin/Projects/BOCHv3_FPGA/src/src/ClkGen/GowinPllFirst/
+-type PLL
+-rPll true
+-file_type vlg
+-dev_type GW1N-9
+-dyn_idiv_sel false
+-idiv_sel 5
+-dyn_fbdiv_sel false
+-fbdiv_sel 42
+-dyn_odiv_sel false
+-odiv_sel 4
+-dyn_da_en true
+-rst_sig false
+-rst_sig_p false
+-fclkin 25
+-clkfb_sel 0
+-en_lock true
+-clkout_bypass false
+-clkout_ft_dir 1
+-en_clkoutp false
+-clkoutp_bypass false
+-en_clkoutd false
+-clkoutd_bypass false
+-en_clkoutd3 false

src/src/ClkGen/GowinPllFirst/GowinPllFirst.v

@@ -0,0 +1,63 @@
+//Copyright (C)2014-2024 Gowin Semiconductor Corporation.
+//All rights reserved.
+//File Title: IP file
+//Tool Version: V1.9.9.03 (64-bit)
+//Part Number: GW1N-UV9QN88C6/I5
+//Device: GW1N-9
+//Created Time: Fri Nov 22 15:11:57 2024
+
+module GowinPllFirst (clkout, lock, clkin);
+
+output clkout;
+output lock;
+input clkin;
+
+wire clkoutp_o;
+wire clkoutd_o;
+wire clkoutd3_o;
+wire gw_gnd;
+
+assign gw_gnd = 1'b0;
+
+rPLL rpll_inst (
+    .CLKOUT(clkout),
+    .LOCK(lock),
+    .CLKOUTP(clkoutp_o),
+    .CLKOUTD(clkoutd_o),
+    .CLKOUTD3(clkoutd3_o),
+    .RESET(gw_gnd),
+    .RESET_P(gw_gnd),
+    .CLKIN(clkin),
+    .CLKFB(gw_gnd),
+    .FBDSEL({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd}),
+    .IDSEL({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd}),
+    .ODSEL({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd}),
+    .PSDA({gw_gnd,gw_gnd,gw_gnd,gw_gnd}),
+    .DUTYDA({gw_gnd,gw_gnd,gw_gnd,gw_gnd}),
+    .FDLY({gw_gnd,gw_gnd,gw_gnd,gw_gnd})
+);
+
+defparam rpll_inst.FCLKIN = "25";
+defparam rpll_inst.DYN_IDIV_SEL = "false";
+defparam rpll_inst.IDIV_SEL = 4;
+defparam rpll_inst.DYN_FBDIV_SEL = "false";
+defparam rpll_inst.FBDIV_SEL = 41;
+defparam rpll_inst.DYN_ODIV_SEL = "false";
+defparam rpll_inst.ODIV_SEL = 4;
+defparam rpll_inst.PSDA_SEL = "0000";
+defparam rpll_inst.DYN_DA_EN = "true";
+defparam rpll_inst.DUTYDA_SEL = "1000";
+defparam rpll_inst.CLKOUT_FT_DIR = 1'b1;
+defparam rpll_inst.CLKOUTP_FT_DIR = 1'b1;
+defparam rpll_inst.CLKOUT_DLY_STEP = 0;
+defparam rpll_inst.CLKOUTP_DLY_STEP = 0;
+defparam rpll_inst.CLKFB_SEL = "internal";
+defparam rpll_inst.CLKOUT_BYPASS = "false";
+defparam rpll_inst.CLKOUTP_BYPASS = "false";
+defparam rpll_inst.CLKOUTD_BYPASS = "false";
+defparam rpll_inst.DYN_SDIV_SEL = 2;
+defparam rpll_inst.CLKOUTD_SRC = "CLKOUT";
+defparam rpll_inst.CLKOUTD3_SRC = "CLKOUT";
+defparam rpll_inst.DEVICE = "GW1N-9";
+
+endmodule //GowinPllFirst

src/src/ClkGen/GowinPllFirst/GowinPllFirst_tmp.v

@@ -0,0 +1,18 @@
+//Copyright (C)2014-2024 Gowin Semiconductor Corporation.
+//All rights reserved.
+//File Title: Template file for instantiation
+//Tool Version: V1.9.9.03 (64-bit)
+//Part Number: GW1N-UV9QN88C6/I5
+//Device: GW1N-9
+//Created Time: Fri Nov 22 15:11:57 2024
+
+//Change the instance name and port connections to the signal names
+//--------Copy here to design--------
+
+    GowinPllFirst your_instance_name(
+        .clkout(clkout), //output clkout
+        .lock(lock), //output lock
+        .clkin(clkin) //input clkin
+    );
+
+//--------Copy end-------------------

src/src/InitRst/InitRst.v

@@ -0,0 +1,104 @@
+module InitRst (
+    clk_i,
+    signal_o
+);
+
+//================================================================================
+//
+//  FUNCTIONS
+//
+//================================================================================
+
+    function integer bit_num;
+        input integer value;
+        begin
+            bit_num = 0;
+            while (value > 0) begin
+                value   = value >> 1;
+                bit_num = bit_num + 1;
+            end
+        end
+    endfunction
+
+//================================================================================
+//
+//  PARAMETER/LOCALPARAM
+//
+//================================================================================
+
+    parameter   DELAY_VALUE     = 12000;
+    localparam  DELAY_CNT_W     = bit_num(DELAY_VALUE);
+
+//================================================================================
+//
+//  PORTS
+//
+//================================================================================
+
+    input           clk_i;
+    output  reg     signal_o;
+
+//================================================================================
+//
+//  STATE MACHINE STATES
+//
+//================================================================================
+
+    localparam      SM_RST_S    = 1'b0;
+    localparam      SM_DONE_S   = 1'b1;
+
+//================================================================================
+//
+//  REG/WIRE
+//
+//================================================================================
+
+    reg                         curr_state  = SM_RST_S;
+    reg     [DELAY_CNT_W-1:0]   delay_cnt   = {DELAY_CNT_W{1'b0}};
+    reg                         delay_flag  = 1'b0;
+
+    reg                         next_state;
+    reg     [DELAY_CNT_W-1:0]   delay_cnt_next	=	{DELAY_CNT_W{1'b0}};
+    reg                         signal_next;
+
+//================================================================================
+//
+//  CODING
+//
+//================================================================================
+
+initial begin
+    curr_state  = SM_RST_S;
+    delay_cnt   = {DELAY_CNT_W{1'b0}};
+    signal_o    = 1'b1;
+    delay_flag  = 1'b0;
+end
+
+always @(posedge clk_i) begin
+    curr_state  <= next_state;
+    delay_cnt   <= delay_cnt_next;
+    signal_o    <= signal_next;
+    delay_flag  <= delay_cnt > (DELAY_VALUE - 1);
+end
+
+always @(*) begin
+    next_state      = SM_RST_S;
+    delay_cnt_next  = delay_cnt;
+    signal_next     = 1'b1;
+    case(curr_state)
+        SM_RST_S    : begin
+            if (delay_flag) begin
+                next_state      = SM_DONE_S;
+            end else begin
+                next_state      = SM_RST_S;
+                delay_cnt_next  = delay_cnt + {{(DELAY_CNT_W-1){1'b0}}, 1'b1};
+            end
+        end
+        SM_DONE_S   : begin
+            signal_next = 1'b0;
+            next_state  = SM_DONE_S;
+        end
+    endcase
+end
+
+endmodule

src/src/InterfaceArbiter/InterfaceArbiter.v

@@ -0,0 +1,416 @@
+`timescale 1ns / 1ps
+
+//////////////////////////////////////////////////////////////////////////////////
+// Company: Tair
+// Engineer: Churbanov S.
+// 
+// Create Date:     
+// Design Name: 
+// Module Name:    InterfaceArbiter
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+
+module InterfaceArbiter 
+#(	
+	parameter OUTWORDWIDTH = 24,
+	parameter SSPIWORDWIDTH = 24,
+	parameter QSPIWORDWIDTH = SSPIWORDWIDTH/4
+)
+(
+	input Rst_i,
+	input Clk_i,
+	
+	input Sck_i,
+	input Ss_i,
+	input SsFlash_i,
+	
+	input Mosi0_i,
+	input Mosi1_i,
+	input Mosi2_i,
+	input Mosi3_i,
+
+	input DirectFlagFlash_i,
+	
+	
+	output DataVal_o,
+	output reg TestTrig_o,
+	output [OUTWORDWIDTH-1:0] Data_o
+);
+
+//================================================================================
+//  REG/WIRE
+
+	localparam [1:0] IDLE = 0;
+	localparam [1:0] DATARX = 1;
+	
+	reg [OUTWORDWIDTH-1:0] dataRegSSpi;
+	reg [OUTWORDWIDTH-1:0] dataRegQSpi;
+	
+	reg [OUTWORDWIDTH-1:0] captRegSspi;
+	
+	reg [QSPIWORDWIDTH-1:0] captReg0;
+	reg [QSPIWORDWIDTH-1:0] captReg1;
+	reg [QSPIWORDWIDTH-1:0] captReg2;
+	reg [QSPIWORDWIDTH-1:0] captReg3;
+
+	reg [OUTWORDWIDTH-1:0] captRegSspiR;
+	reg [OUTWORDWIDTH-1:0] captRegSspiRR;
+
+	reg [QSPIWORDWIDTH-1:0] captReg0R;
+	reg [QSPIWORDWIDTH-1:0] captReg0RR;
+	reg [QSPIWORDWIDTH-1:0] captReg1R;
+	reg [QSPIWORDWIDTH-1:0] captReg1RR;
+	reg [QSPIWORDWIDTH-1:0] captReg2R;
+	reg [QSPIWORDWIDTH-1:0] captReg2RR;
+	reg [QSPIWORDWIDTH-1:0] captReg3R;
+	reg [QSPIWORDWIDTH-1:0] captReg3RR;
+
+	reg ssReg;
+	reg ssRegR;
+	reg ssRegRR;
+	
+	reg spiMode;
+	reg qSpiDirectMode;
+	
+	wire ssPos;
+	reg ssPosR;
+	
+	reg dataValReg;
+	
+	reg [OUTWORDWIDTH/4-1:0] ssCnt;
+	reg [15:0] wordsCnt;
+	// wire [OUTWORDWIDTH/4-1:0] ssCntRstThresh = (spiMode) ? QSPIWORDWIDTH-1:SSPIWORDWIDTH-1;
+	
+	reg [15:0] wordsNum;
+	
+	reg [1:0] nextState;
+	reg [1:0] currState;
+	
+	reg rxDone;
+
+	wire plsToggleSyncSignal;
+	reg plsToggle;
+	reg plsToggleSyncA;
+	reg plsToggleSyncB;
+	reg plsToggleSyncC;
+	reg plsToggleSyncSignalR;
+
+	/*Flash signals*/
+	reg plsToggleFlash;
+
+//================================================================================
+//  ASSIGNMENTS
+	assign ssPos = ssRegR & !ssRegRR;
+
+	
+	assign DataVal_o = plsToggleSyncSignalR;
+	assign Data_o = (spiMode)? dataRegQSpi:dataRegSSpi;
+
+	assign plsToggleSyncSignal = plsToggleSyncA^plsToggle;
+
+	//assign ssCntRstThresh = (spiMode) ? QSPIWORDWIDTH-1:SSPIWORDWIDTH-1;
+	
+//================================================================================
+//  CODING
+
+	always @(posedge Clk_i) begin 
+    	if (Rst_i) begin 
+    	    plsToggleSyncA <= 1'b0;
+    	    plsToggleSyncB <= 1'b0;
+    	end
+    	else begin 
+    	    plsToggleSyncA <= plsToggle;
+    	    plsToggleSyncB <= plsToggleSyncA;
+    	end
+	end
+
+	always @(posedge Clk_i) begin 
+	    if (Rst_i) begin 
+	        plsToggleSyncC <= 1'b0;
+	    end
+	    else begin
+	        plsToggleSyncC <= plsToggleSyncB;
+	    end
+	end
+	
+	always @(posedge Ss_i or posedge Rst_i) begin 
+		if (Rst_i) begin 
+			plsToggle <= 1'b0;
+		end
+		else begin 
+			if (Ss_i) begin 
+				plsToggle <= ~plsToggle;
+			end
+			else begin 
+				plsToggle <= plsToggle;
+			end
+		end
+	end
+
+	always @(posedge SsFlash_i or posedge Rst_i) begin 
+		if (Rst_i) begin 
+			plsToggleFlash <= 1'b0;
+		end
+		else begin 
+			if (SsFlash_i) begin 
+				plsToggleFlash <= ~plsToggleFlash;
+			end
+			else begin 
+				plsToggleFlash <= plsToggleFlash;
+			end
+		end
+	end
+
+	always @(posedge Clk_i) begin 
+		if (Rst_i) begin 
+			plsToggleSyncSignalR <= 1'b0;
+		end
+		else begin 
+			plsToggleSyncSignalR <= plsToggleSyncSignal;
+		end
+	end
+
+	always @(posedge Sck_i or posedge Rst_i) begin 
+		if (Rst_i) begin 
+			captRegSspi <= 0;
+
+			captReg0 <= 0;
+			captReg1 <= 0;
+			captReg2 <= 0;
+			captReg3 <= 0;
+		end
+		else begin 
+			if (!Ss_i) begin 
+				captRegSspi <= {captRegSspi[OUTWORDWIDTH-2:0], Mosi0_i};
+				
+				captReg0 <= {captReg0[QSPIWORDWIDTH-2:0], Mosi0_i};
+				captReg1 <= {captReg1[QSPIWORDWIDTH-2:0], Mosi1_i};
+				captReg2 <= {captReg2[QSPIWORDWIDTH-2:0], Mosi2_i};
+				captReg3 <= {captReg3[QSPIWORDWIDTH-2:0], Mosi3_i};
+			end
+		end
+	end
+
+	always @(posedge Clk_i) begin 
+		if (Rst_i) begin 
+			captRegSspiR <= 0;
+			captRegSspiRR <= 0;
+		end
+		else begin 
+			captRegSspiR <= captRegSspi;
+			captRegSspiRR <= captRegSspiR;
+		end
+	end
+
+	always @(posedge Clk_i) begin 
+		if (Rst_i) begin 
+			captReg0R <= 0;
+			captReg0RR <= 0;
+			captReg1R <= 0;
+			captReg1RR <= 0;
+			captReg2R <= 0;
+			captReg2RR <= 0;
+			captReg3R <= 0;
+			captReg3RR <= 0;
+		end
+		else begin 
+			captReg0R <= captReg0;
+			captReg0RR <= captReg0R;
+			captReg1R <= captReg1;
+			captReg1RR <= captReg1R;
+			captReg2R <= captReg2;
+			captReg2RR <= captReg2R;
+			captReg3R <= captReg3;
+			captReg3RR <= captReg3R;
+		end
+	end
+
+	always @(*) begin
+		if (currState == IDLE && (Data_o[11]& Data_o[8])) begin
+			TestTrig_o = 1'b1;
+		end
+		else begin
+			TestTrig_o = 1'b0;
+		end
+	end
+
+	always @(posedge Sck_i or posedge Rst_i) begin 
+		if (Rst_i) begin 
+			ssCnt <= 0;
+		end
+		else begin 
+			if (currState == IDLE) begin
+				if (!Ss_i) begin 
+					ssCnt <= ssCnt+1; 
+				end
+			end else begin
+				ssCnt <= 0;
+			end
+		end
+	end
+
+	always @(posedge Clk_i) begin
+		if (!Rst_i) begin
+			if (currState == DATARX) begin
+				if (plsToggleSyncSignal) begin
+					if (wordsCnt == wordsNum-1) begin
+						wordsCnt <= 0;
+						rxDone <= 1'b1;
+					end else begin
+						wordsCnt <= wordsCnt+1;
+						rxDone <= 1'b0;
+					end
+				end
+			end else begin
+				wordsCnt <= 0;
+				rxDone <= 1'b0;
+			end
+		end else begin
+			wordsCnt <= 0;
+			rxDone <= 1'b0;
+		end
+	end
+	
+	always @(posedge Sck_i or posedge Rst_i) begin 
+		if (Rst_i) begin 
+			spiMode <= 1'b0;
+		end
+		else begin
+			if (currState == IDLE) begin 
+				if (ssCnt == 1) begin 
+					if (captRegSspi[0]) begin 
+						spiMode <= 1'b1; 
+					end 
+					else begin 
+						spiMode <= 1'b0; 
+					end
+				end
+			end
+		end
+	end
+
+	always @(posedge Sck_i or posedge Rst_i) begin 
+		if (Rst_i) begin 
+			qSpiDirectMode <= 1'b0;
+		end
+		else begin 
+			if (currState == IDLE) begin 
+				if (ssCnt == 2) begin 
+					if (captRegSspi[1:0] == 2'b11) begin 
+						qSpiDirectMode <= 1'b1; 
+					end 
+					else begin 
+						qSpiDirectMode <= 1'b0; 
+					end
+				end
+			end
+		end
+	end
+
+	always @(posedge Clk_i) begin
+		if (!Rst_i) begin
+			if (currState == IDLE) begin
+				if (!spiMode) begin
+					wordsNum <= dataRegSSpi[16:1];
+				end else begin
+					if (!qSpiDirectMode) begin
+						wordsNum <= dataRegQSpi[21:19]+dataRegQSpi[17:16]+dataRegQSpi[15:12]+dataRegQSpi[10:9]+dataRegQSpi[7:6]+dataRegQSpi[4:3]+dataRegQSpi[2]+dataRegQSpi[1];
+					end else begin
+						wordsNum <= dataRegQSpi[16:1];
+					end
+				end 
+			end
+		end else begin
+			wordsNum <= 0;
+		end
+	end 
+	
+	always @(posedge Clk_i) begin
+		if (!Rst_i) begin
+			ssReg <= Ss_i;
+			ssRegR <= ssReg;
+			ssRegRR <= ssRegR;
+			ssPosR <= ssPos;
+		end else begin
+			ssReg <= 1;
+			ssRegR <= 1;
+			ssRegRR <= 1;
+			ssPosR <= 0;
+		end
+	end 
+	
+	always @(posedge Clk_i) begin
+		if (!Rst_i) begin
+			if (plsToggleSyncSignal) begin
+				dataRegSSpi <= captRegSspi;
+				dataRegQSpi <= {captReg0,captReg1,captReg2,captReg3};
+				dataValReg <= 1'b1;
+			end else begin
+				dataValReg <= 1'b0;
+			end
+		end else begin
+			dataRegSSpi <= 0;
+			dataRegQSpi <= 0;
+			dataValReg <= 0;
+		end
+	end
+
+	always @(posedge Clk_i) begin
+		if (Rst_i) begin
+			currState <= IDLE;
+		end else begin
+			currState <= nextState;
+		end
+	end
+
+	always @(*) begin
+		nextState = IDLE;
+		case(currState)
+		IDLE		:begin
+						if (plsToggleSyncSignalR)	begin
+							nextState = DATARX;
+						end	else begin
+							nextState = IDLE;
+						end
+					end
+
+		DATARX		:begin
+						if (rxDone) begin
+							nextState  = IDLE;
+						end	else begin
+							nextState  = DATARX;
+						end
+					end
+		endcase
+	end
+
+endmodule
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+

src/src/PacketAnalyzer1Mosi/PacketAnalyzer1Mosi.v

@@ -0,0 +1,141 @@
+////////////////////////////////////////////////////////////////////////////////////////////
+// Company:			TAIR
+// Engineer:		Zaytsev Mikhail
+// 
+// Create Date:		19/04/2024 
+// Design Name: 
+// Module Name:		PacketAnalyzer1Mosi 
+// Project Name:	BOCHV3_FPGA
+// Target Devices:	Board: BOCHV3. FPGA: GW1N-UV9QN88
+// Tool versions:
+// Description:		The module analyzes the data on the DataFromSpi_i[23:0] bus using the 
+// 					ValDataFromSpi_i validity signal.  When a configuration packet is received, 
+// 					data is captured into the two internal registers devId and cntData. 
+// 					Next, the cntData register is decremented with each incoming data parcel 
+// 					until it becomes zero. If the value in the register is equal to zero means 
+// 					that the module is ready to receive the next configuration packet. 
+// 					As long as the value of cntData is not equal to zero at the output of the 
+// 					module is active signal FlagDirect..._o for the device specified in the 
+// 					register devId. The module also has an output signal Busy_o, which signals 
+// 					that the module is in the state of processing data received in 1MOSI mode.
+// Dependencies:	
+// Revision: 
+// Revision 1.0 - File Created
+// Additional Comments: 
+//
+////////////////////////////////////////////////////////////////////////////////////////////
+module PacketAnalyzer1Mosi (
+	input Clk_i,
+	input Rst_i,
+
+	input [23:0] DataFromSpi_i,
+	input ValDataFromSpi_i,
+
+	input BusyMosi4_i,
+
+	output reg FlagDirectLmkA_o,
+	output reg FlagDirectLmkB_o,
+	output reg FlagDirectHubTfe_o,
+	output reg FlagDirectFlash_o,
+
+	output reg Busy_o
+);
+
+//==========================================
+// Registers
+//==========================================
+reg [4:0] devId;
+reg [16:0] cntData;
+
+//==========================================
+// Wires
+//==========================================
+
+//==========================================
+// Parameters
+//==========================================
+localparam DEV_ID_LMKA 						= 5'd0;
+localparam DEV_ID_LMKB 						= 5'd1;
+localparam DEV_ID_CTRL_COLD_PART 			= 5'd2;
+localparam DEV_ID_HUB_TFE 					= 5'd3;
+localparam DEV_ID_FLASH 					= 5'd4;
+
+//==========================================
+// Assignments
+//==========================================
+
+//==========================================================================//
+//									CODING									//
+//==========================================================================//
+always @(posedge Clk_i) begin
+	if(Rst_i || BusyMosi4_i) begin
+		devId 	<= 5'b0;
+		cntData <= 17'b0;
+	end 
+	else if (ValDataFromSpi_i) begin
+		if (cntData == 0) begin 
+			if (DataFromSpi_i[23] == 0) begin
+				cntData <= DataFromSpi_i[17:1];
+				devId 	<= DataFromSpi_i[22:18];
+			end
+			else begin
+				cntData <= 5'b0;
+				devId 	<= 17'b0;
+			end
+		end	
+		else begin
+			cntData <= cntData - 1'b1;	
+		end
+	end
+	else if (cntData == 0) begin
+		devId <= 5'b0;
+	end
+end
+
+always @(posedge Clk_i) begin
+	if (Rst_i) begin
+		FlagDirectLmkA_o 	<= 1'b0;
+		FlagDirectLmkB_o 	<= 1'b0;
+		FlagDirectHubTfe_o <= 1'b0;
+		FlagDirectFlash_o 	<= 1'b0;
+	end
+	else if (cntData != 0) begin
+		case (devId)
+			DEV_ID_LMKA : begin
+				FlagDirectLmkA_o <= 1'b1;
+			end
+			DEV_ID_LMKB : begin
+				FlagDirectLmkB_o <= 1'b1;
+			end
+			DEV_ID_HUB_TFE : begin
+				FlagDirectHubTfe_o <= 1'b1;
+			end
+			DEV_ID_FLASH : begin
+				FlagDirectFlash_o <= 1'b1;
+			end
+			default : begin
+
+			end
+		endcase
+	end
+	else begin
+		FlagDirectLmkA_o 	<= 1'b0;
+		FlagDirectLmkB_o 	<= 1'b0;
+		FlagDirectHubTfe_o <= 1'b0;
+		FlagDirectFlash_o 	<= 1'b0;
+	end
+end
+
+always @(posedge Clk_i) begin
+	if (Rst_i) begin
+		Busy_o <= 1'b0;
+	end
+	else if (cntData != 0) begin
+		Busy_o <= 1'b1;
+	end
+	else begin
+		Busy_o <= 1'b0;
+	end
+end
+
+endmodule

src/src/PacketAnalyzer4Mosi/PacketAnalyzer4Mosi.v

@@ -0,0 +1,196 @@
+////////////////////////////////////////////////////////////////////////////////////////////
+// Company:			TAIR
+// Engineer:		Zaytsev Mikhail
+// 
+// Create Date:		18/04/2024 
+// Design Name: 
+// Module Name:		PacketAnalyzer4Mosi 
+// Project Name:	BOCHV3_FPGA
+// Target Devices:	Board: BOCHV3. FPGA: GW1N-UV9QN88
+// Tool versions:
+// Description:		The module analyzes the input data bus DataFromSpi_i[23:0] by the 
+//					validity signal ValDataFromSpi_i. When a configuration packet is 
+//					received, it is captured into the internal register. Further, each 
+//					incoming data packet decrements the internal configuration register 
+//					until the internal configuration register is zero, which means that 
+//					the module is ready to receive the next configuration packet. Each 
+//					decrement sets the data validity bit for the specific end device. 
+//					The module also has an output signal Busy_o, which signals that 
+//					the module is in the state of processing the data received in 
+//					4MOSI mode for writing to the FIFO.
+//
+// Dependencies:	
+// Revision: 
+// Revision 1.0 - File Created
+// Additional Comments: 
+//
+////////////////////////////////////////////////////////////////////////////////////////////
+module PacketAnalyzer4Mosi (
+	input Clk_i,
+	input Rst_i,
+
+	input [23:0] DataFromSpi_i,
+	input ValDataFromSpi_i,
+
+	input BusyMosi1_i,
+
+	output reg ValCtrlColdPartDataToFifo_o,
+	output reg ValTfe2BytesDataToFifo_o,
+	output reg ValTfe4BytesDataToFifo_o,
+	output reg ValTfe7BytesDataToFifo_o,
+	output reg ValTfe6BytesDataToFifo_o,
+
+
+	output reg Busy_o
+);
+
+//==========================================
+// Registers
+//==========================================
+reg [22:0] dataSpiReg;
+
+//==========================================
+// Wires
+//==========================================
+wire ctrlColdPartOr;
+wire tfe2BytesOr;
+wire tfe4BytesOr;
+wire tfe7BytesOr;
+wire tfe6BytesOr;
+
+wire [4:0] selector;
+
+//==========================================
+// Parameters
+//==========================================
+localparam [22:0] DECREMENT_CTRL_COLD_PART 	= 23'h40000;	//23'b000 0100 0000 0000 0000 0000
+localparam [22:0] DECREMENT_TFE_2_BYTES 	= 23'h20000;	//23'b000 0010 0000 0000 0000 0000
+localparam [22:0] DECREMENT_TFE_4_BYTES 	= 23'h10000;	//23'b000 0001 0000 0000 0000 0000
+localparam [22:0] DECREMENT_TFE_7_BYTES 	= 23'h2000;		//23'b000 0000 0010 0000 0000 0000
+localparam [22:0] DECREMENT_TFE_6_BYTES 	= 23'h800 ;		//23'b000 0000 0000 1000 0000 0000
+
+//==========================================
+// Assignments
+//==========================================
+assign ctrlColdPartOr 	= 	|dataSpiReg[21:18];
+assign tfe2BytesOr 	= 	|dataSpiReg[17];
+assign tfe4BytesOr 	= 	|dataSpiReg[16:15];
+assign tfe7BytesOr 	= 	|dataSpiReg[14:13];
+assign tfe6BytesOr 	= 	|dataSpiReg[12:11];
+
+assign selector = {ctrlColdPartOr, tfe2BytesOr, tfe4BytesOr, tfe7BytesOr, tfe6BytesOr};
+
+//==========================================================================//
+//									CODING									//
+//==========================================================================//
+always @(posedge Clk_i) begin
+	if (Rst_i) begin
+		Busy_o <= 1'b0;
+	end
+	else if (dataSpiReg != 0) begin
+		Busy_o <= 1'b1;
+	end
+	else begin
+		Busy_o <= 1'b0;
+	end
+end
+
+always @(posedge Clk_i) begin
+	if (Rst_i || BusyMosi1_i) begin
+		dataSpiReg <= 23'b0;
+		ValCtrlColdPartDataToFifo_o <= 1'b0;
+		ValTfe2BytesDataToFifo_o <= 1'b0;
+		ValTfe4BytesDataToFifo_o <= 1'b0;
+		ValTfe7BytesDataToFifo_o <= 1'b0;
+		ValTfe6BytesDataToFifo_o <= 1'b0;
+	end
+	else if (ValDataFromSpi_i) begin
+		if ((dataSpiReg == 0) && (DataFromSpi_i[23] == 1'b1)) begin
+			dataSpiReg[22:1] <= DataFromSpi_i[22:1];
+		end
+		else begin
+			casez(selector)
+			5'b1????: begin //CtrlColdPart
+				dataSpiReg <= dataSpiReg - DECREMENT_CTRL_COLD_PART;
+				ValCtrlColdPartDataToFifo_o <= 1'b1;
+			end
+			5'b01???: begin //Tfe2Bytes
+				dataSpiReg <= dataSpiReg - DECREMENT_TFE_2_BYTES;
+				ValTfe2BytesDataToFifo_o <= 1'b1;
+			end
+			5'b001??: begin //Tfe4Bytes
+				dataSpiReg <= dataSpiReg - DECREMENT_TFE_4_BYTES;
+				ValTfe4BytesDataToFifo_o <= 1'b1;
+			end
+			5'b0001?: begin //Tfe7Bytes
+				dataSpiReg <= dataSpiReg - DECREMENT_TFE_7_BYTES;
+				ValTfe7BytesDataToFifo_o <= 1'b1;
+			end
+			5'b00001: begin //Tfe6Bytes
+				dataSpiReg <= dataSpiReg - DECREMENT_TFE_6_BYTES;
+				ValTfe6BytesDataToFifo_o <= 1'b1;
+			end
+			default: begin
+				ValCtrlColdPartDataToFifo_o <= 1'b0;
+				ValTfe2BytesDataToFifo_o <= 1'b0;
+				ValTfe4BytesDataToFifo_o <= 1'b0;
+				ValTfe7BytesDataToFifo_o <= 1'b0;
+				ValTfe6BytesDataToFifo_o <= 1'b0;
+			end
+		endcase
+//=========================DELETE AFTER HARDWARE TEST===========================
+			/*if (lmxOr) begin //LMX
+				dataSpiReg <= dataSpiReg - DECREMENT_LMX;
+				ValLmxDataToFifo_o 		<= 1'b1;
+			end
+			else if (ddsOr) begin //DDS
+				dataSpiReg <= dataSpiReg - DECREMENT_DDS;
+				ValDdsDataToFifo_o 		<= 1'b1;
+			end
+			else if (potOr) begin //POT
+				dataSpiReg <= dataSpiReg - DECREMENT_POT;
+				ValPotDataToFifo_o 		<= 1'b1;
+			end
+			else if (dacOr) begin //DAC
+				dataSpiReg <= dataSpiReg - DECREMENT_DAC;
+				ValDacDataToFifo_o 		<= 1'b1;
+			end
+			else if (attOr) begin
+				dataSpiReg <= dataSpiReg - DECREMENT_ATT;
+				ValAttDataToFifo_o 		<= 1'b1;
+			end
+			else if (shRegOr) begin
+				dataSpiReg <= dataSpiReg - DECREMENT_SH_REG;
+				ValShRegDataToFifo_o 	<= 1'b1;
+			end
+			else if (maxOr) begin
+				dataSpiReg <= dataSpiReg - DECREMENT_MAX;
+				ValMaxDataToFifo_o 		<= 1'b1;
+			end
+			else if (gpioOr) begin
+				dataSpiReg <= dataSpiReg - DECREMENT_GPIO;
+				ValGpioDataToFifo_o 	<= 1'b1;
+			end
+			else begin
+				ValLmxDataToFifo_o 		<= 1'b0;
+				ValDdsDataToFifo_o 		<= 1'b0;
+				ValPotDataToFifo_o 		<= 1'b0;
+				ValDacDataToFifo_o 		<= 1'b0;
+				ValAttDataToFifo_o 		<= 1'b0;
+				ValShRegDataToFifo_o 	<= 1'b0;
+				ValMaxDataToFifo_o 		<= 1'b0;
+				ValGpioDataToFifo_o 	<= 1'b0;
+			end*/
+//=========================DELETE AFTER HARDWARE TEST===========================
+		end
+	end
+	else begin
+		ValCtrlColdPartDataToFifo_o <= 1'b0;
+		ValTfe2BytesDataToFifo_o <= 1'b0;
+		ValTfe4BytesDataToFifo_o <= 1'b0;
+		ValTfe7BytesDataToFifo_o <= 1'b0;
+		ValTfe6BytesDataToFifo_o <= 1'b0;
+	end
+end
+
+endmodule

src/src/Top/ExtSpiMEmul.v

@@ -0,0 +1,536 @@
+module ExtSpiMEmul (
+    input Clk_i,
+    input Rst_i,
+    input Start_i,
+    input EmptyFlag_i,
+    input ClockPhase_i,
+    input [31:0] SpiData_i,
+    input SelSt_i,
+    input [1:0] WidthSel_i,
+    input  Lag_i,
+    input  Lead_i,
+    input EndianSel_i,
+    input [5:0] Stop_i,
+    input PulsePol_i,
+
+
+    output reg Mosi0_o,
+    output reg Sck_o,
+    output  Ss_o,
+    output reg  Val_o
+);
+
+
+//================================================================================
+//	REG/WIRE
+//================================================================================
+
+    reg startFlag;
+    reg startR;
+    reg [31:0] trCnt;
+    reg valReg;
+    reg valToRxFifo1;
+    reg lineBusy;
+    reg [5:0] ssCnt;
+    reg Ss;
+    reg [31:0]spiDataR;
+    reg oldDataFlag;
+    
+    reg ssR;
+    reg SSR;
+    reg [31:0] mosiReg0;
+    reg [5:0] ssNum;
+    reg [2:0] delayCnt;
+    reg stopFlag;
+    
+    wire ssPol = SelSt_i ? Ss : ~Ss;
+    
+    
+    //================================================================================
+    //  ASSIGNMENTS
+    //================================================================================
+    
+    
+    assign Ss_o = ssPol; 
+    
+    //================================================================================
+    //	CODING
+    //================================================================================
+    
+    always @(*) begin 
+        if (Start_i) begin  
+            Val_o = valReg;
+        end
+        else begin 
+            Val_o = 1'b0;
+        end
+    end
+    
+    
+    always @(*) begin 
+        if (SelSt_i) begin 
+            if (!Ss_o) begin 
+                lineBusy = 1'b1;
+            end
+            else begin 
+                lineBusy = 1'b0;
+            end
+        end
+        else begin 
+            if (Ss_o) begin 
+                lineBusy = 1'b1;
+            end
+            else begin 
+                lineBusy = 1'b0;
+            end
+        end
+    end
+    
+    
+    
+    always @(posedge Clk_i) begin
+        if (valReg) begin  
+            spiDataR <= SpiData_i;
+        end
+    end
+    
+    
+    always @(*) begin 
+        if (Rst_i) begin 
+            oldDataFlag = 1'b0;
+        end
+        else begin 
+            if (spiDataR == SpiData_i && (SpiData_i != 0) || EmptyFlag_i) begin 
+                oldDataFlag = 1'b1;
+            end
+            else begin 
+                oldDataFlag = 1'b0;
+            end
+        end
+    end
+    
+    
+    always @(posedge Clk_i) begin 
+        startR <= Start_i;
+    end
+    
+    always @(*) begin 
+        if (Rst_i) begin 
+            valToRxFifo1 = 1'b0;
+        end
+        else begin 
+            if (Start_i && !startR) begin 
+                valToRxFifo1 = 1'b1;
+            end
+            else begin 
+                valToRxFifo1 = 1'b0;
+            end
+        end
+    end
+    
+    always @(negedge Clk_i) begin 
+        if (Rst_i) begin 
+            delayCnt <= 1'b0;
+        end
+        else begin 
+            if (stopFlag &&delayCnt < Stop_i) begin 
+                delayCnt <= delayCnt + 1'b1;
+            end
+            else begin 
+                delayCnt <= 1'b0;
+            end
+        end
+    end
+    
+    always @(posedge Clk_i) begin 
+        if (Rst_i) begin 
+            stopFlag <= 1'b0;
+        end
+        else begin
+            if (SelSt_i) begin 
+                if (Ss && !ssR) begin 
+                    stopFlag <= 1'b1;
+                end
+                else if ( delayCnt == Stop_i) begin 
+                    stopFlag <= 1'b0;
+                end
+            end
+            else begin 
+                if (!Ss && ssR) begin 
+                    stopFlag <= 1'b1;
+                end
+                else if (delayCnt == Stop_i) begin 
+                    stopFlag <= 1'b0;
+                end
+            end
+        end
+    end
+    
+    
+    
+    
+    always @(*) begin
+        if (SelSt_i) begin 
+            if (PulsePol_i) begin 
+                if (ClockPhase_i) begin
+                    if (Lead_i == 0) begin 
+                        if (!Ss && (ssCnt <= ssNum+Lag_i+Lead_i && ssCnt > Lag_i) ) begin 
+                            Sck_o = ~(~Clk_i);
+                        end
+                        else begin 
+                            Sck_o = 1'b0;
+                        end
+                    end
+                    else begin 
+                        if (!Ss && (ssCnt < ssNum+Lag_i+Lead_i && ssCnt > Lag_i)) begin 
+                            Sck_o = ~(~Clk_i);
+                        end
+                        else begin 
+                            Sck_o = 1'b0;
+                        end
+                    end
+                end
+                else begin
+                    if (Lead_i == 0) begin 
+                        if (!Ss && (ssCnt <= ssNum+Lag_i+Lead_i && ssCnt > Lag_i) ) begin 
+                            Sck_o = ~(Clk_i);
+                        end
+                        else begin 
+                            Sck_o = 1'b0;
+                        end
+                    end
+                    else begin 
+                        if (!Ss && (ssCnt < ssNum + Lag_i + Lead_i && ssCnt > Lag_i)) begin 
+                            Sck_o = ~(Clk_i);
+                        end
+                        else begin 
+                            Sck_o = 1'b0;
+                        end
+                    end
+                end
+            end
+            else begin 
+                if (ClockPhase_i) begin
+                    if (Lead_i == 0) begin  
+                        if (!Ss && (ssCnt <= ssNum+Lag_i+Lead_i && ssCnt > Lag_i) ) begin 
+                            Sck_o = ~(Clk_i);
+                        end
+                        else begin 
+                            Sck_o = 1'b0;
+                        end
+                    end
+                    else begin 
+                        if (!Ss && (ssCnt <ssNum + Lag_i + Lag_i && ssCnt > Lag_i)) begin 
+                            Sck_o = ~(Clk_i);
+                        end
+                        else begin 
+                            Sck_o = 1'b0;
+                        end
+                    end
+                end 
+                else begin
+                    if (Lead_i == 0) begin 
+                        if (!Ss && (ssCnt <= ssNum+Lag_i+Lead_i && ssCnt > Lag_i) ) begin 
+                            Sck_o = ~(~Clk_i);
+                        end
+                        else begin 
+                            Sck_o = 1'b0;
+                        end
+                    end
+                    else begin 
+                        if (!Ss && (ssCnt < ssNum + Lag_i + Lead_i && ssCnt > Lag_i)) begin 
+                            Sck_o = ~(~Clk_i);
+                        end
+                        else begin 
+                            Sck_o = 1'b0;
+                        end
+                    end
+                end
+            end
+        end
+        else begin 
+              if (PulsePol_i) begin 
+                if (ClockPhase_i) begin
+                    if (Lead_i == 0) begin 
+                        if (ssPol && (ssCnt <= ssNum+Lag_i+Lead_i && ssCnt > Lag_i) ) begin 
+                            Sck_o = ~(~Clk_i);
+                        end
+                        else begin 
+                            Sck_o = 1'b0;
+                        end
+                    end
+                    else begin 
+                        if (ssPol && (ssCnt < ssNum+Lag_i+Lead_i && ssCnt > Lag_i)) begin 
+                            Sck_o = ~(~Clk_i);
+                        end
+                        else begin 
+                            Sck_o = 1'b0;
+                        end
+                    end
+                end
+                else begin
+                    if (Lead_i == 0) begin 
+                        if (ssPol && (ssCnt <= ssNum+Lag_i+Lead_i && ssCnt > Lag_i) ) begin 
+                            Sck_o = ~(Clk_i);
+                        end
+                        else begin 
+                            Sck_o = 1'b0;
+                        end
+                    end
+                    else begin 
+                        if (ssPol && (ssCnt < ssNum + Lag_i + Lead_i && ssCnt > Lag_i)) begin 
+                            Sck_o = ~(Clk_i);
+                        end
+                        else begin 
+                            Sck_o = 1'b0;
+                        end
+                    end
+                end
+            end
+            else begin 
+                if (ClockPhase_i) begin
+                    if (Lead_i == 0) begin  
+                        if (ssPol && (ssCnt <= ssNum+Lag_i+Lead_i && ssCnt > Lag_i) ) begin 
+                            Sck_o = ~(Clk_i);
+                        end
+                        else begin 
+                            Sck_o = 1'b0;
+                        end
+                    end
+                    else begin 
+                        if (ssPol && (ssCnt <ssNum + Lag_i + Lag_i && ssCnt > Lag_i)) begin 
+                            Sck_o = ~(Clk_i);
+                        end
+                        else begin 
+                            Sck_o = 1'b0;
+                        end
+                    end
+                end 
+                else begin
+                    if (Lead_i == 0) begin 
+                        if (ssPol && (ssCnt <= ssNum+Lag_i+Lead_i && ssCnt > Lag_i) ) begin 
+                            Sck_o = ~(~Clk_i);
+                        end
+                        else begin 
+                            Sck_o = 1'b0;
+                        end
+                    end
+                    else begin 
+                        if (ssPol && (ssCnt < ssNum + Lag_i + Lead_i && ssCnt > Lag_i)) begin 
+                            Sck_o = ~(~Clk_i);
+                        end
+                        else begin 
+                            Sck_o = 1'b0;
+                        end
+                    end
+                end
+            end
+        end
+            
+    end
+    
+    
+    always @(*) begin
+        if (Rst_i) begin 
+            Mosi0_o = 1'b0;
+        end
+        else begin
+            if (SelSt_i) begin 
+                if (!EndianSel_i) begin 
+                    case (WidthSel_i)  
+                        0 : begin
+                            Mosi0_o = (!Ss&& (ssCnt <= ssNum+Lag_i && ssCnt > Lag_i))? (mosiReg0[7]):1'b0;
+                        end
+                        1 : begin
+                            Mosi0_o = (!Ss&& (ssCnt <= ssNum+Lag_i && ssCnt > Lag_i))? (mosiReg0[15]):1'b0;
+                        end
+                        2 : begin
+                            Mosi0_o = (!Ss&& (ssCnt <= ssNum+Lag_i && ssCnt > Lag_i))? (mosiReg0[23]):1'b0;
+                        end
+                        3 : begin
+                            Mosi0_o = (!Ss&& (ssCnt <= ssNum+Lag_i && ssCnt > Lag_i))? (mosiReg0[31]):1'b0;
+                        end
+                    endcase
+                end
+                else begin 
+                    case (WidthSel_i)  
+                        0 : begin
+                            Mosi0_o = (!Ss&& (ssCnt <= ssNum+Lag_i && ssCnt > Lag_i))? (mosiReg0[0]):1'b0;
+                        end
+                        1 : begin
+                            Mosi0_o = (!Ss&& (ssCnt <= ssNum+Lag_i && ssCnt > Lag_i))? (mosiReg0[0]):1'b0;
+                        end
+                        2 : begin
+                            Mosi0_o = (!Ss&& (ssCnt <= ssNum+Lag_i && ssCnt > Lag_i))? (mosiReg0[0]):1'b0;
+                        end
+                        3 : begin
+                            Mosi0_o = (!Ss&& (ssCnt <= ssNum+Lag_i && ssCnt > Lag_i))? (mosiReg0[0]):1'b0;
+                        end
+                    endcase
+                end
+            end
+            else begin 
+                if (!EndianSel_i) begin 
+                    case (WidthSel_i)  
+                        0 : begin
+                            Mosi0_o = (ssPol&& (ssCnt <= ssNum+Lag_i && ssCnt > Lag_i))? (mosiReg0[7]):1'b0;
+                        end
+                        1 : begin
+                            Mosi0_o = (ssPol&& (ssCnt <= ssNum+Lag_i && ssCnt > Lag_i))? (mosiReg0[15]):1'b0;
+                        end
+                        2 : begin
+                            Mosi0_o = (ssPol&& (ssCnt <= ssNum+Lag_i && ssCnt > Lag_i))? (mosiReg0[23]):1'b0;
+                        end
+                        3 : begin
+                            Mosi0_o = (ssPol&& (ssCnt <= ssNum+Lag_i && ssCnt > Lag_i))? (mosiReg0[31]):1'b0;
+                        end
+                    endcase
+                end
+                else begin 
+                    case (WidthSel_i)  
+                        0 : begin
+                            Mosi0_o = (ssPol&& (ssCnt <= ssNum+Lag_i && ssCnt > Lag_i))? (mosiReg0[0]):1'b0;
+                        end
+                        1 : begin
+                            Mosi0_o = (ssPol&& (ssCnt <= ssNum+Lag_i && ssCnt > Lag_i))? (mosiReg0[0]):1'b0;
+                        end
+                        2 : begin
+                            Mosi0_o = (ssPol&& (ssCnt <= ssNum+Lag_i && ssCnt > Lag_i))? (mosiReg0[0]):1'b0;
+                        end
+                        3 : begin
+                            Mosi0_o = (ssPol&& (ssCnt <= ssNum+Lag_i && ssCnt > Lag_i))? (mosiReg0[0]):1'b0;
+                        end
+                    endcase
+                end
+            end
+        end
+    end
+    
+    
+    
+    always @(posedge Clk_i) begin
+        ssR <= ssPol;
+        SSR <= Ss;
+    end
+    
+    
+    always @(*) begin 
+        if (Rst_i) begin 
+            startFlag = 1'b0;
+        end
+        else begin 
+            if (Start_i && !stopFlag && !EmptyFlag_i) begin 
+                startFlag = 1'b1;
+            end
+            else begin 
+                startFlag = 1'b0;
+            end
+        end
+    end
+    
+    always @(*) begin
+        if (SelSt_i) begin 
+            if (Ss_o && !ssR) begin 
+                valReg = 1'b1;
+            end
+            else begin 
+                valReg = 1'b0;
+            end
+        end
+        else begin 
+            if (!Ss_o&& ssR) begin 
+                valReg = 1'b1;
+            end
+            else begin 
+                valReg = 1'b0;
+            end
+        end
+    end
+    
+    
+    always @(*) begin 
+        if (Rst_i) begin 
+            ssNum = 1'b0;
+        end
+        else begin 
+            case (WidthSel_i) 
+                0 : begin 
+                    ssNum = 8;
+                end
+                1 : begin 
+                    ssNum = 16;
+                end
+                2 : begin 
+                    ssNum = 24;
+                end
+                3 : begin 
+                    ssNum = 32;
+                end
+            endcase
+        end
+    end
+    
+    
+    always @(negedge Clk_i) begin 
+        if (Rst_i) begin 
+            ssCnt <= 1'b0;
+        end
+        else if (ssCnt <= (ssNum+Lag_i+Lead_i)  && startFlag  ) begin 
+            ssCnt <= ssCnt + 1'b1;
+        end
+        else begin
+            if (ssCnt == ssNum-1 || !startFlag) begin 
+                ssCnt <= 1'b0;
+            end
+        end
+    end
+    
+    
+    
+    
+    always @(negedge Clk_i) begin 
+        if (Rst_i) begin 
+            Ss <= 1'b1;
+        end
+        else begin 
+            if (ssCnt <= (ssNum+Lag_i+Lead_i)  && startFlag ) begin 
+                Ss <= 1'b0;
+            end
+            else begin 
+                Ss <= 1'b1;
+            end
+        end
+    end
+    
+    
+    always @(negedge Clk_i) begin 
+        if (Rst_i) begin 
+            mosiReg0 <= SpiData_i[31:0];
+        end
+        else begin
+            if (!EndianSel_i) begin 
+                if (!SSR && (ssCnt > Lag_i && ssCnt < ssNum + Lag_i + Lead_i)) begin
+                    mosiReg0 <= mosiReg0 << 1;
+                end
+                else begin 
+                    mosiReg0 <= SpiData_i[31:0];
+                end
+            end
+            else begin 
+                if (!SSR && (ssCnt > Lag_i && ssCnt < ssNum + Lag_i + Lead_i)) begin
+                    mosiReg0 <= mosiReg0 >> 1;
+                end
+                else begin 
+                    mosiReg0 <= SpiData_i[31:0];
+                end
+            end
+        end
+    end
+    
+    
+    
+    
+    
+    
+    
+    endmodule

src/src/Top/TopBochV3.v

@@ -0,0 +1,180 @@
+module TopBochv3 #(
+    parameter WORDWIDTH = 24,
+    parameter SSPIWORDWIDTH = 24,
+)
+
+input Clk_i,
+input Rst_i,
+
+input Sck_i,
+input Ss_i,
+input SsFlash_i,
+
+input Mosi0_i,
+input Mosi1_io,
+input Mosi2_i,
+input Mosi3_i,
+
+/* LMK_A */
+output LmkAMosi_o,
+output LmkACs_o,
+output LmkASck_o,
+input  LmkAMiso_i,
+/* LMK_B */
+output LmkBMosi_o,
+output LmkBCs_o,
+output LmkBSck_o,
+input  LmkBMiso_i,
+/*  CtrlCp2444v1  */
+output CtrlCp2444v1Mosi0_o,
+output CtrlCp2444v1Mosi1_o,
+output CtrlCp2444v1Mosi2_o,
+output CtrlCp2444v1Mosi3_o,
+output CtrlCp2444v1Cs_o,
+output CtrlCp2444v1CsFlash_o,
+output CtrlCp2444v1Sck_o,
+output CtrlCp2444v1Rst_o,
+input  CtrlCp2444v1Ld_i,
+/*  HUB-1854  */
+output TfeClk_o,
+output TfeMosi_o,
+output TfeCs_o,
+input  TfeMiso_i,
+//***********************************************
+//	                REG/WIRE
+//***********************************************
+wire [23:0] spiData;
+wire spiDataVal;
+
+/* PacketAnalyzer1Mosi Flags */
+wire flagDirectLmkA;
+wire flagDirectLmkB;
+wire flagDirectHubTfe;
+wire flagDirectFlash;
+/* PacketAnalyzer4Mosi Flags */
+wire valCtrlColdPartDataToFifo;
+wire valTfe2BytesDataToFifo;
+wire valTfe4BytesDataToFifo;
+wire valTfe7BytesDataToFifo;
+wire valTfe6BytesDataToFifo;
+/* ClkGen wires */
+wire clk60;
+wire clk25;
+/* InitRst */
+wire initRst;
+
+//***********************************************
+//	                CODING
+//***********************************************
+
+/* MUX SpiM devices */
+always @(*) begin 
+    if (flagDirectLmkA) begin   // LMK_A
+        LmkAMosi_o = Mosi0_i;
+        LmkACs_o = Ss_i;
+        LmkASck_o = Sck_i;
+    end
+    else begin 
+        LmkAMosi_o = 24'b0;
+        LmkACs_o = 1'b1;
+        LmkASck_o = 1'b0;
+    end
+    if (flagDirectLmkB) begin // LMK_B
+        LmkBMosi_o = Mosi0_i;
+        LmkBCs_o = Ss_i;
+        LmkBSck_o = Sck_i;
+    end
+    else begin 
+        LmkBMosi_o = 24'b0;
+        LmkBCs_o = 1'b1;
+        LmkBSck_o = 1'b0;
+    end
+    if (flagDirectHubTfe) begin // HUB-1854
+        TfeClk_o = Sck_i;
+        TfeMosi_o = Mosi0_i;
+        TfeCs_o = Ss_i;
+    end
+    else begin 
+        TfeClk_o = 1'b0;
+        TfeMosi_o = 24'b0;
+        TfeCs_o = 1'b1;
+    end
+    if (flagDirectFlash) begin // Flash
+        CtrlCp2444v1CsFlash_o = SsFlash_i;
+    end
+    else begin 
+        CtrlCp2444v1CsFlash_o = 1'b1;
+    end
+end
+
+ClkGen ClkGen
+(
+    .Clk60Mhz_o(clk60),
+    .Clk25Mhz_o(clk25)
+);
+
+InitRst InitRst
+(
+    .clk_i(clk25),
+    .signal_o(initRst)
+);
+
+InterfaceArbiter#
+(
+    .OUTWORDWIDTH(WORDWIDTH),
+    .SSPIWORDWIDTH(SSPIWORDWIDTH)
+)
+SpiSlaveArbiter
+(
+    .Rst_i(Rst_i),
+    .Clk_i(Clk_i),
+    .Sck_i(Sck_i),
+    .Ss_i(Ss_i),
+    .SsFlash_i(SsFlash_i),
+    .Mosi0_i(Mosi0_i),
+    .Mosi1_i(Mosi1_io),
+    .Mosi2_i(Mosi2_i),
+    .Mosi3_i(Mosi3_i),
+    .DataVal_o(spiDataVal),
+    .Data_o(spiData)
+);
+
+PacketAnalyzer1Mosi	PacketAnalyzer1Mosi
+(
+	.Clk_i					        (clk60),
+	.Rst_i					        (Rst_i),
+
+	.DataFromSpi_i			        (spiData),
+	.ValDataFromSpi_i		        (spiDataVal),
+
+	.BusyMosi4_i			        (busyMosi4),
+
+	.FlagDirectLmkA_o		        (flagDirectLmkA),
+    .FlagDirectLmkB_o		        (flagDirectLmkB),
+    .FlagDirectHubTfe_o		        (flagDirectHubTfe),
+    .FlagDirectFlash_o		        (flagDirectFlash),
+	
+	.Busy_o					        (busyMosi1)
+);
+
+PacketAnalyzer4Mosi PacketAnalyzer4Mosi
+(
+    .Clk_i					        (clk60),
+    .Rst_i					        (Rst_i),
+    
+    .DataFromSpi_i			        (spiData),
+    .ValDataFromSpi_i		        (spiDataVal),
+    
+    .BusyMosi1_i			        (busyMosi1),
+    
+    .ValCtrlColdPartDataToFifo_o	(valCtrlColdPartDataToFifo),
+    .ValTfe2BytesDataToFifo_o		(valTfe2BytesDataToFifo),
+    .ValTfe4BytesDataToFifo_o		(valTfe4BytesDataToFifo),
+    .ValTfe7BytesDataToFifo_o		(valTfe7BytesDataToFifo),
+    .ValTfe6BytesDataToFifo_o		(valTfe6BytesDataToFifo),
+    
+    .Busy_o					        (busyMosi4)
+);
+
+
+endmodule

src/src/Top/TopBochV3Tb.sv

@@ -0,0 +1,497 @@
+`timescale 1ns/1ns
+
+module TopBochV3Tb;
+
+
+//***********************************************
+//	            INPUTS
+//***********************************************
+    logic Clk_i;
+    logic Clk100;
+    logic Clk200;
+    logic Clk125;
+    logic Clk60;
+    logic Clk20;
+    logic Clk80;
+    logic Clk50;
+    logic Clk24;
+    logic Clk10; 
+    logic Rst_i;
+    logic Start_i;
+    logic CPHA_i;
+    logic [31:0] SPIdata;
+	logic SpiDataVal_i;
+    logic SELST_i;
+    logic [1:0] WidthSel_i;
+    logic LAG_i;
+    logic LEAD_i;
+    logic EndianSel_i;
+    logic [5:0] Stop_i;
+    logic PulsePol_i;
+    logic MisoLdLmx_i;
+
+//***********************************************
+//	            OUTPUTS
+//***********************************************
+    wire Mosi0_o;
+    wire Mosi1_o;
+    wire Mosi2_o;
+    wire Mosi3_o;
+    wire Sck_o;
+    wire Ss_o;
+    wire Val_o;
+    wire anyFlag;
+
+    wire valR;
+    wire valQ;
+    wire SckR;
+    wire SckQ;
+    wire SsR;
+    wire SsQ;
+    wire mosi0R;
+    wire mosi0Q;
+
+    wire locked;
+    wire rstInit;
+
+    logic mosi1Reg;
+
+    logic [16:0] trCnt;
+    logic [4:0] trCntSync;
+
+
+    logic modeSel; 
+    logic [23:0] randData;
+    logic [31:0] randData32;
+    logic [5:0] QSPITotalWordNum;
+    logic [5:0] QSpiBochv3TotalWordNum;
+    logic [5:0] QSpiCtrlCp2444v1TotalWordNum;
+    logic Stop;
+    logic [31:0] stopCnt;
+    logic rstForFPGA;
+
+//***********************************************
+//	            Lines From RF Top
+//***********************************************
+
+    logic [7:0] sckFromRFTop;
+    logic [7:0] mosiFromRFTop;
+    logic [7:0] ssFromRFTop;
+
+
+    logic [23:0] dataFromSPItb;
+    logic        valFromSPItb; 
+
+//***********************************************
+//	            CLASSES
+//***********************************************
+
+class Packet;
+    rand bit [23:0] data;
+    rand bit [31:0] data32;
+endclass
+
+Packet pkt;
+
+//***********************************************
+//	            FUNCTIONS
+//***********************************************
+task automatic Packet::randomize();
+    data = $urandom_range(0, 2**24-1);
+    data32 = $urandom_range(0, 2**32-1);
+endtask
+
+//***********************************************
+//	      HEADERS FOR DEVICES - SB_TMSG
+//***********************************************
+localparam [4:0]  DeviceIdLmx2594 = 5'h0;
+localparam [4:0]  DeviceIdDDS = 5'h1;
+localparam [4:0]  DeviceIdPot = 5'h2;
+localparam [4:0]  DeviceIdDac = 5'h3;
+localparam [4:0]  DeviceIdAtt = 5'h4;
+localparam [4:0]  DeviceIdShReg = 5'h5;
+localparam [4:0]  DeviceIdMax2870 = 5'h6;
+localparam [4:0]  DeviceIdGpio1 = 5'h7;
+localparam [4:0]  DeviceIdTemp = 5'h8;
+localparam [4:0]  DeviceIdGpio2 = 5'h9;
+
+localparam [16:0] Gpio1InitWordNum = 17'd1;
+localparam [16:0] Gpio2InitWordNum = 17'd1;
+localparam [16:0] PotWordInitNum = 17'd1;
+localparam [16:0] DacWordInitNum = 17'd1;
+localparam [16:0] AttWordInitNum = 17'd1;
+localparam [16:0] ShRegWordInitNum = 17'd1;
+localparam [16:0] Lmx2594InitWordNum = 17'd13;
+localparam [16:0] DDSInitWordNum = 17'd7;
+localparam [16:0] MaxInitWordNum = 17'd6;
+localparam [16:0] TempSensWordNum = 17'd1;
+
+localparam [23:0] InitGpio1Header       = {1'h0, DeviceIdGpio1, Gpio1InitWordNum, 1'h1};
+localparam [23:0] InitGpio2Header       = {1'b0, DeviceIdGpio2,Gpio2InitWordNum,1'h1 };
+localparam [23:0] TempSensHeader        = {1'h0, DeviceIdTemp, TempSensWordNum, 1'h1};
+localparam [23:0] InitLMX2594Header     = {1'h0, DeviceIdLmx2594, Lmx2594InitWordNum, 1'h1};
+localparam [23:0] InitDDSHeader         = {1'h0, DeviceIdDDS, DDSInitWordNum, 1'h1};
+localparam [23:0] InitMAX2870Header     = {1'h0, DeviceIdMax2870, MaxInitWordNum, 1'h1};
+localparam [23:0] InitPotHeader         = {1'h0, DeviceIdPot, PotWordInitNum, 1'h1};
+localparam [23:0] InitDacHeader         = {1'h0, DeviceIdDac, DacWordInitNum, 1'h1};
+localparam [23:0] InitAttHeader         = {1'h0, DeviceIdAtt, AttWordInitNum, 1'h1};
+localparam [23:0] InitShRegHeader       = {1'h0, DeviceIdShReg, ShRegWordInitNum, 1'h1};
+
+localparam [3:0]  LMXWordNum = 4'd14;
+localparam [2:0]  DDSWordNum = 3'd4;
+localparam        POTWordNum = 2'd2;
+localparam        DACWordNum = 1'd1;
+localparam        ATTWordNum = 1'd1;
+localparam [1:0]  ShRegWordNum = 2'd1;
+localparam [1:0]  MaxWordNum =   2'd2;
+localparam [1:0]  GPIOWordNum =  2'd1;
+
+//***********************************************
+//	           GPIO 1 REG 
+//***********************************************
+localparam [0:0] RF_SW1 = 1'h0;
+localparam [0:0] RF_SW2 = 1'h0;
+localparam [0:0] CTRL_AM_SW3 = 1'h0;
+localparam [0:0] DDS_SYNC_CTRL_FPGA = 1'h0;
+localparam [0:0] DDS_RESET_FPGA = 1'h0;
+localparam [0:0] DDS_SYNC_FPGA = 1'h0;
+localparam [0:0] SW_CAP4 = 1'h0;
+localparam [0:0] AM_ALC_SW = 1'h0;
+localparam [0:0] SW_CAP3 = 1'h0;
+localparam [0:0] SW_CAP2 = 1'h0;
+localparam [0:0] SW_CAP1 = 1'h0;
+localparam [0:0] AM_ALC_1_FIX = 1'h0;
+localparam [0:0] PLL_VTUNE_CTRL = 1'h0;
+localparam [0:0] PLL_SYNC_CTRL = 1'h0;
+localparam [0:0] PLL_SYNC = 1'h0;
+localparam [0:0] PLL_LOOP_CTRL = 1'h0;
+localparam [0:0] DDS_X2_FPGA = 1'h0;
+localparam [0:0] DDS_SAW2_FPGA = 1'h0;
+localparam [0:0] REF_OFFSET_CTRL_FPGA = 1'h0;
+localparam [0:0] GPIO_ADRF_V1 = 1'h0;
+localparam [0:0] GPIO_ADRF_V2 = 1'h0;
+localparam [0:0] DDS_SAW1_FPGA = 1'h0;
+
+localparam [23:0] GPIO_REG = {DDS_SAW1_FPGA,GPIO_ADRF_V2,GPIO_ADRF_V1,REF_OFFSET_CTRL_FPGA,DDS_SAW2_FPGA,DDS_X2_FPGA,PLL_LOOP_CTRL,PLL_SYNC,PLL_SYNC_CTRL,PLL_VTUNE_CTRL,AM_ALC_1_FIX,SW_CAP1,SW_CAP2,SW_CAP3,AM_ALC_SW,SW_CAP4,DDS_SYNC_FPGA,DDS_RESET_FPGA,DDS_SYNC_CTRL_FPGA,CTRL_AM_SW3,RF_SW2,RF_SW1};
+
+//***********************************************
+
+// localparam [23:0] AllDevQSPIHeader = {1'h1, LMXWordNum, DDSWordNum, POTWordNum, DACWordNum,ATTWordNum, ShRegWordNum,MaxWordNum, GPIOWordNum, 7'h1};
+localparam [23:0] AllDevQSPIHeader = {1'h1, 1'h0,DDSWordNum,1'h0,GPIOWordNum, LMXWordNum,1'h0,MaxWordNum,1'h0,ShRegWordNum,1'h0,POTWordNum,DACWordNum,ATTWordNum,1'h1};
+
+//***********************************************
+//	      HEADERS FOR DEVICES - BOCHv3
+//***********************************************
+/* Device ID's for 1 MOSI */
+localparam [4:0]  DeviceIdLmkA = 5'h0;
+localparam [4:0]  DeviceIdLmkB = 5'h1;
+localparam [4:0]  DeviceIdTfeHub = 5'h3;
+localparam [4:0]  DeviceIdFlash = 5'h4;
+/* Init Word Numbers */
+localparam [16:0] LmkAInitWordNum = 17'd129;
+localparam [16:0] LmkBInitWordNum = 17'd129;
+localparam [16:0] TfeHubInitWordNum = 17'd3;
+localparam [16:0] FlashInitWordNum = 17'd1;
+/* Headers */
+localparam [23:0] InitLmkAHeader = {1'h0, DeviceIdLmkA, LmkAInitWordNum, 1'h1};
+localparam [23:0] InitLmkBHeader = {1'h0, DeviceIdLmkB, LmkBInitWordNum, 1'h1};
+localparam [23:0] InitFlashHeader = {1'h0, DeviceIdFlash, FlashInitWordNum, 1'h1};
+/* Word Numbers 4-MOSI */
+localparam [3:0] CtrlColdPartWordNum = 4'd7;
+localparam [0:0]     Tfe2bWordNum = 1'd1;
+localparam [0:0]      Tfe4bWordNum= 2'd2;
+localparam [0:0]      Tfe7bWordNum= 2'd3;
+localparam [0:0]      Tfe6bWordNum= 2'd2;
+/* Headers 4-MOSI */
+localparam [23:0] CtrlColdPartHeader = {1'h1, 1'h0, CtrlColdPartWordNum, 1'h0, 2'h0, 2'h0, 2'h0, 10'h0, 1'h1};
+localparam [23:0] Tfe2bHeader = {1'h1, 1'h0, 4'h0, Tfe2bWordNum, 2'h0, 2'h0, 2'h0, 10'h0, 1'h1};
+localparam [23:0] Tfe4bHeader = {1'h1, 1'h0, 4'h0, 1'h0, Tfe4bWordNum, 2'h0, 2'h0, 10'h0, 1'h1};
+localparam [23:0] Tfe7bHeader = {1'h1, 1'h0, 4'h0, 1'h0, 1'h0, Tfe7bWordNum, 2'h0, 10'h0, 1'h1};
+localparam [23:0] Tfe6bHeader = {1'h1, 1'h0, 4'h0, 1'h0, 1'h0, 1'h0, Tfe6bWordNum, 10'h0, 1'h1};
+/* All Devices Header */
+localparam [23:0] AllDevBochv3QSpiHeader = {1'h1, 1'h0, CtrlColdPartWordNum, Tfe2bWordNum, Tfe4bWordNum, Tfe7bWordNum, Tfe6bWordNum, 10'h0, 1'h1};
+//***********************************************
+//	      HEADERS FOR DEVICES - CTRL_CP2444v1
+//***********************************************
+localparam [4:0] DeviceIdSwCtrlP1 = 5'h0;
+localparam [4:0] DeviceIdAttCtrlP1 = 5'h1;
+localparam [4:0] DeviceIdAttCtrlP2 = 5'h2;
+localparam [4:0] DeviceIdAttCtrlP3 = 5'h3;
+localparam [4:0] DeviceIdAttCtrlP4 = 5'h4;
+localparam [4:0] DeviceIdCtrlCp2444v1Gpio = 5'h5;
+/* Init Word Numbers */
+localparam [16:0] SwCtrlP1WordNum = 17'd1;
+localparam [16:0] AttCtrlP1WordNum = 17'd1;
+localparam [16:0] AttCtrlP2WordNum = 17'd1;
+localparam [16:0] AttCtrlP3WordNum = 17'd1;
+localparam [16:0] AttCtrlP4WordNum = 17'd1;
+localparam [16:0] CtrlCp2444v1GpioWordNum = 17'd1;
+/* Headers */
+localparam [23:0] SwCtrlP1Header = {1'h0, DeviceIdSwCtrlP1, SwCtrlP1WordNum, 1'h1};
+localparam [23:0] AttCtrlP1Header = {1'h0, DeviceIdAttCtrlP1, AttCtrlP1WordNum, 1'h1};
+localparam [23:0] AttCtrlP2Header = {1'h0, DeviceIdAttCtrlP2, AttCtrlP2WordNum, 1'h1};
+localparam [23:0] AttCtrlP3Header = {1'h0, DeviceIdAttCtrlP3, AttCtrlP3WordNum, 1'h1};
+localparam [23:0] AttCtrlP4Header = {1'h0, DeviceIdAttCtrlP4, AttCtrlP4WordNum, 1'h1};
+localparam [23:0] CtrlCp2444v1GpioHeader = {1'h0, DeviceIdCtrlCp2444v1Gpio, CtrlCp2444v1GpioWordNum, 1'h1};
+/* Word Numbers */
+localparam [3:0] SwCtrlP1WordNum = 1'd1;
+localparam [3:0] AttCtrlP1WordNum = 1'd1;
+localparam [3:0] AttCtrlP2WordNum = 1'd1;
+localparam [3:0] AttCtrlP3WordNum = 1'd1;
+localparam [3:0] AttCtrlP4WordNum = 1'd1;
+localparam [3:0] CtrlCp2444v1GpioWordNum = 1'd1;
+/* QSpi Headers */
+localparam [23:0] CtrlCp2444v1GpioHeader = {1'h1, CtrlCp2444v1GpioWordNum, 1'h0,1'h0,1'h0,1'h0,1'h0, 15'h0, 1'h1};
+localparam [23:0] SwCtrlP1Header = {1'h1, 1'h0, SwCtrlP1WordNum, 1'h0, 1'h0, 1'h0, 1'h0, 15'h0, 1'h1};
+localparam [23:0] AttCtrlP1Header = {1'h1, 1'h0, 1'h0, AttCtrlP1WordNum, 1'h0, 1'h0, 1'h0, 15'h0, 1'h1};
+localparam [23:0] AttCtrlP2Header = {1'h1, 1'h0, 1'h0, 1'h0, AttCtrlP2WordNum, 1'h0, 1'h0, 15'h0, 1'h1};
+localparam [23:0] AttCtrlP3Header = {1'h1, 1'h0, 1'h0, 1'h0, 1'h0, AttCtrlP3WordNum, 1'h0, 15'h0, 1'h1};
+localparam [23:0] AttCtrlP4Header = {1'h1, 1'h0, 1'h0, 1'h0, 1'h0, 1'h0, AttCtrlP4WordNum, 15'h0, 1'h1};
+localparam [23:0] AllDevCtrlCp2444v1QSpiHeader = {1'h1,CtrlCp2444v1GpioWordNum, SwCtrlP1WordNum, AttCtrlP1WordNum, AttCtrlP2WordNum, AttCtrlP3WordNum, AttCtrlP4WordNum, 15'h0, 1'h1};
+
+
+//***********************************************
+//	           ASSIGNS
+//***********************************************
+assign Val_o = (modeSel) ? valQ : valR;
+assign Sck_o = (modeSel) ? SckQ : SckR;
+assign Ss_o = (modeSel) ? SsQ : SsR;
+assign Mosi0_o = (modeSel) ? mosi0Q : mosi0R;
+assign Mosi1_io = (anyFlag) ? 1'bz : Mosi1_o;
+assign MisoLdLmx_i = 1'b1;
+
+assign emptyFlagTx = (trCnt > 260+QSpiBochv3TotalWordNum) ? 1'b1 : 1'b0;
+assign QSPITotalWordNum = LMXWordNum + DDSWordNum + POTWordNum + DACWordNum + ATTWordNum + ShRegWordNum + MaxWordNum + GPIOWordNum; 
+assign QSpiBochv3TotalWordNum = CtrlColdPartWordNum + Tfe2bWordNum + Tfe4bWordNum + Tfe7bWordNum + Tfe6bWordNum;
+assign QSpiCtrlCp2444v1TotalWordNum = CtrlCp2444v1GpioWordNum + SwCtrlP1WordNum + AttCtrlP1WordNum + AttCtrlP2WordNum + AttCtrlP3WordNum + AttCtrlP4WordNum;
+
+assign currClk = (modeSel) ? Clk60 : Clk10;
+
+//***********************************************
+//	           CLOCK GENERATION
+//***********************************************
+always #(CLK_PERIOD/2) Clk_i = ~Clk_i;
+always #(10/2) Clk100 = ~Clk100;
+always #(5/2) Clk200 = ~Clk200;
+always #(8/2) Clk125 = ~Clk125;
+always #(16.67/2) Clk60 = ~Clk60;
+always #(20/2) Clk50 = ~Clk50;
+always #(12.5/2) Clk80 = ~Clk80;
+always #(41.67/2) Clk24 = ~Clk24;
+always #(50/2) Clk20 = ~Clk20;
+always #(50)   Clk10 = ~Clk10; 
+
+//***********************************************
+//	           INITIALIZATION
+//***********************************************
+
+initial begin
+      // Initialize Inputs
+      Clk_i = 1;
+      Clk100= 1;
+      Clk200 = 1;
+      Clk125 = 1;
+      Clk60 = 1;
+      Clk20 = 1;
+      Clk50 = 1;
+      Clk80 = 1;
+      Clk24 = 1;
+      rstForFPGA = 0;
+      Clk10 = 1;
+      pkt = new();
+      Rst_i = 1;
+      Start_i = 0;
+      CPHA_i = 0;		SpiDataVal_i = 0;
+      SELST_i = 1;//0:High, 1:Low
+      WidthSel_i = 2; // 3-32bit, 2-24bit, 1-16bit, 0-8bit
+      LAG_i = 0;
+      LEAD_i = 0;
+      EndianSel_i = 0; // 0:MSB first, 1:lsb first
+      PulsePol_i = 0;
+      // Reset the system
+      #(CLK_PERIOD*10) Rst_i = 0;
+      #(700000-60) rstForFPGA = 1;
+      #(CLK_PERIOD*74) rstForFPGA = 0;
+      #(165000) Start_i = 1; // Start SPI transaction
+       wait (trCnt == 45) begin 
+            Start_i = 0;
+        end
+        #(CLK_PERIOD*100) 
+        Start_i = 1; // Start SPI transaction
+      wait (trCnt == 70) begin 
+            Start_i = 0;
+        end
+        #(CLK_PERIOD*1000) 
+        Start_i = 1; // Start SPI transaction
+  end
+//***********************************************
+always_ff @(posedge currClk) begin
+    if (Rst_i) begin 
+        trCnt <= 0;
+    end
+    else begin 
+        if (Val_o) begin 
+            trCnt <= trCnt + 1;
+        end
+    end
+end
+
+always_comb begin 
+    if (Rst_i) begin 
+        mosi1Reg = 0;
+    end
+    else begin 
+        mosi1Reg = Mosi1_io;
+    end
+end
+
+
+
+genvar i;
+// always_comb begin 
+//     if (Rst_i) begin 
+//         WidthSel_i = 2'd0;
+//     end
+//     else begin
+//         if (trCnt == 1 || trCnt == 3 ) begin 
+//             WidthSel_i = 2'd0;
+//         end 
+//         else if (trCnt > 36 && trCnt < 43) begin 
+//             WidthSel_i = 2'd3;
+//         end
+//         else begin 
+//             WidthSel_i = 2'd2;
+//         end
+//     end
+// end
+
+always_comb begin 
+    if (Rst_i) begin 
+        modeSel = 0;
+    end
+    else begin 
+        if (trCnt == 260) begin 
+            modeSel = 1;
+        end
+    end
+end
+
+always_comb begin 
+    if (Rst_i) begin 
+        Stop_i = 6'd0;
+    end
+    else begin 
+        if (trCnt == 158) begin 
+            Stop_i = 6'h0;
+        end
+        else begin
+            Stop_i = 6'd0;
+        end
+    end
+end
+
+always_ff @(posedge currClk) begin 
+    if (Rst_i) begin 
+        randData<=0;
+        randData32 <= 0;
+    end
+    else begin 
+        randData <= pkt.randomize(data);
+        randData32 <= pkt.randomize(data32);
+    end
+end
+
+/* Data generation for SPI */
+always_comb begin 
+    if (Rst_i) begin 
+        SPIdata = 0; 
+    end
+    else begin 
+        /* Firstly the header for LMK_A */
+        if (trCnt == 0) begin 
+            SPIdata = InitLmkAHeader;
+        end
+        /* Then the data for LMK_A */
+        else if (trCnt > 0 && trCnt < 130) begin 
+            SPIdata = randData;
+        end
+        /* Then the header for LMK_B */
+        else if (trCnt == 130) begin 
+            SPIdata = InitLmkBHeader;
+        end
+        /* Then the data for LMK_B */
+        else if (trCnt > 130 && trCnt < 260) begin 
+            SPIdata = randData;
+        end
+        /* Then the header for the Flash */
+        else if (trCnt == 260) begin 
+            SPIdata = InitFlashHeader;
+        end
+        /* Then the data for the Flash but the SsFlash should be active instead of Ss_o */
+        else if (trCnt > 260 && trCnt < 261) begin 
+            SPIdata = randData;
+        end
+        /* Then the header for QSpi header */
+        else if (trCnt == 262) begin 
+            SPIdata = AllDevBochv3QSpiHeader;
+        end
+        /* First word after is a header for CtrlCp2444v1 */
+        else if (trCnt == 263) begin 
+            SPIdata = AllDevCtrlCp2444v1QSpiHeader;
+        end
+        /* Then the data for QSpi */
+        else if (trCnt > 263 && trCnt < 260+QSpiBochv3TotalWordNum) begin
+            SPIdata = randData;
+        end
+    end
+end
+//***********************************************
+//	           DUT INSTANTIATION
+//***********************************************
+ExtSpiMEmul ExtSpiMEmul_inst (
+        .Clk_i(currClk), 
+        .Rst_i(Rst_i || modeSel), 
+        .Start_i(Start_i), 
+        .ClockPhase_i(CPHA_i),
+        .EmptyFlag_i(emptyFlagTx), 
+        .SpiData_i(SPIdata),
+        .SelSt_i(SELST_i),
+        .WidthSel_i(WidthSel_i),
+        .Lag_i(LAG_i),
+        .Lead_i(LEAD_i),
+        .EndianSel_i(EndianSel_i),
+        .Stop_i(6'h0),
+        .PulsePol_i(PulsePol_i),
+        .Mosi0_o(mosi0R),
+        .Sck_o(SckR),
+        .Ss_o(SsR),
+        .Val_o(valR)
+    );
+
+    ExtQspiMEmul ExtQspiMEmul_inst (
+        .Clk_i(currClk),
+        .Rst_i(Rst_i || !modeSel),
+        .Start_i(Start_i),
+        .ClockPhase_i(CPHA_i),
+        .EmptyFlag_i(emptyFlagTx),
+        .SpiData_i(SPIdata),
+        .SelSt_i(SELST_i),
+        .WidthSel_i(WidthSel_i),
+        .Lag_i(LAG_i),
+        .Lead_i(LEAD_i),
+        .EndianSel_i(EndianSel_i),
+        .Stop_i(6'h0),
+        .PulsePol_i(PulsePol_i),
+        .Mosi0_o(mosi0Q),
+        .Mosi1_o(Mosi1_o),
+        .Mosi2_o(Mosi2_o),
+        .Mosi3_o(Mosi3_o),
+        .Sck_o(SckQ),
+        .Ss_o(SsQ),
+        .Val_o(valQ)
+    );
+
+
+
+
+endmodule

src/src/WrapFifoChain/FifoCtrlCp2444/FifoCtrlCp2444.ipc

@@ -0,0 +1,25 @@
+[General]
+ipc_version=4
+file=FifoCtrlCp2444
+module=FifoCtrlCp2444
+target_device=gw1n9-022
+type=fifo_sc_hs
+version=1.0
+
+[Config]
+ALEMPTY=0
+ALFULL=0
+COUNT_W=false
+DEPTH_W=3
+ECC=false
+EN_ALEMPTY=false
+EN_ALFULL=false
+FWFT=true
+IMPL=0
+IO_INSERTION=false
+LANG=0
+OUTPUT_REG=false
+RDEN_CTRL=false
+STD=false
+Synthesis_tool=GowinSynthesis
+WIDTH_W=1

src/src/WrapFifoChain/FifoCtrlCp2444/FifoCtrlCp2444.v

@@ -0,0 +1,213 @@
+//
+//Written by GowinSynthesis
+//Tool Version "V1.9.9.03 (64-bit)"
+//Fri Nov 22 15:53:09 2024
+
+//Source file index table:
+//file0 "\C:/Gowin/Projects/BOCHv3_FPGA/src/src/WrapFifoChain/FifoCtrlCp2444/temp/FIFO_SC/fifo_sc_hs_define.v"
+//file1 "\C:/Gowin/Projects/BOCHv3_FPGA/src/src/WrapFifoChain/FifoCtrlCp2444/temp/FIFO_SC/fifo_sc_hs_parameter.v"
+//file2 "\C:/Gowin/Gowin_V1.9.9.03_x64/IDE/ipcore/FIFO_SC_HS/data/fifo_sc_hs.v"
+//file3 "\C:/Gowin/Gowin_V1.9.9.03_x64/IDE/ipcore/FIFO_SC_HS/data/fifo_sc_hs_top.v"
+`timescale 100 ps/100 ps
+`pragma protect begin_protected
+`pragma protect version="2.3"
+`pragma protect author="default"
+`pragma protect author_info="default"
+`pragma protect encrypt_agent="GOWIN"
+`pragma protect encrypt_agent_info="GOWIN Encrypt Version 2.3"
+
+`pragma protect encoding=(enctype="base64", line_length=76, bytes=256)
+`pragma protect key_keyowner="GOWIN",key_keyname="GWK2023-09",key_method="rsa"
+`pragma protect key_block
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+S+f1ibT0m4sboaD1lgHAky6FI2Ar144lC2gg0g==
+
+`pragma protect encoding=(enctype="base64", line_length=76, bytes=7872)
+`pragma protect data_keyowner="default-ip-vendor"
+`pragma protect data_keyname="default-ip-key"
+`pragma protect data_method="aes128-cfb"
+`pragma protect data_block
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+qo2t5tua
+`pragma protect end_protected
+module FifoCtrlCp2444 (
+  Data,
+  Clk,
+  WrEn,
+  RdEn,
+  Reset,
+  Q,
+  Empty,
+  Full
+)
+;
+input [0:0] Data;
+input Clk;
+input WrEn;
+input RdEn;
+input Reset;
+output [0:0] Q;
+output Empty;
+output Full;
+wire VCC;
+wire GND;
+  \~fifo_sc_hs.FifoCtrlCp2444  fifo_sc_hs_inst (
+    .Clk(Clk),
+    .Reset(Reset),
+    .WrEn(WrEn),
+    .RdEn(RdEn),
+    .Data(Data[0]),
+    .Empty(Empty),
+    .Full(Full),
+    .Q(Q[0])
+);
+  VCC VCC_cZ (
+    .V(VCC)
+);
+  GND GND_cZ (
+    .G(GND)
+);
+  GSR GSR (
+    .GSRI(VCC) 
+);
+endmodule /* FifoCtrlCp2444 */

src/src/WrapFifoChain/FifoCtrlCp2444/FifoCtrlCp2444.vo

@@ -0,0 +1,465 @@
+//Copyright (C)2014-2024 Gowin Semiconductor Corporation.
+//All rights reserved.
+//File Title: Post-PnR Simulation Model file
+//Tool Version: V1.9.9.03 (64-bit)
+//Created Time: Fri Nov 22 15:53:09 2024
+
+`timescale 100 ps/100 ps
+module FifoCtrlCp2444(
+	Data,
+	Clk,
+	WrEn,
+	RdEn,
+	Reset,
+	Q,
+	Empty,
+	Full
+);
+input [0:0] Data;
+input Clk;
+input WrEn;
+input RdEn;
+input Reset;
+output [0:0] Q;
+output Empty;
+output Full;
+wire Clk;
+wire [0:0] Data;
+wire Empty;
+wire Full;
+wire GND;
+wire [0:0] Q;
+wire RdEn;
+wire Reset;
+wire VCC;
+wire WrEn;
+wire \fifo_sc_hs_inst/n7_5 ;
+wire \fifo_sc_hs_inst/n13_4 ;
+wire \fifo_sc_hs_inst/n60_3 ;
+wire \fifo_sc_hs_inst/Wnum_4_8 ;
+wire \fifo_sc_hs_inst/n7_6 ;
+wire \fifo_sc_hs_inst/n60_4 ;
+wire \fifo_sc_hs_inst/rbin_next_2_10 ;
+wire \fifo_sc_hs_inst/n60_1_4 ;
+wire \fifo_sc_hs_inst/n110_2 ;
+wire \fifo_sc_hs_inst/n110_1_1 ;
+wire \fifo_sc_hs_inst/n109_2 ;
+wire \fifo_sc_hs_inst/n109_1_1 ;
+wire \fifo_sc_hs_inst/n108_2 ;
+wire \fifo_sc_hs_inst/n108_1_1 ;
+wire \fifo_sc_hs_inst/n107_2 ;
+wire \fifo_sc_hs_inst/n107_1_1 ;
+wire \fifo_sc_hs_inst/n106_2 ;
+wire \fifo_sc_hs_inst/n106_1_0_COUT ;
+wire \fifo_sc_hs_inst/wbin_next_0_2 ;
+wire \fifo_sc_hs_inst/wbin_next_1_2 ;
+wire \fifo_sc_hs_inst/wbin_next_2_2 ;
+wire \fifo_sc_hs_inst/wbin_next_3_2 ;
+wire \fifo_sc_hs_inst/wbin_next_4_0_COUT ;
+wire \fifo_sc_hs_inst/n123_1_SUM ;
+wire \fifo_sc_hs_inst/n123_3 ;
+wire \fifo_sc_hs_inst/n124_1_SUM ;
+wire \fifo_sc_hs_inst/n124_3 ;
+wire \fifo_sc_hs_inst/n125_1_SUM ;
+wire \fifo_sc_hs_inst/n125_3 ;
+wire \fifo_sc_hs_inst/n126_1_SUM ;
+wire \fifo_sc_hs_inst/n126_3 ;
+wire \fifo_sc_hs_inst/n127_1_SUM ;
+wire \fifo_sc_hs_inst/n127_3 ;
+wire \fifo_sc_hs_inst/rempty_val_5 ;
+wire [4:0] \fifo_sc_hs_inst/rbin_next ;
+wire [4:0] \fifo_sc_hs_inst/rbin ;
+wire [4:0] \fifo_sc_hs_inst/wbin ;
+wire [4:0] \fifo_sc_hs_inst/Wnum ;
+wire [4:0] \fifo_sc_hs_inst/wbin_next ;
+wire [31:1] \fifo_sc_hs_inst/DO ;
+VCC VCC_cZ (
+  .V(VCC)
+);
+GND GND_cZ (
+  .G(GND)
+);
+GSR GSR (
+	.GSRI(VCC)
+);
+LUT3 \fifo_sc_hs_inst/n7_s1  (
+	.I0(\fifo_sc_hs_inst/Wnum [0]),
+	.I1(\fifo_sc_hs_inst/n7_6 ),
+	.I2(WrEn),
+	.F(\fifo_sc_hs_inst/n7_5 )
+);
+defparam \fifo_sc_hs_inst/n7_s1 .INIT=8'hB0;
+LUT3 \fifo_sc_hs_inst/n13_s1  (
+	.I0(RdEn),
+	.I1(Empty),
+	.I2(\fifo_sc_hs_inst/n127_3 ),
+	.F(\fifo_sc_hs_inst/n13_4 )
+);
+defparam \fifo_sc_hs_inst/n13_s1 .INIT=8'hE0;
+LUT4 \fifo_sc_hs_inst/n60_s0  (
+	.I0(\fifo_sc_hs_inst/Wnum [0]),
+	.I1(\fifo_sc_hs_inst/n7_6 ),
+	.I2(\fifo_sc_hs_inst/n60_4 ),
+	.I3(WrEn),
+	.F(\fifo_sc_hs_inst/n60_3 )
+);
+defparam \fifo_sc_hs_inst/n60_s0 .INIT=16'h0B00;
+LUT2 \fifo_sc_hs_inst/Full_d_s  (
+	.I0(\fifo_sc_hs_inst/Wnum [0]),
+	.I1(\fifo_sc_hs_inst/n7_6 ),
+	.F(Full)
+);
+defparam \fifo_sc_hs_inst/Full_d_s .INIT=4'h4;
+LUT4 \fifo_sc_hs_inst/Wnum_4_s3  (
+	.I0(\fifo_sc_hs_inst/n7_6 ),
+	.I1(\fifo_sc_hs_inst/Wnum [0]),
+	.I2(WrEn),
+	.I3(\fifo_sc_hs_inst/n60_4 ),
+	.F(\fifo_sc_hs_inst/Wnum_4_8 )
+);
+defparam \fifo_sc_hs_inst/Wnum_4_s3 .INIT=16'h2FD0;
+LUT2 \fifo_sc_hs_inst/rbin_next_2_s5  (
+	.I0(\fifo_sc_hs_inst/rbin_next_2_10 ),
+	.I1(\fifo_sc_hs_inst/rbin [2]),
+	.F(\fifo_sc_hs_inst/rbin_next [2])
+);
+defparam \fifo_sc_hs_inst/rbin_next_2_s5 .INIT=4'h6;
+LUT3 \fifo_sc_hs_inst/rbin_next_3_s5  (
+	.I0(\fifo_sc_hs_inst/rbin_next_2_10 ),
+	.I1(\fifo_sc_hs_inst/rbin [2]),
+	.I2(\fifo_sc_hs_inst/rbin [3]),
+	.F(\fifo_sc_hs_inst/rbin_next [3])
+);
+defparam \fifo_sc_hs_inst/rbin_next_3_s5 .INIT=8'h78;
+LUT4 \fifo_sc_hs_inst/rbin_next_4_s2  (
+	.I0(\fifo_sc_hs_inst/rbin_next_2_10 ),
+	.I1(\fifo_sc_hs_inst/rbin [2]),
+	.I2(\fifo_sc_hs_inst/rbin [3]),
+	.I3(\fifo_sc_hs_inst/rbin [4]),
+	.F(\fifo_sc_hs_inst/rbin_next [4])
+);
+defparam \fifo_sc_hs_inst/rbin_next_4_s2 .INIT=16'h7F80;
+LUT4 \fifo_sc_hs_inst/n7_s2  (
+	.I0(\fifo_sc_hs_inst/Wnum [1]),
+	.I1(\fifo_sc_hs_inst/Wnum [2]),
+	.I2(\fifo_sc_hs_inst/Wnum [3]),
+	.I3(\fifo_sc_hs_inst/Wnum [4]),
+	.F(\fifo_sc_hs_inst/n7_6 )
+);
+defparam \fifo_sc_hs_inst/n7_s2 .INIT=16'h0100;
+LUT2 \fifo_sc_hs_inst/n60_s1  (
+	.I0(Empty),
+	.I1(RdEn),
+	.F(\fifo_sc_hs_inst/n60_4 )
+);
+defparam \fifo_sc_hs_inst/n60_s1 .INIT=4'h4;
+LUT4 \fifo_sc_hs_inst/rbin_next_2_s6  (
+	.I0(Empty),
+	.I1(RdEn),
+	.I2(\fifo_sc_hs_inst/rbin [0]),
+	.I3(\fifo_sc_hs_inst/rbin [1]),
+	.F(\fifo_sc_hs_inst/rbin_next_2_10 )
+);
+defparam \fifo_sc_hs_inst/rbin_next_2_s6 .INIT=16'h4000;
+LUT4 \fifo_sc_hs_inst/rbin_next_1_s6  (
+	.I0(Empty),
+	.I1(RdEn),
+	.I2(\fifo_sc_hs_inst/rbin [0]),
+	.I3(\fifo_sc_hs_inst/rbin [1]),
+	.F(\fifo_sc_hs_inst/rbin_next [1])
+);
+defparam \fifo_sc_hs_inst/rbin_next_1_s6 .INIT=16'hBF40;
+LUT3 \fifo_sc_hs_inst/rbin_next_0_s6  (
+	.I0(Empty),
+	.I1(RdEn),
+	.I2(\fifo_sc_hs_inst/rbin [0]),
+	.F(\fifo_sc_hs_inst/rbin_next [0])
+);
+defparam \fifo_sc_hs_inst/rbin_next_0_s6 .INIT=8'hB4;
+LUT4 \fifo_sc_hs_inst/n60_1_s1  (
+	.I0(\fifo_sc_hs_inst/Wnum [0]),
+	.I1(\fifo_sc_hs_inst/n7_6 ),
+	.I2(\fifo_sc_hs_inst/n60_4 ),
+	.I3(WrEn),
+	.F(\fifo_sc_hs_inst/n60_1_4 )
+);
+defparam \fifo_sc_hs_inst/n60_1_s1 .INIT=16'hF4FF;
+DFFC \fifo_sc_hs_inst/rbin_4_s0  (
+	.D(\fifo_sc_hs_inst/rbin_next [4]),
+	.CLK(Clk),
+	.CLEAR(Reset),
+	.Q(\fifo_sc_hs_inst/rbin [4])
+);
+defparam \fifo_sc_hs_inst/rbin_4_s0 .INIT=1'b0;
+DFFC \fifo_sc_hs_inst/rbin_3_s0  (
+	.D(\fifo_sc_hs_inst/rbin_next [3]),
+	.CLK(Clk),
+	.CLEAR(Reset),
+	.Q(\fifo_sc_hs_inst/rbin [3])
+);
+defparam \fifo_sc_hs_inst/rbin_3_s0 .INIT=1'b0;
+DFFC \fifo_sc_hs_inst/rbin_2_s0  (
+	.D(\fifo_sc_hs_inst/rbin_next [2]),
+	.CLK(Clk),
+	.CLEAR(Reset),
+	.Q(\fifo_sc_hs_inst/rbin [2])
+);
+defparam \fifo_sc_hs_inst/rbin_2_s0 .INIT=1'b0;
+DFFC \fifo_sc_hs_inst/rbin_1_s0  (
+	.D(\fifo_sc_hs_inst/rbin_next [1]),
+	.CLK(Clk),
+	.CLEAR(Reset),
+	.Q(\fifo_sc_hs_inst/rbin [1])
+);
+defparam \fifo_sc_hs_inst/rbin_1_s0 .INIT=1'b0;
+DFFC \fifo_sc_hs_inst/rbin_0_s0  (
+	.D(\fifo_sc_hs_inst/rbin_next [0]),
+	.CLK(Clk),
+	.CLEAR(Reset),
+	.Q(\fifo_sc_hs_inst/rbin [0])
+);
+defparam \fifo_sc_hs_inst/rbin_0_s0 .INIT=1'b0;
+DFFC \fifo_sc_hs_inst/wbin_4_s0  (
+	.D(\fifo_sc_hs_inst/wbin_next [4]),
+	.CLK(Clk),
+	.CLEAR(Reset),
+	.Q(\fifo_sc_hs_inst/wbin [4])
+);
+defparam \fifo_sc_hs_inst/wbin_4_s0 .INIT=1'b0;
+DFFC \fifo_sc_hs_inst/wbin_3_s0  (
+	.D(\fifo_sc_hs_inst/wbin_next [3]),
+	.CLK(Clk),
+	.CLEAR(Reset),
+	.Q(\fifo_sc_hs_inst/wbin [3])
+);
+defparam \fifo_sc_hs_inst/wbin_3_s0 .INIT=1'b0;
+DFFC \fifo_sc_hs_inst/wbin_2_s0  (
+	.D(\fifo_sc_hs_inst/wbin_next [2]),
+	.CLK(Clk),
+	.CLEAR(Reset),
+	.Q(\fifo_sc_hs_inst/wbin [2])
+);
+defparam \fifo_sc_hs_inst/wbin_2_s0 .INIT=1'b0;
+DFFC \fifo_sc_hs_inst/wbin_1_s0  (
+	.D(\fifo_sc_hs_inst/wbin_next [1]),
+	.CLK(Clk),
+	.CLEAR(Reset),
+	.Q(\fifo_sc_hs_inst/wbin [1])
+);
+defparam \fifo_sc_hs_inst/wbin_1_s0 .INIT=1'b0;
+DFFC \fifo_sc_hs_inst/wbin_0_s0  (
+	.D(\fifo_sc_hs_inst/wbin_next [0]),
+	.CLK(Clk),
+	.CLEAR(Reset),
+	.Q(\fifo_sc_hs_inst/wbin [0])
+);
+defparam \fifo_sc_hs_inst/wbin_0_s0 .INIT=1'b0;
+DFFP \fifo_sc_hs_inst/Empty_s0  (
+	.D(\fifo_sc_hs_inst/rempty_val_5 ),
+	.CLK(Clk),
+	.PRESET(Reset),
+	.Q(Empty)
+);
+defparam \fifo_sc_hs_inst/Empty_s0 .INIT=1'b1;
+DFFCE \fifo_sc_hs_inst/Wnum_4_s1  (
+	.D(\fifo_sc_hs_inst/n106_2 ),
+	.CLK(Clk),
+	.CE(\fifo_sc_hs_inst/Wnum_4_8 ),
+	.CLEAR(Reset),
+	.Q(\fifo_sc_hs_inst/Wnum [4])
+);
+defparam \fifo_sc_hs_inst/Wnum_4_s1 .INIT=1'b0;
+DFFCE \fifo_sc_hs_inst/Wnum_3_s1  (
+	.D(\fifo_sc_hs_inst/n107_2 ),
+	.CLK(Clk),
+	.CE(\fifo_sc_hs_inst/Wnum_4_8 ),
+	.CLEAR(Reset),
+	.Q(\fifo_sc_hs_inst/Wnum [3])
+);
+defparam \fifo_sc_hs_inst/Wnum_3_s1 .INIT=1'b0;
+DFFCE \fifo_sc_hs_inst/Wnum_2_s1  (
+	.D(\fifo_sc_hs_inst/n108_2 ),
+	.CLK(Clk),
+	.CE(\fifo_sc_hs_inst/Wnum_4_8 ),
+	.CLEAR(Reset),
+	.Q(\fifo_sc_hs_inst/Wnum [2])
+);
+defparam \fifo_sc_hs_inst/Wnum_2_s1 .INIT=1'b0;
+DFFCE \fifo_sc_hs_inst/Wnum_1_s1  (
+	.D(\fifo_sc_hs_inst/n109_2 ),
+	.CLK(Clk),
+	.CE(\fifo_sc_hs_inst/Wnum_4_8 ),
+	.CLEAR(Reset),
+	.Q(\fifo_sc_hs_inst/Wnum [1])
+);
+defparam \fifo_sc_hs_inst/Wnum_1_s1 .INIT=1'b0;
+DFFCE \fifo_sc_hs_inst/Wnum_0_s1  (
+	.D(\fifo_sc_hs_inst/n110_2 ),
+	.CLK(Clk),
+	.CE(\fifo_sc_hs_inst/Wnum_4_8 ),
+	.CLEAR(Reset),
+	.Q(\fifo_sc_hs_inst/Wnum [0])
+);
+defparam \fifo_sc_hs_inst/Wnum_0_s1 .INIT=1'b0;
+SDPB \fifo_sc_hs_inst/mem_mem_0_0_s  (
+	.CLKA(Clk),
+	.CEA(\fifo_sc_hs_inst/n7_5 ),
+	.RESETA(GND),
+	.CLKB(Clk),
+	.CEB(\fifo_sc_hs_inst/n13_4 ),
+	.RESETB(Reset),
+	.OCE(GND),
+	.BLKSELA({GND, GND, GND}),
+	.BLKSELB({GND, GND, GND}),
+	.DI({GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, Data[0]}),
+	.ADA({GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, \fifo_sc_hs_inst/wbin [3:0]}),
+	.ADB({GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, \fifo_sc_hs_inst/rbin_next [3:0]}),
+	.DO({\fifo_sc_hs_inst/DO [31:1], Q[0]})
+);
+defparam \fifo_sc_hs_inst/mem_mem_0_0_s .READ_MODE=1'b0;
+defparam \fifo_sc_hs_inst/mem_mem_0_0_s .BIT_WIDTH_0=1;
+defparam \fifo_sc_hs_inst/mem_mem_0_0_s .BIT_WIDTH_1=1;
+defparam \fifo_sc_hs_inst/mem_mem_0_0_s .RESET_MODE="ASYNC";
+defparam \fifo_sc_hs_inst/mem_mem_0_0_s .BLK_SEL_0=3'b000;
+defparam \fifo_sc_hs_inst/mem_mem_0_0_s .BLK_SEL_1=3'b000;
+ALU \fifo_sc_hs_inst/n110_1_s  (
+	.I0(\fifo_sc_hs_inst/Wnum [0]),
+	.I1(VCC),
+	.I3(\fifo_sc_hs_inst/n60_3 ),
+	.CIN(\fifo_sc_hs_inst/n60_1_4 ),
+	.COUT(\fifo_sc_hs_inst/n110_1_1 ),
+	.SUM(\fifo_sc_hs_inst/n110_2 )
+);
+defparam \fifo_sc_hs_inst/n110_1_s .ALU_MODE=2;
+ALU \fifo_sc_hs_inst/n109_1_s  (
+	.I0(\fifo_sc_hs_inst/Wnum [1]),
+	.I1(GND),
+	.I3(\fifo_sc_hs_inst/n60_3 ),
+	.CIN(\fifo_sc_hs_inst/n110_1_1 ),
+	.COUT(\fifo_sc_hs_inst/n109_1_1 ),
+	.SUM(\fifo_sc_hs_inst/n109_2 )
+);
+defparam \fifo_sc_hs_inst/n109_1_s .ALU_MODE=2;
+ALU \fifo_sc_hs_inst/n108_1_s  (
+	.I0(\fifo_sc_hs_inst/Wnum [2]),
+	.I1(GND),
+	.I3(\fifo_sc_hs_inst/n60_3 ),
+	.CIN(\fifo_sc_hs_inst/n109_1_1 ),
+	.COUT(\fifo_sc_hs_inst/n108_1_1 ),
+	.SUM(\fifo_sc_hs_inst/n108_2 )
+);
+defparam \fifo_sc_hs_inst/n108_1_s .ALU_MODE=2;
+ALU \fifo_sc_hs_inst/n107_1_s  (
+	.I0(\fifo_sc_hs_inst/Wnum [3]),
+	.I1(GND),
+	.I3(\fifo_sc_hs_inst/n60_3 ),
+	.CIN(\fifo_sc_hs_inst/n108_1_1 ),
+	.COUT(\fifo_sc_hs_inst/n107_1_1 ),
+	.SUM(\fifo_sc_hs_inst/n107_2 )
+);
+defparam \fifo_sc_hs_inst/n107_1_s .ALU_MODE=2;
+ALU \fifo_sc_hs_inst/n106_1_s  (
+	.I0(\fifo_sc_hs_inst/Wnum [4]),
+	.I1(GND),
+	.I3(\fifo_sc_hs_inst/n60_3 ),
+	.CIN(\fifo_sc_hs_inst/n107_1_1 ),
+	.COUT(\fifo_sc_hs_inst/n106_1_0_COUT ),
+	.SUM(\fifo_sc_hs_inst/n106_2 )
+);
+defparam \fifo_sc_hs_inst/n106_1_s .ALU_MODE=2;
+ALU \fifo_sc_hs_inst/wbin_next_0_s  (
+	.I0(\fifo_sc_hs_inst/wbin [0]),
+	.I1(\fifo_sc_hs_inst/n7_5 ),
+	.I3(GND),
+	.CIN(GND),
+	.COUT(\fifo_sc_hs_inst/wbin_next_0_2 ),
+	.SUM(\fifo_sc_hs_inst/wbin_next [0])
+);
+defparam \fifo_sc_hs_inst/wbin_next_0_s .ALU_MODE=0;
+ALU \fifo_sc_hs_inst/wbin_next_1_s  (
+	.I0(GND),
+	.I1(\fifo_sc_hs_inst/wbin [1]),
+	.I3(GND),
+	.CIN(\fifo_sc_hs_inst/wbin_next_0_2 ),
+	.COUT(\fifo_sc_hs_inst/wbin_next_1_2 ),
+	.SUM(\fifo_sc_hs_inst/wbin_next [1])
+);
+defparam \fifo_sc_hs_inst/wbin_next_1_s .ALU_MODE=0;
+ALU \fifo_sc_hs_inst/wbin_next_2_s  (
+	.I0(GND),
+	.I1(\fifo_sc_hs_inst/wbin [2]),
+	.I3(GND),
+	.CIN(\fifo_sc_hs_inst/wbin_next_1_2 ),
+	.COUT(\fifo_sc_hs_inst/wbin_next_2_2 ),
+	.SUM(\fifo_sc_hs_inst/wbin_next [2])
+);
+defparam \fifo_sc_hs_inst/wbin_next_2_s .ALU_MODE=0;
+ALU \fifo_sc_hs_inst/wbin_next_3_s  (
+	.I0(GND),
+	.I1(\fifo_sc_hs_inst/wbin [3]),
+	.I3(GND),
+	.CIN(\fifo_sc_hs_inst/wbin_next_2_2 ),
+	.COUT(\fifo_sc_hs_inst/wbin_next_3_2 ),
+	.SUM(\fifo_sc_hs_inst/wbin_next [3])
+);
+defparam \fifo_sc_hs_inst/wbin_next_3_s .ALU_MODE=0;
+ALU \fifo_sc_hs_inst/wbin_next_4_s  (
+	.I0(GND),
+	.I1(\fifo_sc_hs_inst/wbin [4]),
+	.I3(GND),
+	.CIN(\fifo_sc_hs_inst/wbin_next_3_2 ),
+	.COUT(\fifo_sc_hs_inst/wbin_next_4_0_COUT ),
+	.SUM(\fifo_sc_hs_inst/wbin_next [4])
+);
+defparam \fifo_sc_hs_inst/wbin_next_4_s .ALU_MODE=0;
+ALU \fifo_sc_hs_inst/n123_s0  (
+	.I0(\fifo_sc_hs_inst/rbin_next [0]),
+	.I1(\fifo_sc_hs_inst/wbin [0]),
+	.I3(GND),
+	.CIN(GND),
+	.COUT(\fifo_sc_hs_inst/n123_3 ),
+	.SUM(\fifo_sc_hs_inst/n123_1_SUM )
+);
+defparam \fifo_sc_hs_inst/n123_s0 .ALU_MODE=3;
+ALU \fifo_sc_hs_inst/n124_s0  (
+	.I0(\fifo_sc_hs_inst/rbin_next [1]),
+	.I1(\fifo_sc_hs_inst/wbin [1]),
+	.I3(GND),
+	.CIN(\fifo_sc_hs_inst/n123_3 ),
+	.COUT(\fifo_sc_hs_inst/n124_3 ),
+	.SUM(\fifo_sc_hs_inst/n124_1_SUM )
+);
+defparam \fifo_sc_hs_inst/n124_s0 .ALU_MODE=3;
+ALU \fifo_sc_hs_inst/n125_s0  (
+	.I0(\fifo_sc_hs_inst/rbin_next [2]),
+	.I1(\fifo_sc_hs_inst/wbin [2]),
+	.I3(GND),
+	.CIN(\fifo_sc_hs_inst/n124_3 ),
+	.COUT(\fifo_sc_hs_inst/n125_3 ),
+	.SUM(\fifo_sc_hs_inst/n125_1_SUM )
+);
+defparam \fifo_sc_hs_inst/n125_s0 .ALU_MODE=3;
+ALU \fifo_sc_hs_inst/n126_s0  (
+	.I0(\fifo_sc_hs_inst/rbin_next [3]),
+	.I1(\fifo_sc_hs_inst/wbin [3]),
+	.I3(GND),
+	.CIN(\fifo_sc_hs_inst/n125_3 ),
+	.COUT(\fifo_sc_hs_inst/n126_3 ),
+	.SUM(\fifo_sc_hs_inst/n126_1_SUM )
+);
+defparam \fifo_sc_hs_inst/n126_s0 .ALU_MODE=3;
+ALU \fifo_sc_hs_inst/n127_s0  (
+	.I0(\fifo_sc_hs_inst/rbin_next [4]),
+	.I1(\fifo_sc_hs_inst/wbin [4]),
+	.I3(GND),
+	.CIN(\fifo_sc_hs_inst/n126_3 ),
+	.COUT(\fifo_sc_hs_inst/n127_3 ),
+	.SUM(\fifo_sc_hs_inst/n127_1_SUM )
+);
+defparam \fifo_sc_hs_inst/n127_s0 .ALU_MODE=3;
+LUT1 \fifo_sc_hs_inst/rempty_val_s1  (
+	.I0(\fifo_sc_hs_inst/n127_3 ),
+	.F(\fifo_sc_hs_inst/rempty_val_5 )
+);
+defparam \fifo_sc_hs_inst/rempty_val_s1 .INIT=2'h1;
+endmodule

src/src/WrapFifoChain/FifoCtrlCp2444/FifoCtrlCp2444_tmp.v

@@ -0,0 +1,23 @@
+//Copyright (C)2014-2024 Gowin Semiconductor Corporation.
+//All rights reserved.
+//File Title: Template file for instantiation
+//Tool Version: V1.9.9.03 (64-bit)
+//Part Number: GW1N-UV9QN88C6/I5
+//Device: GW1N-9
+//Created Time: Fri Nov 22 15:53:09 2024
+
+//Change the instance name and port connections to the signal names
+//--------Copy here to design--------
+
+	FifoCtrlCp2444 your_instance_name(
+		.Data(Data), //input [0:0] Data
+		.Clk(Clk), //input Clk
+		.WrEn(WrEn), //input WrEn
+		.RdEn(RdEn), //input RdEn
+		.Reset(Reset), //input Reset
+		.Q(Q), //output [0:0] Q
+		.Empty(Empty), //output Empty
+		.Full(Full) //output Full
+	);
+
+//--------Copy end-------------------

src/src/WrapFifoChain/FifoCtrlCp2444/temp/FIFO_SC/FIFO_SC.prj

@@ -0,0 +1,20 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!DOCTYPE gowin-synthesis-project>
+<Project>
+    <Version>beta</Version>
+    <Device id="GW1N-9" package="QFN88" speed="6" partNumber="GW1N-UV9QN88C6/I5"/>
+    <FileList>
+        <File path="C:/Gowin/Projects/BOCHv3_FPGA/src/src/WrapFifoChain/FifoCtrlCp2444/temp/FIFO_SC/fifo_sc_hs_define.v" type="verilog"/>
+        <File path="C:/Gowin/Projects/BOCHv3_FPGA/src/src/WrapFifoChain/FifoCtrlCp2444/temp/FIFO_SC/fifo_sc_hs_parameter.v" type="verilog"/>
+        <File path="C:/Gowin/Gowin_V1.9.9.03_x64/IDE/ipcore/FIFO_SC_HS/data/fifo_sc_hs.v" type="verilog"/>
+        <File path="C:/Gowin/Gowin_V1.9.9.03_x64/IDE/ipcore/FIFO_SC_HS/data/fifo_sc_hs_top.v" type="verilog"/>
+    </FileList>
+    <OptionList>
+        <Option type="disable_insert_pad" value="1"/>
+        <Option type="output_file" value="FifoCtrlCp2444.vg"/>
+        <Option type="output_template" value="FifoCtrlCp2444_tmp.v"/>
+        <Option type="ram_balance" value="1"/>
+        <Option type="ram_rw_check" value="1"/>
+        <Option type="verilog_language" value="sysv-2017"/>
+    </OptionList>
+</Project>

src/src/WrapFifoChain/FifoCtrlCp2444/temp/FIFO_SC/FifoCtrlCp2444.log

@@ -0,0 +1,42 @@
+GowinSynthesis start
+Running parser ...
+Analyzing Verilog file 'C:\Gowin\Projects\BOCHv3_FPGA\src\src\WrapFifoChain\FifoCtrlCp2444\temp\FIFO_SC\fifo_sc_hs_define.v'
+Analyzing Verilog file 'C:\Gowin\Projects\BOCHv3_FPGA\src\src\WrapFifoChain\FifoCtrlCp2444\temp\FIFO_SC\fifo_sc_hs_parameter.v'
+Analyzing Verilog file 'C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_SC_HS\data\fifo_sc_hs.v'
+Analyzing included file '**'("C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_SC_HS\data\fifo_sc_hs.v":14570)
+Back to file '**'("C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_SC_HS\data\fifo_sc_hs.v":14570)
+Analyzing Verilog file 'C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_SC_HS\data\fifo_sc_hs_top.v'
+Analyzing included file 'fifo_sc_hs_define.v'("C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_SC_HS\data\fifo_sc_hs_top.v":1)
+Back to file 'C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_SC_HS\data\fifo_sc_hs_top.v'("C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_SC_HS\data\fifo_sc_hs_top.v":1)
+Analyzing included file 'C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_SC_HS\data\static_macro_define.v'("C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_SC_HS\data\fifo_sc_hs_top.v":2)
+Back to file 'C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_SC_HS\data\fifo_sc_hs_top.v'("C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_SC_HS\data\fifo_sc_hs_top.v":2)
+Analyzing included file 'fifo_sc_hs_parameter.v'("C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_SC_HS\data\fifo_sc_hs_top.v":47)
+Back to file 'C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_SC_HS\data\fifo_sc_hs_top.v'("C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_SC_HS\data\fifo_sc_hs_top.v":47)
+WARN  (EX2582) : Parameter 'DEPTH' declared inside compilation unit '$unit_fifo_sc_hs_define_v' shall be treated as localparam("fifo_sc_hs_parameter.v":1)
+WARN  (EX2582) : Parameter 'DSIZE' declared inside compilation unit '$unit_fifo_sc_hs_define_v' shall be treated as localparam("fifo_sc_hs_parameter.v":2)
+WARN  (EX2582) : Parameter 'ASIZE' declared inside compilation unit '$unit_fifo_sc_hs_define_v' shall be treated as localparam("fifo_sc_hs_parameter.v":3)
+Compiling module 'FifoCtrlCp2444'("C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_SC_HS\data\fifo_sc_hs_top.v":4)
+Compiling module '**'("C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_SC_HS\data\fifo_sc_hs.v":14570)
+Extracting RAM for identifier '**'("C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_SC_HS\data\fifo_sc_hs.v":14570)
+WARN  (EX3791) : Expression size ** truncated to fit in target size **("C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_SC_HS\data\fifo_sc_hs.v":14570)
+NOTE  (EX0101) : Current top module is "FifoCtrlCp2444"
+[5%] Running netlist conversion ...
+Running device independent optimization ...
+[10%] Optimizing Phase 0 completed
+[15%] Optimizing Phase 1 completed
+[25%] Optimizing Phase 2 completed
+Running inference ...
+[30%] Inferring Phase 0 completed
+[40%] Inferring Phase 1 completed
+[50%] Inferring Phase 2 completed
+[55%] Inferring Phase 3 completed
+Running technical mapping ...
+[60%] Tech-Mapping Phase 0 completed
+[65%] Tech-Mapping Phase 1 completed
+[75%] Tech-Mapping Phase 2 completed
+[80%] Tech-Mapping Phase 3 completed
+[90%] Tech-Mapping Phase 4 completed
+[95%] Generate netlist file "C:\Gowin\Projects\BOCHv3_FPGA\src\src\WrapFifoChain\FifoCtrlCp2444\temp\FIFO_SC\FifoCtrlCp2444.vg" completed
+Generate template file "C:\Gowin\Projects\BOCHv3_FPGA\src\src\WrapFifoChain\FifoCtrlCp2444\temp\FIFO_SC\FifoCtrlCp2444_tmp.v" completed
+[100%] Generate report file "C:\Gowin\Projects\BOCHv3_FPGA\src\src\WrapFifoChain\FifoCtrlCp2444\temp\FIFO_SC\FifoCtrlCp2444_syn.rpt.html" completed
+GowinSynthesis finish

src/src/WrapFifoChain/FifoCtrlCp2444/temp/FIFO_SC/FifoCtrlCp2444.vg

@@ -0,0 +1,213 @@
+//
+//Written by GowinSynthesis
+//Tool Version "V1.9.9.03 (64-bit)"
+//Fri Nov 22 15:53:09 2024
+
+//Source file index table:
+//file0 "\C:/Gowin/Projects/BOCHv3_FPGA/src/src/WrapFifoChain/FifoCtrlCp2444/temp/FIFO_SC/fifo_sc_hs_define.v"
+//file1 "\C:/Gowin/Projects/BOCHv3_FPGA/src/src/WrapFifoChain/FifoCtrlCp2444/temp/FIFO_SC/fifo_sc_hs_parameter.v"
+//file2 "\C:/Gowin/Gowin_V1.9.9.03_x64/IDE/ipcore/FIFO_SC_HS/data/fifo_sc_hs.v"
+//file3 "\C:/Gowin/Gowin_V1.9.9.03_x64/IDE/ipcore/FIFO_SC_HS/data/fifo_sc_hs_top.v"
+`timescale 100 ps/100 ps
+`pragma protect begin_protected
+`pragma protect version="2.3"
+`pragma protect author="default"
+`pragma protect author_info="default"
+`pragma protect encrypt_agent="GOWIN"
+`pragma protect encrypt_agent_info="GOWIN Encrypt Version 2.3"
+
+`pragma protect encoding=(enctype="base64", line_length=76, bytes=256)
+`pragma protect key_keyowner="GOWIN",key_keyname="GWK2023-09",key_method="rsa"
+`pragma protect key_block
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+S+f1ibT0m4sboaD1lgHAky6FI2Ar144lC2gg0g==
+
+`pragma protect encoding=(enctype="base64", line_length=76, bytes=7872)
+`pragma protect data_keyowner="default-ip-vendor"
+`pragma protect data_keyname="default-ip-key"
+`pragma protect data_method="aes128-cfb"
+`pragma protect data_block
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+qo2t5tua
+`pragma protect end_protected
+module FifoCtrlCp2444 (
+  Data,
+  Clk,
+  WrEn,
+  RdEn,
+  Reset,
+  Q,
+  Empty,
+  Full
+)
+;
+input [0:0] Data;
+input Clk;
+input WrEn;
+input RdEn;
+input Reset;
+output [0:0] Q;
+output Empty;
+output Full;
+wire VCC;
+wire GND;
+  \~fifo_sc_hs.FifoCtrlCp2444  fifo_sc_hs_inst (
+    .Clk(Clk),
+    .Reset(Reset),
+    .WrEn(WrEn),
+    .RdEn(RdEn),
+    .Data(Data[0]),
+    .Empty(Empty),
+    .Full(Full),
+    .Q(Q[0])
+);
+  VCC VCC_cZ (
+    .V(VCC)
+);
+  GND GND_cZ (
+    .G(GND)
+);
+  GSR GSR (
+    .GSRI(VCC) 
+);
+endmodule /* FifoCtrlCp2444 */

src/src/WrapFifoChain/FifoCtrlCp2444/temp/FIFO_SC/FifoCtrlCp2444_syn_resource.html

@@ -0,0 +1,46 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html>
+<head>
+<title>Hierarchy Module Resource</title>
+<style type="text/css">
+body { font-family: Verdana, Arial, sans-serif; font-size: 14px; }
+div#main_wrapper{ width: 100%; }
+h1 {text-align: center; }
+h1 {margin-top: 36px; }
+table, th, td { border: 1px solid #aaa; }
+table { border-collapse:collapse; margin-top: 10px; margin-bottom: 20px; width: 100%; }
+th, td { align = "center"; padding: 5px 2px 5px 5px; }
+th { color: #fff; font-weight: bold; background-color: #0084ff; }
+table td.label { width: 20%; white-space: nowrap; min-width: 20px; background-color: #dee8f4; }
+</style>
+</head>
+<body>
+<div id="main_wrapper">
+<div id="content">
+<h1>Hierarchy Module Resource</h1>
+<table>
+<tr>
+<th class="label">MODULE NAME</th>
+<th class="label">REG NUMBER</th>
+<th class="label">ALU NUMBER</th>
+<th class="label">LUT NUMBER</th>
+<th class="label">DSP NUMBER</th>
+<th class="label">BSRAM NUMBER</th>
+<th class="label">SSRAM NUMBER</th>
+<th class="label">ROM16 NUMBER</th>
+</tr>
+<tr>
+<td class="label">FifoCtrlCp2444 (C:/Gowin/Gowin_V1.9.9.03_x64/IDE/ipcore/FIFO_SC_HS/data/fifo_sc_hs_top.v)</td>
+<td align = "center">16</td>
+<td align = "center">15</td>
+<td align = "center">15</td>
+<td align = "center">-</td>
+<td align = "center">1</td>
+<td align = "center">-</td>
+<td align = "center">-</td>
+</tr>
+</table>
+</div><!-- content -->
+</div><!-- main_wrapper -->
+</body>
+</html>

src/src/WrapFifoChain/FifoCtrlCp2444/temp/FIFO_SC/FifoCtrlCp2444_syn_rsc.xml

@@ -0,0 +1,2 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<Module name="FifoCtrlCp2444" Register="16" Alu="15" Lut="15" Bsram="1" T_Register="16(16)" T_Alu="15(15)" T_Lut="15(15)" T_Bsram="1(1)"/>

src/src/WrapFifoChain/FifoCtrlCp2444/temp/FIFO_SC/FifoCtrlCp2444_tmp.v

@@ -0,0 +1,23 @@
+//Copyright (C)2014-2024 Gowin Semiconductor Corporation.
+//All rights reserved.
+//File Title: Template file for instantiation
+//Tool Version: V1.9.9.03 (64-bit)
+//Part Number: GW1N-UV9QN88C6/I5
+//Device: GW1N-9
+//Created Time: Fri Nov 22 15:53:09 2024
+
+//Change the instance name and port connections to the signal names
+//--------Copy here to design--------
+
+	FifoCtrlCp2444 your_instance_name(
+		.Data(Data), //input [0:0] Data
+		.Clk(Clk), //input Clk
+		.WrEn(WrEn), //input WrEn
+		.RdEn(RdEn), //input RdEn
+		.Reset(Reset), //input Reset
+		.Q(Q), //output [0:0] Q
+		.Empty(Empty), //output Empty
+		.Full(Full) //output Full
+	);
+
+//--------Copy end-------------------

src/src/WrapFifoChain/FifoCtrlCp2444/temp/FIFO_SC/fifo_sc_hs_define.v

@@ -0,0 +1,4 @@
+`define module_name FifoCtrlCp2444
+`define getname(oriName,tmodule_name) \~oriName.tmodule_name 
+`define EBR_BASED
+`define FWFT

src/src/WrapFifoChain/FifoCtrlCp2444/temp/FIFO_SC/fifo_sc_hs_parameter.v

@@ -0,0 +1,3 @@
+parameter DEPTH = 16;
+parameter DSIZE = 1;
+parameter ASIZE = 4;

src/src/WrapFifoChain/FifoCtrlCp2444/temp/FIFO_SC/project.ini

@@ -0,0 +1 @@
+RESOURCE_CHECK=false

src/src/WrapFifoChain/FifoTfe2Bytes/FifoTfe2Bytes.ipc

@@ -0,0 +1,35 @@
+[General]
+ipc_version=4
+file=FifoTfe2Bytes
+module=FifoTfe2Bytes
+target_device=gw1n9-022
+type=fifo_hs
+version=1.0
+
+[Config]
+AlmostEmptyFlag=false
+AlmostEmptyFlagItem=Empty_Single Threshold Constant Parameter
+AlmostFullFlag=false
+AlmostFullFlagItem=Full_Single Threshold Constant Parameter
+BSRAM=true
+ControlledByRdEn=false
+ECCSelected=false
+EmptyClear=1
+EmptySet=1
+EnReset=true
+FirstWordFallThrough=true
+FullClear=1
+FullSet=1
+LANG=0
+OutputRegistersSelected=false
+REG=false
+ReadDataNum=false
+ReadDataWidth=24
+ReadDepth=2
+ResetSynchronization=true
+SSRAM=false
+StandardFIFO=false
+Synthesis_tool=GowinSynthesis
+WriteDataNum=false
+WriteDataWidth=24
+WriteDepth=2

src/src/WrapFifoChain/FifoTfe2Bytes/FifoTfe2Bytes.v

@@ -0,0 +1,187 @@
+//
+//Written by GowinSynthesis
+//Tool Version "V1.9.9.03 (64-bit)"
+//Fri Nov 22 16:03:28 2024
+
+//Source file index table:
+//file0 "\C:/Gowin/Gowin_V1.9.9.03_x64/IDE/ipcore/FIFO_HS/data/fifo_hs.v"
+//file1 "\C:/Gowin/Gowin_V1.9.9.03_x64/IDE/ipcore/FIFO_HS/data/fifo_hs_top.v"
+`timescale 100 ps/100 ps
+`pragma protect begin_protected
+`pragma protect version="2.3"
+`pragma protect author="default"
+`pragma protect author_info="default"
+`pragma protect encrypt_agent="GOWIN"
+`pragma protect encrypt_agent_info="GOWIN Encrypt Version 2.3"
+
+`pragma protect encoding=(enctype="base64", line_length=76, bytes=256)
+`pragma protect key_keyowner="GOWIN",key_keyname="GWK2023-09",key_method="rsa"
+`pragma protect key_block
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+
+`pragma protect encoding=(enctype="base64", line_length=76, bytes=6352)
+`pragma protect data_keyowner="default-ip-vendor"
+`pragma protect data_keyname="default-ip-key"
+`pragma protect data_method="aes128-cfb"
+`pragma protect data_block
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+kfCP2hpOQXKYEiUbsebH95bKxEdsFVOlRA==
+`pragma protect end_protected
+module FifoTfe2Bytes (
+  Data,
+  Reset,
+  WrClk,
+  RdClk,
+  WrEn,
+  RdEn,
+  Q,
+  Empty,
+  Full
+)
+;
+input [23:0] Data;
+input Reset;
+input WrClk;
+input RdClk;
+input WrEn;
+input RdEn;
+output [23:0] Q;
+output Empty;
+output Full;
+wire VCC;
+wire GND;
+  \~fifo.FifoTfe2Bytes  fifo_inst (
+    .Reset(Reset),
+    .RdClk(RdClk),
+    .WrClk(WrClk),
+    .WrEn(WrEn),
+    .RdEn(RdEn),
+    .Data(Data[23:0]),
+    .Empty(Empty),
+    .Full(Full),
+    .Q(Q[23:0])
+);
+  VCC VCC_cZ (
+    .V(VCC)
+);
+  GND GND_cZ (
+    .G(GND)
+);
+  GSR GSR (
+    .GSRI(VCC) 
+);
+endmodule /* FifoTfe2Bytes */

src/src/WrapFifoChain/FifoTfe2Bytes/FifoTfe2Bytes.vo

@@ -0,0 +1,353 @@
+//Copyright (C)2014-2024 Gowin Semiconductor Corporation.
+//All rights reserved.
+//File Title: Post-PnR Simulation Model file
+//Tool Version: V1.9.9.03 (64-bit)
+//Created Time: Fri Nov 22 16:03:28 2024
+
+`timescale 100 ps/100 ps
+module FifoTfe2Bytes(
+	Data,
+	Reset,
+	WrClk,
+	RdClk,
+	WrEn,
+	RdEn,
+	Q,
+	Empty,
+	Full
+);
+input [23:0] Data;
+input Reset;
+input WrClk;
+input RdClk;
+input WrEn;
+input RdEn;
+output [23:0] Q;
+output Empty;
+output Full;
+wire [23:0] Data;
+wire Empty;
+wire Full;
+wire GND;
+wire [23:0] Q;
+wire RdClk;
+wire RdEn;
+wire Reset;
+wire VCC;
+wire WrClk;
+wire WrEn;
+wire \fifo_inst/n20_5 ;
+wire \fifo_inst/n26_4 ;
+wire \fifo_inst/n257_4 ;
+wire \fifo_inst/rempty_val ;
+wire \fifo_inst/wfull_val_7 ;
+wire \fifo_inst/wfull_val1 ;
+wire \fifo_inst/wfull_val1_0 ;
+wire \fifo_inst/Full_1 ;
+wire \fifo_inst/Equal.wbinnext_0_7 ;
+wire \fifo_inst/rempty_val_8 ;
+wire \fifo_inst/wfull_val1_2 ;
+wire \fifo_inst/wfull_val1_3 ;
+wire \fifo_inst/Full_1_2 ;
+wire \fifo_inst/Full_2 ;
+wire \fifo_inst/n4_6 ;
+wire \fifo_inst/n9_6 ;
+wire [0:0] \fifo_inst/Equal.rgraynext ;
+wire [0:0] \fifo_inst/Equal.wgraynext ;
+wire [1:0] \fifo_inst/rbin_num_next ;
+wire [1:1] \fifo_inst/Equal.wbinnext ;
+wire [1:0] \fifo_inst/reset_r ;
+wire [1:0] \fifo_inst/reset_w ;
+wire [1:0] \fifo_inst/rbin_num ;
+wire [1:0] \fifo_inst/Equal.rq1_wptr ;
+wire [1:0] \fifo_inst/Equal.rq2_wptr ;
+wire [0:0] \fifo_inst/rptr ;
+wire [1:0] \fifo_inst/wptr ;
+wire [0:0] \fifo_inst/Equal.wbin ;
+wire [31:24] \fifo_inst/DO ;
+VCC VCC_cZ (
+  .V(VCC)
+);
+GND GND_cZ (
+  .G(GND)
+);
+GSR GSR (
+	.GSRI(VCC)
+);
+LUT4 \fifo_inst/n20_s1  (
+	.I0(\fifo_inst/Full_2 ),
+	.I1(\fifo_inst/Full_1_2 ),
+	.I2(\fifo_inst/Full_1 ),
+	.I3(WrEn),
+	.F(\fifo_inst/n20_5 )
+);
+defparam \fifo_inst/n20_s1 .INIT=16'h5300;
+LUT3 \fifo_inst/n26_s1  (
+	.I0(RdEn),
+	.I1(Empty),
+	.I2(\fifo_inst/rempty_val ),
+	.F(\fifo_inst/n26_4 )
+);
+defparam \fifo_inst/n26_s1 .INIT=8'h0E;
+LUT3 \fifo_inst/Equal.rgraynext_0_s0  (
+	.I0(\fifo_inst/rbin_num [0]),
+	.I1(\fifo_inst/rbin_num_next [0]),
+	.I2(\fifo_inst/rbin_num [1]),
+	.F(\fifo_inst/Equal.rgraynext [0])
+);
+defparam \fifo_inst/Equal.rgraynext_0_s0 .INIT=8'h1E;
+LUT3 \fifo_inst/Equal.wgraynext_0_s0  (
+	.I0(\fifo_inst/Equal.wbin [0]),
+	.I1(\fifo_inst/n20_5 ),
+	.I2(\fifo_inst/wptr [1]),
+	.F(\fifo_inst/Equal.wgraynext [0])
+);
+defparam \fifo_inst/Equal.wgraynext_0_s0 .INIT=8'h1E;
+LUT2 \fifo_inst/n257_s1  (
+	.I0(\fifo_inst/reset_w [1]),
+	.I1(\fifo_inst/wfull_val_7 ),
+	.F(\fifo_inst/n257_4 )
+);
+defparam \fifo_inst/n257_s1 .INIT=4'h4;
+LUT4 \fifo_inst/rempty_val_s3  (
+	.I0(\fifo_inst/Equal.rq2_wptr [1]),
+	.I1(\fifo_inst/rempty_val_8 ),
+	.I2(\fifo_inst/Equal.rq2_wptr [0]),
+	.I3(\fifo_inst/rbin_num_next [0]),
+	.F(\fifo_inst/rempty_val )
+);
+defparam \fifo_inst/rempty_val_s3 .INIT=16'h4221;
+LUT4 \fifo_inst/wfull_val_s3  (
+	.I0(\fifo_inst/wptr [0]),
+	.I1(\fifo_inst/wptr [1]),
+	.I2(\fifo_inst/rbin_num [1]),
+	.I3(\fifo_inst/rptr [0]),
+	.F(\fifo_inst/wfull_val_7 )
+);
+defparam \fifo_inst/wfull_val_s3 .INIT=16'h1428;
+LUT3 \fifo_inst/wfull_val1_s9  (
+	.I0(\fifo_inst/wfull_val1_3 ),
+	.I1(\fifo_inst/wfull_val1_2 ),
+	.I2(\fifo_inst/wfull_val1_0 ),
+	.F(\fifo_inst/wfull_val1 )
+);
+defparam \fifo_inst/wfull_val1_s9 .INIT=8'hAC;
+LUT3 \fifo_inst/wfull_val1_s10  (
+	.I0(\fifo_inst/wfull_val_7 ),
+	.I1(\fifo_inst/wfull_val1_0 ),
+	.I2(\fifo_inst/reset_w [1]),
+	.F(\fifo_inst/wfull_val1_0 )
+);
+defparam \fifo_inst/wfull_val1_s10 .INIT=8'h0E;
+LUT3 \fifo_inst/Full_d_s  (
+	.I0(\fifo_inst/Full_2 ),
+	.I1(\fifo_inst/Full_1_2 ),
+	.I2(\fifo_inst/Full_1 ),
+	.F(Full)
+);
+defparam \fifo_inst/Full_d_s .INIT=8'hAC;
+LUT3 \fifo_inst/Full_s8  (
+	.I0(\fifo_inst/wfull_val_7 ),
+	.I1(\fifo_inst/Full_1 ),
+	.I2(\fifo_inst/reset_w [1]),
+	.F(\fifo_inst/Full_1 )
+);
+defparam \fifo_inst/Full_s8 .INIT=8'h0E;
+LUT3 \fifo_inst/rbin_num_next_0_s5  (
+	.I0(Empty),
+	.I1(RdEn),
+	.I2(\fifo_inst/rbin_num [0]),
+	.F(\fifo_inst/rbin_num_next [0])
+);
+defparam \fifo_inst/rbin_num_next_0_s5 .INIT=8'hB4;
+LUT3 \fifo_inst/rbin_num_next_1_s2  (
+	.I0(\fifo_inst/rbin_num_next [0]),
+	.I1(\fifo_inst/rbin_num [0]),
+	.I2(\fifo_inst/rbin_num [1]),
+	.F(\fifo_inst/rbin_num_next [1])
+);
+defparam \fifo_inst/rbin_num_next_1_s2 .INIT=8'hB4;
+LUT2 \fifo_inst/Equal.wbinnext_0_s3  (
+	.I0(\fifo_inst/Equal.wbin [0]),
+	.I1(\fifo_inst/n20_5 ),
+	.F(\fifo_inst/Equal.wbinnext_0_7 )
+);
+defparam \fifo_inst/Equal.wbinnext_0_s3 .INIT=4'h6;
+LUT3 \fifo_inst/Equal.wbinnext_1_s2  (
+	.I0(\fifo_inst/Equal.wbin [0]),
+	.I1(\fifo_inst/n20_5 ),
+	.I2(\fifo_inst/wptr [1]),
+	.F(\fifo_inst/Equal.wbinnext [1])
+);
+defparam \fifo_inst/Equal.wbinnext_1_s2 .INIT=8'h78;
+LUT4 \fifo_inst/rempty_val_s4  (
+	.I0(\fifo_inst/Equal.rq2_wptr [0]),
+	.I1(\fifo_inst/Equal.rq2_wptr [1]),
+	.I2(\fifo_inst/rbin_num [1]),
+	.I3(\fifo_inst/rbin_num [0]),
+	.F(\fifo_inst/rempty_val_8 )
+);
+defparam \fifo_inst/rempty_val_s4 .INIT=16'h871E;
+DFFP \fifo_inst/reset_r_0_s0  (
+	.D(GND),
+	.CLK(\fifo_inst/n4_6 ),
+	.PRESET(Reset),
+	.Q(\fifo_inst/reset_r [0])
+);
+defparam \fifo_inst/reset_r_0_s0 .INIT=1'b1;
+DFFP \fifo_inst/reset_w_1_s0  (
+	.D(\fifo_inst/reset_w [0]),
+	.CLK(\fifo_inst/n9_6 ),
+	.PRESET(Reset),
+	.Q(\fifo_inst/reset_w [1])
+);
+defparam \fifo_inst/reset_w_1_s0 .INIT=1'b1;
+DFFP \fifo_inst/reset_w_0_s0  (
+	.D(GND),
+	.CLK(\fifo_inst/n9_6 ),
+	.PRESET(Reset),
+	.Q(\fifo_inst/reset_w [0])
+);
+defparam \fifo_inst/reset_w_0_s0 .INIT=1'b1;
+DFFC \fifo_inst/rbin_num_1_s0  (
+	.D(\fifo_inst/rbin_num_next [1]),
+	.CLK(RdClk),
+	.CLEAR(\fifo_inst/reset_r [1]),
+	.Q(\fifo_inst/rbin_num [1])
+);
+defparam \fifo_inst/rbin_num_1_s0 .INIT=1'b0;
+DFFC \fifo_inst/rbin_num_0_s0  (
+	.D(\fifo_inst/rbin_num_next [0]),
+	.CLK(RdClk),
+	.CLEAR(\fifo_inst/reset_r [1]),
+	.Q(\fifo_inst/rbin_num [0])
+);
+defparam \fifo_inst/rbin_num_0_s0 .INIT=1'b0;
+DFFC \fifo_inst/Equal.rq1_wptr_1_s0  (
+	.D(\fifo_inst/wptr [1]),
+	.CLK(RdClk),
+	.CLEAR(\fifo_inst/reset_r [1]),
+	.Q(\fifo_inst/Equal.rq1_wptr [1])
+);
+defparam \fifo_inst/Equal.rq1_wptr_1_s0 .INIT=1'b0;
+DFFC \fifo_inst/Equal.rq1_wptr_0_s0  (
+	.D(\fifo_inst/wptr [0]),
+	.CLK(RdClk),
+	.CLEAR(\fifo_inst/reset_r [1]),
+	.Q(\fifo_inst/Equal.rq1_wptr [0])
+);
+defparam \fifo_inst/Equal.rq1_wptr_0_s0 .INIT=1'b0;
+DFFC \fifo_inst/Equal.rq2_wptr_1_s0  (
+	.D(\fifo_inst/Equal.rq1_wptr [1]),
+	.CLK(RdClk),
+	.CLEAR(\fifo_inst/reset_r [1]),
+	.Q(\fifo_inst/Equal.rq2_wptr [1])
+);
+defparam \fifo_inst/Equal.rq2_wptr_1_s0 .INIT=1'b0;
+DFFC \fifo_inst/Equal.rq2_wptr_0_s0  (
+	.D(\fifo_inst/Equal.rq1_wptr [0]),
+	.CLK(RdClk),
+	.CLEAR(\fifo_inst/reset_r [1]),
+	.Q(\fifo_inst/Equal.rq2_wptr [0])
+);
+defparam \fifo_inst/Equal.rq2_wptr_0_s0 .INIT=1'b0;
+DFFC \fifo_inst/rptr_0_s0  (
+	.D(\fifo_inst/Equal.rgraynext [0]),
+	.CLK(RdClk),
+	.CLEAR(\fifo_inst/reset_r [1]),
+	.Q(\fifo_inst/rptr [0])
+);
+defparam \fifo_inst/rptr_0_s0 .INIT=1'b0;
+DFFC \fifo_inst/wptr_1_s0  (
+	.D(\fifo_inst/Equal.wbinnext [1]),
+	.CLK(WrClk),
+	.CLEAR(\fifo_inst/reset_w [1]),
+	.Q(\fifo_inst/wptr [1])
+);
+defparam \fifo_inst/wptr_1_s0 .INIT=1'b0;
+DFFC \fifo_inst/wptr_0_s0  (
+	.D(\fifo_inst/Equal.wgraynext [0]),
+	.CLK(WrClk),
+	.CLEAR(\fifo_inst/reset_w [1]),
+	.Q(\fifo_inst/wptr [0])
+);
+defparam \fifo_inst/wptr_0_s0 .INIT=1'b0;
+DFFC \fifo_inst/Equal.wbin_0_s0  (
+	.D(\fifo_inst/Equal.wbinnext_0_7 ),
+	.CLK(WrClk),
+	.CLEAR(\fifo_inst/reset_w [1]),
+	.Q(\fifo_inst/Equal.wbin [0])
+);
+defparam \fifo_inst/Equal.wbin_0_s0 .INIT=1'b0;
+DFFP \fifo_inst/Empty_s0  (
+	.D(\fifo_inst/rempty_val ),
+	.CLK(RdClk),
+	.PRESET(\fifo_inst/reset_r [1]),
+	.Q(Empty)
+);
+defparam \fifo_inst/Empty_s0 .INIT=1'b1;
+DFFP \fifo_inst/reset_r_1_s0  (
+	.D(\fifo_inst/reset_r [0]),
+	.CLK(\fifo_inst/n4_6 ),
+	.PRESET(Reset),
+	.Q(\fifo_inst/reset_r [1])
+);
+defparam \fifo_inst/reset_r_1_s0 .INIT=1'b1;
+DFFC \fifo_inst/wfull_val1_s0  (
+	.D(\fifo_inst/wfull_val_7 ),
+	.CLK(WrClk),
+	.CLEAR(\fifo_inst/reset_w [1]),
+	.Q(\fifo_inst/wfull_val1_2 )
+);
+defparam \fifo_inst/wfull_val1_s0 .INIT=1'b0;
+DFFP \fifo_inst/wfull_val1_s1  (
+	.D(\fifo_inst/wfull_val_7 ),
+	.CLK(WrClk),
+	.PRESET(\fifo_inst/n257_4 ),
+	.Q(\fifo_inst/wfull_val1_3 )
+);
+defparam \fifo_inst/wfull_val1_s1 .INIT=1'b1;
+DFFC \fifo_inst/Full_s0  (
+	.D(\fifo_inst/wfull_val1 ),
+	.CLK(WrClk),
+	.CLEAR(\fifo_inst/reset_w [1]),
+	.Q(\fifo_inst/Full_1_2 )
+);
+defparam \fifo_inst/Full_s0 .INIT=1'b0;
+DFFP \fifo_inst/Full_s1  (
+	.D(\fifo_inst/wfull_val1 ),
+	.CLK(WrClk),
+	.PRESET(\fifo_inst/n257_4 ),
+	.Q(\fifo_inst/Full_2 )
+);
+defparam \fifo_inst/Full_s1 .INIT=1'b1;
+SDPB \fifo_inst/Equal.mem_Equal.mem_0_0_s  (
+	.CLKA(WrClk),
+	.CEA(\fifo_inst/n20_5 ),
+	.RESETA(GND),
+	.CLKB(RdClk),
+	.CEB(\fifo_inst/n26_4 ),
+	.RESETB(\fifo_inst/reset_r [1]),
+	.OCE(GND),
+	.BLKSELA({GND, GND, GND}),
+	.BLKSELB({GND, GND, GND}),
+	.DI({GND, GND, GND, GND, GND, GND, GND, GND, Data[23:0]}),
+	.ADA({GND, GND, GND, GND, GND, GND, GND, GND, \fifo_inst/Equal.wbin [0], GND, VCC, VCC, VCC, VCC}),
+	.ADB({GND, GND, GND, GND, GND, GND, GND, GND, \fifo_inst/rbin_num_next [0], GND, GND, GND, GND, GND}),
+	.DO({\fifo_inst/DO [31:24], Q[23:0]})
+);
+defparam \fifo_inst/Equal.mem_Equal.mem_0_0_s .READ_MODE=1'b0;
+defparam \fifo_inst/Equal.mem_Equal.mem_0_0_s .BIT_WIDTH_0=32;
+defparam \fifo_inst/Equal.mem_Equal.mem_0_0_s .BIT_WIDTH_1=32;
+defparam \fifo_inst/Equal.mem_Equal.mem_0_0_s .RESET_MODE="ASYNC";
+defparam \fifo_inst/Equal.mem_Equal.mem_0_0_s .BLK_SEL_0=3'b000;
+defparam \fifo_inst/Equal.mem_Equal.mem_0_0_s .BLK_SEL_1=3'b000;
+INV \fifo_inst/n4_s2  (
+	.I(RdClk),
+	.O(\fifo_inst/n4_6 )
+);
+INV \fifo_inst/n9_s2  (
+	.I(WrClk),
+	.O(\fifo_inst/n9_6 )
+);
+endmodule

src/src/WrapFifoChain/FifoTfe2Bytes/FifoTfe2Bytes_tmp.v

@@ -0,0 +1,24 @@
+//Copyright (C)2014-2024 Gowin Semiconductor Corporation.
+//All rights reserved.
+//File Title: Template file for instantiation
+//Tool Version: V1.9.9.03 (64-bit)
+//Part Number: GW1N-UV9QN88C6/I5
+//Device: GW1N-9
+//Created Time: Fri Nov 22 16:03:28 2024
+
+//Change the instance name and port connections to the signal names
+//--------Copy here to design--------
+
+	FifoTfe2Bytes your_instance_name(
+		.Data(Data), //input [23:0] Data
+		.Reset(Reset), //input Reset
+		.WrClk(WrClk), //input WrClk
+		.RdClk(RdClk), //input RdClk
+		.WrEn(WrEn), //input WrEn
+		.RdEn(RdEn), //input RdEn
+		.Q(Q), //output [23:0] Q
+		.Empty(Empty), //output Empty
+		.Full(Full) //output Full
+	);
+
+//--------Copy end-------------------

src/src/WrapFifoChain/FifoTfe2Bytes/temp/FIFOHS/FIFOHS.prj

@@ -0,0 +1,20 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!DOCTYPE gowin-synthesis-project>
+<Project>
+    <Version>beta</Version>
+    <Device id="GW1N-9" package="QFN88" speed="6" partNumber="GW1N-UV9QN88C6/I5"/>
+    <FileList>
+        <File path="C:/Gowin/Gowin_V1.9.9.03_x64/IDE/ipcore/FIFO_HS/data/fifo_hs.v" type="verilog"/>
+        <File path="C:/Gowin/Gowin_V1.9.9.03_x64/IDE/ipcore/FIFO_HS/data/fifo_hs_top.v" type="verilog"/>
+    </FileList>
+    <OptionList>
+        <Option type="disable_insert_pad" value="1"/>
+        <Option type="include_path" value="C:/Gowin/Gowin_V1.9.9.03_x64/IDE/ipcore/FIFO_HS/data"/>
+        <Option type="include_path" value="C:/Gowin/Projects/BOCHv3_FPGA/src/src/WrapFifoChain/FifoTfe2Bytes/temp/FIFOHS"/>
+        <Option type="output_file" value="FifoTfe2Bytes.vg"/>
+        <Option type="output_template" value="FifoTfe2Bytes_tmp.v"/>
+        <Option type="ram_balance" value="1"/>
+        <Option type="ram_rw_check" value="1"/>
+        <Option type="verilog_language" value="sysv-2017"/>
+    </OptionList>
+</Project>

src/src/WrapFifoChain/FifoTfe2Bytes/temp/FIFOHS/FifoTfe2Bytes.log

@@ -0,0 +1,45 @@
+GowinSynthesis start
+Running parser ...
+Analyzing Verilog file 'C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v'
+Analyzing included file '**'("C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Back to file '**'("C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Undeclared symbol '**', assumed default net type '**'("C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Analyzing Verilog file 'C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v'
+Analyzing included file 'fifo_define.v'("C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":1)
+Back to file 'C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v'("C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":1)
+Analyzing included file 'C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\static_macro_define.v'("C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":2)
+Back to file 'C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v'("C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":2)
+Analyzing included file 'fifo_parameter.v'("C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":57)
+Back to file 'C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v'("C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":57)
+Compiling module 'FifoTfe2Bytes'("C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":4)
+Compiling module '**'("C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Extracting RAM for identifier '**'("C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+NOTE  (EX0101) : Current top module is "FifoTfe2Bytes"
+[5%] Running netlist conversion ...
+Running device independent optimization ...
+[10%] Optimizing Phase 0 completed
+[15%] Optimizing Phase 1 completed
+[25%] Optimizing Phase 2 completed
+Running inference ...
+[30%] Inferring Phase 0 completed
+[40%] Inferring Phase 1 completed
+[50%] Inferring Phase 2 completed
+[55%] Inferring Phase 3 completed
+Running technical mapping ...
+[60%] Tech-Mapping Phase 0 completed
+[65%] Tech-Mapping Phase 1 completed
+[75%] Tech-Mapping Phase 2 completed
+WARN  (AG0100) : Find logical loop signal : "fifo_inst/wfull_val1_s3"("C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+WARN  (AG0100) : Find logical loop signal : "fifo_inst/wfull_val1_s6"("C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+WARN  (AG0100) : Find logical loop signal : "fifo_inst/wfull_val1_s3"("C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+WARN  (AG0101) : The netlist is not one directed acyclic graph
+WARN  (AG0100) : Find logical loop signal : "fifo_inst/Full_s3"("C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+WARN  (AG0100) : Find logical loop signal : "fifo_inst/Full_s6"("C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+WARN  (AG0100) : Find logical loop signal : "fifo_inst/Full_s3"("C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+WARN  (AG0101) : The netlist is not one directed acyclic graph
+[80%] Tech-Mapping Phase 3 completed
+[90%] Tech-Mapping Phase 4 completed
+[95%] Generate netlist file "C:\Gowin\Projects\BOCHv3_FPGA\src\src\WrapFifoChain\FifoTfe2Bytes\temp\FIFOHS\FifoTfe2Bytes.vg" completed
+Generate template file "C:\Gowin\Projects\BOCHv3_FPGA\src\src\WrapFifoChain\FifoTfe2Bytes\temp\FIFOHS\FifoTfe2Bytes_tmp.v" completed
+[100%] Generate report file "C:\Gowin\Projects\BOCHv3_FPGA\src\src\WrapFifoChain\FifoTfe2Bytes\temp\FIFOHS\FifoTfe2Bytes_syn.rpt.html" completed
+GowinSynthesis finish

src/src/WrapFifoChain/FifoTfe2Bytes/temp/FIFOHS/FifoTfe2Bytes.vg

@@ -0,0 +1,187 @@
+//
+//Written by GowinSynthesis
+//Tool Version "V1.9.9.03 (64-bit)"
+//Fri Nov 22 16:03:28 2024
+
+//Source file index table:
+//file0 "\C:/Gowin/Gowin_V1.9.9.03_x64/IDE/ipcore/FIFO_HS/data/fifo_hs.v"
+//file1 "\C:/Gowin/Gowin_V1.9.9.03_x64/IDE/ipcore/FIFO_HS/data/fifo_hs_top.v"
+`timescale 100 ps/100 ps
+`pragma protect begin_protected
+`pragma protect version="2.3"
+`pragma protect author="default"
+`pragma protect author_info="default"
+`pragma protect encrypt_agent="GOWIN"
+`pragma protect encrypt_agent_info="GOWIN Encrypt Version 2.3"
+
+`pragma protect encoding=(enctype="base64", line_length=76, bytes=256)
+`pragma protect key_keyowner="GOWIN",key_keyname="GWK2023-09",key_method="rsa"
+`pragma protect key_block
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+
+`pragma protect encoding=(enctype="base64", line_length=76, bytes=6352)
+`pragma protect data_keyowner="default-ip-vendor"
+`pragma protect data_keyname="default-ip-key"
+`pragma protect data_method="aes128-cfb"
+`pragma protect data_block
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+`pragma protect end_protected
+module FifoTfe2Bytes (
+  Data,
+  Reset,
+  WrClk,
+  RdClk,
+  WrEn,
+  RdEn,
+  Q,
+  Empty,
+  Full
+)
+;
+input [23:0] Data;
+input Reset;
+input WrClk;
+input RdClk;
+input WrEn;
+input RdEn;
+output [23:0] Q;
+output Empty;
+output Full;
+wire VCC;
+wire GND;
+  \~fifo.FifoTfe2Bytes  fifo_inst (
+    .Reset(Reset),
+    .RdClk(RdClk),
+    .WrClk(WrClk),
+    .WrEn(WrEn),
+    .RdEn(RdEn),
+    .Data(Data[23:0]),
+    .Empty(Empty),
+    .Full(Full),
+    .Q(Q[23:0])
+);
+  VCC VCC_cZ (
+    .V(VCC)
+);
+  GND GND_cZ (
+    .G(GND)
+);
+  GSR GSR (
+    .GSRI(VCC) 
+);
+endmodule /* FifoTfe2Bytes */

src/src/WrapFifoChain/FifoTfe2Bytes/temp/FIFOHS/FifoTfe2Bytes_syn_resource.html

@@ -0,0 +1,46 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html>
+<head>
+<title>Hierarchy Module Resource</title>
+<style type="text/css">
+body { font-family: Verdana, Arial, sans-serif; font-size: 14px; }
+div#main_wrapper{ width: 100%; }
+h1 {text-align: center; }
+h1 {margin-top: 36px; }
+table, th, td { border: 1px solid #aaa; }
+table { border-collapse:collapse; margin-top: 10px; margin-bottom: 20px; width: 100%; }
+th, td { align = "center"; padding: 5px 2px 5px 5px; }
+th { color: #fff; font-weight: bold; background-color: #0084ff; }
+table td.label { width: 20%; white-space: nowrap; min-width: 20px; background-color: #dee8f4; }
+</style>
+</head>
+<body>
+<div id="main_wrapper">
+<div id="content">
+<h1>Hierarchy Module Resource</h1>
+<table>
+<tr>
+<th class="label">MODULE NAME</th>
+<th class="label">REG NUMBER</th>
+<th class="label">ALU NUMBER</th>
+<th class="label">LUT NUMBER</th>
+<th class="label">DSP NUMBER</th>
+<th class="label">BSRAM NUMBER</th>
+<th class="label">SSRAM NUMBER</th>
+<th class="label">ROM16 NUMBER</th>
+</tr>
+<tr>
+<td class="label">FifoTfe2Bytes (C:/Gowin/Gowin_V1.9.9.03_x64/IDE/ipcore/FIFO_HS/data/fifo_hs_top.v)</td>
+<td align = "center">19</td>
+<td align = "center">-</td>
+<td align = "center">18</td>
+<td align = "center">-</td>
+<td align = "center">1</td>
+<td align = "center">-</td>
+<td align = "center">-</td>
+</tr>
+</table>
+</div><!-- content -->
+</div><!-- main_wrapper -->
+</body>
+</html>

src/src/WrapFifoChain/FifoTfe2Bytes/temp/FIFOHS/FifoTfe2Bytes_syn_rsc.xml

@@ -0,0 +1,2 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<Module name="FifoTfe2Bytes" Register="19" Lut="18" Bsram="1" T_Register="19(19)" T_Lut="18(18)" T_Bsram="1(1)"/>

src/src/WrapFifoChain/FifoTfe2Bytes/temp/FIFOHS/FifoTfe2Bytes_tmp.v

@@ -0,0 +1,24 @@
+//Copyright (C)2014-2024 Gowin Semiconductor Corporation.
+//All rights reserved.
+//File Title: Template file for instantiation
+//Tool Version: V1.9.9.03 (64-bit)
+//Part Number: GW1N-UV9QN88C6/I5
+//Device: GW1N-9
+//Created Time: Fri Nov 22 16:03:28 2024
+
+//Change the instance name and port connections to the signal names
+//--------Copy here to design--------
+
+	FifoTfe2Bytes your_instance_name(
+		.Data(Data), //input [23:0] Data
+		.Reset(Reset), //input Reset
+		.WrClk(WrClk), //input WrClk
+		.RdClk(RdClk), //input RdClk
+		.WrEn(WrEn), //input WrEn
+		.RdEn(RdEn), //input RdEn
+		.Q(Q), //output [23:0] Q
+		.Empty(Empty), //output Empty
+		.Full(Full) //output Full
+	);
+
+//--------Copy end-------------------

src/src/WrapFifoChain/FifoTfe2Bytes/temp/FIFOHS/fifo_define.v

@@ -0,0 +1,5 @@
+`define module_name FifoTfe2Bytes
+`define EBR_BASED
+`define FWFT
+`define En_Reset
+`define Reset_Synchronization

src/src/WrapFifoChain/FifoTfe2Bytes/temp/FIFOHS/fifo_parameter.v

@@ -0,0 +1,6 @@
+parameter WDEPTH = 2;
+parameter ASIZE = 1;
+parameter WDSIZE = 24;
+parameter RDEPTH = 2;
+parameter RASIZE = 1;
+parameter RDSIZE = 24;

src/src/WrapFifoChain/FifoTfe2Bytes/temp/FIFOHS/project.ini

@@ -0,0 +1 @@
+RESOURCE_CHECK=false

src/src/WrapFifoChain/FifoTfe4Bytes/FifoTfe4Bytes.ipc

@@ -0,0 +1,35 @@
+[General]
+ipc_version=4
+file=FifoTfe4Bytes
+module=FifoTfe4Bytes
+target_device=gw1n9-022
+type=fifo_hs
+version=1.0
+
+[Config]
+AlmostEmptyFlag=false
+AlmostEmptyFlagItem=Empty_Single Threshold Constant Parameter
+AlmostFullFlag=false
+AlmostFullFlagItem=Full_Single Threshold Constant Parameter
+BSRAM=true
+ControlledByRdEn=false
+ECCSelected=false
+EmptyClear=1
+EmptySet=1
+EnReset=true
+FirstWordFallThrough=true
+FullClear=1
+FullSet=1
+LANG=0
+OutputRegistersSelected=false
+REG=false
+ReadDataNum=false
+ReadDataWidth=32
+ReadDepth=2
+ResetSynchronization=true
+SSRAM=false
+StandardFIFO=false
+Synthesis_tool=GowinSynthesis
+WriteDataNum=false
+WriteDataWidth=32
+WriteDepth=2

src/src/WrapFifoChain/FifoTfe4Bytes/FifoTfe4Bytes.v

@@ -0,0 +1,186 @@
+//
+//Written by GowinSynthesis
+//Tool Version "V1.9.9.03 (64-bit)"
+//Fri Nov 22 16:04:43 2024
+
+//Source file index table:
+//file0 "\C:/Gowin/Gowin_V1.9.9.03_x64/IDE/ipcore/FIFO_HS/data/fifo_hs.v"
+//file1 "\C:/Gowin/Gowin_V1.9.9.03_x64/IDE/ipcore/FIFO_HS/data/fifo_hs_top.v"
+`timescale 100 ps/100 ps
+`pragma protect begin_protected
+`pragma protect version="2.3"
+`pragma protect author="default"
+`pragma protect author_info="default"
+`pragma protect encrypt_agent="GOWIN"
+`pragma protect encrypt_agent_info="GOWIN Encrypt Version 2.3"
+
+`pragma protect encoding=(enctype="base64", line_length=76, bytes=256)
+`pragma protect key_keyowner="GOWIN",key_keyname="GWK2023-09",key_method="rsa"
+`pragma protect key_block
+j6k58xrOQ8NiTqxpDvExvVWMNOVIR/lcfZqrbnK1rZSnt+h2pkYESg+2+aOY7tIb67oNaN/2soOE
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+
+`pragma protect encoding=(enctype="base64", line_length=76, bytes=6288)
+`pragma protect data_keyowner="default-ip-vendor"
+`pragma protect data_keyname="default-ip-key"
+`pragma protect data_method="aes128-cfb"
+`pragma protect data_block
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+PKwDKgs7jfaY4CMfOtbtmffk
+`pragma protect end_protected
+module FifoTfe4Bytes (
+  Data,
+  Reset,
+  WrClk,
+  RdClk,
+  WrEn,
+  RdEn,
+  Q,
+  Empty,
+  Full
+)
+;
+input [31:0] Data;
+input Reset;
+input WrClk;
+input RdClk;
+input WrEn;
+input RdEn;
+output [31:0] Q;
+output Empty;
+output Full;
+wire VCC;
+wire GND;
+  \~fifo.FifoTfe4Bytes  fifo_inst (
+    .Reset(Reset),
+    .RdClk(RdClk),
+    .WrClk(WrClk),
+    .WrEn(WrEn),
+    .RdEn(RdEn),
+    .Data(Data[31:0]),
+    .Empty(Empty),
+    .Full(Full),
+    .Q(Q[31:0])
+);
+  VCC VCC_cZ (
+    .V(VCC)
+);
+  GND GND_cZ (
+    .G(GND)
+);
+  GSR GSR (
+    .GSRI(VCC) 
+);
+endmodule /* FifoTfe4Bytes */

src/src/WrapFifoChain/FifoTfe4Bytes/FifoTfe4Bytes.vo

@@ -0,0 +1,352 @@
+//Copyright (C)2014-2024 Gowin Semiconductor Corporation.
+//All rights reserved.
+//File Title: Post-PnR Simulation Model file
+//Tool Version: V1.9.9.03 (64-bit)
+//Created Time: Fri Nov 22 16:04:44 2024
+
+`timescale 100 ps/100 ps
+module FifoTfe4Bytes(
+	Data,
+	Reset,
+	WrClk,
+	RdClk,
+	WrEn,
+	RdEn,
+	Q,
+	Empty,
+	Full
+);
+input [31:0] Data;
+input Reset;
+input WrClk;
+input RdClk;
+input WrEn;
+input RdEn;
+output [31:0] Q;
+output Empty;
+output Full;
+wire [31:0] Data;
+wire Empty;
+wire Full;
+wire GND;
+wire [31:0] Q;
+wire RdClk;
+wire RdEn;
+wire Reset;
+wire VCC;
+wire WrClk;
+wire WrEn;
+wire \fifo_inst/n20_5 ;
+wire \fifo_inst/n26_4 ;
+wire \fifo_inst/n297_4 ;
+wire \fifo_inst/rempty_val ;
+wire \fifo_inst/wfull_val_7 ;
+wire \fifo_inst/wfull_val1 ;
+wire \fifo_inst/wfull_val1_0 ;
+wire \fifo_inst/Full_1 ;
+wire \fifo_inst/Equal.wbinnext_0_7 ;
+wire \fifo_inst/rempty_val_8 ;
+wire \fifo_inst/wfull_val1_2 ;
+wire \fifo_inst/wfull_val1_3 ;
+wire \fifo_inst/Full_1_2 ;
+wire \fifo_inst/Full_2 ;
+wire \fifo_inst/n4_6 ;
+wire \fifo_inst/n9_6 ;
+wire [0:0] \fifo_inst/Equal.rgraynext ;
+wire [0:0] \fifo_inst/Equal.wgraynext ;
+wire [1:0] \fifo_inst/rbin_num_next ;
+wire [1:1] \fifo_inst/Equal.wbinnext ;
+wire [1:0] \fifo_inst/reset_r ;
+wire [1:0] \fifo_inst/reset_w ;
+wire [1:0] \fifo_inst/rbin_num ;
+wire [1:0] \fifo_inst/Equal.rq1_wptr ;
+wire [1:0] \fifo_inst/Equal.rq2_wptr ;
+wire [0:0] \fifo_inst/rptr ;
+wire [1:0] \fifo_inst/wptr ;
+wire [0:0] \fifo_inst/Equal.wbin ;
+VCC VCC_cZ (
+  .V(VCC)
+);
+GND GND_cZ (
+  .G(GND)
+);
+GSR GSR (
+	.GSRI(VCC)
+);
+LUT4 \fifo_inst/n20_s1  (
+	.I0(\fifo_inst/Full_2 ),
+	.I1(\fifo_inst/Full_1_2 ),
+	.I2(\fifo_inst/Full_1 ),
+	.I3(WrEn),
+	.F(\fifo_inst/n20_5 )
+);
+defparam \fifo_inst/n20_s1 .INIT=16'h5300;
+LUT3 \fifo_inst/n26_s1  (
+	.I0(RdEn),
+	.I1(Empty),
+	.I2(\fifo_inst/rempty_val ),
+	.F(\fifo_inst/n26_4 )
+);
+defparam \fifo_inst/n26_s1 .INIT=8'h0E;
+LUT3 \fifo_inst/Equal.rgraynext_0_s0  (
+	.I0(\fifo_inst/rbin_num [0]),
+	.I1(\fifo_inst/rbin_num_next [0]),
+	.I2(\fifo_inst/rbin_num [1]),
+	.F(\fifo_inst/Equal.rgraynext [0])
+);
+defparam \fifo_inst/Equal.rgraynext_0_s0 .INIT=8'h1E;
+LUT3 \fifo_inst/Equal.wgraynext_0_s0  (
+	.I0(\fifo_inst/Equal.wbin [0]),
+	.I1(\fifo_inst/n20_5 ),
+	.I2(\fifo_inst/wptr [1]),
+	.F(\fifo_inst/Equal.wgraynext [0])
+);
+defparam \fifo_inst/Equal.wgraynext_0_s0 .INIT=8'h1E;
+LUT2 \fifo_inst/n297_s1  (
+	.I0(\fifo_inst/reset_w [1]),
+	.I1(\fifo_inst/wfull_val_7 ),
+	.F(\fifo_inst/n297_4 )
+);
+defparam \fifo_inst/n297_s1 .INIT=4'h4;
+LUT4 \fifo_inst/rempty_val_s3  (
+	.I0(\fifo_inst/Equal.rq2_wptr [1]),
+	.I1(\fifo_inst/rempty_val_8 ),
+	.I2(\fifo_inst/Equal.rq2_wptr [0]),
+	.I3(\fifo_inst/rbin_num_next [0]),
+	.F(\fifo_inst/rempty_val )
+);
+defparam \fifo_inst/rempty_val_s3 .INIT=16'h4221;
+LUT4 \fifo_inst/wfull_val_s3  (
+	.I0(\fifo_inst/wptr [0]),
+	.I1(\fifo_inst/wptr [1]),
+	.I2(\fifo_inst/rbin_num [1]),
+	.I3(\fifo_inst/rptr [0]),
+	.F(\fifo_inst/wfull_val_7 )
+);
+defparam \fifo_inst/wfull_val_s3 .INIT=16'h1428;
+LUT3 \fifo_inst/wfull_val1_s9  (
+	.I0(\fifo_inst/wfull_val1_3 ),
+	.I1(\fifo_inst/wfull_val1_2 ),
+	.I2(\fifo_inst/wfull_val1_0 ),
+	.F(\fifo_inst/wfull_val1 )
+);
+defparam \fifo_inst/wfull_val1_s9 .INIT=8'hAC;
+LUT3 \fifo_inst/wfull_val1_s10  (
+	.I0(\fifo_inst/wfull_val_7 ),
+	.I1(\fifo_inst/wfull_val1_0 ),
+	.I2(\fifo_inst/reset_w [1]),
+	.F(\fifo_inst/wfull_val1_0 )
+);
+defparam \fifo_inst/wfull_val1_s10 .INIT=8'h0E;
+LUT3 \fifo_inst/Full_d_s  (
+	.I0(\fifo_inst/Full_2 ),
+	.I1(\fifo_inst/Full_1_2 ),
+	.I2(\fifo_inst/Full_1 ),
+	.F(Full)
+);
+defparam \fifo_inst/Full_d_s .INIT=8'hAC;
+LUT3 \fifo_inst/Full_s8  (
+	.I0(\fifo_inst/wfull_val_7 ),
+	.I1(\fifo_inst/Full_1 ),
+	.I2(\fifo_inst/reset_w [1]),
+	.F(\fifo_inst/Full_1 )
+);
+defparam \fifo_inst/Full_s8 .INIT=8'h0E;
+LUT3 \fifo_inst/rbin_num_next_0_s5  (
+	.I0(Empty),
+	.I1(RdEn),
+	.I2(\fifo_inst/rbin_num [0]),
+	.F(\fifo_inst/rbin_num_next [0])
+);
+defparam \fifo_inst/rbin_num_next_0_s5 .INIT=8'hB4;
+LUT3 \fifo_inst/rbin_num_next_1_s2  (
+	.I0(\fifo_inst/rbin_num_next [0]),
+	.I1(\fifo_inst/rbin_num [0]),
+	.I2(\fifo_inst/rbin_num [1]),
+	.F(\fifo_inst/rbin_num_next [1])
+);
+defparam \fifo_inst/rbin_num_next_1_s2 .INIT=8'hB4;
+LUT2 \fifo_inst/Equal.wbinnext_0_s3  (
+	.I0(\fifo_inst/Equal.wbin [0]),
+	.I1(\fifo_inst/n20_5 ),
+	.F(\fifo_inst/Equal.wbinnext_0_7 )
+);
+defparam \fifo_inst/Equal.wbinnext_0_s3 .INIT=4'h6;
+LUT3 \fifo_inst/Equal.wbinnext_1_s2  (
+	.I0(\fifo_inst/Equal.wbin [0]),
+	.I1(\fifo_inst/n20_5 ),
+	.I2(\fifo_inst/wptr [1]),
+	.F(\fifo_inst/Equal.wbinnext [1])
+);
+defparam \fifo_inst/Equal.wbinnext_1_s2 .INIT=8'h78;
+LUT4 \fifo_inst/rempty_val_s4  (
+	.I0(\fifo_inst/Equal.rq2_wptr [0]),
+	.I1(\fifo_inst/Equal.rq2_wptr [1]),
+	.I2(\fifo_inst/rbin_num [1]),
+	.I3(\fifo_inst/rbin_num [0]),
+	.F(\fifo_inst/rempty_val_8 )
+);
+defparam \fifo_inst/rempty_val_s4 .INIT=16'h871E;
+DFFP \fifo_inst/reset_r_0_s0  (
+	.D(GND),
+	.CLK(\fifo_inst/n4_6 ),
+	.PRESET(Reset),
+	.Q(\fifo_inst/reset_r [0])
+);
+defparam \fifo_inst/reset_r_0_s0 .INIT=1'b1;
+DFFP \fifo_inst/reset_w_1_s0  (
+	.D(\fifo_inst/reset_w [0]),
+	.CLK(\fifo_inst/n9_6 ),
+	.PRESET(Reset),
+	.Q(\fifo_inst/reset_w [1])
+);
+defparam \fifo_inst/reset_w_1_s0 .INIT=1'b1;
+DFFP \fifo_inst/reset_w_0_s0  (
+	.D(GND),
+	.CLK(\fifo_inst/n9_6 ),
+	.PRESET(Reset),
+	.Q(\fifo_inst/reset_w [0])
+);
+defparam \fifo_inst/reset_w_0_s0 .INIT=1'b1;
+DFFC \fifo_inst/rbin_num_1_s0  (
+	.D(\fifo_inst/rbin_num_next [1]),
+	.CLK(RdClk),
+	.CLEAR(\fifo_inst/reset_r [1]),
+	.Q(\fifo_inst/rbin_num [1])
+);
+defparam \fifo_inst/rbin_num_1_s0 .INIT=1'b0;
+DFFC \fifo_inst/rbin_num_0_s0  (
+	.D(\fifo_inst/rbin_num_next [0]),
+	.CLK(RdClk),
+	.CLEAR(\fifo_inst/reset_r [1]),
+	.Q(\fifo_inst/rbin_num [0])
+);
+defparam \fifo_inst/rbin_num_0_s0 .INIT=1'b0;
+DFFC \fifo_inst/Equal.rq1_wptr_1_s0  (
+	.D(\fifo_inst/wptr [1]),
+	.CLK(RdClk),
+	.CLEAR(\fifo_inst/reset_r [1]),
+	.Q(\fifo_inst/Equal.rq1_wptr [1])
+);
+defparam \fifo_inst/Equal.rq1_wptr_1_s0 .INIT=1'b0;
+DFFC \fifo_inst/Equal.rq1_wptr_0_s0  (
+	.D(\fifo_inst/wptr [0]),
+	.CLK(RdClk),
+	.CLEAR(\fifo_inst/reset_r [1]),
+	.Q(\fifo_inst/Equal.rq1_wptr [0])
+);
+defparam \fifo_inst/Equal.rq1_wptr_0_s0 .INIT=1'b0;
+DFFC \fifo_inst/Equal.rq2_wptr_1_s0  (
+	.D(\fifo_inst/Equal.rq1_wptr [1]),
+	.CLK(RdClk),
+	.CLEAR(\fifo_inst/reset_r [1]),
+	.Q(\fifo_inst/Equal.rq2_wptr [1])
+);
+defparam \fifo_inst/Equal.rq2_wptr_1_s0 .INIT=1'b0;
+DFFC \fifo_inst/Equal.rq2_wptr_0_s0  (
+	.D(\fifo_inst/Equal.rq1_wptr [0]),
+	.CLK(RdClk),
+	.CLEAR(\fifo_inst/reset_r [1]),
+	.Q(\fifo_inst/Equal.rq2_wptr [0])
+);
+defparam \fifo_inst/Equal.rq2_wptr_0_s0 .INIT=1'b0;
+DFFC \fifo_inst/rptr_0_s0  (
+	.D(\fifo_inst/Equal.rgraynext [0]),
+	.CLK(RdClk),
+	.CLEAR(\fifo_inst/reset_r [1]),
+	.Q(\fifo_inst/rptr [0])
+);
+defparam \fifo_inst/rptr_0_s0 .INIT=1'b0;
+DFFC \fifo_inst/wptr_1_s0  (
+	.D(\fifo_inst/Equal.wbinnext [1]),
+	.CLK(WrClk),
+	.CLEAR(\fifo_inst/reset_w [1]),
+	.Q(\fifo_inst/wptr [1])
+);
+defparam \fifo_inst/wptr_1_s0 .INIT=1'b0;
+DFFC \fifo_inst/wptr_0_s0  (
+	.D(\fifo_inst/Equal.wgraynext [0]),
+	.CLK(WrClk),
+	.CLEAR(\fifo_inst/reset_w [1]),
+	.Q(\fifo_inst/wptr [0])
+);
+defparam \fifo_inst/wptr_0_s0 .INIT=1'b0;
+DFFC \fifo_inst/Equal.wbin_0_s0  (
+	.D(\fifo_inst/Equal.wbinnext_0_7 ),
+	.CLK(WrClk),
+	.CLEAR(\fifo_inst/reset_w [1]),
+	.Q(\fifo_inst/Equal.wbin [0])
+);
+defparam \fifo_inst/Equal.wbin_0_s0 .INIT=1'b0;
+DFFP \fifo_inst/Empty_s0  (
+	.D(\fifo_inst/rempty_val ),
+	.CLK(RdClk),
+	.PRESET(\fifo_inst/reset_r [1]),
+	.Q(Empty)
+);
+defparam \fifo_inst/Empty_s0 .INIT=1'b1;
+DFFP \fifo_inst/reset_r_1_s0  (
+	.D(\fifo_inst/reset_r [0]),
+	.CLK(\fifo_inst/n4_6 ),
+	.PRESET(Reset),
+	.Q(\fifo_inst/reset_r [1])
+);
+defparam \fifo_inst/reset_r_1_s0 .INIT=1'b1;
+DFFC \fifo_inst/wfull_val1_s0  (
+	.D(\fifo_inst/wfull_val_7 ),
+	.CLK(WrClk),
+	.CLEAR(\fifo_inst/reset_w [1]),
+	.Q(\fifo_inst/wfull_val1_2 )
+);
+defparam \fifo_inst/wfull_val1_s0 .INIT=1'b0;
+DFFP \fifo_inst/wfull_val1_s1  (
+	.D(\fifo_inst/wfull_val_7 ),
+	.CLK(WrClk),
+	.PRESET(\fifo_inst/n297_4 ),
+	.Q(\fifo_inst/wfull_val1_3 )
+);
+defparam \fifo_inst/wfull_val1_s1 .INIT=1'b1;
+DFFC \fifo_inst/Full_s0  (
+	.D(\fifo_inst/wfull_val1 ),
+	.CLK(WrClk),
+	.CLEAR(\fifo_inst/reset_w [1]),
+	.Q(\fifo_inst/Full_1_2 )
+);
+defparam \fifo_inst/Full_s0 .INIT=1'b0;
+DFFP \fifo_inst/Full_s1  (
+	.D(\fifo_inst/wfull_val1 ),
+	.CLK(WrClk),
+	.PRESET(\fifo_inst/n297_4 ),
+	.Q(\fifo_inst/Full_2 )
+);
+defparam \fifo_inst/Full_s1 .INIT=1'b1;
+SDPB \fifo_inst/Equal.mem_Equal.mem_0_0_s  (
+	.CLKA(WrClk),
+	.CEA(\fifo_inst/n20_5 ),
+	.RESETA(GND),
+	.CLKB(RdClk),
+	.CEB(\fifo_inst/n26_4 ),
+	.RESETB(\fifo_inst/reset_r [1]),
+	.OCE(GND),
+	.BLKSELA({GND, GND, GND}),
+	.BLKSELB({GND, GND, GND}),
+	.DI({Data[31:0]}),
+	.ADA({GND, GND, GND, GND, GND, GND, GND, GND, \fifo_inst/Equal.wbin [0], GND, VCC, VCC, VCC, VCC}),
+	.ADB({GND, GND, GND, GND, GND, GND, GND, GND, \fifo_inst/rbin_num_next [0], GND, GND, GND, GND, GND}),
+	.DO({Q[31:0]})
+);
+defparam \fifo_inst/Equal.mem_Equal.mem_0_0_s .READ_MODE=1'b0;
+defparam \fifo_inst/Equal.mem_Equal.mem_0_0_s .BIT_WIDTH_0=32;
+defparam \fifo_inst/Equal.mem_Equal.mem_0_0_s .BIT_WIDTH_1=32;
+defparam \fifo_inst/Equal.mem_Equal.mem_0_0_s .RESET_MODE="ASYNC";
+defparam \fifo_inst/Equal.mem_Equal.mem_0_0_s .BLK_SEL_0=3'b000;
+defparam \fifo_inst/Equal.mem_Equal.mem_0_0_s .BLK_SEL_1=3'b000;
+INV \fifo_inst/n4_s2  (
+	.I(RdClk),
+	.O(\fifo_inst/n4_6 )
+);
+INV \fifo_inst/n9_s2  (
+	.I(WrClk),
+	.O(\fifo_inst/n9_6 )
+);
+endmodule

src/src/WrapFifoChain/FifoTfe4Bytes/FifoTfe4Bytes_tmp.v

@@ -0,0 +1,24 @@
+//Copyright (C)2014-2024 Gowin Semiconductor Corporation.
+//All rights reserved.
+//File Title: Template file for instantiation
+//Tool Version: V1.9.9.03 (64-bit)
+//Part Number: GW1N-UV9QN88C6/I5
+//Device: GW1N-9
+//Created Time: Fri Nov 22 16:04:43 2024
+
+//Change the instance name and port connections to the signal names
+//--------Copy here to design--------
+
+	FifoTfe4Bytes your_instance_name(
+		.Data(Data), //input [31:0] Data
+		.Reset(Reset), //input Reset
+		.WrClk(WrClk), //input WrClk
+		.RdClk(RdClk), //input RdClk
+		.WrEn(WrEn), //input WrEn
+		.RdEn(RdEn), //input RdEn
+		.Q(Q), //output [31:0] Q
+		.Empty(Empty), //output Empty
+		.Full(Full) //output Full
+	);
+
+//--------Copy end-------------------

src/src/WrapFifoChain/FifoTfe4Bytes/temp/FIFOHS/FIFOHS.prj

@@ -0,0 +1,20 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!DOCTYPE gowin-synthesis-project>
+<Project>
+    <Version>beta</Version>
+    <Device id="GW1N-9" package="QFN88" speed="6" partNumber="GW1N-UV9QN88C6/I5"/>
+    <FileList>
+        <File path="C:/Gowin/Gowin_V1.9.9.03_x64/IDE/ipcore/FIFO_HS/data/fifo_hs.v" type="verilog"/>
+        <File path="C:/Gowin/Gowin_V1.9.9.03_x64/IDE/ipcore/FIFO_HS/data/fifo_hs_top.v" type="verilog"/>
+    </FileList>
+    <OptionList>
+        <Option type="disable_insert_pad" value="1"/>
+        <Option type="include_path" value="C:/Gowin/Gowin_V1.9.9.03_x64/IDE/ipcore/FIFO_HS/data"/>
+        <Option type="include_path" value="C:/Gowin/Projects/BOCHv3_FPGA/src/src/WrapFifoChain/FifoTfe4Bytes/temp/FIFOHS"/>
+        <Option type="output_file" value="FifoTfe4Bytes.vg"/>
+        <Option type="output_template" value="FifoTfe4Bytes_tmp.v"/>
+        <Option type="ram_balance" value="1"/>
+        <Option type="ram_rw_check" value="1"/>
+        <Option type="verilog_language" value="sysv-2017"/>
+    </OptionList>
+</Project>

src/src/WrapFifoChain/FifoTfe4Bytes/temp/FIFOHS/FifoTfe4Bytes.log

@@ -0,0 +1,45 @@
+GowinSynthesis start
+Running parser ...
+Analyzing Verilog file 'C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v'
+Analyzing included file '**'("C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Back to file '**'("C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Undeclared symbol '**', assumed default net type '**'("C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Analyzing Verilog file 'C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v'
+Analyzing included file 'fifo_define.v'("C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":1)
+Back to file 'C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v'("C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":1)
+Analyzing included file 'C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\static_macro_define.v'("C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":2)
+Back to file 'C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v'("C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":2)
+Analyzing included file 'fifo_parameter.v'("C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":57)
+Back to file 'C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v'("C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":57)
+Compiling module 'FifoTfe4Bytes'("C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":4)
+Compiling module '**'("C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Extracting RAM for identifier '**'("C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+NOTE  (EX0101) : Current top module is "FifoTfe4Bytes"
+[5%] Running netlist conversion ...
+Running device independent optimization ...
+[10%] Optimizing Phase 0 completed
+[15%] Optimizing Phase 1 completed
+[25%] Optimizing Phase 2 completed
+Running inference ...
+[30%] Inferring Phase 0 completed
+[40%] Inferring Phase 1 completed
+[50%] Inferring Phase 2 completed
+[55%] Inferring Phase 3 completed
+Running technical mapping ...
+[60%] Tech-Mapping Phase 0 completed
+[65%] Tech-Mapping Phase 1 completed
+[75%] Tech-Mapping Phase 2 completed
+WARN  (AG0100) : Find logical loop signal : "fifo_inst/wfull_val1_s3"("C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+WARN  (AG0100) : Find logical loop signal : "fifo_inst/wfull_val1_s6"("C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+WARN  (AG0100) : Find logical loop signal : "fifo_inst/wfull_val1_s3"("C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+WARN  (AG0101) : The netlist is not one directed acyclic graph
+WARN  (AG0100) : Find logical loop signal : "fifo_inst/Full_s3"("C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+WARN  (AG0100) : Find logical loop signal : "fifo_inst/Full_s6"("C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+WARN  (AG0100) : Find logical loop signal : "fifo_inst/Full_s3"("C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+WARN  (AG0101) : The netlist is not one directed acyclic graph
+[80%] Tech-Mapping Phase 3 completed
+[90%] Tech-Mapping Phase 4 completed
+[95%] Generate netlist file "C:\Gowin\Projects\BOCHv3_FPGA\src\src\WrapFifoChain\FifoTfe4Bytes\temp\FIFOHS\FifoTfe4Bytes.vg" completed
+Generate template file "C:\Gowin\Projects\BOCHv3_FPGA\src\src\WrapFifoChain\FifoTfe4Bytes\temp\FIFOHS\FifoTfe4Bytes_tmp.v" completed
+[100%] Generate report file "C:\Gowin\Projects\BOCHv3_FPGA\src\src\WrapFifoChain\FifoTfe4Bytes\temp\FIFOHS\FifoTfe4Bytes_syn.rpt.html" completed
+GowinSynthesis finish

src/src/WrapFifoChain/FifoTfe4Bytes/temp/FIFOHS/FifoTfe4Bytes.vg

@@ -0,0 +1,186 @@
+//
+//Written by GowinSynthesis
+//Tool Version "V1.9.9.03 (64-bit)"
+//Fri Nov 22 16:04:43 2024
+
+//Source file index table:
+//file0 "\C:/Gowin/Gowin_V1.9.9.03_x64/IDE/ipcore/FIFO_HS/data/fifo_hs.v"
+//file1 "\C:/Gowin/Gowin_V1.9.9.03_x64/IDE/ipcore/FIFO_HS/data/fifo_hs_top.v"
+`timescale 100 ps/100 ps
+`pragma protect begin_protected
+`pragma protect version="2.3"
+`pragma protect author="default"
+`pragma protect author_info="default"
+`pragma protect encrypt_agent="GOWIN"
+`pragma protect encrypt_agent_info="GOWIN Encrypt Version 2.3"
+
+`pragma protect encoding=(enctype="base64", line_length=76, bytes=256)
+`pragma protect key_keyowner="GOWIN",key_keyname="GWK2023-09",key_method="rsa"
+`pragma protect key_block
+j6k58xrOQ8NiTqxpDvExvVWMNOVIR/lcfZqrbnK1rZSnt+h2pkYESg+2+aOY7tIb67oNaN/2soOE
+ITv8IjkNrSdsNbdZ+Wty97ml+ogpICKi4iMdF99xjcvQl1y1gQtGpW8fqnvb9a8mnGIb4Pa90SnS
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+
+`pragma protect encoding=(enctype="base64", line_length=76, bytes=6288)
+`pragma protect data_keyowner="default-ip-vendor"
+`pragma protect data_keyname="default-ip-key"
+`pragma protect data_method="aes128-cfb"
+`pragma protect data_block
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+PKwDKgs7jfaY4CMfOtbtmffk
+`pragma protect end_protected
+module FifoTfe4Bytes (
+  Data,
+  Reset,
+  WrClk,
+  RdClk,
+  WrEn,
+  RdEn,
+  Q,
+  Empty,
+  Full
+)
+;
+input [31:0] Data;
+input Reset;
+input WrClk;
+input RdClk;
+input WrEn;
+input RdEn;
+output [31:0] Q;
+output Empty;
+output Full;
+wire VCC;
+wire GND;
+  \~fifo.FifoTfe4Bytes  fifo_inst (
+    .Reset(Reset),
+    .RdClk(RdClk),
+    .WrClk(WrClk),
+    .WrEn(WrEn),
+    .RdEn(RdEn),
+    .Data(Data[31:0]),
+    .Empty(Empty),
+    .Full(Full),
+    .Q(Q[31:0])
+);
+  VCC VCC_cZ (
+    .V(VCC)
+);
+  GND GND_cZ (
+    .G(GND)
+);
+  GSR GSR (
+    .GSRI(VCC) 
+);
+endmodule /* FifoTfe4Bytes */

src/src/WrapFifoChain/FifoTfe4Bytes/temp/FIFOHS/FifoTfe4Bytes_syn_resource.html

@@ -0,0 +1,46 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html>
+<head>
+<title>Hierarchy Module Resource</title>
+<style type="text/css">
+body { font-family: Verdana, Arial, sans-serif; font-size: 14px; }
+div#main_wrapper{ width: 100%; }
+h1 {text-align: center; }
+h1 {margin-top: 36px; }
+table, th, td { border: 1px solid #aaa; }
+table { border-collapse:collapse; margin-top: 10px; margin-bottom: 20px; width: 100%; }
+th, td { align = "center"; padding: 5px 2px 5px 5px; }
+th { color: #fff; font-weight: bold; background-color: #0084ff; }
+table td.label { width: 20%; white-space: nowrap; min-width: 20px; background-color: #dee8f4; }
+</style>
+</head>
+<body>
+<div id="main_wrapper">
+<div id="content">
+<h1>Hierarchy Module Resource</h1>
+<table>
+<tr>
+<th class="label">MODULE NAME</th>
+<th class="label">REG NUMBER</th>
+<th class="label">ALU NUMBER</th>
+<th class="label">LUT NUMBER</th>
+<th class="label">DSP NUMBER</th>
+<th class="label">BSRAM NUMBER</th>
+<th class="label">SSRAM NUMBER</th>
+<th class="label">ROM16 NUMBER</th>
+</tr>
+<tr>
+<td class="label">FifoTfe4Bytes (C:/Gowin/Gowin_V1.9.9.03_x64/IDE/ipcore/FIFO_HS/data/fifo_hs_top.v)</td>
+<td align = "center">19</td>
+<td align = "center">-</td>
+<td align = "center">18</td>
+<td align = "center">-</td>
+<td align = "center">1</td>
+<td align = "center">-</td>
+<td align = "center">-</td>
+</tr>
+</table>
+</div><!-- content -->
+</div><!-- main_wrapper -->
+</body>
+</html>

src/src/WrapFifoChain/FifoTfe4Bytes/temp/FIFOHS/FifoTfe4Bytes_syn_rsc.xml

@@ -0,0 +1,2 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<Module name="FifoTfe4Bytes" Register="19" Lut="18" Bsram="1" T_Register="19(19)" T_Lut="18(18)" T_Bsram="1(1)"/>

src/src/WrapFifoChain/FifoTfe4Bytes/temp/FIFOHS/FifoTfe4Bytes_tmp.v

@@ -0,0 +1,24 @@
+//Copyright (C)2014-2024 Gowin Semiconductor Corporation.
+//All rights reserved.
+//File Title: Template file for instantiation
+//Tool Version: V1.9.9.03 (64-bit)
+//Part Number: GW1N-UV9QN88C6/I5
+//Device: GW1N-9
+//Created Time: Fri Nov 22 16:04:43 2024
+
+//Change the instance name and port connections to the signal names
+//--------Copy here to design--------
+
+	FifoTfe4Bytes your_instance_name(
+		.Data(Data), //input [31:0] Data
+		.Reset(Reset), //input Reset
+		.WrClk(WrClk), //input WrClk
+		.RdClk(RdClk), //input RdClk
+		.WrEn(WrEn), //input WrEn
+		.RdEn(RdEn), //input RdEn
+		.Q(Q), //output [31:0] Q
+		.Empty(Empty), //output Empty
+		.Full(Full) //output Full
+	);
+
+//--------Copy end-------------------

src/src/WrapFifoChain/FifoTfe4Bytes/temp/FIFOHS/fifo_define.v

@@ -0,0 +1,5 @@
+`define module_name FifoTfe4Bytes
+`define EBR_BASED
+`define FWFT
+`define En_Reset
+`define Reset_Synchronization

src/src/WrapFifoChain/FifoTfe4Bytes/temp/FIFOHS/fifo_parameter.v

@@ -0,0 +1,6 @@
+parameter WDEPTH = 2;
+parameter ASIZE = 1;
+parameter WDSIZE = 32;
+parameter RDEPTH = 2;
+parameter RASIZE = 1;
+parameter RDSIZE = 32;

src/src/WrapFifoChain/FifoTfe4Bytes/temp/FIFOHS/project.ini

@@ -0,0 +1 @@
+RESOURCE_CHECK=false

src/src/WrapFifoChain/FifoTfe6Bytes/fifo_hs/FifoTfe6Bytes.ipc

@@ -0,0 +1,35 @@
+[General]
+ipc_version=4
+file=FifoTfe6Bytes
+module=FifoTfe6Bytes
+target_device=gw1n9-022
+type=fifo_hs
+version=1.0
+
+[Config]
+AlmostEmptyFlag=false
+AlmostEmptyFlagItem=Empty_Single Threshold Constant Parameter
+AlmostFullFlag=false
+AlmostFullFlagItem=Full_Single Threshold Constant Parameter
+BSRAM=true
+ControlledByRdEn=false
+ECCSelected=false
+EmptyClear=1
+EmptySet=1
+EnReset=true
+FirstWordFallThrough=true
+FullClear=1
+FullSet=1
+LANG=0
+OutputRegistersSelected=false
+REG=false
+ReadDataNum=false
+ReadDataWidth=48
+ReadDepth=2
+ResetSynchronization=true
+SSRAM=false
+StandardFIFO=false
+Synthesis_tool=GowinSynthesis
+WriteDataNum=false
+WriteDataWidth=48
+WriteDepth=2

src/src/WrapFifoChain/FifoTfe6Bytes/fifo_hs/FifoTfe6Bytes.v

@@ -0,0 +1,201 @@
+//
+//Written by GowinSynthesis
+//Tool Version "V1.9.9.03 (64-bit)"
+//Fri Nov 22 16:07:51 2024
+
+//Source file index table:
+//file0 "\C:/Gowin/Gowin_V1.9.9.03_x64/IDE/ipcore/FIFO_HS/data/fifo_hs.v"
+//file1 "\C:/Gowin/Gowin_V1.9.9.03_x64/IDE/ipcore/FIFO_HS/data/fifo_hs_top.v"
+`timescale 100 ps/100 ps
+`pragma protect begin_protected
+`pragma protect version="2.3"
+`pragma protect author="default"
+`pragma protect author_info="default"
+`pragma protect encrypt_agent="GOWIN"
+`pragma protect encrypt_agent_info="GOWIN Encrypt Version 2.3"
+
+`pragma protect encoding=(enctype="base64", line_length=76, bytes=256)
+`pragma protect key_keyowner="GOWIN",key_keyname="GWK2023-09",key_method="rsa"
+`pragma protect key_block
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+
+`pragma protect encoding=(enctype="base64", line_length=76, bytes=7136)
+`pragma protect data_keyowner="default-ip-vendor"
+`pragma protect data_keyname="default-ip-key"
+`pragma protect data_method="aes128-cfb"
+`pragma protect data_block
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+NBPem3oOxNVc6/RSvAcM3ZzFjVwXnc3GOa5xVYFSQeHRJjIVYPzjgRDJcnoEZDBWDSJpW8EhxjcE
+LMCydUYIo9CHSSoY1Aw/xbTDhyY51m7TV37X+Kte7u5YrCjyUJi7zChcj8wqlkIK5Fvv5YEUjTdq
+Dg2LyYg04dhWTQd8afoqV+i25U3sM8Y5a2swZbivXXVLZZCB5KPOS3vzqcM6WKHD41c+TMhSjm2K
+6M1OoRbF3pbaZ0uGFzB+Lh/ac9KYEvL8TiM8DR8KbucOwkpqie5trdXpQZlLr4SCdpSt/8iOOmY+
+std/lcv1FqX4Wk4=
+`pragma protect end_protected
+module FifoTfe6Bytes (
+  Data,
+  Reset,
+  WrClk,
+  RdClk,
+  WrEn,
+  RdEn,
+  Q,
+  Empty,
+  Full
+)
+;
+input [47:0] Data;
+input Reset;
+input WrClk;
+input RdClk;
+input WrEn;
+input RdEn;
+output [47:0] Q;
+output Empty;
+output Full;
+wire VCC;
+wire GND;
+  \~fifo.FifoTfe6Bytes  fifo_inst (
+    .Reset(Reset),
+    .RdClk(RdClk),
+    .WrClk(WrClk),
+    .WrEn(WrEn),
+    .RdEn(RdEn),
+    .Data(Data[47:0]),
+    .Empty(Empty),
+    .Full(Full),
+    .Q(Q[47:0])
+);
+  VCC VCC_cZ (
+    .V(VCC)
+);
+  GND GND_cZ (
+    .G(GND)
+);
+  GSR GSR (
+    .GSRI(VCC) 
+);
+endmodule /* FifoTfe6Bytes */

src/src/WrapFifoChain/FifoTfe6Bytes/fifo_hs/FifoTfe6Bytes.vo

@@ -0,0 +1,374 @@
+//Copyright (C)2014-2024 Gowin Semiconductor Corporation.
+//All rights reserved.
+//File Title: Post-PnR Simulation Model file
+//Tool Version: V1.9.9.03 (64-bit)
+//Created Time: Fri Nov 22 16:07:51 2024
+
+`timescale 100 ps/100 ps
+module FifoTfe6Bytes(
+	Data,
+	Reset,
+	WrClk,
+	RdClk,
+	WrEn,
+	RdEn,
+	Q,
+	Empty,
+	Full
+);
+input [47:0] Data;
+input Reset;
+input WrClk;
+input RdClk;
+input WrEn;
+input RdEn;
+output [47:0] Q;
+output Empty;
+output Full;
+wire [47:0] Data;
+wire Empty;
+wire Full;
+wire GND;
+wire [47:0] Q;
+wire RdClk;
+wire RdEn;
+wire Reset;
+wire VCC;
+wire WrClk;
+wire WrEn;
+wire \fifo_inst/n20_5 ;
+wire \fifo_inst/n26_4 ;
+wire \fifo_inst/n377_4 ;
+wire \fifo_inst/rempty_val ;
+wire \fifo_inst/wfull_val_7 ;
+wire \fifo_inst/wfull_val1 ;
+wire \fifo_inst/wfull_val1_0 ;
+wire \fifo_inst/Full_1 ;
+wire \fifo_inst/Equal.wbinnext_0_7 ;
+wire \fifo_inst/rempty_val_8 ;
+wire \fifo_inst/wfull_val1_2 ;
+wire \fifo_inst/wfull_val1_3 ;
+wire \fifo_inst/Full_1_2 ;
+wire \fifo_inst/Full_2 ;
+wire \fifo_inst/n4_6 ;
+wire \fifo_inst/n9_6 ;
+wire [0:0] \fifo_inst/Equal.rgraynext ;
+wire [0:0] \fifo_inst/Equal.wgraynext ;
+wire [1:0] \fifo_inst/rbin_num_next ;
+wire [1:1] \fifo_inst/Equal.wbinnext ;
+wire [1:0] \fifo_inst/reset_r ;
+wire [1:0] \fifo_inst/reset_w ;
+wire [1:0] \fifo_inst/rbin_num ;
+wire [1:0] \fifo_inst/Equal.rq1_wptr ;
+wire [1:0] \fifo_inst/Equal.rq2_wptr ;
+wire [0:0] \fifo_inst/rptr ;
+wire [1:0] \fifo_inst/wptr ;
+wire [0:0] \fifo_inst/Equal.wbin ;
+wire [31:16] \fifo_inst/DO ;
+VCC VCC_cZ (
+  .V(VCC)
+);
+GND GND_cZ (
+  .G(GND)
+);
+GSR GSR (
+	.GSRI(VCC)
+);
+LUT4 \fifo_inst/n20_s1  (
+	.I0(\fifo_inst/Full_2 ),
+	.I1(\fifo_inst/Full_1_2 ),
+	.I2(\fifo_inst/Full_1 ),
+	.I3(WrEn),
+	.F(\fifo_inst/n20_5 )
+);
+defparam \fifo_inst/n20_s1 .INIT=16'h5300;
+LUT3 \fifo_inst/n26_s1  (
+	.I0(RdEn),
+	.I1(Empty),
+	.I2(\fifo_inst/rempty_val ),
+	.F(\fifo_inst/n26_4 )
+);
+defparam \fifo_inst/n26_s1 .INIT=8'h0E;
+LUT3 \fifo_inst/Equal.rgraynext_0_s0  (
+	.I0(\fifo_inst/rbin_num [0]),
+	.I1(\fifo_inst/rbin_num_next [0]),
+	.I2(\fifo_inst/rbin_num [1]),
+	.F(\fifo_inst/Equal.rgraynext [0])
+);
+defparam \fifo_inst/Equal.rgraynext_0_s0 .INIT=8'h1E;
+LUT3 \fifo_inst/Equal.wgraynext_0_s0  (
+	.I0(\fifo_inst/Equal.wbin [0]),
+	.I1(\fifo_inst/n20_5 ),
+	.I2(\fifo_inst/wptr [1]),
+	.F(\fifo_inst/Equal.wgraynext [0])
+);
+defparam \fifo_inst/Equal.wgraynext_0_s0 .INIT=8'h1E;
+LUT2 \fifo_inst/n377_s1  (
+	.I0(\fifo_inst/reset_w [1]),
+	.I1(\fifo_inst/wfull_val_7 ),
+	.F(\fifo_inst/n377_4 )
+);
+defparam \fifo_inst/n377_s1 .INIT=4'h4;
+LUT4 \fifo_inst/rempty_val_s3  (
+	.I0(\fifo_inst/Equal.rq2_wptr [1]),
+	.I1(\fifo_inst/rempty_val_8 ),
+	.I2(\fifo_inst/Equal.rq2_wptr [0]),
+	.I3(\fifo_inst/rbin_num_next [0]),
+	.F(\fifo_inst/rempty_val )
+);
+defparam \fifo_inst/rempty_val_s3 .INIT=16'h4221;
+LUT4 \fifo_inst/wfull_val_s3  (
+	.I0(\fifo_inst/wptr [0]),
+	.I1(\fifo_inst/wptr [1]),
+	.I2(\fifo_inst/rbin_num [1]),
+	.I3(\fifo_inst/rptr [0]),
+	.F(\fifo_inst/wfull_val_7 )
+);
+defparam \fifo_inst/wfull_val_s3 .INIT=16'h1428;
+LUT3 \fifo_inst/wfull_val1_s9  (
+	.I0(\fifo_inst/wfull_val1_3 ),
+	.I1(\fifo_inst/wfull_val1_2 ),
+	.I2(\fifo_inst/wfull_val1_0 ),
+	.F(\fifo_inst/wfull_val1 )
+);
+defparam \fifo_inst/wfull_val1_s9 .INIT=8'hAC;
+LUT3 \fifo_inst/wfull_val1_s10  (
+	.I0(\fifo_inst/wfull_val_7 ),
+	.I1(\fifo_inst/wfull_val1_0 ),
+	.I2(\fifo_inst/reset_w [1]),
+	.F(\fifo_inst/wfull_val1_0 )
+);
+defparam \fifo_inst/wfull_val1_s10 .INIT=8'h0E;
+LUT3 \fifo_inst/Full_d_s  (
+	.I0(\fifo_inst/Full_2 ),
+	.I1(\fifo_inst/Full_1_2 ),
+	.I2(\fifo_inst/Full_1 ),
+	.F(Full)
+);
+defparam \fifo_inst/Full_d_s .INIT=8'hAC;
+LUT3 \fifo_inst/Full_s8  (
+	.I0(\fifo_inst/wfull_val_7 ),
+	.I1(\fifo_inst/Full_1 ),
+	.I2(\fifo_inst/reset_w [1]),
+	.F(\fifo_inst/Full_1 )
+);
+defparam \fifo_inst/Full_s8 .INIT=8'h0E;
+LUT3 \fifo_inst/rbin_num_next_0_s5  (
+	.I0(Empty),
+	.I1(RdEn),
+	.I2(\fifo_inst/rbin_num [0]),
+	.F(\fifo_inst/rbin_num_next [0])
+);
+defparam \fifo_inst/rbin_num_next_0_s5 .INIT=8'hB4;
+LUT3 \fifo_inst/rbin_num_next_1_s2  (
+	.I0(\fifo_inst/rbin_num_next [0]),
+	.I1(\fifo_inst/rbin_num [0]),
+	.I2(\fifo_inst/rbin_num [1]),
+	.F(\fifo_inst/rbin_num_next [1])
+);
+defparam \fifo_inst/rbin_num_next_1_s2 .INIT=8'hB4;
+LUT2 \fifo_inst/Equal.wbinnext_0_s3  (
+	.I0(\fifo_inst/Equal.wbin [0]),
+	.I1(\fifo_inst/n20_5 ),
+	.F(\fifo_inst/Equal.wbinnext_0_7 )
+);
+defparam \fifo_inst/Equal.wbinnext_0_s3 .INIT=4'h6;
+LUT3 \fifo_inst/Equal.wbinnext_1_s2  (
+	.I0(\fifo_inst/Equal.wbin [0]),
+	.I1(\fifo_inst/n20_5 ),
+	.I2(\fifo_inst/wptr [1]),
+	.F(\fifo_inst/Equal.wbinnext [1])
+);
+defparam \fifo_inst/Equal.wbinnext_1_s2 .INIT=8'h78;
+LUT4 \fifo_inst/rempty_val_s4  (
+	.I0(\fifo_inst/Equal.rq2_wptr [0]),
+	.I1(\fifo_inst/Equal.rq2_wptr [1]),
+	.I2(\fifo_inst/rbin_num [1]),
+	.I3(\fifo_inst/rbin_num [0]),
+	.F(\fifo_inst/rempty_val_8 )
+);
+defparam \fifo_inst/rempty_val_s4 .INIT=16'h871E;
+DFFP \fifo_inst/reset_r_0_s0  (
+	.D(GND),
+	.CLK(\fifo_inst/n4_6 ),
+	.PRESET(Reset),
+	.Q(\fifo_inst/reset_r [0])
+);
+defparam \fifo_inst/reset_r_0_s0 .INIT=1'b1;
+DFFP \fifo_inst/reset_w_1_s0  (
+	.D(\fifo_inst/reset_w [0]),
+	.CLK(\fifo_inst/n9_6 ),
+	.PRESET(Reset),
+	.Q(\fifo_inst/reset_w [1])
+);
+defparam \fifo_inst/reset_w_1_s0 .INIT=1'b1;
+DFFP \fifo_inst/reset_w_0_s0  (
+	.D(GND),
+	.CLK(\fifo_inst/n9_6 ),
+	.PRESET(Reset),
+	.Q(\fifo_inst/reset_w [0])
+);
+defparam \fifo_inst/reset_w_0_s0 .INIT=1'b1;
+DFFC \fifo_inst/rbin_num_1_s0  (
+	.D(\fifo_inst/rbin_num_next [1]),
+	.CLK(RdClk),
+	.CLEAR(\fifo_inst/reset_r [1]),
+	.Q(\fifo_inst/rbin_num [1])
+);
+defparam \fifo_inst/rbin_num_1_s0 .INIT=1'b0;
+DFFC \fifo_inst/rbin_num_0_s0  (
+	.D(\fifo_inst/rbin_num_next [0]),
+	.CLK(RdClk),
+	.CLEAR(\fifo_inst/reset_r [1]),
+	.Q(\fifo_inst/rbin_num [0])
+);
+defparam \fifo_inst/rbin_num_0_s0 .INIT=1'b0;
+DFFC \fifo_inst/Equal.rq1_wptr_1_s0  (
+	.D(\fifo_inst/wptr [1]),
+	.CLK(RdClk),
+	.CLEAR(\fifo_inst/reset_r [1]),
+	.Q(\fifo_inst/Equal.rq1_wptr [1])
+);
+defparam \fifo_inst/Equal.rq1_wptr_1_s0 .INIT=1'b0;
+DFFC \fifo_inst/Equal.rq1_wptr_0_s0  (
+	.D(\fifo_inst/wptr [0]),
+	.CLK(RdClk),
+	.CLEAR(\fifo_inst/reset_r [1]),
+	.Q(\fifo_inst/Equal.rq1_wptr [0])
+);
+defparam \fifo_inst/Equal.rq1_wptr_0_s0 .INIT=1'b0;
+DFFC \fifo_inst/Equal.rq2_wptr_1_s0  (
+	.D(\fifo_inst/Equal.rq1_wptr [1]),
+	.CLK(RdClk),
+	.CLEAR(\fifo_inst/reset_r [1]),
+	.Q(\fifo_inst/Equal.rq2_wptr [1])
+);
+defparam \fifo_inst/Equal.rq2_wptr_1_s0 .INIT=1'b0;
+DFFC \fifo_inst/Equal.rq2_wptr_0_s0  (
+	.D(\fifo_inst/Equal.rq1_wptr [0]),
+	.CLK(RdClk),
+	.CLEAR(\fifo_inst/reset_r [1]),
+	.Q(\fifo_inst/Equal.rq2_wptr [0])
+);
+defparam \fifo_inst/Equal.rq2_wptr_0_s0 .INIT=1'b0;
+DFFC \fifo_inst/rptr_0_s0  (
+	.D(\fifo_inst/Equal.rgraynext [0]),
+	.CLK(RdClk),
+	.CLEAR(\fifo_inst/reset_r [1]),
+	.Q(\fifo_inst/rptr [0])
+);
+defparam \fifo_inst/rptr_0_s0 .INIT=1'b0;
+DFFC \fifo_inst/wptr_1_s0  (
+	.D(\fifo_inst/Equal.wbinnext [1]),
+	.CLK(WrClk),
+	.CLEAR(\fifo_inst/reset_w [1]),
+	.Q(\fifo_inst/wptr [1])
+);
+defparam \fifo_inst/wptr_1_s0 .INIT=1'b0;
+DFFC \fifo_inst/wptr_0_s0  (
+	.D(\fifo_inst/Equal.wgraynext [0]),
+	.CLK(WrClk),
+	.CLEAR(\fifo_inst/reset_w [1]),
+	.Q(\fifo_inst/wptr [0])
+);
+defparam \fifo_inst/wptr_0_s0 .INIT=1'b0;
+DFFC \fifo_inst/Equal.wbin_0_s0  (
+	.D(\fifo_inst/Equal.wbinnext_0_7 ),
+	.CLK(WrClk),
+	.CLEAR(\fifo_inst/reset_w [1]),
+	.Q(\fifo_inst/Equal.wbin [0])
+);
+defparam \fifo_inst/Equal.wbin_0_s0 .INIT=1'b0;
+DFFP \fifo_inst/Empty_s0  (
+	.D(\fifo_inst/rempty_val ),
+	.CLK(RdClk),
+	.PRESET(\fifo_inst/reset_r [1]),
+	.Q(Empty)
+);
+defparam \fifo_inst/Empty_s0 .INIT=1'b1;
+DFFP \fifo_inst/reset_r_1_s0  (
+	.D(\fifo_inst/reset_r [0]),
+	.CLK(\fifo_inst/n4_6 ),
+	.PRESET(Reset),
+	.Q(\fifo_inst/reset_r [1])
+);
+defparam \fifo_inst/reset_r_1_s0 .INIT=1'b1;
+DFFC \fifo_inst/wfull_val1_s0  (
+	.D(\fifo_inst/wfull_val_7 ),
+	.CLK(WrClk),
+	.CLEAR(\fifo_inst/reset_w [1]),
+	.Q(\fifo_inst/wfull_val1_2 )
+);
+defparam \fifo_inst/wfull_val1_s0 .INIT=1'b0;
+DFFP \fifo_inst/wfull_val1_s1  (
+	.D(\fifo_inst/wfull_val_7 ),
+	.CLK(WrClk),
+	.PRESET(\fifo_inst/n377_4 ),
+	.Q(\fifo_inst/wfull_val1_3 )
+);
+defparam \fifo_inst/wfull_val1_s1 .INIT=1'b1;
+DFFC \fifo_inst/Full_s0  (
+	.D(\fifo_inst/wfull_val1 ),
+	.CLK(WrClk),
+	.CLEAR(\fifo_inst/reset_w [1]),
+	.Q(\fifo_inst/Full_1_2 )
+);
+defparam \fifo_inst/Full_s0 .INIT=1'b0;
+DFFP \fifo_inst/Full_s1  (
+	.D(\fifo_inst/wfull_val1 ),
+	.CLK(WrClk),
+	.PRESET(\fifo_inst/n377_4 ),
+	.Q(\fifo_inst/Full_2 )
+);
+defparam \fifo_inst/Full_s1 .INIT=1'b1;
+SDPB \fifo_inst/Equal.mem_Equal.mem_0_0_s  (
+	.CLKA(WrClk),
+	.CEA(\fifo_inst/n20_5 ),
+	.RESETA(GND),
+	.CLKB(RdClk),
+	.CEB(\fifo_inst/n26_4 ),
+	.RESETB(\fifo_inst/reset_r [1]),
+	.OCE(GND),
+	.BLKSELA({GND, GND, GND}),
+	.BLKSELB({GND, GND, GND}),
+	.DI({Data[31:0]}),
+	.ADA({GND, GND, GND, GND, GND, GND, GND, GND, \fifo_inst/Equal.wbin [0], GND, VCC, VCC, VCC, VCC}),
+	.ADB({GND, GND, GND, GND, GND, GND, GND, GND, \fifo_inst/rbin_num_next [0], GND, GND, GND, GND, GND}),
+	.DO({Q[31:0]})
+);
+defparam \fifo_inst/Equal.mem_Equal.mem_0_0_s .READ_MODE=1'b0;
+defparam \fifo_inst/Equal.mem_Equal.mem_0_0_s .BIT_WIDTH_0=32;
+defparam \fifo_inst/Equal.mem_Equal.mem_0_0_s .BIT_WIDTH_1=32;
+defparam \fifo_inst/Equal.mem_Equal.mem_0_0_s .RESET_MODE="ASYNC";
+defparam \fifo_inst/Equal.mem_Equal.mem_0_0_s .BLK_SEL_0=3'b000;
+defparam \fifo_inst/Equal.mem_Equal.mem_0_0_s .BLK_SEL_1=3'b000;
+SDPB \fifo_inst/Equal.mem_Equal.mem_0_1_s  (
+	.CLKA(WrClk),
+	.CEA(\fifo_inst/n20_5 ),
+	.RESETA(GND),
+	.CLKB(RdClk),
+	.CEB(\fifo_inst/n26_4 ),
+	.RESETB(\fifo_inst/reset_r [1]),
+	.OCE(GND),
+	.BLKSELA({GND, GND, GND}),
+	.BLKSELB({GND, GND, GND}),
+	.DI({GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, Data[47:32]}),
+	.ADA({GND, GND, GND, GND, GND, GND, GND, GND, \fifo_inst/Equal.wbin [0], GND, VCC, VCC, VCC, VCC}),
+	.ADB({GND, GND, GND, GND, GND, GND, GND, GND, \fifo_inst/rbin_num_next [0], GND, GND, GND, GND, GND}),
+	.DO({\fifo_inst/DO [31:16], Q[47:32]})
+);
+defparam \fifo_inst/Equal.mem_Equal.mem_0_1_s .READ_MODE=1'b0;
+defparam \fifo_inst/Equal.mem_Equal.mem_0_1_s .BIT_WIDTH_0=32;
+defparam \fifo_inst/Equal.mem_Equal.mem_0_1_s .BIT_WIDTH_1=32;
+defparam \fifo_inst/Equal.mem_Equal.mem_0_1_s .RESET_MODE="ASYNC";
+defparam \fifo_inst/Equal.mem_Equal.mem_0_1_s .BLK_SEL_0=3'b000;
+defparam \fifo_inst/Equal.mem_Equal.mem_0_1_s .BLK_SEL_1=3'b000;
+INV \fifo_inst/n4_s2  (
+	.I(RdClk),
+	.O(\fifo_inst/n4_6 )
+);
+INV \fifo_inst/n9_s2  (
+	.I(WrClk),
+	.O(\fifo_inst/n9_6 )
+);
+endmodule

src/src/WrapFifoChain/FifoTfe6Bytes/fifo_hs/FifoTfe6Bytes_tmp.v

@@ -0,0 +1,24 @@
+//Copyright (C)2014-2024 Gowin Semiconductor Corporation.
+//All rights reserved.
+//File Title: Template file for instantiation
+//Tool Version: V1.9.9.03 (64-bit)
+//Part Number: GW1N-UV9QN88C6/I5
+//Device: GW1N-9
+//Created Time: Fri Nov 22 16:07:51 2024
+
+//Change the instance name and port connections to the signal names
+//--------Copy here to design--------
+
+	FifoTfe6Bytes your_instance_name(
+		.Data(Data), //input [47:0] Data
+		.Reset(Reset), //input Reset
+		.WrClk(WrClk), //input WrClk
+		.RdClk(RdClk), //input RdClk
+		.WrEn(WrEn), //input WrEn
+		.RdEn(RdEn), //input RdEn
+		.Q(Q), //output [47:0] Q
+		.Empty(Empty), //output Empty
+		.Full(Full) //output Full
+	);
+
+//--------Copy end-------------------

src/src/WrapFifoChain/FifoTfe6Bytes/fifo_hs/temp/FIFOHS/FIFOHS.prj

@@ -0,0 +1,20 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!DOCTYPE gowin-synthesis-project>
+<Project>
+    <Version>beta</Version>
+    <Device id="GW1N-9" package="QFN88" speed="6" partNumber="GW1N-UV9QN88C6/I5"/>
+    <FileList>
+        <File path="C:/Gowin/Gowin_V1.9.9.03_x64/IDE/ipcore/FIFO_HS/data/fifo_hs.v" type="verilog"/>
+        <File path="C:/Gowin/Gowin_V1.9.9.03_x64/IDE/ipcore/FIFO_HS/data/fifo_hs_top.v" type="verilog"/>
+    </FileList>
+    <OptionList>
+        <Option type="disable_insert_pad" value="1"/>
+        <Option type="include_path" value="C:/Gowin/Gowin_V1.9.9.03_x64/IDE/ipcore/FIFO_HS/data"/>
+        <Option type="include_path" value="C:/Gowin/Projects/BOCHv3_FPGA/src/src/WrapFifoChain/FifoTfe6Bytes/fifo_hs/temp/FIFOHS"/>
+        <Option type="output_file" value="FifoTfe6Bytes.vg"/>
+        <Option type="output_template" value="FifoTfe6Bytes_tmp.v"/>
+        <Option type="ram_balance" value="1"/>
+        <Option type="ram_rw_check" value="1"/>
+        <Option type="verilog_language" value="sysv-2017"/>
+    </OptionList>
+</Project>

src/src/WrapFifoChain/FifoTfe6Bytes/fifo_hs/temp/FIFOHS/FifoTfe6Bytes.log

@@ -0,0 +1,45 @@
+GowinSynthesis start
+Running parser ...
+Analyzing Verilog file 'C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v'
+Analyzing included file '**'("C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Back to file '**'("C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Undeclared symbol '**', assumed default net type '**'("C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Analyzing Verilog file 'C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v'
+Analyzing included file 'fifo_define.v'("C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":1)
+Back to file 'C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v'("C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":1)
+Analyzing included file 'C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\static_macro_define.v'("C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":2)
+Back to file 'C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v'("C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":2)
+Analyzing included file 'fifo_parameter.v'("C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":57)
+Back to file 'C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v'("C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":57)
+Compiling module 'FifoTfe6Bytes'("C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":4)
+Compiling module '**'("C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Extracting RAM for identifier '**'("C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+NOTE  (EX0101) : Current top module is "FifoTfe6Bytes"
+[5%] Running netlist conversion ...
+Running device independent optimization ...
+[10%] Optimizing Phase 0 completed
+[15%] Optimizing Phase 1 completed
+[25%] Optimizing Phase 2 completed
+Running inference ...
+[30%] Inferring Phase 0 completed
+[40%] Inferring Phase 1 completed
+[50%] Inferring Phase 2 completed
+[55%] Inferring Phase 3 completed
+Running technical mapping ...
+[60%] Tech-Mapping Phase 0 completed
+[65%] Tech-Mapping Phase 1 completed
+[75%] Tech-Mapping Phase 2 completed
+WARN  (AG0100) : Find logical loop signal : "fifo_inst/wfull_val1_s3"("C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+WARN  (AG0100) : Find logical loop signal : "fifo_inst/wfull_val1_s6"("C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+WARN  (AG0100) : Find logical loop signal : "fifo_inst/wfull_val1_s3"("C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+WARN  (AG0101) : The netlist is not one directed acyclic graph
+WARN  (AG0100) : Find logical loop signal : "fifo_inst/Full_s3"("C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+WARN  (AG0100) : Find logical loop signal : "fifo_inst/Full_s6"("C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+WARN  (AG0100) : Find logical loop signal : "fifo_inst/Full_s3"("C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+WARN  (AG0101) : The netlist is not one directed acyclic graph
+[80%] Tech-Mapping Phase 3 completed
+[90%] Tech-Mapping Phase 4 completed
+[95%] Generate netlist file "C:\Gowin\Projects\BOCHv3_FPGA\src\src\WrapFifoChain\FifoTfe6Bytes\fifo_hs\temp\FIFOHS\FifoTfe6Bytes.vg" completed
+Generate template file "C:\Gowin\Projects\BOCHv3_FPGA\src\src\WrapFifoChain\FifoTfe6Bytes\fifo_hs\temp\FIFOHS\FifoTfe6Bytes_tmp.v" completed
+[100%] Generate report file "C:\Gowin\Projects\BOCHv3_FPGA\src\src\WrapFifoChain\FifoTfe6Bytes\fifo_hs\temp\FIFOHS\FifoTfe6Bytes_syn.rpt.html" completed
+GowinSynthesis finish

src/src/WrapFifoChain/FifoTfe6Bytes/fifo_hs/temp/FIFOHS/FifoTfe6Bytes.vg

@@ -0,0 +1,201 @@
+//
+//Written by GowinSynthesis
+//Tool Version "V1.9.9.03 (64-bit)"
+//Fri Nov 22 16:07:51 2024
+
+//Source file index table:
+//file0 "\C:/Gowin/Gowin_V1.9.9.03_x64/IDE/ipcore/FIFO_HS/data/fifo_hs.v"
+//file1 "\C:/Gowin/Gowin_V1.9.9.03_x64/IDE/ipcore/FIFO_HS/data/fifo_hs_top.v"
+`timescale 100 ps/100 ps
+`pragma protect begin_protected
+`pragma protect version="2.3"
+`pragma protect author="default"
+`pragma protect author_info="default"
+`pragma protect encrypt_agent="GOWIN"
+`pragma protect encrypt_agent_info="GOWIN Encrypt Version 2.3"
+
+`pragma protect encoding=(enctype="base64", line_length=76, bytes=256)
+`pragma protect key_keyowner="GOWIN",key_keyname="GWK2023-09",key_method="rsa"
+`pragma protect key_block
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+TMz6WSobcGnS0P51nPOCv6H7tiXNIwziR7+ekg==
+
+`pragma protect encoding=(enctype="base64", line_length=76, bytes=7136)
+`pragma protect data_keyowner="default-ip-vendor"
+`pragma protect data_keyname="default-ip-key"
+`pragma protect data_method="aes128-cfb"
+`pragma protect data_block
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+std/lcv1FqX4Wk4=
+`pragma protect end_protected
+module FifoTfe6Bytes (
+  Data,
+  Reset,
+  WrClk,
+  RdClk,
+  WrEn,
+  RdEn,
+  Q,
+  Empty,
+  Full
+)
+;
+input [47:0] Data;
+input Reset;
+input WrClk;
+input RdClk;
+input WrEn;
+input RdEn;
+output [47:0] Q;
+output Empty;
+output Full;
+wire VCC;
+wire GND;
+  \~fifo.FifoTfe6Bytes  fifo_inst (
+    .Reset(Reset),
+    .RdClk(RdClk),
+    .WrClk(WrClk),
+    .WrEn(WrEn),
+    .RdEn(RdEn),
+    .Data(Data[47:0]),
+    .Empty(Empty),
+    .Full(Full),
+    .Q(Q[47:0])
+);
+  VCC VCC_cZ (
+    .V(VCC)
+);
+  GND GND_cZ (
+    .G(GND)
+);
+  GSR GSR (
+    .GSRI(VCC) 
+);
+endmodule /* FifoTfe6Bytes */

src/src/WrapFifoChain/FifoTfe6Bytes/fifo_hs/temp/FIFOHS/FifoTfe6Bytes_syn_resource.html

@@ -0,0 +1,46 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html>
+<head>
+<title>Hierarchy Module Resource</title>
+<style type="text/css">
+body { font-family: Verdana, Arial, sans-serif; font-size: 14px; }
+div#main_wrapper{ width: 100%; }
+h1 {text-align: center; }
+h1 {margin-top: 36px; }
+table, th, td { border: 1px solid #aaa; }
+table { border-collapse:collapse; margin-top: 10px; margin-bottom: 20px; width: 100%; }
+th, td { align = "center"; padding: 5px 2px 5px 5px; }
+th { color: #fff; font-weight: bold; background-color: #0084ff; }
+table td.label { width: 20%; white-space: nowrap; min-width: 20px; background-color: #dee8f4; }
+</style>
+</head>
+<body>
+<div id="main_wrapper">
+<div id="content">
+<h1>Hierarchy Module Resource</h1>
+<table>
+<tr>
+<th class="label">MODULE NAME</th>
+<th class="label">REG NUMBER</th>
+<th class="label">ALU NUMBER</th>
+<th class="label">LUT NUMBER</th>
+<th class="label">DSP NUMBER</th>
+<th class="label">BSRAM NUMBER</th>
+<th class="label">SSRAM NUMBER</th>
+<th class="label">ROM16 NUMBER</th>
+</tr>
+<tr>
+<td class="label">FifoTfe6Bytes (C:/Gowin/Gowin_V1.9.9.03_x64/IDE/ipcore/FIFO_HS/data/fifo_hs_top.v)</td>
+<td align = "center">19</td>
+<td align = "center">-</td>
+<td align = "center">18</td>
+<td align = "center">-</td>
+<td align = "center">2</td>
+<td align = "center">-</td>
+<td align = "center">-</td>
+</tr>
+</table>
+</div><!-- content -->
+</div><!-- main_wrapper -->
+</body>
+</html>

src/src/WrapFifoChain/FifoTfe6Bytes/fifo_hs/temp/FIFOHS/FifoTfe6Bytes_syn_rsc.xml

@@ -0,0 +1,2 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<Module name="FifoTfe6Bytes" Register="19" Lut="18" Bsram="2" T_Register="19(19)" T_Lut="18(18)" T_Bsram="2(2)"/>

src/src/WrapFifoChain/FifoTfe6Bytes/fifo_hs/temp/FIFOHS/FifoTfe6Bytes_tmp.v

@@ -0,0 +1,24 @@
+//Copyright (C)2014-2024 Gowin Semiconductor Corporation.
+//All rights reserved.
+//File Title: Template file for instantiation
+//Tool Version: V1.9.9.03 (64-bit)
+//Part Number: GW1N-UV9QN88C6/I5
+//Device: GW1N-9
+//Created Time: Fri Nov 22 16:07:51 2024
+
+//Change the instance name and port connections to the signal names
+//--------Copy here to design--------
+
+	FifoTfe6Bytes your_instance_name(
+		.Data(Data), //input [47:0] Data
+		.Reset(Reset), //input Reset
+		.WrClk(WrClk), //input WrClk
+		.RdClk(RdClk), //input RdClk
+		.WrEn(WrEn), //input WrEn
+		.RdEn(RdEn), //input RdEn
+		.Q(Q), //output [47:0] Q
+		.Empty(Empty), //output Empty
+		.Full(Full) //output Full
+	);
+
+//--------Copy end-------------------

src/src/WrapFifoChain/FifoTfe6Bytes/fifo_hs/temp/FIFOHS/fifo_define.v

@@ -0,0 +1,5 @@
+`define module_name FifoTfe6Bytes
+`define EBR_BASED
+`define FWFT
+`define En_Reset
+`define Reset_Synchronization

src/src/WrapFifoChain/FifoTfe6Bytes/fifo_hs/temp/FIFOHS/fifo_parameter.v

@@ -0,0 +1,6 @@
+parameter WDEPTH = 2;
+parameter ASIZE = 1;
+parameter WDSIZE = 48;
+parameter RDEPTH = 2;
+parameter RASIZE = 1;
+parameter RDSIZE = 48;

src/src/WrapFifoChain/FifoTfe6Bytes/fifo_hs/temp/FIFOHS/project.ini

@@ -0,0 +1 @@
+RESOURCE_CHECK=false

src/src/WrapFifoChain/FifoTfe7Bytes/FifoTfe7Bytes.ipc

@@ -0,0 +1,35 @@
+[General]
+ipc_version=4
+file=FifoTfe7Bytes
+module=FifoTfe2Bytes
+target_device=gw1n9-022
+type=fifo_hs
+version=1.0
+
+[Config]
+AlmostEmptyFlag=false
+AlmostEmptyFlagItem=Empty_Single Threshold Constant Parameter
+AlmostFullFlag=false
+AlmostFullFlagItem=Full_Dual Threshold Constant Parameter
+BSRAM=true
+ControlledByRdEn=false
+ECCSelected=false
+EmptyClear=1
+EmptySet=1
+EnReset=true
+FirstWordFallThrough=true
+FullClear=1
+FullSet=1
+LANG=0
+OutputRegistersSelected=false
+REG=false
+ReadDataNum=false
+ReadDataWidth=56
+ReadDepth=2
+ResetSynchronization=true
+SSRAM=false
+StandardFIFO=false
+Synthesis_tool=GowinSynthesis
+WriteDataNum=false
+WriteDataWidth=56
+WriteDepth=2

src/src/WrapFifoChain/FifoTfe7Bytes/FifoTfe7Bytes.v

@@ -0,0 +1,200 @@
+//
+//Written by GowinSynthesis
+//Tool Version "V1.9.9.03 (64-bit)"
+//Fri Nov 22 16:10:39 2024
+
+//Source file index table:
+//file0 "\C:/Gowin/Gowin_V1.9.9.03_x64/IDE/ipcore/FIFO_HS/data/fifo_hs.v"
+//file1 "\C:/Gowin/Gowin_V1.9.9.03_x64/IDE/ipcore/FIFO_HS/data/fifo_hs_top.v"
+`timescale 100 ps/100 ps
+`pragma protect begin_protected
+`pragma protect version="2.3"
+`pragma protect author="default"
+`pragma protect author_info="default"
+`pragma protect encrypt_agent="GOWIN"
+`pragma protect encrypt_agent_info="GOWIN Encrypt Version 2.3"
+
+`pragma protect encoding=(enctype="base64", line_length=76, bytes=256)
+`pragma protect key_keyowner="GOWIN",key_keyname="GWK2023-09",key_method="rsa"
+`pragma protect key_block
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++pfQH0mMgLnxdZ7w6KkL07UfaqpA4YTfcqQl7w==
+
+`pragma protect encoding=(enctype="base64", line_length=76, bytes=7104)
+`pragma protect data_keyowner="default-ip-vendor"
+`pragma protect data_keyname="default-ip-key"
+`pragma protect data_method="aes128-cfb"
+`pragma protect data_block
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+12+CYCxkZq2f7KWis+57wQF8vtTcMM397pEbkTnsWcQqjnyd
+`pragma protect end_protected
+module FifoTfe2Bytes (
+  Data,
+  Reset,
+  WrClk,
+  RdClk,
+  WrEn,
+  RdEn,
+  Q,
+  Empty,
+  Full
+)
+;
+input [55:0] Data;
+input Reset;
+input WrClk;
+input RdClk;
+input WrEn;
+input RdEn;
+output [55:0] Q;
+output Empty;
+output Full;
+wire VCC;
+wire GND;
+  \~fifo.FifoTfe2Bytes  fifo_inst (
+    .Reset(Reset),
+    .RdClk(RdClk),
+    .WrClk(WrClk),
+    .WrEn(WrEn),
+    .RdEn(RdEn),
+    .Data(Data[55:0]),
+    .Empty(Empty),
+    .Full(Full),
+    .Q(Q[55:0])
+);
+  VCC VCC_cZ (
+    .V(VCC)
+);
+  GND GND_cZ (
+    .G(GND)
+);
+  GSR GSR (
+    .GSRI(VCC) 
+);
+endmodule /* FifoTfe2Bytes */

src/src/WrapFifoChain/FifoTfe7Bytes/FifoTfe7Bytes.vo

@@ -0,0 +1,374 @@
+//Copyright (C)2014-2024 Gowin Semiconductor Corporation.
+//All rights reserved.
+//File Title: Post-PnR Simulation Model file
+//Tool Version: V1.9.9.03 (64-bit)
+//Created Time: Fri Nov 22 16:10:39 2024
+
+`timescale 100 ps/100 ps
+module FifoTfe2Bytes(
+	Data,
+	Reset,
+	WrClk,
+	RdClk,
+	WrEn,
+	RdEn,
+	Q,
+	Empty,
+	Full
+);
+input [55:0] Data;
+input Reset;
+input WrClk;
+input RdClk;
+input WrEn;
+input RdEn;
+output [55:0] Q;
+output Empty;
+output Full;
+wire [55:0] Data;
+wire Empty;
+wire Full;
+wire GND;
+wire [55:0] Q;
+wire RdClk;
+wire RdEn;
+wire Reset;
+wire VCC;
+wire WrClk;
+wire WrEn;
+wire \fifo_inst/n20_5 ;
+wire \fifo_inst/n26_4 ;
+wire \fifo_inst/n417_4 ;
+wire \fifo_inst/rempty_val ;
+wire \fifo_inst/wfull_val_7 ;
+wire \fifo_inst/wfull_val1 ;
+wire \fifo_inst/wfull_val1_0 ;
+wire \fifo_inst/Full_1 ;
+wire \fifo_inst/Equal.wbinnext_0_7 ;
+wire \fifo_inst/rempty_val_8 ;
+wire \fifo_inst/wfull_val1_2 ;
+wire \fifo_inst/wfull_val1_3 ;
+wire \fifo_inst/Full_1_2 ;
+wire \fifo_inst/Full_2 ;
+wire \fifo_inst/n4_6 ;
+wire \fifo_inst/n9_6 ;
+wire [0:0] \fifo_inst/Equal.rgraynext ;
+wire [0:0] \fifo_inst/Equal.wgraynext ;
+wire [1:0] \fifo_inst/rbin_num_next ;
+wire [1:1] \fifo_inst/Equal.wbinnext ;
+wire [1:0] \fifo_inst/reset_r ;
+wire [1:0] \fifo_inst/reset_w ;
+wire [1:0] \fifo_inst/rbin_num ;
+wire [1:0] \fifo_inst/Equal.rq1_wptr ;
+wire [1:0] \fifo_inst/Equal.rq2_wptr ;
+wire [0:0] \fifo_inst/rptr ;
+wire [1:0] \fifo_inst/wptr ;
+wire [0:0] \fifo_inst/Equal.wbin ;
+wire [31:24] \fifo_inst/DO ;
+VCC VCC_cZ (
+  .V(VCC)
+);
+GND GND_cZ (
+  .G(GND)
+);
+GSR GSR (
+	.GSRI(VCC)
+);
+LUT4 \fifo_inst/n20_s1  (
+	.I0(\fifo_inst/Full_2 ),
+	.I1(\fifo_inst/Full_1_2 ),
+	.I2(\fifo_inst/Full_1 ),
+	.I3(WrEn),
+	.F(\fifo_inst/n20_5 )
+);
+defparam \fifo_inst/n20_s1 .INIT=16'h5300;
+LUT3 \fifo_inst/n26_s1  (
+	.I0(RdEn),
+	.I1(Empty),
+	.I2(\fifo_inst/rempty_val ),
+	.F(\fifo_inst/n26_4 )
+);
+defparam \fifo_inst/n26_s1 .INIT=8'h0E;
+LUT3 \fifo_inst/Equal.rgraynext_0_s0  (
+	.I0(\fifo_inst/rbin_num [0]),
+	.I1(\fifo_inst/rbin_num_next [0]),
+	.I2(\fifo_inst/rbin_num [1]),
+	.F(\fifo_inst/Equal.rgraynext [0])
+);
+defparam \fifo_inst/Equal.rgraynext_0_s0 .INIT=8'h1E;
+LUT3 \fifo_inst/Equal.wgraynext_0_s0  (
+	.I0(\fifo_inst/Equal.wbin [0]),
+	.I1(\fifo_inst/n20_5 ),
+	.I2(\fifo_inst/wptr [1]),
+	.F(\fifo_inst/Equal.wgraynext [0])
+);
+defparam \fifo_inst/Equal.wgraynext_0_s0 .INIT=8'h1E;
+LUT2 \fifo_inst/n417_s1  (
+	.I0(\fifo_inst/reset_w [1]),
+	.I1(\fifo_inst/wfull_val_7 ),
+	.F(\fifo_inst/n417_4 )
+);
+defparam \fifo_inst/n417_s1 .INIT=4'h4;
+LUT4 \fifo_inst/rempty_val_s3  (
+	.I0(\fifo_inst/Equal.rq2_wptr [1]),
+	.I1(\fifo_inst/rempty_val_8 ),
+	.I2(\fifo_inst/Equal.rq2_wptr [0]),
+	.I3(\fifo_inst/rbin_num_next [0]),
+	.F(\fifo_inst/rempty_val )
+);
+defparam \fifo_inst/rempty_val_s3 .INIT=16'h4221;
+LUT4 \fifo_inst/wfull_val_s3  (
+	.I0(\fifo_inst/wptr [0]),
+	.I1(\fifo_inst/wptr [1]),
+	.I2(\fifo_inst/rbin_num [1]),
+	.I3(\fifo_inst/rptr [0]),
+	.F(\fifo_inst/wfull_val_7 )
+);
+defparam \fifo_inst/wfull_val_s3 .INIT=16'h1428;
+LUT3 \fifo_inst/wfull_val1_s9  (
+	.I0(\fifo_inst/wfull_val1_3 ),
+	.I1(\fifo_inst/wfull_val1_2 ),
+	.I2(\fifo_inst/wfull_val1_0 ),
+	.F(\fifo_inst/wfull_val1 )
+);
+defparam \fifo_inst/wfull_val1_s9 .INIT=8'hAC;
+LUT3 \fifo_inst/wfull_val1_s10  (
+	.I0(\fifo_inst/wfull_val_7 ),
+	.I1(\fifo_inst/wfull_val1_0 ),
+	.I2(\fifo_inst/reset_w [1]),
+	.F(\fifo_inst/wfull_val1_0 )
+);
+defparam \fifo_inst/wfull_val1_s10 .INIT=8'h0E;
+LUT3 \fifo_inst/Full_d_s  (
+	.I0(\fifo_inst/Full_2 ),
+	.I1(\fifo_inst/Full_1_2 ),
+	.I2(\fifo_inst/Full_1 ),
+	.F(Full)
+);
+defparam \fifo_inst/Full_d_s .INIT=8'hAC;
+LUT3 \fifo_inst/Full_s8  (
+	.I0(\fifo_inst/wfull_val_7 ),
+	.I1(\fifo_inst/Full_1 ),
+	.I2(\fifo_inst/reset_w [1]),
+	.F(\fifo_inst/Full_1 )
+);
+defparam \fifo_inst/Full_s8 .INIT=8'h0E;
+LUT3 \fifo_inst/rbin_num_next_0_s5  (
+	.I0(Empty),
+	.I1(RdEn),
+	.I2(\fifo_inst/rbin_num [0]),
+	.F(\fifo_inst/rbin_num_next [0])
+);
+defparam \fifo_inst/rbin_num_next_0_s5 .INIT=8'hB4;
+LUT3 \fifo_inst/rbin_num_next_1_s2  (
+	.I0(\fifo_inst/rbin_num_next [0]),
+	.I1(\fifo_inst/rbin_num [0]),
+	.I2(\fifo_inst/rbin_num [1]),
+	.F(\fifo_inst/rbin_num_next [1])
+);
+defparam \fifo_inst/rbin_num_next_1_s2 .INIT=8'hB4;
+LUT2 \fifo_inst/Equal.wbinnext_0_s3  (
+	.I0(\fifo_inst/Equal.wbin [0]),
+	.I1(\fifo_inst/n20_5 ),
+	.F(\fifo_inst/Equal.wbinnext_0_7 )
+);
+defparam \fifo_inst/Equal.wbinnext_0_s3 .INIT=4'h6;
+LUT3 \fifo_inst/Equal.wbinnext_1_s2  (
+	.I0(\fifo_inst/Equal.wbin [0]),
+	.I1(\fifo_inst/n20_5 ),
+	.I2(\fifo_inst/wptr [1]),
+	.F(\fifo_inst/Equal.wbinnext [1])
+);
+defparam \fifo_inst/Equal.wbinnext_1_s2 .INIT=8'h78;
+LUT4 \fifo_inst/rempty_val_s4  (
+	.I0(\fifo_inst/Equal.rq2_wptr [0]),
+	.I1(\fifo_inst/Equal.rq2_wptr [1]),
+	.I2(\fifo_inst/rbin_num [1]),
+	.I3(\fifo_inst/rbin_num [0]),
+	.F(\fifo_inst/rempty_val_8 )
+);
+defparam \fifo_inst/rempty_val_s4 .INIT=16'h871E;
+DFFP \fifo_inst/reset_r_0_s0  (
+	.D(GND),
+	.CLK(\fifo_inst/n4_6 ),
+	.PRESET(Reset),
+	.Q(\fifo_inst/reset_r [0])
+);
+defparam \fifo_inst/reset_r_0_s0 .INIT=1'b1;
+DFFP \fifo_inst/reset_w_1_s0  (
+	.D(\fifo_inst/reset_w [0]),
+	.CLK(\fifo_inst/n9_6 ),
+	.PRESET(Reset),
+	.Q(\fifo_inst/reset_w [1])
+);
+defparam \fifo_inst/reset_w_1_s0 .INIT=1'b1;
+DFFP \fifo_inst/reset_w_0_s0  (
+	.D(GND),
+	.CLK(\fifo_inst/n9_6 ),
+	.PRESET(Reset),
+	.Q(\fifo_inst/reset_w [0])
+);
+defparam \fifo_inst/reset_w_0_s0 .INIT=1'b1;
+DFFC \fifo_inst/rbin_num_1_s0  (
+	.D(\fifo_inst/rbin_num_next [1]),
+	.CLK(RdClk),
+	.CLEAR(\fifo_inst/reset_r [1]),
+	.Q(\fifo_inst/rbin_num [1])
+);
+defparam \fifo_inst/rbin_num_1_s0 .INIT=1'b0;
+DFFC \fifo_inst/rbin_num_0_s0  (
+	.D(\fifo_inst/rbin_num_next [0]),
+	.CLK(RdClk),
+	.CLEAR(\fifo_inst/reset_r [1]),
+	.Q(\fifo_inst/rbin_num [0])
+);
+defparam \fifo_inst/rbin_num_0_s0 .INIT=1'b0;
+DFFC \fifo_inst/Equal.rq1_wptr_1_s0  (
+	.D(\fifo_inst/wptr [1]),
+	.CLK(RdClk),
+	.CLEAR(\fifo_inst/reset_r [1]),
+	.Q(\fifo_inst/Equal.rq1_wptr [1])
+);
+defparam \fifo_inst/Equal.rq1_wptr_1_s0 .INIT=1'b0;
+DFFC \fifo_inst/Equal.rq1_wptr_0_s0  (
+	.D(\fifo_inst/wptr [0]),
+	.CLK(RdClk),
+	.CLEAR(\fifo_inst/reset_r [1]),
+	.Q(\fifo_inst/Equal.rq1_wptr [0])
+);
+defparam \fifo_inst/Equal.rq1_wptr_0_s0 .INIT=1'b0;
+DFFC \fifo_inst/Equal.rq2_wptr_1_s0  (
+	.D(\fifo_inst/Equal.rq1_wptr [1]),
+	.CLK(RdClk),
+	.CLEAR(\fifo_inst/reset_r [1]),
+	.Q(\fifo_inst/Equal.rq2_wptr [1])
+);
+defparam \fifo_inst/Equal.rq2_wptr_1_s0 .INIT=1'b0;
+DFFC \fifo_inst/Equal.rq2_wptr_0_s0  (
+	.D(\fifo_inst/Equal.rq1_wptr [0]),
+	.CLK(RdClk),
+	.CLEAR(\fifo_inst/reset_r [1]),
+	.Q(\fifo_inst/Equal.rq2_wptr [0])
+);
+defparam \fifo_inst/Equal.rq2_wptr_0_s0 .INIT=1'b0;
+DFFC \fifo_inst/rptr_0_s0  (
+	.D(\fifo_inst/Equal.rgraynext [0]),
+	.CLK(RdClk),
+	.CLEAR(\fifo_inst/reset_r [1]),
+	.Q(\fifo_inst/rptr [0])
+);
+defparam \fifo_inst/rptr_0_s0 .INIT=1'b0;
+DFFC \fifo_inst/wptr_1_s0  (
+	.D(\fifo_inst/Equal.wbinnext [1]),
+	.CLK(WrClk),
+	.CLEAR(\fifo_inst/reset_w [1]),
+	.Q(\fifo_inst/wptr [1])
+);
+defparam \fifo_inst/wptr_1_s0 .INIT=1'b0;
+DFFC \fifo_inst/wptr_0_s0  (
+	.D(\fifo_inst/Equal.wgraynext [0]),
+	.CLK(WrClk),
+	.CLEAR(\fifo_inst/reset_w [1]),
+	.Q(\fifo_inst/wptr [0])
+);
+defparam \fifo_inst/wptr_0_s0 .INIT=1'b0;
+DFFC \fifo_inst/Equal.wbin_0_s0  (
+	.D(\fifo_inst/Equal.wbinnext_0_7 ),
+	.CLK(WrClk),
+	.CLEAR(\fifo_inst/reset_w [1]),
+	.Q(\fifo_inst/Equal.wbin [0])
+);
+defparam \fifo_inst/Equal.wbin_0_s0 .INIT=1'b0;
+DFFP \fifo_inst/Empty_s0  (
+	.D(\fifo_inst/rempty_val ),
+	.CLK(RdClk),
+	.PRESET(\fifo_inst/reset_r [1]),
+	.Q(Empty)
+);
+defparam \fifo_inst/Empty_s0 .INIT=1'b1;
+DFFP \fifo_inst/reset_r_1_s0  (
+	.D(\fifo_inst/reset_r [0]),
+	.CLK(\fifo_inst/n4_6 ),
+	.PRESET(Reset),
+	.Q(\fifo_inst/reset_r [1])
+);
+defparam \fifo_inst/reset_r_1_s0 .INIT=1'b1;
+DFFC \fifo_inst/wfull_val1_s0  (
+	.D(\fifo_inst/wfull_val_7 ),
+	.CLK(WrClk),
+	.CLEAR(\fifo_inst/reset_w [1]),
+	.Q(\fifo_inst/wfull_val1_2 )
+);
+defparam \fifo_inst/wfull_val1_s0 .INIT=1'b0;
+DFFP \fifo_inst/wfull_val1_s1  (
+	.D(\fifo_inst/wfull_val_7 ),
+	.CLK(WrClk),
+	.PRESET(\fifo_inst/n417_4 ),
+	.Q(\fifo_inst/wfull_val1_3 )
+);
+defparam \fifo_inst/wfull_val1_s1 .INIT=1'b1;
+DFFC \fifo_inst/Full_s0  (
+	.D(\fifo_inst/wfull_val1 ),
+	.CLK(WrClk),
+	.CLEAR(\fifo_inst/reset_w [1]),
+	.Q(\fifo_inst/Full_1_2 )
+);
+defparam \fifo_inst/Full_s0 .INIT=1'b0;
+DFFP \fifo_inst/Full_s1  (
+	.D(\fifo_inst/wfull_val1 ),
+	.CLK(WrClk),
+	.PRESET(\fifo_inst/n417_4 ),
+	.Q(\fifo_inst/Full_2 )
+);
+defparam \fifo_inst/Full_s1 .INIT=1'b1;
+SDPB \fifo_inst/Equal.mem_Equal.mem_0_0_s  (
+	.CLKA(WrClk),
+	.CEA(\fifo_inst/n20_5 ),
+	.RESETA(GND),
+	.CLKB(RdClk),
+	.CEB(\fifo_inst/n26_4 ),
+	.RESETB(\fifo_inst/reset_r [1]),
+	.OCE(GND),
+	.BLKSELA({GND, GND, GND}),
+	.BLKSELB({GND, GND, GND}),
+	.DI({Data[31:0]}),
+	.ADA({GND, GND, GND, GND, GND, GND, GND, GND, \fifo_inst/Equal.wbin [0], GND, VCC, VCC, VCC, VCC}),
+	.ADB({GND, GND, GND, GND, GND, GND, GND, GND, \fifo_inst/rbin_num_next [0], GND, GND, GND, GND, GND}),
+	.DO({Q[31:0]})
+);
+defparam \fifo_inst/Equal.mem_Equal.mem_0_0_s .READ_MODE=1'b0;
+defparam \fifo_inst/Equal.mem_Equal.mem_0_0_s .BIT_WIDTH_0=32;
+defparam \fifo_inst/Equal.mem_Equal.mem_0_0_s .BIT_WIDTH_1=32;
+defparam \fifo_inst/Equal.mem_Equal.mem_0_0_s .RESET_MODE="ASYNC";
+defparam \fifo_inst/Equal.mem_Equal.mem_0_0_s .BLK_SEL_0=3'b000;
+defparam \fifo_inst/Equal.mem_Equal.mem_0_0_s .BLK_SEL_1=3'b000;
+SDPB \fifo_inst/Equal.mem_Equal.mem_0_1_s  (
+	.CLKA(WrClk),
+	.CEA(\fifo_inst/n20_5 ),
+	.RESETA(GND),
+	.CLKB(RdClk),
+	.CEB(\fifo_inst/n26_4 ),
+	.RESETB(\fifo_inst/reset_r [1]),
+	.OCE(GND),
+	.BLKSELA({GND, GND, GND}),
+	.BLKSELB({GND, GND, GND}),
+	.DI({GND, GND, GND, GND, GND, GND, GND, GND, Data[55:32]}),
+	.ADA({GND, GND, GND, GND, GND, GND, GND, GND, \fifo_inst/Equal.wbin [0], GND, VCC, VCC, VCC, VCC}),
+	.ADB({GND, GND, GND, GND, GND, GND, GND, GND, \fifo_inst/rbin_num_next [0], GND, GND, GND, GND, GND}),
+	.DO({\fifo_inst/DO [31:24], Q[55:32]})
+);
+defparam \fifo_inst/Equal.mem_Equal.mem_0_1_s .READ_MODE=1'b0;
+defparam \fifo_inst/Equal.mem_Equal.mem_0_1_s .BIT_WIDTH_0=32;
+defparam \fifo_inst/Equal.mem_Equal.mem_0_1_s .BIT_WIDTH_1=32;
+defparam \fifo_inst/Equal.mem_Equal.mem_0_1_s .RESET_MODE="ASYNC";
+defparam \fifo_inst/Equal.mem_Equal.mem_0_1_s .BLK_SEL_0=3'b000;
+defparam \fifo_inst/Equal.mem_Equal.mem_0_1_s .BLK_SEL_1=3'b000;
+INV \fifo_inst/n4_s2  (
+	.I(RdClk),
+	.O(\fifo_inst/n4_6 )
+);
+INV \fifo_inst/n9_s2  (
+	.I(WrClk),
+	.O(\fifo_inst/n9_6 )
+);
+endmodule

src/src/WrapFifoChain/FifoTfe7Bytes/FifoTfe7Bytes_tmp.v

@@ -0,0 +1,24 @@
+//Copyright (C)2014-2024 Gowin Semiconductor Corporation.
+//All rights reserved.
+//File Title: Template file for instantiation
+//Tool Version: V1.9.9.03 (64-bit)
+//Part Number: GW1N-UV9QN88C6/I5
+//Device: GW1N-9
+//Created Time: Fri Nov 22 16:10:39 2024
+
+//Change the instance name and port connections to the signal names
+//--------Copy here to design--------
+
+	FifoTfe2Bytes your_instance_name(
+		.Data(Data), //input [55:0] Data
+		.Reset(Reset), //input Reset
+		.WrClk(WrClk), //input WrClk
+		.RdClk(RdClk), //input RdClk
+		.WrEn(WrEn), //input WrEn
+		.RdEn(RdEn), //input RdEn
+		.Q(Q), //output [55:0] Q
+		.Empty(Empty), //output Empty
+		.Full(Full) //output Full
+	);
+
+//--------Copy end-------------------

src/src/WrapFifoChain/FifoTfe7Bytes/temp/FIFOHS/FIFOHS.prj

@@ -0,0 +1,20 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!DOCTYPE gowin-synthesis-project>
+<Project>
+    <Version>beta</Version>
+    <Device id="GW1N-9" package="QFN88" speed="6" partNumber="GW1N-UV9QN88C6/I5"/>
+    <FileList>
+        <File path="C:/Gowin/Gowin_V1.9.9.03_x64/IDE/ipcore/FIFO_HS/data/fifo_hs.v" type="verilog"/>
+        <File path="C:/Gowin/Gowin_V1.9.9.03_x64/IDE/ipcore/FIFO_HS/data/fifo_hs_top.v" type="verilog"/>
+    </FileList>
+    <OptionList>
+        <Option type="disable_insert_pad" value="1"/>
+        <Option type="include_path" value="C:/Gowin/Gowin_V1.9.9.03_x64/IDE/ipcore/FIFO_HS/data"/>
+        <Option type="include_path" value="C:/Gowin/Projects/BOCHv3_FPGA/src/src/WrapFifoChain/FifoTfe7Bytes/temp/FIFOHS"/>
+        <Option type="output_file" value="FifoTfe7Bytes.vg"/>
+        <Option type="output_template" value="FifoTfe7Bytes_tmp.v"/>
+        <Option type="ram_balance" value="1"/>
+        <Option type="ram_rw_check" value="1"/>
+        <Option type="verilog_language" value="sysv-2017"/>
+    </OptionList>
+</Project>

src/src/WrapFifoChain/FifoTfe7Bytes/temp/FIFOHS/FifoTfe7Bytes.log

@@ -0,0 +1,45 @@
+GowinSynthesis start
+Running parser ...
+Analyzing Verilog file 'C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v'
+Analyzing included file '**'("C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Back to file '**'("C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Undeclared symbol '**', assumed default net type '**'("C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Analyzing Verilog file 'C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v'
+Analyzing included file 'fifo_define.v'("C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":1)
+Back to file 'C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v'("C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":1)
+Analyzing included file 'C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\static_macro_define.v'("C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":2)
+Back to file 'C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v'("C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":2)
+Analyzing included file 'fifo_parameter.v'("C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":57)
+Back to file 'C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v'("C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":57)
+Compiling module 'FifoTfe2Bytes'("C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":4)
+Compiling module '**'("C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Extracting RAM for identifier '**'("C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+NOTE  (EX0101) : Current top module is "FifoTfe2Bytes"
+[5%] Running netlist conversion ...
+Running device independent optimization ...
+[10%] Optimizing Phase 0 completed
+[15%] Optimizing Phase 1 completed
+[25%] Optimizing Phase 2 completed
+Running inference ...
+[30%] Inferring Phase 0 completed
+[40%] Inferring Phase 1 completed
+[50%] Inferring Phase 2 completed
+[55%] Inferring Phase 3 completed
+Running technical mapping ...
+[60%] Tech-Mapping Phase 0 completed
+[65%] Tech-Mapping Phase 1 completed
+[75%] Tech-Mapping Phase 2 completed
+WARN  (AG0100) : Find logical loop signal : "fifo_inst/wfull_val1_s3"("C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+WARN  (AG0100) : Find logical loop signal : "fifo_inst/wfull_val1_s6"("C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+WARN  (AG0100) : Find logical loop signal : "fifo_inst/wfull_val1_s3"("C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+WARN  (AG0101) : The netlist is not one directed acyclic graph
+WARN  (AG0100) : Find logical loop signal : "fifo_inst/Full_s3"("C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+WARN  (AG0100) : Find logical loop signal : "fifo_inst/Full_s6"("C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+WARN  (AG0100) : Find logical loop signal : "fifo_inst/Full_s3"("C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+WARN  (AG0101) : The netlist is not one directed acyclic graph
+[80%] Tech-Mapping Phase 3 completed
+[90%] Tech-Mapping Phase 4 completed
+[95%] Generate netlist file "C:\Gowin\Projects\BOCHv3_FPGA\src\src\WrapFifoChain\FifoTfe7Bytes\temp\FIFOHS\FifoTfe7Bytes.vg" completed
+Generate template file "C:\Gowin\Projects\BOCHv3_FPGA\src\src\WrapFifoChain\FifoTfe7Bytes\temp\FIFOHS\FifoTfe7Bytes_tmp.v" completed
+[100%] Generate report file "C:\Gowin\Projects\BOCHv3_FPGA\src\src\WrapFifoChain\FifoTfe7Bytes\temp\FIFOHS\FifoTfe7Bytes_syn.rpt.html" completed
+GowinSynthesis finish

src/src/WrapFifoChain/FifoTfe7Bytes/temp/FIFOHS/FifoTfe7Bytes.vg

@@ -0,0 +1,200 @@
+//
+//Written by GowinSynthesis
+//Tool Version "V1.9.9.03 (64-bit)"
+//Fri Nov 22 16:10:39 2024
+
+//Source file index table:
+//file0 "\C:/Gowin/Gowin_V1.9.9.03_x64/IDE/ipcore/FIFO_HS/data/fifo_hs.v"
+//file1 "\C:/Gowin/Gowin_V1.9.9.03_x64/IDE/ipcore/FIFO_HS/data/fifo_hs_top.v"
+`timescale 100 ps/100 ps
+`pragma protect begin_protected
+`pragma protect version="2.3"
+`pragma protect author="default"
+`pragma protect author_info="default"
+`pragma protect encrypt_agent="GOWIN"
+`pragma protect encrypt_agent_info="GOWIN Encrypt Version 2.3"
+
+`pragma protect encoding=(enctype="base64", line_length=76, bytes=256)
+`pragma protect key_keyowner="GOWIN",key_keyname="GWK2023-09",key_method="rsa"
+`pragma protect key_block
+C5fLb2KxIhKnQirCC/KZ5sfPTjLqghcylp11BntEaEweKJe5CJcVbHpVkkr664QmVjQrgNPK5WZY
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+EOp+UGM8ZtlaF0wZPeiGX45BrdoqePgJ+gs/I/85yYFfutqYHGkBekcPLIC9Mz6H+QykDF/IYj1P
+GvD2aunMa/hBACYVcSI7NTLgRY1w6asJ/8bwInSKqluaGgsedXPxaohyWFR9wYXFSaY/Xv8wIWiQ
++pfQH0mMgLnxdZ7w6KkL07UfaqpA4YTfcqQl7w==
+
+`pragma protect encoding=(enctype="base64", line_length=76, bytes=7104)
+`pragma protect data_keyowner="default-ip-vendor"
+`pragma protect data_keyname="default-ip-key"
+`pragma protect data_method="aes128-cfb"
+`pragma protect data_block
+24Dhwz3gdx0V5AbfwkEAA70Hpl/mFz8vxw9tQ2jf+4aBqYyJqL4CuOqhg0CC1fgaNlIpfpi183aG
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+lXXCbmgwNKBjdfNosP/J3oX5b1jxhoYjhwgiCnYEjWbaUf57PadlsMDNEpM5gtNDcYXwJvOYRIRp
+ugqxJYQJMZVxBP7RxagPD1fiTMaFUW4sA3gY7u0/AJ85fCKZymYNExhXHf3WxRHprYa2lqon+ODb
+dn6OhmMIZCoDvyDPqxat/deAI7ek9QLnl+OPwwF9nGZTbfqFuJ2koj2GLOr4A8nd/FPCui9uwiOs
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+VsvLO9E3BXYPdS+8/szI29fCnZVwX++qHAp5yod017PcZIj87e06T272ih43F6BjLaa+r2PSAzqu
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+12+CYCxkZq2f7KWis+57wQF8vtTcMM397pEbkTnsWcQqjnyd
+`pragma protect end_protected
+module FifoTfe2Bytes (
+  Data,
+  Reset,
+  WrClk,
+  RdClk,
+  WrEn,
+  RdEn,
+  Q,
+  Empty,
+  Full
+)
+;
+input [55:0] Data;
+input Reset;
+input WrClk;
+input RdClk;
+input WrEn;
+input RdEn;
+output [55:0] Q;
+output Empty;
+output Full;
+wire VCC;
+wire GND;
+  \~fifo.FifoTfe2Bytes  fifo_inst (
+    .Reset(Reset),
+    .RdClk(RdClk),
+    .WrClk(WrClk),
+    .WrEn(WrEn),
+    .RdEn(RdEn),
+    .Data(Data[55:0]),
+    .Empty(Empty),
+    .Full(Full),
+    .Q(Q[55:0])
+);
+  VCC VCC_cZ (
+    .V(VCC)
+);
+  GND GND_cZ (
+    .G(GND)
+);
+  GSR GSR (
+    .GSRI(VCC) 
+);
+endmodule /* FifoTfe2Bytes */

src/src/WrapFifoChain/FifoTfe7Bytes/temp/FIFOHS/FifoTfe7Bytes_syn_resource.html

@@ -0,0 +1,46 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html>
+<head>
+<title>Hierarchy Module Resource</title>
+<style type="text/css">
+body { font-family: Verdana, Arial, sans-serif; font-size: 14px; }
+div#main_wrapper{ width: 100%; }
+h1 {text-align: center; }
+h1 {margin-top: 36px; }
+table, th, td { border: 1px solid #aaa; }
+table { border-collapse:collapse; margin-top: 10px; margin-bottom: 20px; width: 100%; }
+th, td { align = "center"; padding: 5px 2px 5px 5px; }
+th { color: #fff; font-weight: bold; background-color: #0084ff; }
+table td.label { width: 20%; white-space: nowrap; min-width: 20px; background-color: #dee8f4; }
+</style>
+</head>
+<body>
+<div id="main_wrapper">
+<div id="content">
+<h1>Hierarchy Module Resource</h1>
+<table>
+<tr>
+<th class="label">MODULE NAME</th>
+<th class="label">REG NUMBER</th>
+<th class="label">ALU NUMBER</th>
+<th class="label">LUT NUMBER</th>
+<th class="label">DSP NUMBER</th>
+<th class="label">BSRAM NUMBER</th>
+<th class="label">SSRAM NUMBER</th>
+<th class="label">ROM16 NUMBER</th>
+</tr>
+<tr>
+<td class="label">FifoTfe2Bytes (C:/Gowin/Gowin_V1.9.9.03_x64/IDE/ipcore/FIFO_HS/data/fifo_hs_top.v)</td>
+<td align = "center">19</td>
+<td align = "center">-</td>
+<td align = "center">18</td>
+<td align = "center">-</td>
+<td align = "center">2</td>
+<td align = "center">-</td>
+<td align = "center">-</td>
+</tr>
+</table>
+</div><!-- content -->
+</div><!-- main_wrapper -->
+</body>
+</html>

src/src/WrapFifoChain/FifoTfe7Bytes/temp/FIFOHS/FifoTfe7Bytes_syn_rsc.xml

@@ -0,0 +1,2 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<Module name="FifoTfe2Bytes" Register="19" Lut="18" Bsram="2" T_Register="19(19)" T_Lut="18(18)" T_Bsram="2(2)"/>

src/src/WrapFifoChain/FifoTfe7Bytes/temp/FIFOHS/FifoTfe7Bytes_tmp.v

@@ -0,0 +1,24 @@
+//Copyright (C)2014-2024 Gowin Semiconductor Corporation.
+//All rights reserved.
+//File Title: Template file for instantiation
+//Tool Version: V1.9.9.03 (64-bit)
+//Part Number: GW1N-UV9QN88C6/I5
+//Device: GW1N-9
+//Created Time: Fri Nov 22 16:10:39 2024
+
+//Change the instance name and port connections to the signal names
+//--------Copy here to design--------
+
+	FifoTfe2Bytes your_instance_name(
+		.Data(Data), //input [55:0] Data
+		.Reset(Reset), //input Reset
+		.WrClk(WrClk), //input WrClk
+		.RdClk(RdClk), //input RdClk
+		.WrEn(WrEn), //input WrEn
+		.RdEn(RdEn), //input RdEn
+		.Q(Q), //output [55:0] Q
+		.Empty(Empty), //output Empty
+		.Full(Full) //output Full
+	);
+
+//--------Copy end-------------------

src/src/WrapFifoChain/FifoTfe7Bytes/temp/FIFOHS/fifo_define.v

@@ -0,0 +1,5 @@
+`define module_name FifoTfe2Bytes
+`define EBR_BASED
+`define FWFT
+`define En_Reset
+`define Reset_Synchronization

src/src/WrapFifoChain/FifoTfe7Bytes/temp/FIFOHS/fifo_parameter.v

@@ -0,0 +1,6 @@
+parameter WDEPTH = 2;
+parameter ASIZE = 1;
+parameter WDSIZE = 56;
+parameter RDEPTH = 2;
+parameter RASIZE = 1;
+parameter RDSIZE = 56;

src/src/WrapFifoChain/FifoTfe7Bytes/temp/FIFOHS/project.ini

@@ -0,0 +1 @@
+RESOURCE_CHECK=false