Добавил скрипт

script/recreate.tcl

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+set DSN_ROOT [file normalize [file join [file dirname [info script]] "."]]
+create_project -name CP2444v1_FPGA -dir $::DSN_ROOT/CP2444v1_FPGA_PROJ -pn GW1N-UV9QN88C6/I5 -device_version NA -force
+
+
+add_file -type verilog "$::DSN_ROOT/CP2444v1_FPGA/src/src/ClkGen/ClkGenCp2444v1.v"
+add_file -type verilog "$::DSN_ROOT/CP2444v1_FPGA/src/src/ClkGen/GowinClkDiv3dot5/GowinClkDiv3dot5.v"
+add_file -type verilog "$::DSN_ROOT/CP2444v1_FPGA/src/src/ClkGen/GowinClkDiv8/GowinClkDiv8.v"
+add_file -type verilog "$::DSN_ROOT/CP2444v1_FPGA/src/src/ClkGen/GowinInternalOsc25MHz/GowinInternalOsc25MHz.v"
+add_file -type verilog "$::DSN_ROOT/CP2444v1_FPGA/src/src/ClkGen/GowinPllFirst/GowinPllFirst.v"
+add_file -type verilog "$::DSN_ROOT/CP2444v1_FPGA/src/src/FifoCtrl/FifoCtrl.v"
+add_file -type verilog "$::DSN_ROOT/CP2444v1_FPGA/src/src/Gpio1Ctrl/Gpio1Ctrl.v"
+add_file -type verilog "$::DSN_ROOT/CP2444v1_FPGA/src/src/InitRst/InitRst.v"
+add_file -type verilog "$::DSN_ROOT/CP2444v1_FPGA/src/src/InterfaceArbiter/InterfaceArbiterCp2444v1.v"
+add_file -type verilog "$::DSN_ROOT/CP2444v1_FPGA/src/src/PacketAnalyzer1Mosi/PacketAnalyzer1MosiCp2444v1.v"
+add_file -type verilog "$::DSN_ROOT/CP2444v1_FPGA/src/src/PacketAnalyzer4Mosi/PacketAnalyzer4MosiCp2444v1.v"
+add_file -type verilog "$::DSN_ROOT/CP2444v1_FPGA/src/src/SpiM/SpiM.v"
+add_file -type verilog "$::DSN_ROOT/CP2444v1_FPGA/src/src/Top/TopCp2444v1.v"
+add_file -type verilog "$::DSN_ROOT/CP2444v1_FPGA/src/src/WrapFifoChain/AttCtrlWrapper.v"
+add_file -type verilog "$::DSN_ROOT/CP2444v1_FPGA/src/src/WrapFifoChain/FifoShReg16/FifoShReg16.v"
+add_file -type verilog "$::DSN_ROOT/CP2444v1_FPGA/src/src/WrapFifoChain/FifoShReg8/FifoShReg8.v"
+add_file -type verilog "$::DSN_ROOT/CP2444v1_FPGA/src/src/WrapFifoChain/SwCtrlWrapper.v"
+add_file -type cst "$::DSN_ROOT/CP2444v1_FPGA/src/constr/Cp2444v1.cst"
+add_file -type sdc "$::DSN_ROOT/CP2444v1_FPGA/src/constr/Cp2444v1.sdc"
+
+
+
+set_option -synthesis_tool gowinsynthesis
+set_option -output_base_name CP2444v1_FPGA_PROJ
+set_option -global_freq default
+set_option -top_module TopCp2444v1
+set_option -verilog_std v2001
+set_option -vhdl_std vhd1993
+
+set_option -print_all_synthesis_warning 0
+set_option -disable_io_insertion 0
+set_option -looplimit 2000
+set_option -rw_check_on_ram 0
+set_option -gen_sdf 0
+set_option -gen_io_cst 0
+set_option -vccaux 3.3
+set_option -gen_ibis 0
+set_option -gen_posp 0
+set_option -gen_text_timing_rpt 0
+set_option -gen_verilog_sim_netlist 0
+set_option -gen_vhdl_sim_netlist 0
+set_option -show_init_in_vo 0
+set_option -show_all_warn 0
+set_option -timing_driven 1
+set_option -ireg_in_iob 1
+set_option -oreg_in_iob 1
+set_option -ioreg_in_iob 1
+set_option -replicate_resources 1
+set_option -cst_warn_to_error 1
+set_option -rpt_auto_place_io_info 0
+set_option -correct_hold_violation 1
+set_option -place_option 2
+set_option -route_option 1
+set_option -clock_route_order 0
+set_option -route_maxfan 23
+set_option -use_jtag_as_gpio 0
+set_option -use_sspi_as_gpio 1
+set_option -use_mspi_as_gpio 0
+set_option -use_ready_as_gpio 0
+set_option -use_done_as_gpio 0
+set_option -use_reconfign_as_gpio 0
+set_option -use_mode_as_gpio 0
+set_option -use_i2c_as_gpio 0
+set_option -use_cpu_as_gpio 0
+set_option -power_on_reset_monitor 1
+set_option -bit_format bin
+set_option -bit_crc_check 1
+set_option -bit_compress 0
+set_option -bit_encrypt 0
+set_option -bit_encrypt_key 00000000000000000000000000000000
+set_option -bit_security 1
+set_option -bit_incl_bsram_init 1
+set_option -bg_programming off
+set_option -hotboot 0
+set_option -i2c_slave_addr 00
+set_option -secure_mode 0
+set_option -loading_rate default
+set_option -program_done_bypass 0
+set_option -wakeup_mode 0
+set_option -user_code default
+set_option -unused_pin default
+set_option -multi_boot 1
+set_option -multiboot_address_width 24
+set_option -multiboot_mode normal
+set_option -multiboot_spi_flash_address 00000000
+set_option -mspi_jump 0
+set_option -turn_off_bg 0
+set_option -vccx 3.3
+set_option -seu_handler 0
+set_option -seu_handler_checksum 0
+set_option -seu_handler_mode auto
+set_option -error_detection false
+set_option -error_detection_correction false
+set_option -stop_seu_handler false
+set_option -error_injection false
+set_option -ext_cclk false
+set_option -ext_cclk_div