Init commit

src/constr/Cp2444v1.cst

@@ -0,0 +1,78 @@
+//Copyright (C)2014-2024 Gowin Semiconductor Corporation.
+//All rights reserved. 
+//File Title: Physical Constraints file
+//Tool Version: V1.9.9.03 (64-bit)
+//Part Number: GW1N-UV9QN88C6/I5
+//Device: GW1N-9
+//Created Time: Thu 11 28 16:15:07 2024
+
+IO_LOC "FpgaLedP4_o" 32;
+IO_PORT "FpgaLedP4_o" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;
+IO_LOC "FpgaLedP3_o" 31;
+IO_PORT "FpgaLedP3_o" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;
+IO_LOC "FpgaLedP2_o" 30;
+IO_PORT "FpgaLedP2_o" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;
+IO_LOC "FpgaLedP1_o" 29;
+IO_PORT "FpgaLedP1_o" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;
+IO_LOC "FpgaP34SwP2_o" 13;
+IO_PORT "FpgaP34SwP2_o" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;
+IO_LOC "FpgaP34SwP1_o" 14;
+IO_PORT "FpgaP34SwP1_o" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;
+IO_LOC "FpgaP12SwP2_o" 15;
+IO_PORT "FpgaP12SwP2_o" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;
+IO_LOC "FpgaP12SwP1_o" 16;
+IO_PORT "FpgaP12SwP1_o" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;
+IO_LOC "FpgaCfP4_o" 20;
+IO_PORT "FpgaCfP4_o" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;
+IO_LOC "FpgaCfP3_o" 19;
+IO_PORT "FpgaCfP3_o" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;
+IO_LOC "FpgaCfP2_o" 18;
+IO_PORT "FpgaCfP2_o" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;
+IO_LOC "FpgaCfP1_o" 17;
+IO_PORT "FpgaCfP1_o" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;
+IO_LOC "AttP4Sck_o" 26;
+IO_PORT "AttP4Sck_o" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;
+IO_LOC "AttP4Cs_o" 27;
+IO_PORT "AttP4Cs_o" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;
+IO_LOC "AttP4Mosi_o" 25;
+IO_PORT "AttP4Mosi_o" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;
+IO_LOC "AttP3Sck_o" 41;
+IO_PORT "AttP3Sck_o" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;
+IO_LOC "AttP3Cs_o" 42;
+IO_PORT "AttP3Cs_o" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;
+IO_LOC "AttP3Mosi_o" 40;
+IO_PORT "AttP3Mosi_o" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;
+IO_LOC "AttP2Sck_o" 50;
+IO_PORT "AttP2Sck_o" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;
+IO_LOC "AttP2Cs_o" 51;
+IO_PORT "AttP2Cs_o" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;
+IO_LOC "AttP2Mosi_o" 49;
+IO_PORT "AttP2Mosi_o" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;
+IO_LOC "AttP1Sck_o" 53;
+IO_PORT "AttP1Sck_o" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;
+IO_LOC "AttP1Cs_o" 54;
+IO_PORT "AttP1Cs_o" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;
+IO_LOC "AttP1Mosi_o" 52;
+IO_PORT "AttP1Mosi_o" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;
+IO_LOC "SwP1Sck_o" 57;
+IO_PORT "SwP1Sck_o" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;
+IO_LOC "SwP1Cs_o" 56;
+IO_PORT "SwP1Cs_o" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;
+IO_LOC "SwP1Mosi_o" 55;
+IO_PORT "SwP1Mosi_o" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;
+IO_LOC "Mosi3_i" 86;
+IO_PORT "Mosi3_i" IO_TYPE=LVCMOS33 PULL_MODE=UP BANK_VCCIO=3.3;
+IO_LOC "Mosi2_i" 85;
+IO_PORT "Mosi2_i" IO_TYPE=LVCMOS33 PULL_MODE=UP BANK_VCCIO=3.3;
+IO_LOC "Mosi1_io" 84;
+IO_PORT "Mosi1_io" IO_TYPE=LVCMOS33 PULL_MODE=UP BANK_VCCIO=3.3;
+IO_LOC "Mosi0_i" 83;
+IO_PORT "Mosi0_i" IO_TYPE=LVCMOS33 PULL_MODE=UP BANK_VCCIO=3.3;
+IO_LOC "Ss_i" 80;
+IO_PORT "Ss_i" IO_TYPE=LVCMOS33 PULL_MODE=UP BANK_VCCIO=3.3;
+IO_LOC "Sck_i" 79;
+IO_PORT "Sck_i" IO_TYPE=LVCMOS33 PULL_MODE=UP BANK_VCCIO=3.3;
+IO_LOC "Rst_i" 81;
+IO_PORT "Rst_i" IO_TYPE=LVCMOS33 PULL_MODE=UP BANK_VCCIO=3.3;
+IO_LOC "Clk_i" 11;
+IO_PORT "Clk_i" IO_TYPE=LVCMOS33 PULL_MODE=UP BANK_VCCIO=3.3;

src/constr/Cp2444v1.sdc

@@ -0,0 +1,10 @@
+//Copyright (C)2014-2024 GOWIN Semiconductor Corporation.
+//All rights reserved.
+//File Title: Timing Constraints file
+//Tool Version: V1.9.9.03 (64-bit) 
+//Created Time: 2024-11-28 16:12:05
+create_clock -name clk26dot25 -period 38.095 -waveform {0 19.047} [get_nets {clk26dot25}]
+create_clock -name clk60 -period 16.667 -waveform {0 8.334} [get_nets {clk60}]
+create_clock -name Clk_i -period 41.667 -waveform {0 20.834} [get_ports {Clk_i}]
+create_clock -name Sck_i -period 10 -waveform {0 5} [get_ports {Sck_i}]
+set_clock_groups -asynchronous -group [get_clocks {Sck_i}] -group [get_clocks {clk60 clk26dot25 Clk_i}]

src/src/ClkGen/ClkGenCp2444v1.v

@@ -0,0 +1,67 @@
+////////////////////////////////////////////////////////////////////////////////////////////
+// Company:			TAIR
+// Engineer:		Zaytsev Mikhail
+// 
+// Create Date:		23/04/2024 
+// Design Name: 
+// Module Name:		ClkGen 
+// Project Name:	BOCHV3_FPGA
+// Target Devices:	Board: BOCHV3. FPGA: GW1N-UV9QN88C6/I5
+// Tool versions:					
+// Dependencies:	
+// Revision: 
+// Revision 1.0 - File Created
+// Additional Comments: 
+//
+////////////////////////////////////////////////////////////////////////////////////////////
+module ClkGenCp2444v1 (
+	input Clk24MHz_i,
+
+	output Clk60Mhz_o,
+	output Clk26dot25Mhz_o,
+	output Clk24Mhz_o
+);
+
+//==========================================
+// Wires
+//==========================================
+wire clk25Mhz;
+wire clk210Mhz;
+wire clkBufg24Mhz;
+
+wire lockFirstPll;
+
+//==========================================
+// Assignments
+//==========================================
+assign Clk24Mhz_o = clkBufg24Mhz;
+//==========================================================================//
+//									CODING									//
+//==========================================================================//
+GowinPllFirst GowinPllFirst
+(
+	.clkin(Clk24MHz_i),
+	.lock(lockFirstPll),
+	.clkout(clk210Mhz)
+);
+
+GowinClkDiv3dot5 GowinClkDiv210MhzTo60Mhz
+(
+	.hclkin(clk210Mhz),
+	.clkout(Clk60Mhz_o),
+	.resetn(lockFirstPll)
+);
+
+GowinClkDiv8 GowinClkDiv210MhzTo26dot25Mhz
+(
+	.hclkin(clk210Mhz),
+	.clkout(Clk26dot25Mhz_o),
+	.resetn(lockFirstPll)
+);
+
+BUFG BUFG_24MHz (
+	.O(clkBufg24Mhz),
+	.I(Clk24Mhz_i)
+);
+
+endmodule

src/src/ClkGen/GowinClkDiv3dot5/GowinClkDiv3dot5.ipc

@@ -0,0 +1,12 @@
+[General]
+ipc_version=4
+file=GowinClkDiv3dot5
+module=GowinClkDiv3dot5
+target_device=gw1n9-022
+type=clock_clkdiv
+version=1.0
+
+[Config]
+Calibration=false
+Division_Factor=3.5
+Language=0

src/src/ClkGen/GowinClkDiv3dot5/GowinClkDiv3dot5.mod

@@ -0,0 +1,14 @@
+-series GW1N
+-device GW1N-9
+-device_version 
+-package QFN88
+-part_number GW1N-UV9QN88C6/I5
+
+
+-mod_name GowinClkDiv3dot5
+-file_name GowinClkDiv3dot5
+-path C:/Gowin/Projects/CP2444v1_FPGA/src/src/ClkGen/GowinClkDiv3dot5/
+-type CLKDIV
+-file_type vlg
+-division_factor 3.5
+-calib false

src/src/ClkGen/GowinClkDiv3dot5/GowinClkDiv3dot5.v

@@ -0,0 +1,29 @@
+//Copyright (C)2014-2024 Gowin Semiconductor Corporation.
+//All rights reserved.
+//File Title: IP file
+//Tool Version: V1.9.9.03 (64-bit)
+//Part Number: GW1N-UV9QN88C6/I5
+//Device: GW1N-9
+//Created Time: Thu Nov 28 11:29:22 2024
+
+module GowinClkDiv3dot5 (clkout, hclkin, resetn);
+
+output clkout;
+input hclkin;
+input resetn;
+
+wire gw_gnd;
+
+assign gw_gnd = 1'b0;
+
+CLKDIV clkdiv_inst (
+    .CLKOUT(clkout),
+    .HCLKIN(hclkin),
+    .RESETN(resetn),
+    .CALIB(gw_gnd)
+);
+
+defparam clkdiv_inst.DIV_MODE = "3.5";
+defparam clkdiv_inst.GSREN = "false";
+
+endmodule //GowinClkDiv3dot5

src/src/ClkGen/GowinClkDiv3dot5/GowinClkDiv3dot5_tmp.v

@@ -0,0 +1,18 @@
+//Copyright (C)2014-2024 Gowin Semiconductor Corporation.
+//All rights reserved.
+//File Title: Template file for instantiation
+//Tool Version: V1.9.9.03 (64-bit)
+//Part Number: GW1N-UV9QN88C6/I5
+//Device: GW1N-9
+//Created Time: Thu Nov 28 11:29:22 2024
+
+//Change the instance name and port connections to the signal names
+//--------Copy here to design--------
+
+    GowinClkDiv3dot5 your_instance_name(
+        .clkout(clkout), //output clkout
+        .hclkin(hclkin), //input hclkin
+        .resetn(resetn) //input resetn
+    );
+
+//--------Copy end-------------------

src/src/ClkGen/GowinClkDiv8/GowinClkDiv8.ipc

@@ -0,0 +1,12 @@
+[General]
+ipc_version=4
+file=GowinClkDiv8
+module=GowinClkDiv8
+target_device=gw1n9-022
+type=clock_clkdiv
+version=1.0
+
+[Config]
+Calibration=false
+Division_Factor=8
+Language=0

src/src/ClkGen/GowinClkDiv8/GowinClkDiv8.mod

@@ -0,0 +1,14 @@
+-series GW1N
+-device GW1N-9
+-device_version 
+-package QFN88
+-part_number GW1N-UV9QN88C6/I5
+
+
+-mod_name GowinClkDiv8
+-file_name GowinClkDiv8
+-path C:/Gowin/Projects/CP2444v1_FPGA/src/src/ClkGen/GowinClkDiv8/
+-type CLKDIV
+-file_type vlg
+-division_factor 8
+-calib false

src/src/ClkGen/GowinClkDiv8/GowinClkDiv8.v

@@ -0,0 +1,29 @@
+//Copyright (C)2014-2024 Gowin Semiconductor Corporation.
+//All rights reserved.
+//File Title: IP file
+//Tool Version: V1.9.9.03 (64-bit)
+//Part Number: GW1N-UV9QN88C6/I5
+//Device: GW1N-9
+//Created Time: Thu Nov 28 11:30:08 2024
+
+module GowinClkDiv8 (clkout, hclkin, resetn);
+
+output clkout;
+input hclkin;
+input resetn;
+
+wire gw_gnd;
+
+assign gw_gnd = 1'b0;
+
+CLKDIV clkdiv_inst (
+    .CLKOUT(clkout),
+    .HCLKIN(hclkin),
+    .RESETN(resetn),
+    .CALIB(gw_gnd)
+);
+
+defparam clkdiv_inst.DIV_MODE = "8";
+defparam clkdiv_inst.GSREN = "false";
+
+endmodule //GowinClkDiv8

src/src/ClkGen/GowinClkDiv8/GowinClkDiv8_tmp.v

@@ -0,0 +1,18 @@
+//Copyright (C)2014-2024 Gowin Semiconductor Corporation.
+//All rights reserved.
+//File Title: Template file for instantiation
+//Tool Version: V1.9.9.03 (64-bit)
+//Part Number: GW1N-UV9QN88C6/I5
+//Device: GW1N-9
+//Created Time: Thu Nov 28 11:30:08 2024
+
+//Change the instance name and port connections to the signal names
+//--------Copy here to design--------
+
+    GowinClkDiv8 your_instance_name(
+        .clkout(clkout), //output clkout
+        .hclkin(hclkin), //input hclkin
+        .resetn(resetn) //input resetn
+    );
+
+//--------Copy end-------------------

src/src/ClkGen/GowinInternalOsc25MHz/GowinInternalOsc25MHz.ipc

@@ -0,0 +1,14 @@
+[General]
+ipc_version=4
+file=GowinInternalOsc25MHz
+module=GowinInternalOsc25MHz
+target_device=gw1n9-022
+type=clock_osc
+version=3.0
+
+[Config]
+FREQ=10
+LANG=0
+OSCILLATOR_FREQUENCY_210MHz=false
+OSCILLATOR_FREQUENCY_25MHz=false
+REGULATOR_ENABLE=false

src/src/ClkGen/GowinInternalOsc25MHz/GowinInternalOsc25MHz.mod

@@ -0,0 +1,14 @@
+-series GW1N
+-device GW1N-9
+-device_version 
+-package QFN88
+-part_number GW1N-UV9QN88C6/I5
+
+
+-mod_name GowinInternalOsc25MHz
+-file_name GowinInternalOsc25MHz
+-path C:/Gowin/Projects/CP2444v1_FPGA/src/src/ClkGen/GowinInternalOsc25MHz/
+-type OSC
+-file_type vlg
+-dev_type GW1N-9
+-freq_div 10

src/src/ClkGen/GowinInternalOsc25MHz/GowinInternalOsc25MHz.v

@@ -0,0 +1,20 @@
+//Copyright (C)2014-2024 Gowin Semiconductor Corporation.
+//All rights reserved.
+//File Title: IP file
+//Tool Version: V1.9.9.03 (64-bit)
+//Part Number: GW1N-UV9QN88C6/I5
+//Device: GW1N-9
+//Created Time: Thu Nov 28 11:28:13 2024
+
+module GowinInternalOsc25MHz (oscout);
+
+output oscout;
+
+OSC osc_inst (
+    .OSCOUT(oscout)
+);
+
+defparam osc_inst.FREQ_DIV = 10;
+defparam osc_inst.DEVICE = "GW1N-9";
+
+endmodule //GowinInternalOsc25MHz

src/src/ClkGen/GowinInternalOsc25MHz/GowinInternalOsc25MHz_tmp.v

@@ -0,0 +1,16 @@
+//Copyright (C)2014-2024 Gowin Semiconductor Corporation.
+//All rights reserved.
+//File Title: Template file for instantiation
+//Tool Version: V1.9.9.03 (64-bit)
+//Part Number: GW1N-UV9QN88C6/I5
+//Device: GW1N-9
+//Created Time: Thu Nov 28 11:28:13 2024
+
+//Change the instance name and port connections to the signal names
+//--------Copy here to design--------
+
+    GowinInternalOsc25MHz your_instance_name(
+        .oscout(oscout) //output oscout
+    );
+
+//--------Copy end-------------------

src/src/ClkGen/GowinPllFirst/GowinPllFirst.ipc

@@ -0,0 +1,24 @@
+[General]
+ipc_version=4
+file=GowinPllFirst
+module=GowinPllFirst
+target_device=gw1n9-022
+type=clock_rpll
+version=1.0
+
+[Config]
+CKLOUTD3=false
+CLKFB_SOURCE=0
+CLKIN_FREQ=24
+CLKOUTD=false
+CLKOUTP=false
+CLKOUT_BYPASS=false
+CLKOUT_DIVIDE_DYN=true
+CLKOUT_FREQ=210
+CLKOUT_TOLERANCE=0
+DYNAMIC=true
+LANG=0
+LOCK_EN=true
+MODE_GENERAL=true
+PLL_PWD=false
+RESET_PLL=false

src/src/ClkGen/GowinPllFirst/GowinPllFirst.mod

@@ -0,0 +1,33 @@
+-series GW1N
+-device GW1N-9
+-device_version 
+-package QFN88
+-part_number GW1N-UV9QN88C6/I5
+
+
+-mod_name GowinPllFirst
+-file_name GowinPllFirst
+-path C:/Gowin/Projects/CP2444v1_FPGA/src/src/ClkGen/GowinPllFirst/
+-type PLL
+-rPll true
+-file_type vlg
+-dev_type GW1N-9
+-dyn_idiv_sel false
+-idiv_sel 4
+-dyn_fbdiv_sel false
+-fbdiv_sel 35
+-dyn_odiv_sel false
+-odiv_sel 4
+-dyn_da_en true
+-rst_sig false
+-rst_sig_p false
+-fclkin 24
+-clkfb_sel 0
+-en_lock true
+-clkout_bypass false
+-clkout_ft_dir 1
+-en_clkoutp false
+-clkoutp_bypass false
+-en_clkoutd false
+-clkoutd_bypass false
+-en_clkoutd3 false

src/src/ClkGen/GowinPllFirst/GowinPllFirst.v

@@ -0,0 +1,63 @@
+//Copyright (C)2014-2024 Gowin Semiconductor Corporation.
+//All rights reserved.
+//File Title: IP file
+//Tool Version: V1.9.9.03 (64-bit)
+//Part Number: GW1N-UV9QN88C6/I5
+//Device: GW1N-9
+//Created Time: Thu Nov 28 14:25:29 2024
+
+module GowinPllFirst (clkout, lock, clkin);
+
+output clkout;
+output lock;
+input clkin;
+
+wire clkoutp_o;
+wire clkoutd_o;
+wire clkoutd3_o;
+wire gw_gnd;
+
+assign gw_gnd = 1'b0;
+
+rPLL rpll_inst (
+    .CLKOUT(clkout),
+    .LOCK(lock),
+    .CLKOUTP(clkoutp_o),
+    .CLKOUTD(clkoutd_o),
+    .CLKOUTD3(clkoutd3_o),
+    .RESET(gw_gnd),
+    .RESET_P(gw_gnd),
+    .CLKIN(clkin),
+    .CLKFB(gw_gnd),
+    .FBDSEL({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd}),
+    .IDSEL({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd}),
+    .ODSEL({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd}),
+    .PSDA({gw_gnd,gw_gnd,gw_gnd,gw_gnd}),
+    .DUTYDA({gw_gnd,gw_gnd,gw_gnd,gw_gnd}),
+    .FDLY({gw_gnd,gw_gnd,gw_gnd,gw_gnd})
+);
+
+defparam rpll_inst.FCLKIN = "24";
+defparam rpll_inst.DYN_IDIV_SEL = "false";
+defparam rpll_inst.IDIV_SEL = 3;
+defparam rpll_inst.DYN_FBDIV_SEL = "false";
+defparam rpll_inst.FBDIV_SEL = 34;
+defparam rpll_inst.DYN_ODIV_SEL = "false";
+defparam rpll_inst.ODIV_SEL = 4;
+defparam rpll_inst.PSDA_SEL = "0000";
+defparam rpll_inst.DYN_DA_EN = "true";
+defparam rpll_inst.DUTYDA_SEL = "1000";
+defparam rpll_inst.CLKOUT_FT_DIR = 1'b1;
+defparam rpll_inst.CLKOUTP_FT_DIR = 1'b1;
+defparam rpll_inst.CLKOUT_DLY_STEP = 0;
+defparam rpll_inst.CLKOUTP_DLY_STEP = 0;
+defparam rpll_inst.CLKFB_SEL = "internal";
+defparam rpll_inst.CLKOUT_BYPASS = "false";
+defparam rpll_inst.CLKOUTP_BYPASS = "false";
+defparam rpll_inst.CLKOUTD_BYPASS = "false";
+defparam rpll_inst.DYN_SDIV_SEL = 2;
+defparam rpll_inst.CLKOUTD_SRC = "CLKOUT";
+defparam rpll_inst.CLKOUTD3_SRC = "CLKOUT";
+defparam rpll_inst.DEVICE = "GW1N-9";
+
+endmodule //GowinPllFirst

src/src/ClkGen/GowinPllFirst/GowinPllFirst_tmp.v

@@ -0,0 +1,18 @@
+//Copyright (C)2014-2024 Gowin Semiconductor Corporation.
+//All rights reserved.
+//File Title: Template file for instantiation
+//Tool Version: V1.9.9.03 (64-bit)
+//Part Number: GW1N-UV9QN88C6/I5
+//Device: GW1N-9
+//Created Time: Thu Nov 28 14:25:29 2024
+
+//Change the instance name and port connections to the signal names
+//--------Copy here to design--------
+
+    GowinPllFirst your_instance_name(
+        .clkout(clkout), //output clkout
+        .lock(lock), //output lock
+        .clkin(clkin) //input clkin
+    );
+
+//--------Copy end-------------------

src/src/FifoCtrl/FifoCtrl.v

@@ -0,0 +1,188 @@
+////////////////////////////////////////////////////////////////////////////////////////////
+// Company:         TAIR
+// Engineer:        Chigrinskiy A.  
+// 
+// Create Date:     18/04/2024 
+// Design Name: 
+// Module Name:     FifoCtrl
+// Project Name:    SB_TMSG44V1_FPGA
+// Target Devices:  Board: SB_TMSG44v1. FPGA: GW1N-LV9PG256C6/I5
+// Tool versions:
+// Description:     This module is a controller for the FIFOs. It controls the read and write pointers of the FIFOs.
+//
+// Dependencies:  
+// Revision: 
+// Revision 1.0 - File Created
+// Additional Comments: 
+//
+////////////////////////////////////////////////////////////////////////////////////////////
+module FifoCtrl #(
+    parameter IN_WIDTH = 24,
+    parameter WR_NUM = 1,
+    parameter OUT_WIDTH = 24
+)(
+    input WrClk_i,
+    input RdClk_i,
+    input Rst_i,
+    input [IN_WIDTH-1:0] Data_i,
+    input Val_i,
+    input BusySpiM_i,
+    input FifoFull_i,
+    input FifoEmpty_i,
+
+    output [OUT_WIDTH-1:0] Data_o,
+    output reg ReadEn_o,
+    output reg  WriteEn_o,
+    output reg ValRdData_o
+
+);
+//================================================================================
+//	LOCAL PARAMETERS
+//================================================================================
+localparam DATA_WIDTH = WR_NUM*IN_WIDTH;
+
+//================================================================================
+//	REG/WIRE
+//================================================================================
+reg [DATA_WIDTH-1:0] dataReg;
+reg [1:0]  wrCnt;
+
+//================================================================================
+//  ASSIGNMENTS
+//================================================================================
+assign Data_o = dataReg[OUT_WIDTH-1:0];
+
+//================================================================================
+//	CODING
+//================================================================================
+always @(posedge WrClk_i) begin 
+    if (Rst_i) begin 
+        wrCnt <= 0;
+    end
+    else begin 
+        if (Val_i) begin 
+            wrCnt <= wrCnt + 1;
+        end
+        else if (wrCnt == WR_NUM) begin 
+            wrCnt <= 0;
+        end
+    end
+end
+
+always @(posedge WrClk_i) begin 
+    if (Rst_i) begin 
+        dataReg <= 0;
+    end
+    else begin
+        if (WR_NUM>1) begin
+            case (WR_NUM)
+            4: begin 
+                case (wrCnt)  
+                    0 : begin 
+                        if (Val_i) begin 
+                            dataReg[(4*IN_WIDTH)-1:(3*IN_WIDTH)] <= Data_i;
+                        end
+                    end
+                    1 : begin 
+                        if (Val_i) begin 
+                            dataReg[(3*IN_WIDTH)-1:(2*IN_WIDTH)] <= Data_i;
+                        end
+                    end
+                    2:  begin
+                        if (Val_i) begin
+                            dataReg[(2*IN_WIDTH)-1:IN_WIDTH] <= Data_i;
+                        end
+                    end
+                    3: begin
+                        if (Val_i) begin 
+                        dataReg[IN_WIDTH-1:0] <= Data_i;
+                        end
+                    end
+                endcase
+            end
+            3: begin
+                case (wrCnt)
+                0 : begin 
+                    if (Val_i) begin 
+                        dataReg[(3*IN_WIDTH)-1:(2*IN_WIDTH)] <= Data_i;
+                    end
+                end
+                1 : begin 
+                    if (Val_i) begin 
+                        dataReg[(2*IN_WIDTH)-1:IN_WIDTH] <= Data_i;
+                    end
+                end
+                2 : begin 
+                    if (Val_i) begin 
+                        dataReg[IN_WIDTH-1:0] <= Data_i;
+                    end
+                end
+                endcase
+            end
+            2 : begin 
+                case (wrCnt)
+                0: begin 
+                    if (Val_i) begin 
+                        dataReg[(2*IN_WIDTH)-1:IN_WIDTH] <= Data_i;
+                    end
+                end
+                1: begin 
+                    if (Val_i) begin 
+                        dataReg[IN_WIDTH-1:0] <= Data_i;
+                    end
+                end
+                endcase
+            end
+            endcase
+        end
+        else begin
+            if (Val_i) begin 
+                dataReg[IN_WIDTH-1:0] <= Data_i;
+            end
+        end
+    end
+end
+
+always @(posedge WrClk_i) begin
+    if (Rst_i) begin 
+        WriteEn_o <= 1'b0;
+    end
+    else begin  
+        if (Val_i && wrCnt == WR_NUM-1 && !FifoFull_i) begin
+            WriteEn_o <= 1'b1;
+        end
+        else begin 
+            WriteEn_o <= 1'b0;
+        end
+    end
+end
+
+always @(posedge RdClk_i) begin
+    if (Rst_i) begin 
+        ReadEn_o <= 1'b0;
+    end
+    else begin  
+        if (!FifoEmpty_i && !BusySpiM_i) begin 
+            ReadEn_o <= 1'b1;
+        end
+        else begin 
+            ReadEn_o <= 1'b0;
+        end
+    end
+end
+
+always @(posedge RdClk_i) begin 
+    if (Rst_i) begin 
+        ValRdData_o <= 1'b0;
+    end
+    else begin
+        if (!FifoEmpty_i && !BusySpiM_i) begin 
+            ValRdData_o <= 1'b1;
+        end
+        else begin 
+            ValRdData_o <= 1'b0;
+        end
+    end
+end
+
+endmodule

src/src/Gpio1Ctrl/Gpio1Ctrl.v

@@ -0,0 +1,37 @@
+////////////////////////////////////////////////////////////////////////////////////////////
+// Company:			TAIR
+// Engineer:		Zaytsev Mikhail
+// 
+// Create Date:		24/04/2024 
+// Design Name: 
+// Module Name:		Gpio1Ctrl 
+// Project Name:	SB_TMSG44V1_FPGA
+// Target Devices:	Board: SB_TMSG44v1. FPGA: GW1N-LV9PG256C6/I5
+// Tool versions:
+// Description:		The module saves data to the register by validity signal for GPIO devices.
+//
+// Dependencies:	
+// Revision: 
+// Revision 1.0 - File Created
+// Additional Comments: 
+//
+////////////////////////////////////////////////////////////////////////////////////////////
+module Gpio1Ctrl (
+	input Clk_i,
+	
+	input ValGpioDataToFifo_i,
+	input [23:0] Data_i,
+	input ValDataFromSpi_i,
+
+	input FlagDirectGpio1_i,
+
+	output reg [23:0] GpioReg_o
+);
+
+always @(posedge Clk_i) begin 
+	if (ValGpioDataToFifo_i || (FlagDirectGpio1_i && ValDataFromSpi_i)) begin 
+		GpioReg_o <= Data_i[23:0];
+	end
+end
+
+endmodule

src/src/InitRst/InitRst.v

@@ -0,0 +1,104 @@
+module InitRst (
+    clk_i,
+    signal_o
+);
+
+//================================================================================
+//
+//  FUNCTIONS
+//
+//================================================================================
+
+    function integer bit_num;
+        input integer value;
+        begin
+            bit_num = 0;
+            while (value > 0) begin
+                value   = value >> 1;
+                bit_num = bit_num + 1;
+            end
+        end
+    endfunction
+
+//================================================================================
+//
+//  PARAMETER/LOCALPARAM
+//
+//================================================================================
+
+    parameter   DELAY_VALUE     = 12000;
+    localparam  DELAY_CNT_W     = bit_num(DELAY_VALUE);
+
+//================================================================================
+//
+//  PORTS
+//
+//================================================================================
+
+    input           clk_i;
+    output  reg     signal_o;
+
+//================================================================================
+//
+//  STATE MACHINE STATES
+//
+//================================================================================
+
+    localparam      SM_RST_S    = 1'b0;
+    localparam      SM_DONE_S   = 1'b1;
+
+//================================================================================
+//
+//  REG/WIRE
+//
+//================================================================================
+
+    reg                         curr_state  = SM_RST_S;
+    reg     [DELAY_CNT_W-1:0]   delay_cnt   = {DELAY_CNT_W{1'b0}};
+    reg                         delay_flag  = 1'b0;
+
+    reg                         next_state;
+    reg     [DELAY_CNT_W-1:0]   delay_cnt_next	=	{DELAY_CNT_W{1'b0}};
+    reg                         signal_next;
+
+//================================================================================
+//
+//  CODING
+//
+//================================================================================
+
+initial begin
+    curr_state  = SM_RST_S;
+    delay_cnt   = {DELAY_CNT_W{1'b0}};
+    signal_o    = 1'b1;
+    delay_flag  = 1'b0;
+end
+
+always @(posedge clk_i) begin
+    curr_state  <= next_state;
+    delay_cnt   <= delay_cnt_next;
+    signal_o    <= signal_next;
+    delay_flag  <= delay_cnt > (DELAY_VALUE - 1);
+end
+
+always @(*) begin
+    next_state      = SM_RST_S;
+    delay_cnt_next  = delay_cnt;
+    signal_next     = 1'b1;
+    case(curr_state)
+        SM_RST_S    : begin
+            if (delay_flag) begin
+                next_state      = SM_DONE_S;
+            end else begin
+                next_state      = SM_RST_S;
+                delay_cnt_next  = delay_cnt + {{(DELAY_CNT_W-1){1'b0}}, 1'b1};
+            end
+        end
+        SM_DONE_S   : begin
+            signal_next = 1'b0;
+            next_state  = SM_DONE_S;
+        end
+    endcase
+end
+
+endmodule

src/src/InterfaceArbiter/InterfaceArbiterCp2444v1.v

@@ -0,0 +1,363 @@
+`timescale 1ns / 1ps
+
+//////////////////////////////////////////////////////////////////////////////////
+// Company: Tair
+// Engineer: Churbanov S.
+// 
+// Create Date:     
+// Design Name: 
+// Module Name:    InterfaceArbiter
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+
+module InterfaceArbiterCp2444v1 
+#(	
+	parameter OUTWORDWIDTH = 24,
+	parameter SSPIWORDWIDTH = 24,
+	parameter QSPIWORDWIDTH = SSPIWORDWIDTH/4
+)
+(
+	input Rst_i,
+	input Clk_i,
+	
+	input Sck_i,
+	input Ss_i,
+	
+	input Mosi0_i,
+	input Mosi1_i,
+	input Mosi2_i,
+	input Mosi3_i,
+	
+	
+	output DataVal_o,
+	output [OUTWORDWIDTH-1:0] Data_o
+);
+
+//================================================================================
+//  REG/WIRE
+
+	localparam [1:0] IDLE = 0;
+	localparam [1:0] DATARX = 1;
+	
+	reg [OUTWORDWIDTH-1:0] dataRegSSpi;
+	reg [OUTWORDWIDTH-1:0] dataRegQSpi;
+	
+	reg [OUTWORDWIDTH-1:0] captRegSspi;
+	
+	reg [QSPIWORDWIDTH-1:0] captReg0;
+	reg [QSPIWORDWIDTH-1:0] captReg1;
+	reg [QSPIWORDWIDTH-1:0] captReg2;
+	reg [QSPIWORDWIDTH-1:0] captReg3;
+
+	reg [OUTWORDWIDTH-1:0] captRegSspiR;
+	reg [OUTWORDWIDTH-1:0] captRegSspiRR;
+
+	reg [QSPIWORDWIDTH-1:0] captReg0R;
+	reg [QSPIWORDWIDTH-1:0] captReg0RR;
+	reg [QSPIWORDWIDTH-1:0] captReg1R;
+	reg [QSPIWORDWIDTH-1:0] captReg1RR;
+	reg [QSPIWORDWIDTH-1:0] captReg2R;
+	reg [QSPIWORDWIDTH-1:0] captReg2RR;
+	reg [QSPIWORDWIDTH-1:0] captReg3R;
+	reg [QSPIWORDWIDTH-1:0] captReg3RR;
+
+	reg ssReg;
+	reg ssRegR;
+	reg ssRegRR;
+	
+	reg spiMode;
+	
+	wire ssPos;
+	reg ssPosR;
+	
+	reg dataValReg;
+	
+	reg [OUTWORDWIDTH/4-1:0] ssCnt;
+	reg [16:0] wordsCnt;
+	// wire [OUTWORDWIDTH/4-1:0] ssCntRstThresh = (spiMode) ? QSPIWORDWIDTH-1:SSPIWORDWIDTH-1;
+	
+	reg [16:0] wordsNum;
+	
+	reg [1:0] nextState;
+	reg [1:0] currState;
+	
+	reg rxDone;
+
+	wire plsToggleSyncSignal;
+	reg plsToggle;
+	reg plsToggleSyncA;
+	reg plsToggleSyncB;
+	reg plsToggleSyncC;
+	reg plsToggleSyncSignalR;
+
+//================================================================================
+//  ASSIGNMENTS
+	assign ssPos = ssRegR & !ssRegRR;
+
+	
+	assign DataVal_o = plsToggleSyncSignalR;
+	assign Data_o = (spiMode)? dataRegQSpi:dataRegSSpi;
+
+	assign plsToggleSyncSignal = plsToggleSyncB^plsToggleSyncA;
+
+	//assign ssCntRstThresh = (spiMode) ? QSPIWORDWIDTH-1:SSPIWORDWIDTH-1;
+	
+//================================================================================
+//  CODING
+
+	always @(posedge Clk_i) begin 
+    	if (Rst_i) begin 
+    	    plsToggleSyncA <= 1'b0;
+    	    plsToggleSyncB <= 1'b0;
+    	end
+    	else begin 
+    	    plsToggleSyncA <= plsToggle;
+    	    plsToggleSyncB <= plsToggleSyncA;
+    	end
+	end
+
+	always @(posedge Clk_i) begin 
+	    if (Rst_i) begin 
+	        plsToggleSyncC <= 1'b0;
+	    end
+	    else begin
+	        plsToggleSyncC <= plsToggleSyncB;
+	    end
+	end
+	
+	always @(posedge Ss_i or posedge Rst_i) begin 
+		if (Rst_i) begin 
+			plsToggle <= 1'b0;
+		end
+		else begin 
+			if (Ss_i) begin 
+				plsToggle <= ~plsToggle;
+			end
+			else begin 
+				plsToggle <= plsToggle;
+			end
+		end
+	end
+
+	always @(posedge Clk_i) begin 
+		if (Rst_i) begin 
+			plsToggleSyncSignalR <= 1'b0;
+		end
+		else begin 
+			plsToggleSyncSignalR <= plsToggleSyncSignal;
+		end
+	end
+
+	always @(posedge Sck_i or posedge Rst_i) begin 
+		if (Rst_i) begin 
+			captRegSspi <= 0;
+
+			captReg0 <= 0;
+			captReg1 <= 0;
+			captReg2 <= 0;
+			captReg3 <= 0;
+		end
+		else begin 
+			if (!Ss_i) begin 
+				captRegSspi <= {captRegSspi[OUTWORDWIDTH-2:0], Mosi0_i};
+				
+				captReg0 <= {captReg0[QSPIWORDWIDTH-2:0], Mosi0_i};
+				captReg1 <= {captReg1[QSPIWORDWIDTH-2:0], Mosi1_i};
+				captReg2 <= {captReg2[QSPIWORDWIDTH-2:0], Mosi2_i};
+				captReg3 <= {captReg3[QSPIWORDWIDTH-2:0], Mosi3_i};
+			end
+		end
+	end
+
+	always @(posedge Clk_i) begin 
+		if (Rst_i) begin 
+			captRegSspiR <= 0;
+			captRegSspiRR <= 0;
+		end
+		else begin 
+			captRegSspiR <= captRegSspi;
+			captRegSspiRR <= captRegSspiR;
+		end
+	end
+
+	always @(posedge Clk_i) begin 
+		if (Rst_i) begin 
+			captReg0R <= 0;
+			captReg0RR <= 0;
+			captReg1R <= 0;
+			captReg1RR <= 0;
+			captReg2R <= 0;
+			captReg2RR <= 0;
+			captReg3R <= 0;
+			captReg3RR <= 0;
+		end
+		else begin 
+			captReg0R <= captReg0;
+			captReg0RR <= captReg0R;
+			captReg1R <= captReg1;
+			captReg1RR <= captReg1R;
+			captReg2R <= captReg2;
+			captReg2RR <= captReg2R;
+			captReg3R <= captReg3;
+			captReg3RR <= captReg3R;
+		end
+	end
+	
+	always @(posedge Sck_i or posedge Rst_i) begin 
+		if (Rst_i) begin 
+			ssCnt <= 0;
+		end
+		else begin 
+			if (currState == IDLE) begin
+				if (!Ss_i) begin 
+					ssCnt <= ssCnt+1; 
+				end
+			end else begin
+				ssCnt <= 0;
+			end
+		end
+	end
+
+	always @(posedge Clk_i) begin
+		if (!Rst_i) begin
+			if (currState == DATARX) begin
+				if (plsToggleSyncSignal) begin
+					if (wordsCnt == wordsNum-1) begin
+						wordsCnt <= 0;
+						rxDone <= 1'b1;
+					end else begin
+						wordsCnt <= wordsCnt+1;
+						rxDone <= 1'b0;
+					end
+				end
+			end else begin
+				wordsCnt <= 0;
+				rxDone <= 1'b0;
+			end
+		end else begin
+			wordsCnt <= 0;
+			rxDone <= 1'b0;
+		end
+	end
+	
+	always @(posedge Sck_i or posedge Rst_i) begin 
+		if (Rst_i) begin 
+			spiMode <= 1'b0;
+		end
+		else begin
+			if (currState == IDLE) begin 
+				if (ssCnt == 1) begin 
+					if (captRegSspi[0]) begin 
+						spiMode <= 1'b1; 
+					end 
+					else begin 
+						spiMode <= 1'b0; 
+					end
+				end
+			end
+		end
+	end
+	
+	always @(posedge Clk_i) begin
+		if (!Rst_i) begin
+			if (currState == IDLE) begin
+				if (!spiMode) begin
+					wordsNum <= dataRegSSpi[17:1];
+				end else begin
+					wordsNum <= dataRegQSpi[22]+dataRegQSpi[21]+dataRegQSpi[20]+dataRegQSpi[19]+dataRegQSpi[18]+dataRegQSpi[17];
+				end 
+			end
+		end else begin
+			wordsNum <= 0;
+		end
+	end 
+	
+	always @(posedge Clk_i) begin
+		if (!Rst_i) begin
+			ssReg <= Ss_i;
+			ssRegR <= ssReg;
+			ssRegRR <= ssRegR;
+			ssPosR <= ssPos;
+		end else begin
+			ssReg <= 1;
+			ssRegR <= 1;
+			ssRegRR <= 1;
+			ssPosR <= 0;
+		end
+	end 
+	
+	always @(posedge Clk_i) begin
+		if (!Rst_i) begin
+			if (plsToggleSyncSignal) begin
+				dataRegSSpi <= captRegSspiRR;
+				dataRegQSpi <= {captReg0R,captReg1R,captReg2R,captReg3R};
+				dataValReg <= 1'b1;
+			end else begin
+				dataValReg <= 1'b0;
+			end
+		end else begin
+			dataRegSSpi <= 0;
+			dataRegQSpi <= 0;
+			dataValReg <= 0;
+		end
+	end
+
+	always @(posedge Clk_i) begin
+		if (Rst_i) begin
+			currState <= IDLE;
+		end else begin
+			currState <= nextState;
+		end
+	end
+
+	always @(*) begin
+		nextState = IDLE;
+		case(currState)
+		IDLE		:begin
+						if (plsToggleSyncSignalR)	begin
+							nextState = DATARX;
+						end	else begin
+							nextState = IDLE;
+						end
+					end
+
+		DATARX		:begin
+						if (rxDone) begin
+							nextState  = IDLE;
+						end	else begin
+							nextState  = DATARX;
+						end
+					end
+		endcase
+	end
+
+endmodule
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+

src/src/PacketAnalyzer1Mosi/PacketAnalyzer1MosiCp2444v1.v

@@ -0,0 +1,151 @@
+////////////////////////////////////////////////////////////////////////////////////////////
+// Company:			TAIR
+// Engineer:		Zaytsev Mikhail
+// 
+// Create Date:		19/04/2024 
+// Design Name: 
+// Module Name:		PacketAnalyzer1Mosi 
+// Project Name:	BOCHV3_FPGA
+// Target Devices:	Board: BOCHV3. FPGA: GW1N-UV9QN88
+// Tool versions:
+// Description:		The module analyzes the data on the DataFromSpi_i[23:0] bus using the 
+// 					ValDataFromSpi_i validity signal.  When a configuration packet is received, 
+// 					data is captured into the two internal registers devId and cntData. 
+// 					Next, the cntData register is decremented with each incoming data parcel 
+// 					until it becomes zero. If the value in the register is equal to zero means 
+// 					that the module is ready to receive the next configuration packet. 
+// 					As long as the value of cntData is not equal to zero at the output of the 
+// 					module is active signal FlagDirect..._o for the device specified in the 
+// 					register devId. The module also has an output signal Busy_o, which signals 
+// 					that the module is in the state of processing data received in 1MOSI mode.
+// Dependencies:	
+// Revision: 
+// Revision 1.0 - File Created
+// Additional Comments: 
+//
+////////////////////////////////////////////////////////////////////////////////////////////
+module PacketAnalyzer1MosiCp2444v1 (
+	input Clk_i,
+	input Rst_i,
+
+	input [23:0] DataFromSpi_i,
+	input ValDataFromSpi_i,
+
+	input BusyMosi4_i,
+
+	output reg FlagDirectSwCtrlP1_o,
+	output reg FlagDirectAttCtrlP1_o,
+	output reg FlagDirectAttCtrlP2_o,
+	output reg FlagDirectAttCtrlP3_o,
+	output reg FlagDirectAttCtrlP4_o,
+	output reg FlagDirectGpio_o,
+
+	output reg Busy_o
+);
+
+//==========================================
+// Registers
+//==========================================
+reg [4:0] devId;
+reg [16:0] cntData;
+
+//==========================================
+// Wires
+//==========================================
+
+//==========================================
+// Parameters
+//==========================================
+localparam DEV_ID_SW_CTRL_P1 = 5'd0;
+localparam DEV_ID_ATT_CTRL_P1 = 5'd1;
+localparam DEV_ID_ATT_CTRL_P2 = 5'd2;
+localparam DEV_ID_ATT_CTRL_P3 = 5'd3;
+localparam DEV_ID_ATT_CTRL_P4 = 5'd4;
+localparam DEV_ID_GPIO = 5'd5;
+
+//==========================================
+// Assignments
+//==========================================
+
+//==========================================================================//
+//									CODING									//
+//==========================================================================//
+always @(posedge Clk_i) begin
+	if(Rst_i || BusyMosi4_i) begin
+		devId 	<= 5'b0;
+		cntData <= 17'b0;
+	end 
+	else if (ValDataFromSpi_i) begin
+		if (cntData == 0) begin 
+			if (DataFromSpi_i[23] == 0) begin
+				cntData <= DataFromSpi_i[17:1];
+				devId 	<= DataFromSpi_i[22:18];
+			end
+			else begin
+				cntData <= 5'b0;
+				devId 	<= 17'b0;
+			end
+		end	
+		else begin
+			cntData <= cntData - 1'b1;	
+		end
+	end
+	else if (cntData == 0) begin
+		devId <= 5'b0;
+	end
+end
+
+always @(posedge Clk_i) begin
+	if (Rst_i) begin
+		FlagDirectSwCtrlP1_o <= 1'b0;
+		FlagDirectAttCtrlP1_o <= 1'b0;
+		FlagDirectAttCtrlP2_o <= 1'b0;
+		FlagDirectAttCtrlP3_o <= 1'b0;
+		FlagDirectAttCtrlP4_o <= 1'b0;
+		FlagDirectGpio_o <= 1'b0;
+	end
+	else if (cntData != 0) begin
+		case (devId)
+			DEV_ID_SW_CTRL_P1: begin 
+				FlagDirectSwCtrlP1_o <= 1'b1;
+			end
+			DEV_ID_ATT_CTRL_P1: begin 
+				FlagDirectAttCtrlP1_o <= 1'b1;
+			end
+			DEV_ID_ATT_CTRL_P2: begin 
+				FlagDirectAttCtrlP2_o <= 1'b1;
+			end
+			DEV_ID_ATT_CTRL_P3: begin 
+				FlagDirectAttCtrlP3_o <= 1'b1;
+			end
+			DEV_ID_ATT_CTRL_P4: begin 
+				FlagDirectAttCtrlP4_o <= 1'b1;
+			end
+			DEV_ID_GPIO: begin 
+				FlagDirectGpio_o <= 1'b1;
+			end
+		endcase
+	end
+	else begin
+		FlagDirectSwCtrlP1_o <= 1'b0;
+		FlagDirectAttCtrlP1_o <= 1'b0;
+		FlagDirectAttCtrlP2_o <= 1'b0;
+		FlagDirectAttCtrlP3_o <= 1'b0;
+		FlagDirectAttCtrlP4_o <= 1'b0;
+		FlagDirectGpio_o <= 1'b0;
+	end
+end
+
+always @(posedge Clk_i) begin
+	if (Rst_i) begin
+		Busy_o <= 1'b0;
+	end
+	else if (cntData != 0) begin
+		Busy_o <= 1'b1;
+	end
+	else begin
+		Busy_o <= 1'b0;
+	end
+end
+
+endmodule

src/src/PacketAnalyzer4Mosi/PacketAnalyzer4MosiCp2444v1.v

@@ -0,0 +1,162 @@
+////////////////////////////////////////////////////////////////////////////////////////////
+// Company:			TAIR
+// Engineer:		Zaytsev Mikhail
+// 
+// Create Date:		18/04/2024 
+// Design Name: 
+// Module Name:		PacketAnalyzer4Mosi 
+// Project Name:	Cp2444v1
+// Target Devices:	Board: Cp2444v1. FPGA: GW1N-UV9QN88
+// Tool versions:
+// Description:		The module analyzes the input data bus DataFromSpi_i[23:0] by the 
+//					validity signal ValDataFromSpi_i. When a configuration packet is 
+//					received, it is captured into the internal register. Further, each 
+//					incoming data packet decrements the internal configuration register 
+//					until the internal configuration register is zero, which means that 
+//					the module is ready to receive the next configuration packet. Each 
+//					decrement sets the data validity bit for the specific end device. 
+//					The module also has an output signal Busy_o, which signals that 
+//					the module is in the state of processing the data received in 
+//					4MOSI mode for writing to the FIFO.
+//
+// Dependencies:	
+// Revision: 
+// Revision 1.0 - File Created
+// Additional Comments: 
+//
+////////////////////////////////////////////////////////////////////////////////////////////
+module PacketAnalyzer4MosiCp2444v1 (
+	input Clk_i,
+	input Rst_i,
+
+	input [23:0] DataFromSpi_i,
+	input ValDataFromSpi_i,
+
+	input BusyMosi1_i,
+
+	output reg ValGpioDataToFifo_o,
+	output reg ValSwP1DataToFifo_o,
+	output reg ValAttP1DataToFifo_o,
+	output reg ValAttP2DataToFifo_o,
+	output reg ValAttP3DataToFifo_o,
+	output reg ValAttP4DataToFifo_o,
+
+	output reg Busy_o
+);
+
+//==========================================
+// Registers
+//==========================================
+reg [22:0] dataSpiReg;
+
+//==========================================
+// Wires
+//==========================================
+wire gpioOr;
+wire swP1Or;
+wire attP1Or;
+wire attP2Or;
+wire attP3Or;
+wire attP4Or;
+
+wire [5:0] selector;
+
+//==========================================
+// Parameters
+//==========================================
+localparam [22:0] DECREMENT_GPIO = 23'h400000; //23'b100 0000 0000 0000 0000 0000
+localparam [22:0] DECREMENT_SW_P1 = 23'h200000; //23'b010 0000 0000 0000 0000 0000
+localparam [22:0] DECREMENT_ATT_P1 = 23'h100000; //23'b001 0000 0000 0000 0000 0000
+localparam [22:0] DECREMENT_ATT_P2 = 23'h80000; //23'b000 1000 0000 0000 0000 0000
+localparam [22:0] DECREMENT_ATT_P3 = 23'h40000; //23'b000 0100 0000 0000 0000 0000
+localparam [22:0] DECREMENT_ATT_P4 = 23'h20000; //23'b000 0010 0000 0000 0000 0000
+ 
+//==========================================
+// Assignments
+//==========================================
+assign gpioOr = |dataSpiReg[22];
+assign swP1Or = |dataSpiReg[21];
+assign attP1Or = |dataSpiReg[20];
+assign attP2Or = |dataSpiReg[19];
+assign attP3Or = |dataSpiReg[18];
+assign attP4Or = |dataSpiReg[17];
+
+assign selector = {gpioOr, swP1Or, attP1Or, attP2Or, attP3Or, attP4Or};
+
+//==========================================================================//
+//									CODING									//
+//==========================================================================//
+always @(posedge Clk_i) begin
+	if (Rst_i) begin
+		Busy_o <= 1'b0;
+	end
+	else if (dataSpiReg != 0) begin
+		Busy_o <= 1'b1;
+	end
+	else begin
+		Busy_o <= 1'b0;
+	end
+end
+
+always @(posedge Clk_i) begin
+	if (Rst_i || BusyMosi1_i) begin
+		dataSpiReg <= 23'b0;
+		ValGpioDataToFifo_o <= 1'b0;
+		ValSwP1DataToFifo_o <= 1'b0;
+		ValAttP1DataToFifo_o <= 1'b0;
+		ValAttP2DataToFifo_o <= 1'b0;
+		ValAttP3DataToFifo_o <= 1'b0;
+		ValAttP4DataToFifo_o <= 1'b0;
+	end
+	else if (ValDataFromSpi_i) begin
+		if ((dataSpiReg == 0) && (DataFromSpi_i[23] == 1'b1)) begin
+			dataSpiReg[22:1] <= DataFromSpi_i[22:1];
+		end
+		else begin
+			casez(selector)
+			6'b1?????: begin //Gpio
+				dataSpiReg <= dataSpiReg - DECREMENT_GPIO;
+				ValGpioDataToFifo_o <= 1'b1;
+			end
+			6'b01????: begin //SwP1
+				dataSpiReg <= dataSpiReg - DECREMENT_SW_P1;
+				ValSwP1DataToFifo_o <= 1'b1;
+			end
+			6'b001???: begin //AttP1
+				dataSpiReg <= dataSpiReg - DECREMENT_ATT_P1;
+				ValAttP1DataToFifo_o <= 1'b1;
+			end
+			6'b0001??: begin //AttP2
+				dataSpiReg <= dataSpiReg - DECREMENT_ATT_P2;
+				ValAttP2DataToFifo_o <= 1'b1;
+			end
+			6'b00001?: begin //AttP3
+				dataSpiReg <= dataSpiReg - DECREMENT_ATT_P3;
+				ValAttP3DataToFifo_o <= 1'b1;
+			end
+			6'b000001: begin //AttP4
+				dataSpiReg <= dataSpiReg - DECREMENT_ATT_P4;
+				ValAttP4DataToFifo_o <= 1'b1;
+			end
+			default: begin
+				ValGpioDataToFifo_o <= 1'b0;
+				ValSwP1DataToFifo_o <= 1'b0;
+				ValAttP1DataToFifo_o <= 1'b0;
+				ValAttP2DataToFifo_o <= 1'b0;
+				ValAttP3DataToFifo_o <= 1'b0;
+				ValAttP4DataToFifo_o <= 1'b0;
+			end
+		endcase
+		end
+	end
+	else begin
+		ValGpioDataToFifo_o <= 1'b0;
+		ValSwP1DataToFifo_o <= 1'b0;
+		ValAttP1DataToFifo_o <= 1'b0;
+		ValAttP2DataToFifo_o <= 1'b0;
+		ValAttP3DataToFifo_o <= 1'b0;
+		ValAttP4DataToFifo_o <= 1'b0;
+	end
+end
+
+endmodule

src/src/SpiM/SpiM.v

@@ -0,0 +1,111 @@
+////////////////////////////////////////////////////////////////////////////////////////////
+// Company:         TAIR
+// Engineer:        Chigrinskiy A.  
+// 
+// Create Date:     18/04/2024 
+// Design Name: 
+// Module Name:     SPIm
+// Project Name:    SB_TMSG44V1_FPGA
+// Target Devices:  Board: SB_TMSG44v1. FPGA: GW1N-LV9PG256C6/I5
+// Tool versions:
+// Description:     This module implements SPI master interface
+//
+// Dependencies:  
+// Revision: 
+// Revision 1.0 - File Created
+// Additional Comments: 
+//
+////////////////////////////////////////////////////////////////////////////////////////////
+module SpiM #(
+    parameter DATA_WIDTH = 24
+)(
+    input Clk_i,
+    input Rst_i,
+    input Val_i,
+    input [DATA_WIDTH-1:0] SpiData_i,
+
+    output Ss_o,
+    output Mosi_o,
+    output Sck_o,
+    output Busy_o
+);
+
+//================================================================================
+//FUNCTIONS
+//================================================================================
+function integer log2;
+input [31:0] value;
+	begin
+		log2 = 0;
+		while (value > 1) begin
+			value   = value >> 1;
+			log2    = log2 + 1;
+		end
+		if	((2**log2)<DATA_WIDTH)	begin
+			log2	=	log2+1;
+		end	
+	end
+endfunction
+
+//================================================================================
+//	REG/WIRE
+//================================================================================
+reg [log2(DATA_WIDTH)-1:0] ssCnt;
+reg [DATA_WIDTH-1:0] mosiReg;
+reg	ssReg;
+
+//================================================================================
+//  ASSIGNMENTS
+//================================================================================
+assign Ss_o = ssReg;
+assign Mosi_o = (!ssReg) ? mosiReg[DATA_WIDTH-1] : 1'b0;
+assign Sck_o = (!ssReg) ? Clk_i : 1'b0;
+assign Busy_o = !ssReg;
+
+//================================================================================
+//	CODING
+//================================================================================
+always @(negedge Clk_i) begin 
+    if (Rst_i) begin 
+        ssCnt <= 7'h0;
+    end
+    else begin
+        if (!ssReg) begin
+			ssCnt <= ssCnt+1;
+		end else begin
+			ssCnt <= 0;
+		end
+    end
+end
+
+always @(negedge Clk_i) begin 
+    if (Rst_i) begin 
+        mosiReg <= 0;
+    end
+    else begin 
+        if (!ssReg) begin 
+            mosiReg <= mosiReg << 1;
+        end
+        else begin
+            if (Val_i) begin
+                mosiReg <= SpiData_i;
+            end
+        end
+    end
+end
+
+always @(negedge Clk_i) begin 
+    if (Rst_i) begin 
+        ssReg <= 1'b1;
+    end
+    else begin 
+        if (Val_i) begin
+			ssReg <= 0;
+		end
+		if (ssCnt == DATA_WIDTH-1) begin
+			ssReg <= 1;
+		end
+    end
+end
+
+endmodule

src/src/Top/TopCp2444v1.v

@@ -0,0 +1,337 @@
+module TopCp2444v1 #(
+    parameter WORDWIDTH = 24,
+    parameter SSPIWORDWIDTH = 24
+)
+(
+input Clk_i,    
+input Rst_i,
+
+
+input Sck_i,
+input Ss_i,
+
+input Mosi0_i,
+input Mosi1_io,
+input Mosi2_i,
+input Mosi3_i,
+
+/* SW_P1 */
+output reg  SwP1Mosi_o,
+output reg  SwP1Cs_o,
+output reg  SwP1Sck_o,
+/* ATT_P1 */
+output reg  AttP1Mosi_o,
+output reg  AttP1Cs_o,
+output reg  AttP1Sck_o,
+/* ATT_P2 */
+output reg  AttP2Mosi_o,
+output reg  AttP2Cs_o,
+output reg  AttP2Sck_o,
+/* ATT_P3 */
+output reg  AttP3Mosi_o,
+output reg  AttP3Cs_o,
+output reg  AttP3Sck_o,
+/* ATT_P4 */
+output reg  AttP4Mosi_o,
+output reg  AttP4Cs_o,
+output reg  AttP4Sck_o,
+/* CF CONTROL */
+output FpgaCfP1_o,
+output FpgaCfP2_o,
+output FpgaCfP3_o,
+output FpgaCfP4_o,
+/* SWA_CONTROL */
+output FpgaP12SwP1_o,
+output FpgaP12SwP2_o,
+output FpgaP34SwP1_o,
+output FpgaP34SwP2_o,
+/* LEDs CONTROL */
+output FpgaLedP1_o,
+output FpgaLedP2_o,
+output FpgaLedP3_o,
+output FpgaLedP4_o
+
+);
+//***********************************************
+//	                REG/WIRE
+//***********************************************
+wire [23:0]     spiData;
+wire            spiDataVal;
+
+/* PacketAnalyzer1Mosi Flags */
+wire flagDirectSwP1;
+wire flagDirectAttP1;
+wire flagDirectAttP2;
+wire flagDirectAttP3;
+wire flagDirectAttP4;
+/* PacketAnalyzer4Mosi Flags */
+wire valGpioDataToFifo;
+wire valSwP1DataToFifo;
+wire valAttP1DataToFifo;
+wire valAttP2DataToFifo;
+wire valAttP3DataToFifo;
+wire valAttP4DataToFifo;
+/* ClkGen wires */
+wire clk60;
+wire clk26dot25;
+wire gclk; //24MHz
+/* InitRst */ 
+wire initRst;
+/* Busy wires */
+wire busyMosi1;
+wire busyMosi4;
+/* Gpio1Ctrl */
+wire [23:0] gpio1CtrlData;
+/* SpiM signals from devices */
+/* ATT_P1 */
+wire attP1Cs;
+wire attP1Sck;
+wire attP1Mosi;
+/* ATT_P2 */
+wire attP2Cs;
+wire attP2Sck;
+wire attP2Mosi;
+/* ATT_P3 */
+wire attP3Cs;
+wire attP3Sck;
+wire attP3Mosi;
+/* ATT_P4 */
+wire attP4Cs;
+wire attP4Sck;
+wire attP4Mosi;
+/* SW_P1 */
+wire swP1Cs;
+wire swP1Sck;
+wire swP1Mosi;
+
+//***********************************************
+//	                ASSIGNMENTS
+//***********************************************
+assign FpgaLedP1_o = gpio1CtrlData[0];
+assign FpgaLedP2_o = gpio1CtrlData[1];
+assign FpgaLedP3_o = gpio1CtrlData[2];
+assign FpgaLedP4_o = gpio1CtrlData[3];
+assign FpgaP12SwP1_o = gpio1CtrlData[4];
+assign FpgaP12SwP2_o = gpio1CtrlData[5];
+assign FpgaP34SwP1_o = gpio1CtrlData[6];
+assign FpgaP34SwP2_o = gpio1CtrlData[7];
+assign FpgaCfP1_o = gpio1CtrlData[8];
+assign FpgaCfP2_o = gpio1CtrlData[9];
+assign FpgaCfP3_o = gpio1CtrlData[10];
+assign FpgaCfP4_o = gpio1CtrlData[11];
+
+//***********************************************
+//	                CODING
+//***********************************************
+
+/*Mux SpiM signals from devices*/
+always @(*) begin 
+    if (flagDirectSwP1) begin //SW_P1
+        SwP1Mosi_o = Mosi0_i;
+        SwP1Cs_o = Ss_i;
+        SwP1Sck_o = Sck_i;
+    end
+    else begin
+        SwP1Mosi_o = swP1Mosi;
+        SwP1Cs_o = swP1Cs;
+        SwP1Sck_o = swP1Sck;
+    end
+    if (flagDirectAttP1) begin //ATT_P1
+        AttP1Mosi_o = Mosi0_i;
+        AttP1Cs_o = Ss_i;
+        AttP1Sck_o = Sck_i;
+    end
+    else begin
+        AttP1Mosi_o = attP1Mosi;
+        AttP1Cs_o = attP1Cs;
+        AttP1Sck_o = attP1Sck;
+    end
+    if (flagDirectAttP2) begin //ATT_P2
+        AttP2Mosi_o = Mosi0_i;
+        AttP2Cs_o = Ss_i;
+        AttP2Sck_o = Sck_i;
+    end
+    else begin
+        AttP2Mosi_o = attP2Mosi;
+        AttP2Cs_o = attP2Cs;
+        AttP2Sck_o = attP2Sck;
+    end
+    if (flagDirectAttP3) begin //ATT_P3
+        AttP3Mosi_o = Mosi0_i;
+        AttP3Cs_o = Ss_i;
+        AttP3Sck_o = Sck_i;
+    end
+    else begin
+        AttP3Mosi_o = attP3Mosi;
+        AttP3Cs_o = attP3Cs;
+        AttP3Sck_o = attP3Sck;
+    end
+    if (flagDirectAttP4) begin //ATT_P4
+        AttP4Mosi_o = Mosi0_i;
+        AttP4Cs_o = Ss_i;
+        AttP4Sck_o = Sck_i;
+    end
+    else begin
+        AttP4Mosi_o = attP4Mosi;
+        AttP4Cs_o = attP4Cs;
+        AttP4Sck_o = attP4Sck;
+    end
+end
+
+ClkGenCp2444v1 ClkGenCp2444v1 (
+    .Clk24MHz_i(Clk_i),
+
+    .Clk60Mhz_o(clk60),
+    .Clk26dot25Mhz_o(clk26dot25),
+    .Clk24Mhz_o(gclk)
+);
+
+InitRst InitRst (
+    .clk_i(gclk),
+    .signal_o(initRst)
+);
+
+InterfaceArbiterCp2444v1 #(
+    .OUTWORDWIDTH(WORDWIDTH),
+    .SSPIWORDWIDTH(SSPIWORDWIDTH)
+)
+InterfaceArbiterCp2444v1 (
+    .Rst_i(Rst_i),
+    .Clk_i(clk60),
+    .Sck_i(Sck_i),
+    .Ss_i(Ss_i),
+    .Mosi0_i(Mosi0_i),
+    .Mosi1_i(Mosi1_io),
+    .Mosi2_i(Mosi2_i),
+    .Mosi3_i(Mosi3_i),
+    .DataVal_o(spiDataVal),
+    .Data_o(spiData)
+);
+
+PacketAnalyzer1MosiCp2444v1 PacketAnalyzer1MosiCp2444v1 (
+    .Clk_i  (clk60),
+    .Rst_i  (Rst_i),
+
+    .DataFromSpi_i (spiData),
+    .ValDataFromSpi_i (spiDataVal),
+
+    .BusyMosi4_i (busyMosi4),
+
+    .FlagDirectSwCtrlP1_o (flagDirectSwP1),
+    .FlagDirectAttCtrlP1_o (flagDirectAttP1),
+    .FlagDirectAttCtrlP2_o (flagDirectAttP2),
+    .FlagDirectAttCtrlP3_o (flagDirectAttP3),
+    .FlagDirectAttCtrlP4_o (flagDirectAttP4),
+    .FlagDirectGpio_o (flagDirectGpio),
+    .Busy_o (busyMosi1)
+);
+
+PacketAnalyzer4MosiCp2444v1 PacketAnalyzer4MosiCp2444v1 (
+    .Clk_i                  (clk60),
+    .Rst_i                  (Rst_i),
+
+    .DataFromSpi_i          (spiData),
+    .ValDataFromSpi_i       (spiDataVal),
+
+    .BusyMosi1_i            (busyMosi1),
+
+    .ValGpioDataToFifo_o    (valGpioDataToFifo),
+    .ValSwP1DataToFifo_o    (valSwP1DataToFifo),
+    .ValAttP1DataToFifo_o   (valAttP1DataToFifo),
+    .ValAttP2DataToFifo_o   (valAttP2DataToFifo),
+    .ValAttP3DataToFifo_o   (valAttP3DataToFifo),
+    .ValAttP4DataToFifo_o   (valAttP4DataToFifo),
+
+    .Busy_o                 (busyMosi4)
+);
+
+Gpio1Ctrl Gpio1Ctrl (
+    .Clk_i(clk60),
+    .ValGpioDataToFifo_i(valGpioDataToFifo),
+    .ValDataFromSpi_i(spiDataVal),
+    .FlagDirectGpio1_i(flagDirectGpio),
+    .Data_i(spiData),
+    .GpioReg_o(gpio1CtrlData)
+);
+
+AttCtrlWrapper #(
+    .IN_WIDTH(24),
+    .WR_NUM(1),
+    .OUT_WIDTH(16),
+    .DATA_WIDTH(16)
+) AttCtrlP1Wrapper (
+    .WrClk_i(clk60),
+    .RdClk_i(clk26dot25),
+    .Rst_i(initRst),
+    .Data_i(spiData),
+    .Val_i(valAttP1DataToFifo),
+    .Ss_o(attP1Cs),
+    .Sck_o(attP1Sck),
+    .Mosi_o(attP1Mosi)
+);
+
+AttCtrlWrapper #(
+    .IN_WIDTH(24),
+    .WR_NUM(1),
+    .OUT_WIDTH(16),
+    .DATA_WIDTH(16)
+) AttCtrlP2Wrapper (
+    .WrClk_i(clk60),
+    .RdClk_i(clk26dot25),
+    .Rst_i(initRst),
+    .Data_i(spiData),
+    .Val_i(valAttP2DataToFifo),
+    .Ss_o(attP2Cs),
+    .Sck_o(attP2Sck),
+    .Mosi_o(attP2Mosi)
+);
+
+AttCtrlWrapper #(
+    .IN_WIDTH(24),
+    .WR_NUM(1),
+    .OUT_WIDTH(16),
+    .DATA_WIDTH(16)
+) AttCtrlP3Wrapper (
+    .WrClk_i(clk60),
+    .RdClk_i(clk26dot25),
+    .Rst_i(initRst),
+    .Data_i(spiData),
+    .Val_i(valAttP3DataToFifo),
+    .Ss_o(attP3Cs),
+    .Sck_o(attP3Sck),
+    .Mosi_o(attP3Mosi)
+);
+
+AttCtrlWrapper #(
+    .IN_WIDTH(24),
+    .WR_NUM(1),
+    .OUT_WIDTH(16),
+    .DATA_WIDTH(16)
+) AttCtrlP4Wrapper (
+    .WrClk_i(clk60),
+    .RdClk_i(clk26dot25),
+    .Rst_i(initRst),
+    .Data_i(spiData),
+    .Val_i(valAttP4DataToFifo),
+    .Ss_o(attP4Cs),
+    .Sck_o(attP4Sck),
+    .Mosi_o(attP4Mosi)
+);
+
+SwCtrlWrapper #(
+    .IN_WIDTH(24),
+    .WR_NUM(1),
+    .OUT_WIDTH(8),
+    .DATA_WIDTH(8)
+) SwCtrlWrapper(
+    .WrClk_i(clk60),
+    .RdClk_i(clk26dot25),
+    .Rst_i(initRst),
+    .Data_i(spiData),
+    .Val_i(valSwP1DataToFifo),
+    .Ss_o(swP1Cs),
+    .Sck_o(swP1Sck),
+    .Mosi_o(swP1Mosi)
+);
+
+endmodule

src/src/WrapFifoChain/AttCtrlWrapper.v

@@ -0,0 +1,76 @@
+module AttCtrlWrapper #(
+    parameter IN_WIDTH = 24,
+    parameter WR_NUM = 1,
+    parameter OUT_WIDTH = 16,
+    parameter DATA_WIDTH = 16
+)(
+    input WrClk_i,
+    input RdClk_i,
+    input Rst_i,
+    input [IN_WIDTH-1:0] Data_i,
+    input Val_i,
+
+    output Ss_o,
+    output Sck_o,
+    output Mosi_o
+);
+//================================================================================
+//	                                REG/WIRE
+//================================================================================  
+wire [OUT_WIDTH-1:0] dataFromFifoCtrl;
+wire [OUT_WIDTH-1:0] dataFromFifo;
+wire readEn;
+wire writeEn;
+wire valRdData;
+wire busySpiM;
+wire fifoFull;
+wire fifoEmpty;
+//==========================================================================//
+//									CODING									//
+//==========================================================================//
+FifoCtrl #(
+    .IN_WIDTH		(IN_WIDTH),
+    .WR_NUM			(WR_NUM),
+    .OUT_WIDTH		(OUT_WIDTH)
+) FifoCtrl
+(
+    .WrClk_i		(WrClk_i),
+    .RdClk_i		(RdClk_i),
+    .Rst_i			(Rst_i),
+    .Data_i			(Data_i),
+    .Val_i			(Val_i),
+    .BusySpiM_i		(busySpiM),
+    .FifoFull_i		(fifoFull),
+    .FifoEmpty_i	(fifoEmpty),
+    .Data_o			(dataFromFifoCtrl),
+    .ReadEn_o		(readEn),
+    .WriteEn_o		(writeEn),
+    .ValRdData_o	(valRdData)
+);
+
+FifoShReg16  FifoAttCtrl_inst (
+    .Data	        (dataFromFifoCtrl),
+    .WrClk	        (WrClk_i),
+    .RdClk	        (RdClk_i),
+    .Reset	        (Rst_i),
+    .WrEn	        (writeEn),
+    .RdEn	        (readEn),
+    .Full           (fifoFull),
+    .Empty          (fifoEmpty),
+    .Q              (dataFromFifo)
+);
+
+SpiM #(
+    .DATA_WIDTH(DATA_WIDTH)
+) SpiMAttCtrl (
+    .Clk_i        (RdClk_i),
+    .Rst_i        (Rst_i),
+    .Val_i        (valRdData),
+    .SpiData_i       (dataFromFifo),
+    .Busy_o       (busySpiM),
+    .Ss_o         (Ss_o),
+    .Sck_o        (Sck_o),
+    .Mosi_o       (Mosi_o)
+);
+
+endmodule

src/src/WrapFifoChain/FifoShReg16/FifoShReg16.ipc

@@ -0,0 +1,35 @@
+[General]
+ipc_version=4
+file=FifoShReg16
+module=FifoShReg16
+target_device=gw1n9-022
+type=fifo_hs
+version=1.0
+
+[Config]
+AlmostEmptyFlag=false
+AlmostEmptyFlagItem=Empty_Single Threshold Constant Parameter
+AlmostFullFlag=false
+AlmostFullFlagItem=Full_Single Threshold Constant Parameter
+BSRAM=true
+ControlledByRdEn=false
+ECCSelected=false
+EmptyClear=1
+EmptySet=1
+EnReset=true
+FirstWordFallThrough=true
+FullClear=1
+FullSet=1
+LANG=0
+OutputRegistersSelected=false
+REG=false
+ReadDataNum=false
+ReadDataWidth=16
+ReadDepth=2
+ResetSynchronization=true
+SSRAM=false
+StandardFIFO=false
+Synthesis_tool=GowinSynthesis
+WriteDataNum=false
+WriteDataWidth=16
+WriteDepth=2

src/src/WrapFifoChain/FifoShReg16/FifoShReg16.v

@@ -0,0 +1,187 @@
+//
+//Written by GowinSynthesis
+//Tool Version "V1.9.9.03 (64-bit)"
+//Thu Nov 28 11:58:21 2024
+
+//Source file index table:
+//file0 "\C:/Gowin/Gowin_V1.9.9.03_x64/IDE/ipcore/FIFO_HS/data/fifo_hs.v"
+//file1 "\C:/Gowin/Gowin_V1.9.9.03_x64/IDE/ipcore/FIFO_HS/data/fifo_hs_top.v"
+`timescale 100 ps/100 ps
+`pragma protect begin_protected
+`pragma protect version="2.3"
+`pragma protect author="default"
+`pragma protect author_info="default"
+`pragma protect encrypt_agent="GOWIN"
+`pragma protect encrypt_agent_info="GOWIN Encrypt Version 2.3"
+
+`pragma protect encoding=(enctype="base64", line_length=76, bytes=256)
+`pragma protect key_keyowner="GOWIN",key_keyname="GWK2023-09",key_method="rsa"
+`pragma protect key_block
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+vn+qjfDch5LzEIV4t4Lf3yywUW4CXFBNDdMUGQ==
+
+`pragma protect encoding=(enctype="base64", line_length=76, bytes=6368)
+`pragma protect data_keyowner="default-ip-vendor"
+`pragma protect data_keyname="default-ip-key"
+`pragma protect data_method="aes128-cfb"
+`pragma protect data_block
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+JG8lurZc2C1jRoxFfsSqgM9X2y9ADgDF/XWEmL+1t7e4gB54N9lPAb8xOuEap8KAjdzpEozKdmIp
+g05ZN47mt+kXZS63545TvwyAir02VODC4BvLj08ql5Q9rFm5NF3pv1qtHcAeKZWLa/BAurJ3hFzO
+lMK5moWIxbUALbtxdHg1/G/gbEUKg+P0bLRkmOtvo4Hxna5QdNY8mRU=
+`pragma protect end_protected
+module FifoShReg16 (
+  Data,
+  Reset,
+  WrClk,
+  RdClk,
+  WrEn,
+  RdEn,
+  Q,
+  Empty,
+  Full
+)
+;
+input [15:0] Data;
+input Reset;
+input WrClk;
+input RdClk;
+input WrEn;
+input RdEn;
+output [15:0] Q;
+output Empty;
+output Full;
+wire VCC;
+wire GND;
+  \~fifo.FifoShReg16  fifo_inst (
+    .Reset(Reset),
+    .RdClk(RdClk),
+    .WrClk(WrClk),
+    .WrEn(WrEn),
+    .RdEn(RdEn),
+    .Data(Data[15:0]),
+    .Empty(Empty),
+    .Full(Full),
+    .Q(Q[15:0])
+);
+  VCC VCC_cZ (
+    .V(VCC)
+);
+  GND GND_cZ (
+    .G(GND)
+);
+  GSR GSR (
+    .GSRI(VCC) 
+);
+endmodule /* FifoShReg16 */

src/src/WrapFifoChain/FifoShReg16/FifoShReg16.vo

@@ -0,0 +1,353 @@
+//Copyright (C)2014-2024 Gowin Semiconductor Corporation.
+//All rights reserved.
+//File Title: Post-PnR Simulation Model file
+//Tool Version: V1.9.9.03 (64-bit)
+//Created Time: Thu Nov 28 11:58:21 2024
+
+`timescale 100 ps/100 ps
+module FifoShReg16(
+	Data,
+	Reset,
+	WrClk,
+	RdClk,
+	WrEn,
+	RdEn,
+	Q,
+	Empty,
+	Full
+);
+input [15:0] Data;
+input Reset;
+input WrClk;
+input RdClk;
+input WrEn;
+input RdEn;
+output [15:0] Q;
+output Empty;
+output Full;
+wire [15:0] Data;
+wire Empty;
+wire Full;
+wire GND;
+wire [15:0] Q;
+wire RdClk;
+wire RdEn;
+wire Reset;
+wire VCC;
+wire WrClk;
+wire WrEn;
+wire \fifo_inst/n20_5 ;
+wire \fifo_inst/n26_4 ;
+wire \fifo_inst/n217_4 ;
+wire \fifo_inst/rempty_val ;
+wire \fifo_inst/wfull_val_7 ;
+wire \fifo_inst/wfull_val1 ;
+wire \fifo_inst/wfull_val1_0 ;
+wire \fifo_inst/Full_1 ;
+wire \fifo_inst/Equal.wbinnext_0_7 ;
+wire \fifo_inst/rempty_val_8 ;
+wire \fifo_inst/wfull_val1_2 ;
+wire \fifo_inst/wfull_val1_3 ;
+wire \fifo_inst/Full_1_2 ;
+wire \fifo_inst/Full_2 ;
+wire \fifo_inst/n4_6 ;
+wire \fifo_inst/n9_6 ;
+wire [0:0] \fifo_inst/Equal.rgraynext ;
+wire [0:0] \fifo_inst/Equal.wgraynext ;
+wire [1:0] \fifo_inst/rbin_num_next ;
+wire [1:1] \fifo_inst/Equal.wbinnext ;
+wire [1:0] \fifo_inst/reset_r ;
+wire [1:0] \fifo_inst/reset_w ;
+wire [1:0] \fifo_inst/rbin_num ;
+wire [1:0] \fifo_inst/Equal.rq1_wptr ;
+wire [1:0] \fifo_inst/Equal.rq2_wptr ;
+wire [0:0] \fifo_inst/rptr ;
+wire [1:0] \fifo_inst/wptr ;
+wire [0:0] \fifo_inst/Equal.wbin ;
+wire [31:16] \fifo_inst/DO ;
+VCC VCC_cZ (
+  .V(VCC)
+);
+GND GND_cZ (
+  .G(GND)
+);
+GSR GSR (
+	.GSRI(VCC)
+);
+LUT4 \fifo_inst/n20_s1  (
+	.I0(\fifo_inst/Full_2 ),
+	.I1(\fifo_inst/Full_1_2 ),
+	.I2(\fifo_inst/Full_1 ),
+	.I3(WrEn),
+	.F(\fifo_inst/n20_5 )
+);
+defparam \fifo_inst/n20_s1 .INIT=16'h5300;
+LUT3 \fifo_inst/n26_s1  (
+	.I0(RdEn),
+	.I1(Empty),
+	.I2(\fifo_inst/rempty_val ),
+	.F(\fifo_inst/n26_4 )
+);
+defparam \fifo_inst/n26_s1 .INIT=8'h0E;
+LUT3 \fifo_inst/Equal.rgraynext_0_s0  (
+	.I0(\fifo_inst/rbin_num [0]),
+	.I1(\fifo_inst/rbin_num_next [0]),
+	.I2(\fifo_inst/rbin_num [1]),
+	.F(\fifo_inst/Equal.rgraynext [0])
+);
+defparam \fifo_inst/Equal.rgraynext_0_s0 .INIT=8'h1E;
+LUT3 \fifo_inst/Equal.wgraynext_0_s0  (
+	.I0(\fifo_inst/Equal.wbin [0]),
+	.I1(\fifo_inst/n20_5 ),
+	.I2(\fifo_inst/wptr [1]),
+	.F(\fifo_inst/Equal.wgraynext [0])
+);
+defparam \fifo_inst/Equal.wgraynext_0_s0 .INIT=8'h1E;
+LUT2 \fifo_inst/n217_s1  (
+	.I0(\fifo_inst/reset_w [1]),
+	.I1(\fifo_inst/wfull_val_7 ),
+	.F(\fifo_inst/n217_4 )
+);
+defparam \fifo_inst/n217_s1 .INIT=4'h4;
+LUT4 \fifo_inst/rempty_val_s3  (
+	.I0(\fifo_inst/Equal.rq2_wptr [1]),
+	.I1(\fifo_inst/rempty_val_8 ),
+	.I2(\fifo_inst/Equal.rq2_wptr [0]),
+	.I3(\fifo_inst/rbin_num_next [0]),
+	.F(\fifo_inst/rempty_val )
+);
+defparam \fifo_inst/rempty_val_s3 .INIT=16'h4221;
+LUT4 \fifo_inst/wfull_val_s3  (
+	.I0(\fifo_inst/wptr [0]),
+	.I1(\fifo_inst/wptr [1]),
+	.I2(\fifo_inst/rbin_num [1]),
+	.I3(\fifo_inst/rptr [0]),
+	.F(\fifo_inst/wfull_val_7 )
+);
+defparam \fifo_inst/wfull_val_s3 .INIT=16'h1428;
+LUT3 \fifo_inst/wfull_val1_s9  (
+	.I0(\fifo_inst/wfull_val1_3 ),
+	.I1(\fifo_inst/wfull_val1_2 ),
+	.I2(\fifo_inst/wfull_val1_0 ),
+	.F(\fifo_inst/wfull_val1 )
+);
+defparam \fifo_inst/wfull_val1_s9 .INIT=8'hAC;
+LUT3 \fifo_inst/wfull_val1_s10  (
+	.I0(\fifo_inst/wfull_val_7 ),
+	.I1(\fifo_inst/wfull_val1_0 ),
+	.I2(\fifo_inst/reset_w [1]),
+	.F(\fifo_inst/wfull_val1_0 )
+);
+defparam \fifo_inst/wfull_val1_s10 .INIT=8'h0E;
+LUT3 \fifo_inst/Full_d_s  (
+	.I0(\fifo_inst/Full_2 ),
+	.I1(\fifo_inst/Full_1_2 ),
+	.I2(\fifo_inst/Full_1 ),
+	.F(Full)
+);
+defparam \fifo_inst/Full_d_s .INIT=8'hAC;
+LUT3 \fifo_inst/Full_s8  (
+	.I0(\fifo_inst/wfull_val_7 ),
+	.I1(\fifo_inst/Full_1 ),
+	.I2(\fifo_inst/reset_w [1]),
+	.F(\fifo_inst/Full_1 )
+);
+defparam \fifo_inst/Full_s8 .INIT=8'h0E;
+LUT3 \fifo_inst/rbin_num_next_0_s5  (
+	.I0(Empty),
+	.I1(RdEn),
+	.I2(\fifo_inst/rbin_num [0]),
+	.F(\fifo_inst/rbin_num_next [0])
+);
+defparam \fifo_inst/rbin_num_next_0_s5 .INIT=8'hB4;
+LUT3 \fifo_inst/rbin_num_next_1_s2  (
+	.I0(\fifo_inst/rbin_num_next [0]),
+	.I1(\fifo_inst/rbin_num [0]),
+	.I2(\fifo_inst/rbin_num [1]),
+	.F(\fifo_inst/rbin_num_next [1])
+);
+defparam \fifo_inst/rbin_num_next_1_s2 .INIT=8'hB4;
+LUT2 \fifo_inst/Equal.wbinnext_0_s3  (
+	.I0(\fifo_inst/Equal.wbin [0]),
+	.I1(\fifo_inst/n20_5 ),
+	.F(\fifo_inst/Equal.wbinnext_0_7 )
+);
+defparam \fifo_inst/Equal.wbinnext_0_s3 .INIT=4'h6;
+LUT3 \fifo_inst/Equal.wbinnext_1_s2  (
+	.I0(\fifo_inst/Equal.wbin [0]),
+	.I1(\fifo_inst/n20_5 ),
+	.I2(\fifo_inst/wptr [1]),
+	.F(\fifo_inst/Equal.wbinnext [1])
+);
+defparam \fifo_inst/Equal.wbinnext_1_s2 .INIT=8'h78;
+LUT4 \fifo_inst/rempty_val_s4  (
+	.I0(\fifo_inst/Equal.rq2_wptr [0]),
+	.I1(\fifo_inst/Equal.rq2_wptr [1]),
+	.I2(\fifo_inst/rbin_num [1]),
+	.I3(\fifo_inst/rbin_num [0]),
+	.F(\fifo_inst/rempty_val_8 )
+);
+defparam \fifo_inst/rempty_val_s4 .INIT=16'h871E;
+DFFP \fifo_inst/reset_r_0_s0  (
+	.D(GND),
+	.CLK(\fifo_inst/n4_6 ),
+	.PRESET(Reset),
+	.Q(\fifo_inst/reset_r [0])
+);
+defparam \fifo_inst/reset_r_0_s0 .INIT=1'b1;
+DFFP \fifo_inst/reset_w_1_s0  (
+	.D(\fifo_inst/reset_w [0]),
+	.CLK(\fifo_inst/n9_6 ),
+	.PRESET(Reset),
+	.Q(\fifo_inst/reset_w [1])
+);
+defparam \fifo_inst/reset_w_1_s0 .INIT=1'b1;
+DFFP \fifo_inst/reset_w_0_s0  (
+	.D(GND),
+	.CLK(\fifo_inst/n9_6 ),
+	.PRESET(Reset),
+	.Q(\fifo_inst/reset_w [0])
+);
+defparam \fifo_inst/reset_w_0_s0 .INIT=1'b1;
+DFFC \fifo_inst/rbin_num_1_s0  (
+	.D(\fifo_inst/rbin_num_next [1]),
+	.CLK(RdClk),
+	.CLEAR(\fifo_inst/reset_r [1]),
+	.Q(\fifo_inst/rbin_num [1])
+);
+defparam \fifo_inst/rbin_num_1_s0 .INIT=1'b0;
+DFFC \fifo_inst/rbin_num_0_s0  (
+	.D(\fifo_inst/rbin_num_next [0]),
+	.CLK(RdClk),
+	.CLEAR(\fifo_inst/reset_r [1]),
+	.Q(\fifo_inst/rbin_num [0])
+);
+defparam \fifo_inst/rbin_num_0_s0 .INIT=1'b0;
+DFFC \fifo_inst/Equal.rq1_wptr_1_s0  (
+	.D(\fifo_inst/wptr [1]),
+	.CLK(RdClk),
+	.CLEAR(\fifo_inst/reset_r [1]),
+	.Q(\fifo_inst/Equal.rq1_wptr [1])
+);
+defparam \fifo_inst/Equal.rq1_wptr_1_s0 .INIT=1'b0;
+DFFC \fifo_inst/Equal.rq1_wptr_0_s0  (
+	.D(\fifo_inst/wptr [0]),
+	.CLK(RdClk),
+	.CLEAR(\fifo_inst/reset_r [1]),
+	.Q(\fifo_inst/Equal.rq1_wptr [0])
+);
+defparam \fifo_inst/Equal.rq1_wptr_0_s0 .INIT=1'b0;
+DFFC \fifo_inst/Equal.rq2_wptr_1_s0  (
+	.D(\fifo_inst/Equal.rq1_wptr [1]),
+	.CLK(RdClk),
+	.CLEAR(\fifo_inst/reset_r [1]),
+	.Q(\fifo_inst/Equal.rq2_wptr [1])
+);
+defparam \fifo_inst/Equal.rq2_wptr_1_s0 .INIT=1'b0;
+DFFC \fifo_inst/Equal.rq2_wptr_0_s0  (
+	.D(\fifo_inst/Equal.rq1_wptr [0]),
+	.CLK(RdClk),
+	.CLEAR(\fifo_inst/reset_r [1]),
+	.Q(\fifo_inst/Equal.rq2_wptr [0])
+);
+defparam \fifo_inst/Equal.rq2_wptr_0_s0 .INIT=1'b0;
+DFFC \fifo_inst/rptr_0_s0  (
+	.D(\fifo_inst/Equal.rgraynext [0]),
+	.CLK(RdClk),
+	.CLEAR(\fifo_inst/reset_r [1]),
+	.Q(\fifo_inst/rptr [0])
+);
+defparam \fifo_inst/rptr_0_s0 .INIT=1'b0;
+DFFC \fifo_inst/wptr_1_s0  (
+	.D(\fifo_inst/Equal.wbinnext [1]),
+	.CLK(WrClk),
+	.CLEAR(\fifo_inst/reset_w [1]),
+	.Q(\fifo_inst/wptr [1])
+);
+defparam \fifo_inst/wptr_1_s0 .INIT=1'b0;
+DFFC \fifo_inst/wptr_0_s0  (
+	.D(\fifo_inst/Equal.wgraynext [0]),
+	.CLK(WrClk),
+	.CLEAR(\fifo_inst/reset_w [1]),
+	.Q(\fifo_inst/wptr [0])
+);
+defparam \fifo_inst/wptr_0_s0 .INIT=1'b0;
+DFFC \fifo_inst/Equal.wbin_0_s0  (
+	.D(\fifo_inst/Equal.wbinnext_0_7 ),
+	.CLK(WrClk),
+	.CLEAR(\fifo_inst/reset_w [1]),
+	.Q(\fifo_inst/Equal.wbin [0])
+);
+defparam \fifo_inst/Equal.wbin_0_s0 .INIT=1'b0;
+DFFP \fifo_inst/Empty_s0  (
+	.D(\fifo_inst/rempty_val ),
+	.CLK(RdClk),
+	.PRESET(\fifo_inst/reset_r [1]),
+	.Q(Empty)
+);
+defparam \fifo_inst/Empty_s0 .INIT=1'b1;
+DFFP \fifo_inst/reset_r_1_s0  (
+	.D(\fifo_inst/reset_r [0]),
+	.CLK(\fifo_inst/n4_6 ),
+	.PRESET(Reset),
+	.Q(\fifo_inst/reset_r [1])
+);
+defparam \fifo_inst/reset_r_1_s0 .INIT=1'b1;
+DFFC \fifo_inst/wfull_val1_s0  (
+	.D(\fifo_inst/wfull_val_7 ),
+	.CLK(WrClk),
+	.CLEAR(\fifo_inst/reset_w [1]),
+	.Q(\fifo_inst/wfull_val1_2 )
+);
+defparam \fifo_inst/wfull_val1_s0 .INIT=1'b0;
+DFFP \fifo_inst/wfull_val1_s1  (
+	.D(\fifo_inst/wfull_val_7 ),
+	.CLK(WrClk),
+	.PRESET(\fifo_inst/n217_4 ),
+	.Q(\fifo_inst/wfull_val1_3 )
+);
+defparam \fifo_inst/wfull_val1_s1 .INIT=1'b1;
+DFFC \fifo_inst/Full_s0  (
+	.D(\fifo_inst/wfull_val1 ),
+	.CLK(WrClk),
+	.CLEAR(\fifo_inst/reset_w [1]),
+	.Q(\fifo_inst/Full_1_2 )
+);
+defparam \fifo_inst/Full_s0 .INIT=1'b0;
+DFFP \fifo_inst/Full_s1  (
+	.D(\fifo_inst/wfull_val1 ),
+	.CLK(WrClk),
+	.PRESET(\fifo_inst/n217_4 ),
+	.Q(\fifo_inst/Full_2 )
+);
+defparam \fifo_inst/Full_s1 .INIT=1'b1;
+SDPB \fifo_inst/Equal.mem_Equal.mem_0_0_s  (
+	.CLKA(WrClk),
+	.CEA(\fifo_inst/n20_5 ),
+	.RESETA(GND),
+	.CLKB(RdClk),
+	.CEB(\fifo_inst/n26_4 ),
+	.RESETB(\fifo_inst/reset_r [1]),
+	.OCE(GND),
+	.BLKSELA({GND, GND, GND}),
+	.BLKSELB({GND, GND, GND}),
+	.DI({GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, Data[15:0]}),
+	.ADA({GND, GND, GND, GND, GND, GND, GND, GND, GND, \fifo_inst/Equal.wbin [0], GND, GND, VCC, VCC}),
+	.ADB({GND, GND, GND, GND, GND, GND, GND, GND, GND, \fifo_inst/rbin_num_next [0], GND, GND, GND, GND}),
+	.DO({\fifo_inst/DO [31:16], Q[15:0]})
+);
+defparam \fifo_inst/Equal.mem_Equal.mem_0_0_s .READ_MODE=1'b0;
+defparam \fifo_inst/Equal.mem_Equal.mem_0_0_s .BIT_WIDTH_0=16;
+defparam \fifo_inst/Equal.mem_Equal.mem_0_0_s .BIT_WIDTH_1=16;
+defparam \fifo_inst/Equal.mem_Equal.mem_0_0_s .RESET_MODE="ASYNC";
+defparam \fifo_inst/Equal.mem_Equal.mem_0_0_s .BLK_SEL_0=3'b000;
+defparam \fifo_inst/Equal.mem_Equal.mem_0_0_s .BLK_SEL_1=3'b000;
+INV \fifo_inst/n4_s2  (
+	.I(RdClk),
+	.O(\fifo_inst/n4_6 )
+);
+INV \fifo_inst/n9_s2  (
+	.I(WrClk),
+	.O(\fifo_inst/n9_6 )
+);
+endmodule

src/src/WrapFifoChain/FifoShReg16/FifoShReg16_tmp.v

@@ -0,0 +1,24 @@
+//Copyright (C)2014-2024 Gowin Semiconductor Corporation.
+//All rights reserved.
+//File Title: Template file for instantiation
+//Tool Version: V1.9.9.03 (64-bit)
+//Part Number: GW1N-UV9QN88C6/I5
+//Device: GW1N-9
+//Created Time: Thu Nov 28 11:58:21 2024
+
+//Change the instance name and port connections to the signal names
+//--------Copy here to design--------
+
+	FifoShReg16 your_instance_name(
+		.Data(Data), //input [15:0] Data
+		.Reset(Reset), //input Reset
+		.WrClk(WrClk), //input WrClk
+		.RdClk(RdClk), //input RdClk
+		.WrEn(WrEn), //input WrEn
+		.RdEn(RdEn), //input RdEn
+		.Q(Q), //output [15:0] Q
+		.Empty(Empty), //output Empty
+		.Full(Full) //output Full
+	);
+
+//--------Copy end-------------------

src/src/WrapFifoChain/FifoShReg16/temp/FIFOHS/FIFOHS.prj

@@ -0,0 +1,20 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!DOCTYPE gowin-synthesis-project>
+<Project>
+    <Version>beta</Version>
+    <Device id="GW1N-9" package="QFN88" speed="6" partNumber="GW1N-UV9QN88C6/I5"/>
+    <FileList>
+        <File path="C:/Gowin/Gowin_V1.9.9.03_x64/IDE/ipcore/FIFO_HS/data/fifo_hs.v" type="verilog"/>
+        <File path="C:/Gowin/Gowin_V1.9.9.03_x64/IDE/ipcore/FIFO_HS/data/fifo_hs_top.v" type="verilog"/>
+    </FileList>
+    <OptionList>
+        <Option type="disable_insert_pad" value="1"/>
+        <Option type="include_path" value="C:/Gowin/Gowin_V1.9.9.03_x64/IDE/ipcore/FIFO_HS/data"/>
+        <Option type="include_path" value="C:/Gowin/Projects/CP2444v1_FPGA/src/src/WrapFifoChain/FifoShReg16/temp/FIFOHS"/>
+        <Option type="output_file" value="FifoShReg16.vg"/>
+        <Option type="output_template" value="FifoShReg16_tmp.v"/>
+        <Option type="ram_balance" value="1"/>
+        <Option type="ram_rw_check" value="1"/>
+        <Option type="verilog_language" value="sysv-2017"/>
+    </OptionList>
+</Project>

src/src/WrapFifoChain/FifoShReg16/temp/FIFOHS/FifoShReg16.log

@@ -0,0 +1,45 @@
+GowinSynthesis start
+Running parser ...
+Analyzing Verilog file 'C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v'
+Analyzing included file '**'("C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Back to file '**'("C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Undeclared symbol '**', assumed default net type '**'("C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Analyzing Verilog file 'C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v'
+Analyzing included file 'fifo_define.v'("C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":1)
+Back to file 'C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v'("C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":1)
+Analyzing included file 'C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\static_macro_define.v'("C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":2)
+Back to file 'C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v'("C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":2)
+Analyzing included file 'fifo_parameter.v'("C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":57)
+Back to file 'C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v'("C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":57)
+Compiling module 'FifoShReg16'("C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":4)
+Compiling module '**'("C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Extracting RAM for identifier '**'("C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+NOTE  (EX0101) : Current top module is "FifoShReg16"
+[5%] Running netlist conversion ...
+Running device independent optimization ...
+[10%] Optimizing Phase 0 completed
+[15%] Optimizing Phase 1 completed
+[25%] Optimizing Phase 2 completed
+Running inference ...
+[30%] Inferring Phase 0 completed
+[40%] Inferring Phase 1 completed
+[50%] Inferring Phase 2 completed
+[55%] Inferring Phase 3 completed
+Running technical mapping ...
+[60%] Tech-Mapping Phase 0 completed
+[65%] Tech-Mapping Phase 1 completed
+[75%] Tech-Mapping Phase 2 completed
+WARN  (AG0100) : Find logical loop signal : "fifo_inst/wfull_val1_s3"("C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+WARN  (AG0100) : Find logical loop signal : "fifo_inst/wfull_val1_s6"("C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+WARN  (AG0100) : Find logical loop signal : "fifo_inst/wfull_val1_s3"("C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+WARN  (AG0101) : The netlist is not one directed acyclic graph
+WARN  (AG0100) : Find logical loop signal : "fifo_inst/Full_s3"("C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+WARN  (AG0100) : Find logical loop signal : "fifo_inst/Full_s6"("C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+WARN  (AG0100) : Find logical loop signal : "fifo_inst/Full_s3"("C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+WARN  (AG0101) : The netlist is not one directed acyclic graph
+[80%] Tech-Mapping Phase 3 completed
+[90%] Tech-Mapping Phase 4 completed
+[95%] Generate netlist file "C:\Gowin\Projects\CP2444v1_FPGA\src\src\WrapFifoChain\FifoShReg16\temp\FIFOHS\FifoShReg16.vg" completed
+Generate template file "C:\Gowin\Projects\CP2444v1_FPGA\src\src\WrapFifoChain\FifoShReg16\temp\FIFOHS\FifoShReg16_tmp.v" completed
+[100%] Generate report file "C:\Gowin\Projects\CP2444v1_FPGA\src\src\WrapFifoChain\FifoShReg16\temp\FIFOHS\FifoShReg16_syn.rpt.html" completed
+GowinSynthesis finish

src/src/WrapFifoChain/FifoShReg16/temp/FIFOHS/FifoShReg16.vg

@@ -0,0 +1,187 @@
+//
+//Written by GowinSynthesis
+//Tool Version "V1.9.9.03 (64-bit)"
+//Thu Nov 28 11:58:21 2024
+
+//Source file index table:
+//file0 "\C:/Gowin/Gowin_V1.9.9.03_x64/IDE/ipcore/FIFO_HS/data/fifo_hs.v"
+//file1 "\C:/Gowin/Gowin_V1.9.9.03_x64/IDE/ipcore/FIFO_HS/data/fifo_hs_top.v"
+`timescale 100 ps/100 ps
+`pragma protect begin_protected
+`pragma protect version="2.3"
+`pragma protect author="default"
+`pragma protect author_info="default"
+`pragma protect encrypt_agent="GOWIN"
+`pragma protect encrypt_agent_info="GOWIN Encrypt Version 2.3"
+
+`pragma protect encoding=(enctype="base64", line_length=76, bytes=256)
+`pragma protect key_keyowner="GOWIN",key_keyname="GWK2023-09",key_method="rsa"
+`pragma protect key_block
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+vn+qjfDch5LzEIV4t4Lf3yywUW4CXFBNDdMUGQ==
+
+`pragma protect encoding=(enctype="base64", line_length=76, bytes=6368)
+`pragma protect data_keyowner="default-ip-vendor"
+`pragma protect data_keyname="default-ip-key"
+`pragma protect data_method="aes128-cfb"
+`pragma protect data_block
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+lMK5moWIxbUALbtxdHg1/G/gbEUKg+P0bLRkmOtvo4Hxna5QdNY8mRU=
+`pragma protect end_protected
+module FifoShReg16 (
+  Data,
+  Reset,
+  WrClk,
+  RdClk,
+  WrEn,
+  RdEn,
+  Q,
+  Empty,
+  Full
+)
+;
+input [15:0] Data;
+input Reset;
+input WrClk;
+input RdClk;
+input WrEn;
+input RdEn;
+output [15:0] Q;
+output Empty;
+output Full;
+wire VCC;
+wire GND;
+  \~fifo.FifoShReg16  fifo_inst (
+    .Reset(Reset),
+    .RdClk(RdClk),
+    .WrClk(WrClk),
+    .WrEn(WrEn),
+    .RdEn(RdEn),
+    .Data(Data[15:0]),
+    .Empty(Empty),
+    .Full(Full),
+    .Q(Q[15:0])
+);
+  VCC VCC_cZ (
+    .V(VCC)
+);
+  GND GND_cZ (
+    .G(GND)
+);
+  GSR GSR (
+    .GSRI(VCC) 
+);
+endmodule /* FifoShReg16 */

src/src/WrapFifoChain/FifoShReg16/temp/FIFOHS/FifoShReg16_syn_resource.html

@@ -0,0 +1,46 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html>
+<head>
+<title>Hierarchy Module Resource</title>
+<style type="text/css">
+body { font-family: Verdana, Arial, sans-serif; font-size: 14px; }
+div#main_wrapper{ width: 100%; }
+h1 {text-align: center; }
+h1 {margin-top: 36px; }
+table, th, td { border: 1px solid #aaa; }
+table { border-collapse:collapse; margin-top: 10px; margin-bottom: 20px; width: 100%; }
+th, td { align = "center"; padding: 5px 2px 5px 5px; }
+th { color: #fff; font-weight: bold; background-color: #0084ff; }
+table td.label { width: 20%; white-space: nowrap; min-width: 20px; background-color: #dee8f4; }
+</style>
+</head>
+<body>
+<div id="main_wrapper">
+<div id="content">
+<h1>Hierarchy Module Resource</h1>
+<table>
+<tr>
+<th class="label">MODULE NAME</th>
+<th class="label">REG NUMBER</th>
+<th class="label">ALU NUMBER</th>
+<th class="label">LUT NUMBER</th>
+<th class="label">DSP NUMBER</th>
+<th class="label">BSRAM NUMBER</th>
+<th class="label">SSRAM NUMBER</th>
+<th class="label">ROM16 NUMBER</th>
+</tr>
+<tr>
+<td class="label">FifoShReg16 (C:/Gowin/Gowin_V1.9.9.03_x64/IDE/ipcore/FIFO_HS/data/fifo_hs_top.v)</td>
+<td align = "center">19</td>
+<td align = "center">-</td>
+<td align = "center">18</td>
+<td align = "center">-</td>
+<td align = "center">1</td>
+<td align = "center">-</td>
+<td align = "center">-</td>
+</tr>
+</table>
+</div><!-- content -->
+</div><!-- main_wrapper -->
+</body>
+</html>

src/src/WrapFifoChain/FifoShReg16/temp/FIFOHS/FifoShReg16_syn_rsc.xml

@@ -0,0 +1,2 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<Module name="FifoShReg16" Register="19" Lut="18" Bsram="1" T_Register="19(19)" T_Lut="18(18)" T_Bsram="1(1)"/>

src/src/WrapFifoChain/FifoShReg16/temp/FIFOHS/FifoShReg16_tmp.v

@@ -0,0 +1,24 @@
+//Copyright (C)2014-2024 Gowin Semiconductor Corporation.
+//All rights reserved.
+//File Title: Template file for instantiation
+//Tool Version: V1.9.9.03 (64-bit)
+//Part Number: GW1N-UV9QN88C6/I5
+//Device: GW1N-9
+//Created Time: Thu Nov 28 11:58:21 2024
+
+//Change the instance name and port connections to the signal names
+//--------Copy here to design--------
+
+	FifoShReg16 your_instance_name(
+		.Data(Data), //input [15:0] Data
+		.Reset(Reset), //input Reset
+		.WrClk(WrClk), //input WrClk
+		.RdClk(RdClk), //input RdClk
+		.WrEn(WrEn), //input WrEn
+		.RdEn(RdEn), //input RdEn
+		.Q(Q), //output [15:0] Q
+		.Empty(Empty), //output Empty
+		.Full(Full) //output Full
+	);
+
+//--------Copy end-------------------

src/src/WrapFifoChain/FifoShReg16/temp/FIFOHS/fifo_define.v

@@ -0,0 +1,5 @@
+`define module_name FifoShReg16
+`define EBR_BASED
+`define FWFT
+`define En_Reset
+`define Reset_Synchronization

src/src/WrapFifoChain/FifoShReg16/temp/FIFOHS/fifo_parameter.v

@@ -0,0 +1,6 @@
+parameter WDEPTH = 2;
+parameter ASIZE = 1;
+parameter WDSIZE = 16;
+parameter RDEPTH = 2;
+parameter RASIZE = 1;
+parameter RDSIZE = 16;

src/src/WrapFifoChain/FifoShReg16/temp/FIFOHS/project.ini

@@ -0,0 +1 @@
+RESOURCE_CHECK=false

src/src/WrapFifoChain/FifoShReg8/FifoShReg8.ipc

@@ -0,0 +1,35 @@
+[General]
+ipc_version=4
+file=FifoShReg8
+module=FifoShReg8
+target_device=gw1n9-022
+type=fifo_hs
+version=1.0
+
+[Config]
+AlmostEmptyFlag=false
+AlmostEmptyFlagItem=Empty_Single Threshold Constant Parameter
+AlmostFullFlag=false
+AlmostFullFlagItem=Full_Single Threshold Constant Parameter
+BSRAM=true
+ControlledByRdEn=false
+ECCSelected=false
+EmptyClear=1
+EmptySet=1
+EnReset=true
+FirstWordFallThrough=true
+FullClear=1
+FullSet=1
+LANG=0
+OutputRegistersSelected=false
+REG=false
+ReadDataNum=false
+ReadDataWidth=8
+ReadDepth=2
+ResetSynchronization=true
+SSRAM=false
+StandardFIFO=false
+Synthesis_tool=GowinSynthesis
+WriteDataNum=false
+WriteDataWidth=8
+WriteDepth=2

src/src/WrapFifoChain/FifoShReg8/FifoShReg8.v

@@ -0,0 +1,188 @@
+//
+//Written by GowinSynthesis
+//Tool Version "V1.9.9.03 (64-bit)"
+//Thu Nov 28 11:57:53 2024
+
+//Source file index table:
+//file0 "\C:/Gowin/Gowin_V1.9.9.03_x64/IDE/ipcore/FIFO_HS/data/fifo_hs.v"
+//file1 "\C:/Gowin/Gowin_V1.9.9.03_x64/IDE/ipcore/FIFO_HS/data/fifo_hs_top.v"
+`timescale 100 ps/100 ps
+`pragma protect begin_protected
+`pragma protect version="2.3"
+`pragma protect author="default"
+`pragma protect author_info="default"
+`pragma protect encrypt_agent="GOWIN"
+`pragma protect encrypt_agent_info="GOWIN Encrypt Version 2.3"
+
+`pragma protect encoding=(enctype="base64", line_length=76, bytes=256)
+`pragma protect key_keyowner="GOWIN",key_keyname="GWK2023-09",key_method="rsa"
+`pragma protect key_block
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+
+`pragma protect encoding=(enctype="base64", line_length=76, bytes=6400)
+`pragma protect data_keyowner="default-ip-vendor"
+`pragma protect data_keyname="default-ip-key"
+`pragma protect data_method="aes128-cfb"
+`pragma protect data_block
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+cEEw/cAm1Gimtcg5Kv7+TA==
+`pragma protect end_protected
+module FifoShReg8 (
+  Data,
+  Reset,
+  WrClk,
+  RdClk,
+  WrEn,
+  RdEn,
+  Q,
+  Empty,
+  Full
+)
+;
+input [7:0] Data;
+input Reset;
+input WrClk;
+input RdClk;
+input WrEn;
+input RdEn;
+output [7:0] Q;
+output Empty;
+output Full;
+wire VCC;
+wire GND;
+  \~fifo.FifoShReg8  fifo_inst (
+    .Reset(Reset),
+    .RdClk(RdClk),
+    .WrClk(WrClk),
+    .WrEn(WrEn),
+    .RdEn(RdEn),
+    .Data(Data[7:0]),
+    .Empty(Empty),
+    .Full(Full),
+    .Q(Q[7:0])
+);
+  VCC VCC_cZ (
+    .V(VCC)
+);
+  GND GND_cZ (
+    .G(GND)
+);
+  GSR GSR (
+    .GSRI(VCC) 
+);
+endmodule /* FifoShReg8 */

src/src/WrapFifoChain/FifoShReg8/FifoShReg8.vo

@@ -0,0 +1,353 @@
+//Copyright (C)2014-2024 Gowin Semiconductor Corporation.
+//All rights reserved.
+//File Title: Post-PnR Simulation Model file
+//Tool Version: V1.9.9.03 (64-bit)
+//Created Time: Thu Nov 28 11:57:54 2024
+
+`timescale 100 ps/100 ps
+module FifoShReg8(
+	Data,
+	Reset,
+	WrClk,
+	RdClk,
+	WrEn,
+	RdEn,
+	Q,
+	Empty,
+	Full
+);
+input [7:0] Data;
+input Reset;
+input WrClk;
+input RdClk;
+input WrEn;
+input RdEn;
+output [7:0] Q;
+output Empty;
+output Full;
+wire [7:0] Data;
+wire Empty;
+wire Full;
+wire GND;
+wire [7:0] Q;
+wire RdClk;
+wire RdEn;
+wire Reset;
+wire VCC;
+wire WrClk;
+wire WrEn;
+wire \fifo_inst/n20_5 ;
+wire \fifo_inst/n26_4 ;
+wire \fifo_inst/n177_4 ;
+wire \fifo_inst/rempty_val ;
+wire \fifo_inst/wfull_val_7 ;
+wire \fifo_inst/wfull_val1 ;
+wire \fifo_inst/wfull_val1_0 ;
+wire \fifo_inst/Full_1 ;
+wire \fifo_inst/Equal.wbinnext_0_7 ;
+wire \fifo_inst/rempty_val_8 ;
+wire \fifo_inst/wfull_val1_2 ;
+wire \fifo_inst/wfull_val1_3 ;
+wire \fifo_inst/Full_1_2 ;
+wire \fifo_inst/Full_2 ;
+wire \fifo_inst/n4_6 ;
+wire \fifo_inst/n9_6 ;
+wire [0:0] \fifo_inst/Equal.rgraynext ;
+wire [0:0] \fifo_inst/Equal.wgraynext ;
+wire [1:0] \fifo_inst/rbin_num_next ;
+wire [1:1] \fifo_inst/Equal.wbinnext ;
+wire [1:0] \fifo_inst/reset_r ;
+wire [1:0] \fifo_inst/reset_w ;
+wire [1:0] \fifo_inst/rbin_num ;
+wire [1:0] \fifo_inst/Equal.rq1_wptr ;
+wire [1:0] \fifo_inst/Equal.rq2_wptr ;
+wire [0:0] \fifo_inst/rptr ;
+wire [1:0] \fifo_inst/wptr ;
+wire [0:0] \fifo_inst/Equal.wbin ;
+wire [31:8] \fifo_inst/DO ;
+VCC VCC_cZ (
+  .V(VCC)
+);
+GND GND_cZ (
+  .G(GND)
+);
+GSR GSR (
+	.GSRI(VCC)
+);
+LUT4 \fifo_inst/n20_s1  (
+	.I0(\fifo_inst/Full_2 ),
+	.I1(\fifo_inst/Full_1_2 ),
+	.I2(\fifo_inst/Full_1 ),
+	.I3(WrEn),
+	.F(\fifo_inst/n20_5 )
+);
+defparam \fifo_inst/n20_s1 .INIT=16'h5300;
+LUT3 \fifo_inst/n26_s1  (
+	.I0(RdEn),
+	.I1(Empty),
+	.I2(\fifo_inst/rempty_val ),
+	.F(\fifo_inst/n26_4 )
+);
+defparam \fifo_inst/n26_s1 .INIT=8'h0E;
+LUT3 \fifo_inst/Equal.rgraynext_0_s0  (
+	.I0(\fifo_inst/rbin_num [0]),
+	.I1(\fifo_inst/rbin_num_next [0]),
+	.I2(\fifo_inst/rbin_num [1]),
+	.F(\fifo_inst/Equal.rgraynext [0])
+);
+defparam \fifo_inst/Equal.rgraynext_0_s0 .INIT=8'h1E;
+LUT3 \fifo_inst/Equal.wgraynext_0_s0  (
+	.I0(\fifo_inst/Equal.wbin [0]),
+	.I1(\fifo_inst/n20_5 ),
+	.I2(\fifo_inst/wptr [1]),
+	.F(\fifo_inst/Equal.wgraynext [0])
+);
+defparam \fifo_inst/Equal.wgraynext_0_s0 .INIT=8'h1E;
+LUT2 \fifo_inst/n177_s1  (
+	.I0(\fifo_inst/reset_w [1]),
+	.I1(\fifo_inst/wfull_val_7 ),
+	.F(\fifo_inst/n177_4 )
+);
+defparam \fifo_inst/n177_s1 .INIT=4'h4;
+LUT4 \fifo_inst/rempty_val_s3  (
+	.I0(\fifo_inst/Equal.rq2_wptr [1]),
+	.I1(\fifo_inst/rempty_val_8 ),
+	.I2(\fifo_inst/Equal.rq2_wptr [0]),
+	.I3(\fifo_inst/rbin_num_next [0]),
+	.F(\fifo_inst/rempty_val )
+);
+defparam \fifo_inst/rempty_val_s3 .INIT=16'h4221;
+LUT4 \fifo_inst/wfull_val_s3  (
+	.I0(\fifo_inst/wptr [0]),
+	.I1(\fifo_inst/wptr [1]),
+	.I2(\fifo_inst/rbin_num [1]),
+	.I3(\fifo_inst/rptr [0]),
+	.F(\fifo_inst/wfull_val_7 )
+);
+defparam \fifo_inst/wfull_val_s3 .INIT=16'h1428;
+LUT3 \fifo_inst/wfull_val1_s9  (
+	.I0(\fifo_inst/wfull_val1_3 ),
+	.I1(\fifo_inst/wfull_val1_2 ),
+	.I2(\fifo_inst/wfull_val1_0 ),
+	.F(\fifo_inst/wfull_val1 )
+);
+defparam \fifo_inst/wfull_val1_s9 .INIT=8'hAC;
+LUT3 \fifo_inst/wfull_val1_s10  (
+	.I0(\fifo_inst/wfull_val_7 ),
+	.I1(\fifo_inst/wfull_val1_0 ),
+	.I2(\fifo_inst/reset_w [1]),
+	.F(\fifo_inst/wfull_val1_0 )
+);
+defparam \fifo_inst/wfull_val1_s10 .INIT=8'h0E;
+LUT3 \fifo_inst/Full_d_s  (
+	.I0(\fifo_inst/Full_2 ),
+	.I1(\fifo_inst/Full_1_2 ),
+	.I2(\fifo_inst/Full_1 ),
+	.F(Full)
+);
+defparam \fifo_inst/Full_d_s .INIT=8'hAC;
+LUT3 \fifo_inst/Full_s8  (
+	.I0(\fifo_inst/wfull_val_7 ),
+	.I1(\fifo_inst/Full_1 ),
+	.I2(\fifo_inst/reset_w [1]),
+	.F(\fifo_inst/Full_1 )
+);
+defparam \fifo_inst/Full_s8 .INIT=8'h0E;
+LUT3 \fifo_inst/rbin_num_next_0_s5  (
+	.I0(Empty),
+	.I1(RdEn),
+	.I2(\fifo_inst/rbin_num [0]),
+	.F(\fifo_inst/rbin_num_next [0])
+);
+defparam \fifo_inst/rbin_num_next_0_s5 .INIT=8'hB4;
+LUT3 \fifo_inst/rbin_num_next_1_s2  (
+	.I0(\fifo_inst/rbin_num_next [0]),
+	.I1(\fifo_inst/rbin_num [0]),
+	.I2(\fifo_inst/rbin_num [1]),
+	.F(\fifo_inst/rbin_num_next [1])
+);
+defparam \fifo_inst/rbin_num_next_1_s2 .INIT=8'hB4;
+LUT2 \fifo_inst/Equal.wbinnext_0_s3  (
+	.I0(\fifo_inst/Equal.wbin [0]),
+	.I1(\fifo_inst/n20_5 ),
+	.F(\fifo_inst/Equal.wbinnext_0_7 )
+);
+defparam \fifo_inst/Equal.wbinnext_0_s3 .INIT=4'h6;
+LUT3 \fifo_inst/Equal.wbinnext_1_s2  (
+	.I0(\fifo_inst/Equal.wbin [0]),
+	.I1(\fifo_inst/n20_5 ),
+	.I2(\fifo_inst/wptr [1]),
+	.F(\fifo_inst/Equal.wbinnext [1])
+);
+defparam \fifo_inst/Equal.wbinnext_1_s2 .INIT=8'h78;
+LUT4 \fifo_inst/rempty_val_s4  (
+	.I0(\fifo_inst/Equal.rq2_wptr [0]),
+	.I1(\fifo_inst/Equal.rq2_wptr [1]),
+	.I2(\fifo_inst/rbin_num [1]),
+	.I3(\fifo_inst/rbin_num [0]),
+	.F(\fifo_inst/rempty_val_8 )
+);
+defparam \fifo_inst/rempty_val_s4 .INIT=16'h871E;
+DFFP \fifo_inst/reset_r_0_s0  (
+	.D(GND),
+	.CLK(\fifo_inst/n4_6 ),
+	.PRESET(Reset),
+	.Q(\fifo_inst/reset_r [0])
+);
+defparam \fifo_inst/reset_r_0_s0 .INIT=1'b1;
+DFFP \fifo_inst/reset_w_1_s0  (
+	.D(\fifo_inst/reset_w [0]),
+	.CLK(\fifo_inst/n9_6 ),
+	.PRESET(Reset),
+	.Q(\fifo_inst/reset_w [1])
+);
+defparam \fifo_inst/reset_w_1_s0 .INIT=1'b1;
+DFFP \fifo_inst/reset_w_0_s0  (
+	.D(GND),
+	.CLK(\fifo_inst/n9_6 ),
+	.PRESET(Reset),
+	.Q(\fifo_inst/reset_w [0])
+);
+defparam \fifo_inst/reset_w_0_s0 .INIT=1'b1;
+DFFC \fifo_inst/rbin_num_1_s0  (
+	.D(\fifo_inst/rbin_num_next [1]),
+	.CLK(RdClk),
+	.CLEAR(\fifo_inst/reset_r [1]),
+	.Q(\fifo_inst/rbin_num [1])
+);
+defparam \fifo_inst/rbin_num_1_s0 .INIT=1'b0;
+DFFC \fifo_inst/rbin_num_0_s0  (
+	.D(\fifo_inst/rbin_num_next [0]),
+	.CLK(RdClk),
+	.CLEAR(\fifo_inst/reset_r [1]),
+	.Q(\fifo_inst/rbin_num [0])
+);
+defparam \fifo_inst/rbin_num_0_s0 .INIT=1'b0;
+DFFC \fifo_inst/Equal.rq1_wptr_1_s0  (
+	.D(\fifo_inst/wptr [1]),
+	.CLK(RdClk),
+	.CLEAR(\fifo_inst/reset_r [1]),
+	.Q(\fifo_inst/Equal.rq1_wptr [1])
+);
+defparam \fifo_inst/Equal.rq1_wptr_1_s0 .INIT=1'b0;
+DFFC \fifo_inst/Equal.rq1_wptr_0_s0  (
+	.D(\fifo_inst/wptr [0]),
+	.CLK(RdClk),
+	.CLEAR(\fifo_inst/reset_r [1]),
+	.Q(\fifo_inst/Equal.rq1_wptr [0])
+);
+defparam \fifo_inst/Equal.rq1_wptr_0_s0 .INIT=1'b0;
+DFFC \fifo_inst/Equal.rq2_wptr_1_s0  (
+	.D(\fifo_inst/Equal.rq1_wptr [1]),
+	.CLK(RdClk),
+	.CLEAR(\fifo_inst/reset_r [1]),
+	.Q(\fifo_inst/Equal.rq2_wptr [1])
+);
+defparam \fifo_inst/Equal.rq2_wptr_1_s0 .INIT=1'b0;
+DFFC \fifo_inst/Equal.rq2_wptr_0_s0  (
+	.D(\fifo_inst/Equal.rq1_wptr [0]),
+	.CLK(RdClk),
+	.CLEAR(\fifo_inst/reset_r [1]),
+	.Q(\fifo_inst/Equal.rq2_wptr [0])
+);
+defparam \fifo_inst/Equal.rq2_wptr_0_s0 .INIT=1'b0;
+DFFC \fifo_inst/rptr_0_s0  (
+	.D(\fifo_inst/Equal.rgraynext [0]),
+	.CLK(RdClk),
+	.CLEAR(\fifo_inst/reset_r [1]),
+	.Q(\fifo_inst/rptr [0])
+);
+defparam \fifo_inst/rptr_0_s0 .INIT=1'b0;
+DFFC \fifo_inst/wptr_1_s0  (
+	.D(\fifo_inst/Equal.wbinnext [1]),
+	.CLK(WrClk),
+	.CLEAR(\fifo_inst/reset_w [1]),
+	.Q(\fifo_inst/wptr [1])
+);
+defparam \fifo_inst/wptr_1_s0 .INIT=1'b0;
+DFFC \fifo_inst/wptr_0_s0  (
+	.D(\fifo_inst/Equal.wgraynext [0]),
+	.CLK(WrClk),
+	.CLEAR(\fifo_inst/reset_w [1]),
+	.Q(\fifo_inst/wptr [0])
+);
+defparam \fifo_inst/wptr_0_s0 .INIT=1'b0;
+DFFC \fifo_inst/Equal.wbin_0_s0  (
+	.D(\fifo_inst/Equal.wbinnext_0_7 ),
+	.CLK(WrClk),
+	.CLEAR(\fifo_inst/reset_w [1]),
+	.Q(\fifo_inst/Equal.wbin [0])
+);
+defparam \fifo_inst/Equal.wbin_0_s0 .INIT=1'b0;
+DFFP \fifo_inst/Empty_s0  (
+	.D(\fifo_inst/rempty_val ),
+	.CLK(RdClk),
+	.PRESET(\fifo_inst/reset_r [1]),
+	.Q(Empty)
+);
+defparam \fifo_inst/Empty_s0 .INIT=1'b1;
+DFFP \fifo_inst/reset_r_1_s0  (
+	.D(\fifo_inst/reset_r [0]),
+	.CLK(\fifo_inst/n4_6 ),
+	.PRESET(Reset),
+	.Q(\fifo_inst/reset_r [1])
+);
+defparam \fifo_inst/reset_r_1_s0 .INIT=1'b1;
+DFFC \fifo_inst/wfull_val1_s0  (
+	.D(\fifo_inst/wfull_val_7 ),
+	.CLK(WrClk),
+	.CLEAR(\fifo_inst/reset_w [1]),
+	.Q(\fifo_inst/wfull_val1_2 )
+);
+defparam \fifo_inst/wfull_val1_s0 .INIT=1'b0;
+DFFP \fifo_inst/wfull_val1_s1  (
+	.D(\fifo_inst/wfull_val_7 ),
+	.CLK(WrClk),
+	.PRESET(\fifo_inst/n177_4 ),
+	.Q(\fifo_inst/wfull_val1_3 )
+);
+defparam \fifo_inst/wfull_val1_s1 .INIT=1'b1;
+DFFC \fifo_inst/Full_s0  (
+	.D(\fifo_inst/wfull_val1 ),
+	.CLK(WrClk),
+	.CLEAR(\fifo_inst/reset_w [1]),
+	.Q(\fifo_inst/Full_1_2 )
+);
+defparam \fifo_inst/Full_s0 .INIT=1'b0;
+DFFP \fifo_inst/Full_s1  (
+	.D(\fifo_inst/wfull_val1 ),
+	.CLK(WrClk),
+	.PRESET(\fifo_inst/n177_4 ),
+	.Q(\fifo_inst/Full_2 )
+);
+defparam \fifo_inst/Full_s1 .INIT=1'b1;
+SDPB \fifo_inst/Equal.mem_Equal.mem_0_0_s  (
+	.CLKA(WrClk),
+	.CEA(\fifo_inst/n20_5 ),
+	.RESETA(GND),
+	.CLKB(RdClk),
+	.CEB(\fifo_inst/n26_4 ),
+	.RESETB(\fifo_inst/reset_r [1]),
+	.OCE(GND),
+	.BLKSELA({GND, GND, GND}),
+	.BLKSELB({GND, GND, GND}),
+	.DI({GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, Data[7:0]}),
+	.ADA({GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, \fifo_inst/Equal.wbin [0], GND, GND, GND}),
+	.ADB({GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, \fifo_inst/rbin_num_next [0], GND, GND, GND}),
+	.DO({\fifo_inst/DO [31:8], Q[7:0]})
+);
+defparam \fifo_inst/Equal.mem_Equal.mem_0_0_s .READ_MODE=1'b0;
+defparam \fifo_inst/Equal.mem_Equal.mem_0_0_s .BIT_WIDTH_0=8;
+defparam \fifo_inst/Equal.mem_Equal.mem_0_0_s .BIT_WIDTH_1=8;
+defparam \fifo_inst/Equal.mem_Equal.mem_0_0_s .RESET_MODE="ASYNC";
+defparam \fifo_inst/Equal.mem_Equal.mem_0_0_s .BLK_SEL_0=3'b000;
+defparam \fifo_inst/Equal.mem_Equal.mem_0_0_s .BLK_SEL_1=3'b000;
+INV \fifo_inst/n4_s2  (
+	.I(RdClk),
+	.O(\fifo_inst/n4_6 )
+);
+INV \fifo_inst/n9_s2  (
+	.I(WrClk),
+	.O(\fifo_inst/n9_6 )
+);
+endmodule

src/src/WrapFifoChain/FifoShReg8/FifoShReg8_tmp.v

@@ -0,0 +1,24 @@
+//Copyright (C)2014-2024 Gowin Semiconductor Corporation.
+//All rights reserved.
+//File Title: Template file for instantiation
+//Tool Version: V1.9.9.03 (64-bit)
+//Part Number: GW1N-UV9QN88C6/I5
+//Device: GW1N-9
+//Created Time: Thu Nov 28 11:57:53 2024
+
+//Change the instance name and port connections to the signal names
+//--------Copy here to design--------
+
+	FifoShReg8 your_instance_name(
+		.Data(Data), //input [7:0] Data
+		.Reset(Reset), //input Reset
+		.WrClk(WrClk), //input WrClk
+		.RdClk(RdClk), //input RdClk
+		.WrEn(WrEn), //input WrEn
+		.RdEn(RdEn), //input RdEn
+		.Q(Q), //output [7:0] Q
+		.Empty(Empty), //output Empty
+		.Full(Full) //output Full
+	);
+
+//--------Copy end-------------------

src/src/WrapFifoChain/FifoShReg8/temp/FIFOHS/FIFOHS.prj

@@ -0,0 +1,20 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!DOCTYPE gowin-synthesis-project>
+<Project>
+    <Version>beta</Version>
+    <Device id="GW1N-9" package="QFN88" speed="6" partNumber="GW1N-UV9QN88C6/I5"/>
+    <FileList>
+        <File path="C:/Gowin/Gowin_V1.9.9.03_x64/IDE/ipcore/FIFO_HS/data/fifo_hs.v" type="verilog"/>
+        <File path="C:/Gowin/Gowin_V1.9.9.03_x64/IDE/ipcore/FIFO_HS/data/fifo_hs_top.v" type="verilog"/>
+    </FileList>
+    <OptionList>
+        <Option type="disable_insert_pad" value="1"/>
+        <Option type="include_path" value="C:/Gowin/Gowin_V1.9.9.03_x64/IDE/ipcore/FIFO_HS/data"/>
+        <Option type="include_path" value="C:/Gowin/Projects/CP2444v1_FPGA/src/src/WrapFifoChain/FifoShReg8/temp/FIFOHS"/>
+        <Option type="output_file" value="FifoShReg8.vg"/>
+        <Option type="output_template" value="FifoShReg8_tmp.v"/>
+        <Option type="ram_balance" value="1"/>
+        <Option type="ram_rw_check" value="1"/>
+        <Option type="verilog_language" value="sysv-2017"/>
+    </OptionList>
+</Project>

src/src/WrapFifoChain/FifoShReg8/temp/FIFOHS/FifoShReg8.log

@@ -0,0 +1,45 @@
+GowinSynthesis start
+Running parser ...
+Analyzing Verilog file 'C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v'
+Analyzing included file '**'("C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Back to file '**'("C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Undeclared symbol '**', assumed default net type '**'("C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Analyzing Verilog file 'C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v'
+Analyzing included file 'fifo_define.v'("C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":1)
+Back to file 'C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v'("C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":1)
+Analyzing included file 'C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\static_macro_define.v'("C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":2)
+Back to file 'C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v'("C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":2)
+Analyzing included file 'fifo_parameter.v'("C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":57)
+Back to file 'C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v'("C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":57)
+Compiling module 'FifoShReg8'("C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":4)
+Compiling module '**'("C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Extracting RAM for identifier '**'("C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+NOTE  (EX0101) : Current top module is "FifoShReg8"
+[5%] Running netlist conversion ...
+Running device independent optimization ...
+[10%] Optimizing Phase 0 completed
+[15%] Optimizing Phase 1 completed
+[25%] Optimizing Phase 2 completed
+Running inference ...
+[30%] Inferring Phase 0 completed
+[40%] Inferring Phase 1 completed
+[50%] Inferring Phase 2 completed
+[55%] Inferring Phase 3 completed
+Running technical mapping ...
+[60%] Tech-Mapping Phase 0 completed
+[65%] Tech-Mapping Phase 1 completed
+[75%] Tech-Mapping Phase 2 completed
+WARN  (AG0100) : Find logical loop signal : "fifo_inst/wfull_val1_s3"("C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+WARN  (AG0100) : Find logical loop signal : "fifo_inst/wfull_val1_s6"("C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+WARN  (AG0100) : Find logical loop signal : "fifo_inst/wfull_val1_s3"("C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+WARN  (AG0101) : The netlist is not one directed acyclic graph
+WARN  (AG0100) : Find logical loop signal : "fifo_inst/Full_s3"("C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+WARN  (AG0100) : Find logical loop signal : "fifo_inst/Full_s6"("C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+WARN  (AG0100) : Find logical loop signal : "fifo_inst/Full_s3"("C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+WARN  (AG0101) : The netlist is not one directed acyclic graph
+[80%] Tech-Mapping Phase 3 completed
+[90%] Tech-Mapping Phase 4 completed
+[95%] Generate netlist file "C:\Gowin\Projects\CP2444v1_FPGA\src\src\WrapFifoChain\FifoShReg8\temp\FIFOHS\FifoShReg8.vg" completed
+Generate template file "C:\Gowin\Projects\CP2444v1_FPGA\src\src\WrapFifoChain\FifoShReg8\temp\FIFOHS\FifoShReg8_tmp.v" completed
+[100%] Generate report file "C:\Gowin\Projects\CP2444v1_FPGA\src\src\WrapFifoChain\FifoShReg8\temp\FIFOHS\FifoShReg8_syn.rpt.html" completed
+GowinSynthesis finish

src/src/WrapFifoChain/FifoShReg8/temp/FIFOHS/FifoShReg8.vg

@@ -0,0 +1,188 @@
+//
+//Written by GowinSynthesis
+//Tool Version "V1.9.9.03 (64-bit)"
+//Thu Nov 28 11:57:53 2024
+
+//Source file index table:
+//file0 "\C:/Gowin/Gowin_V1.9.9.03_x64/IDE/ipcore/FIFO_HS/data/fifo_hs.v"
+//file1 "\C:/Gowin/Gowin_V1.9.9.03_x64/IDE/ipcore/FIFO_HS/data/fifo_hs_top.v"
+`timescale 100 ps/100 ps
+`pragma protect begin_protected
+`pragma protect version="2.3"
+`pragma protect author="default"
+`pragma protect author_info="default"
+`pragma protect encrypt_agent="GOWIN"
+`pragma protect encrypt_agent_info="GOWIN Encrypt Version 2.3"
+
+`pragma protect encoding=(enctype="base64", line_length=76, bytes=256)
+`pragma protect key_keyowner="GOWIN",key_keyname="GWK2023-09",key_method="rsa"
+`pragma protect key_block
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+gQSiGDyNofJkht17RrnQkrg0BGeB+svTtaf34Q==
+
+`pragma protect encoding=(enctype="base64", line_length=76, bytes=6400)
+`pragma protect data_keyowner="default-ip-vendor"
+`pragma protect data_keyname="default-ip-key"
+`pragma protect data_method="aes128-cfb"
+`pragma protect data_block
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+cEEw/cAm1Gimtcg5Kv7+TA==
+`pragma protect end_protected
+module FifoShReg8 (
+  Data,
+  Reset,
+  WrClk,
+  RdClk,
+  WrEn,
+  RdEn,
+  Q,
+  Empty,
+  Full
+)
+;
+input [7:0] Data;
+input Reset;
+input WrClk;
+input RdClk;
+input WrEn;
+input RdEn;
+output [7:0] Q;
+output Empty;
+output Full;
+wire VCC;
+wire GND;
+  \~fifo.FifoShReg8  fifo_inst (
+    .Reset(Reset),
+    .RdClk(RdClk),
+    .WrClk(WrClk),
+    .WrEn(WrEn),
+    .RdEn(RdEn),
+    .Data(Data[7:0]),
+    .Empty(Empty),
+    .Full(Full),
+    .Q(Q[7:0])
+);
+  VCC VCC_cZ (
+    .V(VCC)
+);
+  GND GND_cZ (
+    .G(GND)
+);
+  GSR GSR (
+    .GSRI(VCC) 
+);
+endmodule /* FifoShReg8 */

src/src/WrapFifoChain/FifoShReg8/temp/FIFOHS/FifoShReg8_syn_resource.html

@@ -0,0 +1,46 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html>
+<head>
+<title>Hierarchy Module Resource</title>
+<style type="text/css">
+body { font-family: Verdana, Arial, sans-serif; font-size: 14px; }
+div#main_wrapper{ width: 100%; }
+h1 {text-align: center; }
+h1 {margin-top: 36px; }
+table, th, td { border: 1px solid #aaa; }
+table { border-collapse:collapse; margin-top: 10px; margin-bottom: 20px; width: 100%; }
+th, td { align = "center"; padding: 5px 2px 5px 5px; }
+th { color: #fff; font-weight: bold; background-color: #0084ff; }
+table td.label { width: 20%; white-space: nowrap; min-width: 20px; background-color: #dee8f4; }
+</style>
+</head>
+<body>
+<div id="main_wrapper">
+<div id="content">
+<h1>Hierarchy Module Resource</h1>
+<table>
+<tr>
+<th class="label">MODULE NAME</th>
+<th class="label">REG NUMBER</th>
+<th class="label">ALU NUMBER</th>
+<th class="label">LUT NUMBER</th>
+<th class="label">DSP NUMBER</th>
+<th class="label">BSRAM NUMBER</th>
+<th class="label">SSRAM NUMBER</th>
+<th class="label">ROM16 NUMBER</th>
+</tr>
+<tr>
+<td class="label">FifoShReg8 (C:/Gowin/Gowin_V1.9.9.03_x64/IDE/ipcore/FIFO_HS/data/fifo_hs_top.v)</td>
+<td align = "center">19</td>
+<td align = "center">-</td>
+<td align = "center">18</td>
+<td align = "center">-</td>
+<td align = "center">1</td>
+<td align = "center">-</td>
+<td align = "center">-</td>
+</tr>
+</table>
+</div><!-- content -->
+</div><!-- main_wrapper -->
+</body>
+</html>

src/src/WrapFifoChain/FifoShReg8/temp/FIFOHS/FifoShReg8_syn_rsc.xml

@@ -0,0 +1,2 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<Module name="FifoShReg8" Register="19" Lut="18" Bsram="1" T_Register="19(19)" T_Lut="18(18)" T_Bsram="1(1)"/>

src/src/WrapFifoChain/FifoShReg8/temp/FIFOHS/FifoShReg8_tmp.v

@@ -0,0 +1,24 @@
+//Copyright (C)2014-2024 Gowin Semiconductor Corporation.
+//All rights reserved.
+//File Title: Template file for instantiation
+//Tool Version: V1.9.9.03 (64-bit)
+//Part Number: GW1N-UV9QN88C6/I5
+//Device: GW1N-9
+//Created Time: Thu Nov 28 11:57:53 2024
+
+//Change the instance name and port connections to the signal names
+//--------Copy here to design--------
+
+	FifoShReg8 your_instance_name(
+		.Data(Data), //input [7:0] Data
+		.Reset(Reset), //input Reset
+		.WrClk(WrClk), //input WrClk
+		.RdClk(RdClk), //input RdClk
+		.WrEn(WrEn), //input WrEn
+		.RdEn(RdEn), //input RdEn
+		.Q(Q), //output [7:0] Q
+		.Empty(Empty), //output Empty
+		.Full(Full) //output Full
+	);
+
+//--------Copy end-------------------

src/src/WrapFifoChain/FifoShReg8/temp/FIFOHS/fifo_define.v

@@ -0,0 +1,5 @@
+`define module_name FifoShReg8
+`define EBR_BASED
+`define FWFT
+`define En_Reset
+`define Reset_Synchronization

src/src/WrapFifoChain/FifoShReg8/temp/FIFOHS/fifo_parameter.v

@@ -0,0 +1,6 @@
+parameter WDEPTH = 2;
+parameter ASIZE = 1;
+parameter WDSIZE = 8;
+parameter RDEPTH = 2;
+parameter RASIZE = 1;
+parameter RDSIZE = 8;

src/src/WrapFifoChain/FifoShReg8/temp/FIFOHS/project.ini

@@ -0,0 +1 @@
+RESOURCE_CHECK=false

src/src/WrapFifoChain/SwCtrlWrapper.v

@@ -0,0 +1,76 @@
+module SwCtrlWrapper #(
+    parameter IN_WIDTH = 24,
+    parameter WR_NUM = 1,
+    parameter OUT_WIDTH = 8,
+    parameter DATA_WIDTH = 8
+)(
+    input WrClk_i,
+    input RdClk_i,
+    input Rst_i,
+    input [IN_WIDTH-1:0] Data_i,
+    input Val_i,
+
+    output Ss_o,
+    output Sck_o,
+    output Mosi_o
+);
+//================================================================================
+//	                                REG/WIRE
+//================================================================================  
+wire [OUT_WIDTH-1:0] dataFromFifoCtrl;
+wire [OUT_WIDTH-1:0] dataFromFifo;
+wire readEn;
+wire writeEn;
+wire valRdData;
+wire busySpiM;
+wire fifoFull;
+wire fifoEmpty;
+//==========================================================================//
+//									CODING									//
+//==========================================================================//
+FifoCtrl #(
+    .IN_WIDTH		(IN_WIDTH),
+    .WR_NUM			(WR_NUM),
+    .OUT_WIDTH		(OUT_WIDTH)
+) FifoCtrl
+(
+    .WrClk_i		(WrClk_i),
+    .RdClk_i		(RdClk_i),
+    .Rst_i			(Rst_i),
+    .Data_i			(Data_i),
+    .Val_i			(Val_i),
+    .BusySpiM_i		(busySpiM),
+    .FifoFull_i		(fifoFull),
+    .FifoEmpty_i	(fifoEmpty),
+    .Data_o			(dataFromFifoCtrl),
+    .ReadEn_o		(readEn),
+    .WriteEn_o		(writeEn),
+    .ValRdData_o	(valRdData)
+);
+
+FifoShReg8  FifoSwCtrl_inst (
+    .Data	        (dataFromFifoCtrl),
+    .WrClk	        (WrClk_i),
+    .RdClk	        (RdClk_i),
+    .Reset	        (Rst_i),
+    .WrEn	        (writeEn),
+    .RdEn	        (readEn),
+    .Full           (fifoFull),
+    .Empty          (fifoEmpty),
+    .Q              (dataFromFifo)
+);
+
+SpiM #(
+    .DATA_WIDTH(DATA_WIDTH)
+) SpiMSwCtrl (
+    .Clk_i        (RdClk_i),
+    .Rst_i        (Rst_i),
+    .Val_i        (valRdData),
+    .SpiData_i       (dataFromFifo),
+    .Busy_o       (busySpiM),
+    .Ss_o         (Ss_o),
+    .Sck_o        (Sck_o),
+    .Mosi_o       (Mosi_o)
+);
+
+endmodule