Обновил заголовок и расширил FIFO.

src/src/PacketAnalyzer4Mosi/PacketAnalyzer4MosiCp2444v1.v

@@ -64,22 +64,21 @@ wire [5:0] selector;
 //==========================================
 // Parameters
 //==========================================
-localparam [22:0] DECREMENT_GPIO = 23'h400000; //23'b100 0000 0000 0000 0000 0000
-localparam [22:0] DECREMENT_SW_P1 = 23'h200000; //23'b010 0000 0000 0000 0000 0000
-localparam [22:0] DECREMENT_ATT_P1 = 23'h100000; //23'b001 0000 0000 0000 0000 0000
-localparam [22:0] DECREMENT_ATT_P2 = 23'h80000; //23'b000 1000 0000 0000 0000 0000
-localparam [22:0] DECREMENT_ATT_P3 = 23'h40000; //23'b000 0100 0000 0000 0000 0000
-localparam [22:0] DECREMENT_ATT_P4 = 23'h20000; //23'b000 0010 0000 0000 0000 0000
- 
+localparam [22:0] DECREMENT_GPIO = 23'h100000; //23'b001 0000 0000 0000 0000 0000
+localparam [22:0] DECREMENT_SW_P1 = 23'h20000; //23'b000 0010 0000 0000 0000 0000
+localparam [22:0] DECREMENT_ATT_P1 = 23'h4000; //23'b000 0000 1000 0000 0000 0000
+localparam [22:0] DECREMENT_ATT_P2 = 23'h800; //23'b000 0000 0000 1000 0000 0000
+localparam [22:0] DECREMENT_ATT_P3 = 23'h100; //23'b000 0000 0000 0001 0000 0000
+localparam [22:0] DECREMENT_ATT_P4 = 23'h20; //23'b000 0000 0000 0000 0010 0000
 //==========================================
 // Assignments
 //==========================================
-assign gpioOr = |dataSpiReg[22];
-assign swP1Or = |dataSpiReg[21];
-assign attP1Or = |dataSpiReg[20];
-assign attP2Or = |dataSpiReg[19];
-assign attP3Or = |dataSpiReg[18];
-assign attP4Or = |dataSpiReg[17];
+assign gpioOr = |dataSpiReg[21:20];
+assign swP1Or = |dataSpiReg[18:17];
+assign attP1Or = |dataSpiReg[15:14];
+assign attP2Or = |dataSpiReg[12:11];
+assign attP3Or = |dataSpiReg[9:8];
+assign attP4Or = |dataSpiReg[6:5];
 
 assign selector = {gpioOr, swP1Or, attP1Or, attP2Or, attP3Or, attP4Or};
 

src/src/WrapFifoChain/FifoShReg16/FifoShReg16.ipc

@@ -25,11 +25,11 @@ OutputRegistersSelected=false
 REG=false
 ReadDataNum=false
 ReadDataWidth=16
-ReadDepth=2
+ReadDepth=4
 ResetSynchronization=true
 SSRAM=false
 StandardFIFO=false
 Synthesis_tool=GowinSynthesis
 WriteDataNum=false
 WriteDataWidth=16
-WriteDepth=2
+WriteDepth=4

src/src/WrapFifoChain/FifoShReg16/FifoShReg16.v

@@ -1,7 +1,7 @@
 //
 //Written by GowinSynthesis
 //Tool Version "V1.9.9.03 (64-bit)"
-//Thu Nov 28 11:58:21 2024
+//Wed Dec 11 18:12:33 2024
 
 //Source file index table:
 //file0 "\C:/Gowin/Gowin_V1.9.9.03_x64/IDE/ipcore/FIFO_HS/data/fifo_hs.v"
@@ -17,129 +17,165 @@
 `pragma protect encoding=(enctype="base64", line_length=76, bytes=256)
 `pragma protect key_keyowner="GOWIN",key_keyname="GWK2023-09",key_method="rsa"
 `pragma protect key_block
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+GR4X2fnd5l3q7jAUMgo+jjDHE8W5vdph2o9ztA==
 
-`pragma protect encoding=(enctype="base64", line_length=76, bytes=6368)
+`pragma protect encoding=(enctype="base64", line_length=76, bytes=8432)
 `pragma protect data_keyowner="default-ip-vendor"
 `pragma protect data_keyname="default-ip-key"
 `pragma protect data_method="aes128-cfb"
 `pragma protect data_block
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+jpxIde8vVmOndbazWKGx9Hpcp1r3DAV2M/sXrNvBycZ4C8LTUeE6VUHmTG9bysjJOY5w0NVprMZY
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+o2kKONDNkQNa3HQgoATDwWurKq2GCFl4v1TTV2BhpZm4e2eqz7DF2kFtxGpziXtumpZOo1FS9b/W
+e1tJP2/NJJhoP7pZYvTAj+i7Bc+duVp/cRRJLuSpy+ZjZ96HwjPx1Wx0Bfmbzv9OnPoXA5ZtIsuY
+B5OyUNuyanAGbrEzO7pYg3DkIoXbgLQ9xyFecGDzVIzAVVpDw0JL+MzIucecUyzwet7PO1K54zC4
+CarWJ/G6DWewFkacBFkkdadNGDOH6Vq1FcwjXcEdTgTflg+uWRA4UMov1ncx1a1kl9/Tp2qGI+ha
+m/0rq2Qh7DUM8Ac2RqLWkXeCUiCmfLYRnbnS8N5SDJjdh4IPW2KevnhE7lu3TcrSW5dwVITP1tsW
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+Vx0FqdCtx8xNuBukqlLGZ5AMR6yssLXHk0H3+ANO32nfl2D/3BS5ZXExP8yyKzLcrts1uraPJf1/
+1tOHrtssXoxpMJ+01j43bGDt3u7MDXEapbxe8s3eltZ47yk0a2CxfNLS4MRy58dI6ctgTLo=
 `pragma protect end_protected
 module FifoShReg16 (
   Data,

src/src/WrapFifoChain/FifoShReg16/FifoShReg16.vo

@@ -2,7 +2,7 @@
 //All rights reserved.
 //File Title: Post-PnR Simulation Model file
 //Tool Version: V1.9.9.03 (64-bit)
-//Created Time: Thu Nov 28 11:58:21 2024
+//Created Time: Wed Dec 11 18:12:33 2024
 
 `timescale 100 ps/100 ps
 module FifoShReg16(
@@ -36,34 +36,39 @@ wire Reset;
 wire VCC;
 wire WrClk;
 wire WrEn;
-wire \fifo_inst/n20_5 ;
-wire \fifo_inst/n26_4 ;
-wire \fifo_inst/n217_4 ;
-wire \fifo_inst/rempty_val ;
-wire \fifo_inst/wfull_val_7 ;
+wire \fifo_inst/n21_5 ;
+wire \fifo_inst/n27_4 ;
 wire \fifo_inst/wfull_val1 ;
 wire \fifo_inst/wfull_val1_0 ;
 wire \fifo_inst/Full_1 ;
 wire \fifo_inst/Equal.wbinnext_0_7 ;
-wire \fifo_inst/rempty_val_8 ;
+wire \fifo_inst/wfull_val_4 ;
+wire \fifo_inst/wfull_val_5 ;
+wire \fifo_inst/n255_6 ;
+wire \fifo_inst/wfull_val ;
+wire \fifo_inst/rempty_val ;
 wire \fifo_inst/wfull_val1_2 ;
 wire \fifo_inst/wfull_val1_3 ;
 wire \fifo_inst/Full_1_2 ;
 wire \fifo_inst/Full_2 ;
+wire \fifo_inst/n94_1_SUM ;
+wire \fifo_inst/n94_3 ;
+wire \fifo_inst/n95_1_SUM ;
+wire \fifo_inst/n95_3 ;
 wire \fifo_inst/n4_6 ;
 wire \fifo_inst/n9_6 ;
-wire [0:0] \fifo_inst/Equal.rgraynext ;
-wire [0:0] \fifo_inst/Equal.wgraynext ;
-wire [1:0] \fifo_inst/rbin_num_next ;
-wire [1:1] \fifo_inst/Equal.wbinnext ;
+wire [1:0] \fifo_inst/Equal.rgraynext ;
+wire [1:0] \fifo_inst/Equal.wgraynext ;
+wire [2:0] \fifo_inst/rbin_num_next ;
+wire [2:1] \fifo_inst/Equal.wbinnext ;
 wire [1:0] \fifo_inst/reset_r ;
 wire [1:0] \fifo_inst/reset_w ;
-wire [1:0] \fifo_inst/rbin_num ;
-wire [1:0] \fifo_inst/Equal.rq1_wptr ;
-wire [1:0] \fifo_inst/Equal.rq2_wptr ;
-wire [0:0] \fifo_inst/rptr ;
-wire [1:0] \fifo_inst/wptr ;
-wire [0:0] \fifo_inst/Equal.wbin ;
+wire [2:0] \fifo_inst/rbin_num ;
+wire [2:0] \fifo_inst/Equal.rq1_wptr ;
+wire [2:0] \fifo_inst/Equal.rq2_wptr ;
+wire [1:0] \fifo_inst/rptr ;
+wire [2:0] \fifo_inst/wptr ;
+wire [1:0] \fifo_inst/Equal.wbin ;
 wire [31:16] \fifo_inst/DO ;
 VCC VCC_cZ (
   .V(VCC)
@@ -74,57 +79,51 @@ GND GND_cZ (
 GSR GSR (
 	.GSRI(VCC)
 );
-LUT4 \fifo_inst/n20_s1  (
+LUT4 \fifo_inst/n21_s1  (
 	.I0(\fifo_inst/Full_2 ),
 	.I1(\fifo_inst/Full_1_2 ),
 	.I2(\fifo_inst/Full_1 ),
 	.I3(WrEn),
-	.F(\fifo_inst/n20_5 )
+	.F(\fifo_inst/n21_5 )
 );
-defparam \fifo_inst/n20_s1 .INIT=16'h5300;
-LUT3 \fifo_inst/n26_s1  (
+defparam \fifo_inst/n21_s1 .INIT=16'h5300;
+LUT3 \fifo_inst/n27_s1  (
 	.I0(RdEn),
 	.I1(Empty),
 	.I2(\fifo_inst/rempty_val ),
-	.F(\fifo_inst/n26_4 )
+	.F(\fifo_inst/n27_4 )
 );
-defparam \fifo_inst/n26_s1 .INIT=8'h0E;
+defparam \fifo_inst/n27_s1 .INIT=8'h0E;
 LUT3 \fifo_inst/Equal.rgraynext_0_s0  (
-	.I0(\fifo_inst/rbin_num [0]),
-	.I1(\fifo_inst/rbin_num_next [0]),
+	.I0(\fifo_inst/rbin_num_next [0]),
+	.I1(\fifo_inst/rbin_num [0]),
 	.I2(\fifo_inst/rbin_num [1]),
 	.F(\fifo_inst/Equal.rgraynext [0])
 );
 defparam \fifo_inst/Equal.rgraynext_0_s0 .INIT=8'h1E;
+LUT4 \fifo_inst/Equal.rgraynext_1_s0  (
+	.I0(\fifo_inst/rbin_num_next [0]),
+	.I1(\fifo_inst/rbin_num [0]),
+	.I2(\fifo_inst/rbin_num [1]),
+	.I3(\fifo_inst/rbin_num [2]),
+	.F(\fifo_inst/Equal.rgraynext [1])
+);
+defparam \fifo_inst/Equal.rgraynext_1_s0 .INIT=16'h0BF4;
 LUT3 \fifo_inst/Equal.wgraynext_0_s0  (
-	.I0(\fifo_inst/Equal.wbin [0]),
-	.I1(\fifo_inst/n20_5 ),
-	.I2(\fifo_inst/wptr [1]),
+	.I0(\fifo_inst/n21_5 ),
+	.I1(\fifo_inst/Equal.wbin [0]),
+	.I2(\fifo_inst/Equal.wbin [1]),
 	.F(\fifo_inst/Equal.wgraynext [0])
 );
 defparam \fifo_inst/Equal.wgraynext_0_s0 .INIT=8'h1E;
-LUT2 \fifo_inst/n217_s1  (
-	.I0(\fifo_inst/reset_w [1]),
-	.I1(\fifo_inst/wfull_val_7 ),
-	.F(\fifo_inst/n217_4 )
-);
-defparam \fifo_inst/n217_s1 .INIT=4'h4;
-LUT4 \fifo_inst/rempty_val_s3  (
-	.I0(\fifo_inst/Equal.rq2_wptr [1]),
-	.I1(\fifo_inst/rempty_val_8 ),
-	.I2(\fifo_inst/Equal.rq2_wptr [0]),
-	.I3(\fifo_inst/rbin_num_next [0]),
-	.F(\fifo_inst/rempty_val )
-);
-defparam \fifo_inst/rempty_val_s3 .INIT=16'h4221;
-LUT4 \fifo_inst/wfull_val_s3  (
-	.I0(\fifo_inst/wptr [0]),
-	.I1(\fifo_inst/wptr [1]),
-	.I2(\fifo_inst/rbin_num [1]),
-	.I3(\fifo_inst/rptr [0]),
-	.F(\fifo_inst/wfull_val_7 )
-);
-defparam \fifo_inst/wfull_val_s3 .INIT=16'h1428;
+LUT4 \fifo_inst/Equal.wgraynext_1_s0  (
+	.I0(\fifo_inst/n21_5 ),
+	.I1(\fifo_inst/Equal.wbin [0]),
+	.I2(\fifo_inst/Equal.wbin [1]),
+	.I3(\fifo_inst/wptr [2]),
+	.F(\fifo_inst/Equal.wgraynext [1])
+);
+defparam \fifo_inst/Equal.wgraynext_1_s0 .INIT=16'h07F8;
 LUT3 \fifo_inst/wfull_val1_s9  (
 	.I0(\fifo_inst/wfull_val1_3 ),
 	.I1(\fifo_inst/wfull_val1_2 ),
@@ -132,13 +131,14 @@ LUT3 \fifo_inst/wfull_val1_s9  (
 	.F(\fifo_inst/wfull_val1 )
 );
 defparam \fifo_inst/wfull_val1_s9 .INIT=8'hAC;
-LUT3 \fifo_inst/wfull_val1_s10  (
-	.I0(\fifo_inst/wfull_val_7 ),
-	.I1(\fifo_inst/wfull_val1_0 ),
-	.I2(\fifo_inst/reset_w [1]),
+LUT4 \fifo_inst/wfull_val1_s10  (
+	.I0(\fifo_inst/wfull_val_4 ),
+	.I1(\fifo_inst/wfull_val_5 ),
+	.I2(\fifo_inst/wfull_val1_0 ),
+	.I3(\fifo_inst/reset_w [1]),
 	.F(\fifo_inst/wfull_val1_0 )
 );
-defparam \fifo_inst/wfull_val1_s10 .INIT=8'h0E;
+defparam \fifo_inst/wfull_val1_s10 .INIT=16'h00F8;
 LUT3 \fifo_inst/Full_d_s  (
 	.I0(\fifo_inst/Full_2 ),
 	.I1(\fifo_inst/Full_1_2 ),
@@ -146,13 +146,14 @@ LUT3 \fifo_inst/Full_d_s  (
 	.F(Full)
 );
 defparam \fifo_inst/Full_d_s .INIT=8'hAC;
-LUT3 \fifo_inst/Full_s8  (
-	.I0(\fifo_inst/wfull_val_7 ),
-	.I1(\fifo_inst/Full_1 ),
-	.I2(\fifo_inst/reset_w [1]),
+LUT4 \fifo_inst/Full_s8  (
+	.I0(\fifo_inst/wfull_val_4 ),
+	.I1(\fifo_inst/wfull_val_5 ),
+	.I2(\fifo_inst/Full_1 ),
+	.I3(\fifo_inst/reset_w [1]),
 	.F(\fifo_inst/Full_1 )
 );
-defparam \fifo_inst/Full_s8 .INIT=8'h0E;
+defparam \fifo_inst/Full_s8 .INIT=16'h00F8;
 LUT3 \fifo_inst/rbin_num_next_0_s5  (
 	.I0(Empty),
 	.I1(RdEn),
@@ -160,34 +161,78 @@ LUT3 \fifo_inst/rbin_num_next_0_s5  (
 	.F(\fifo_inst/rbin_num_next [0])
 );
 defparam \fifo_inst/rbin_num_next_0_s5 .INIT=8'hB4;
-LUT3 \fifo_inst/rbin_num_next_1_s2  (
+LUT3 \fifo_inst/rbin_num_next_1_s5  (
 	.I0(\fifo_inst/rbin_num_next [0]),
 	.I1(\fifo_inst/rbin_num [0]),
 	.I2(\fifo_inst/rbin_num [1]),
 	.F(\fifo_inst/rbin_num_next [1])
 );
-defparam \fifo_inst/rbin_num_next_1_s2 .INIT=8'hB4;
+defparam \fifo_inst/rbin_num_next_1_s5 .INIT=8'hB4;
+LUT4 \fifo_inst/rbin_num_next_2_s2  (
+	.I0(\fifo_inst/rbin_num_next [0]),
+	.I1(\fifo_inst/rbin_num [0]),
+	.I2(\fifo_inst/rbin_num [1]),
+	.I3(\fifo_inst/rbin_num [2]),
+	.F(\fifo_inst/rbin_num_next [2])
+);
+defparam \fifo_inst/rbin_num_next_2_s2 .INIT=16'hBF40;
 LUT2 \fifo_inst/Equal.wbinnext_0_s3  (
-	.I0(\fifo_inst/Equal.wbin [0]),
-	.I1(\fifo_inst/n20_5 ),
+	.I0(\fifo_inst/n21_5 ),
+	.I1(\fifo_inst/Equal.wbin [0]),
 	.F(\fifo_inst/Equal.wbinnext_0_7 )
 );
 defparam \fifo_inst/Equal.wbinnext_0_s3 .INIT=4'h6;
-LUT3 \fifo_inst/Equal.wbinnext_1_s2  (
-	.I0(\fifo_inst/Equal.wbin [0]),
-	.I1(\fifo_inst/n20_5 ),
-	.I2(\fifo_inst/wptr [1]),
+LUT3 \fifo_inst/Equal.wbinnext_1_s3  (
+	.I0(\fifo_inst/n21_5 ),
+	.I1(\fifo_inst/Equal.wbin [0]),
+	.I2(\fifo_inst/Equal.wbin [1]),
 	.F(\fifo_inst/Equal.wbinnext [1])
 );
-defparam \fifo_inst/Equal.wbinnext_1_s2 .INIT=8'h78;
-LUT4 \fifo_inst/rempty_val_s4  (
-	.I0(\fifo_inst/Equal.rq2_wptr [0]),
-	.I1(\fifo_inst/Equal.rq2_wptr [1]),
-	.I2(\fifo_inst/rbin_num [1]),
-	.I3(\fifo_inst/rbin_num [0]),
-	.F(\fifo_inst/rempty_val_8 )
+defparam \fifo_inst/Equal.wbinnext_1_s3 .INIT=8'h78;
+LUT4 \fifo_inst/Equal.wbinnext_2_s2  (
+	.I0(\fifo_inst/n21_5 ),
+	.I1(\fifo_inst/Equal.wbin [0]),
+	.I2(\fifo_inst/Equal.wbin [1]),
+	.I3(\fifo_inst/wptr [2]),
+	.F(\fifo_inst/Equal.wbinnext [2])
+);
+defparam \fifo_inst/Equal.wbinnext_2_s2 .INIT=16'h7F80;
+LUT2 \fifo_inst/wfull_val_s1  (
+	.I0(\fifo_inst/wptr [2]),
+	.I1(\fifo_inst/rbin_num [2]),
+	.F(\fifo_inst/wfull_val_4 )
+);
+defparam \fifo_inst/wfull_val_s1 .INIT=4'h6;
+LUT4 \fifo_inst/wfull_val_s2  (
+	.I0(\fifo_inst/wptr [0]),
+	.I1(\fifo_inst/rptr [0]),
+	.I2(\fifo_inst/wptr [1]),
+	.I3(\fifo_inst/rptr [1]),
+	.F(\fifo_inst/wfull_val_5 )
+);
+defparam \fifo_inst/wfull_val_s2 .INIT=16'h0990;
+LUT4 \fifo_inst/n255_s2  (
+	.I0(\fifo_inst/wptr [2]),
+	.I1(\fifo_inst/rbin_num [2]),
+	.I2(\fifo_inst/reset_w [1]),
+	.I3(\fifo_inst/wfull_val_5 ),
+	.F(\fifo_inst/n255_6 )
+);
+defparam \fifo_inst/n255_s2 .INIT=16'h0600;
+LUT3 \fifo_inst/wfull_val_s3  (
+	.I0(\fifo_inst/wptr [2]),
+	.I1(\fifo_inst/rbin_num [2]),
+	.I2(\fifo_inst/wfull_val_5 ),
+	.F(\fifo_inst/wfull_val )
+);
+defparam \fifo_inst/wfull_val_s3 .INIT=8'h60;
+LUT3 \fifo_inst/rempty_val_s2  (
+	.I0(\fifo_inst/rbin_num_next [2]),
+	.I1(\fifo_inst/Equal.rq2_wptr [2]),
+	.I2(\fifo_inst/n95_3 ),
+	.F(\fifo_inst/rempty_val )
 );
-defparam \fifo_inst/rempty_val_s4 .INIT=16'h871E;
+defparam \fifo_inst/rempty_val_s2 .INIT=8'h09;
 DFFP \fifo_inst/reset_r_0_s0  (
 	.D(GND),
 	.CLK(\fifo_inst/n4_6 ),
@@ -209,6 +254,13 @@ DFFP \fifo_inst/reset_w_0_s0  (
 	.Q(\fifo_inst/reset_w [0])
 );
 defparam \fifo_inst/reset_w_0_s0 .INIT=1'b1;
+DFFC \fifo_inst/rbin_num_2_s0  (
+	.D(\fifo_inst/rbin_num_next [2]),
+	.CLK(RdClk),
+	.CLEAR(\fifo_inst/reset_r [1]),
+	.Q(\fifo_inst/rbin_num [2])
+);
+defparam \fifo_inst/rbin_num_2_s0 .INIT=1'b0;
 DFFC \fifo_inst/rbin_num_1_s0  (
 	.D(\fifo_inst/rbin_num_next [1]),
 	.CLK(RdClk),
@@ -223,6 +275,13 @@ DFFC \fifo_inst/rbin_num_0_s0  (
 	.Q(\fifo_inst/rbin_num [0])
 );
 defparam \fifo_inst/rbin_num_0_s0 .INIT=1'b0;
+DFFC \fifo_inst/Equal.rq1_wptr_2_s0  (
+	.D(\fifo_inst/wptr [2]),
+	.CLK(RdClk),
+	.CLEAR(\fifo_inst/reset_r [1]),
+	.Q(\fifo_inst/Equal.rq1_wptr [2])
+);
+defparam \fifo_inst/Equal.rq1_wptr_2_s0 .INIT=1'b0;
 DFFC \fifo_inst/Equal.rq1_wptr_1_s0  (
 	.D(\fifo_inst/wptr [1]),
 	.CLK(RdClk),
@@ -237,6 +296,13 @@ DFFC \fifo_inst/Equal.rq1_wptr_0_s0  (
 	.Q(\fifo_inst/Equal.rq1_wptr [0])
 );
 defparam \fifo_inst/Equal.rq1_wptr_0_s0 .INIT=1'b0;
+DFFC \fifo_inst/Equal.rq2_wptr_2_s0  (
+	.D(\fifo_inst/Equal.rq1_wptr [2]),
+	.CLK(RdClk),
+	.CLEAR(\fifo_inst/reset_r [1]),
+	.Q(\fifo_inst/Equal.rq2_wptr [2])
+);
+defparam \fifo_inst/Equal.rq2_wptr_2_s0 .INIT=1'b0;
 DFFC \fifo_inst/Equal.rq2_wptr_1_s0  (
 	.D(\fifo_inst/Equal.rq1_wptr [1]),
 	.CLK(RdClk),
@@ -251,6 +317,13 @@ DFFC \fifo_inst/Equal.rq2_wptr_0_s0  (
 	.Q(\fifo_inst/Equal.rq2_wptr [0])
 );
 defparam \fifo_inst/Equal.rq2_wptr_0_s0 .INIT=1'b0;
+DFFC \fifo_inst/rptr_1_s0  (
+	.D(\fifo_inst/Equal.rgraynext [1]),
+	.CLK(RdClk),
+	.CLEAR(\fifo_inst/reset_r [1]),
+	.Q(\fifo_inst/rptr [1])
+);
+defparam \fifo_inst/rptr_1_s0 .INIT=1'b0;
 DFFC \fifo_inst/rptr_0_s0  (
 	.D(\fifo_inst/Equal.rgraynext [0]),
 	.CLK(RdClk),
@@ -258,8 +331,15 @@ DFFC \fifo_inst/rptr_0_s0  (
 	.Q(\fifo_inst/rptr [0])
 );
 defparam \fifo_inst/rptr_0_s0 .INIT=1'b0;
+DFFC \fifo_inst/wptr_2_s0  (
+	.D(\fifo_inst/Equal.wbinnext [2]),
+	.CLK(WrClk),
+	.CLEAR(\fifo_inst/reset_w [1]),
+	.Q(\fifo_inst/wptr [2])
+);
+defparam \fifo_inst/wptr_2_s0 .INIT=1'b0;
 DFFC \fifo_inst/wptr_1_s0  (
-	.D(\fifo_inst/Equal.wbinnext [1]),
+	.D(\fifo_inst/Equal.wgraynext [1]),
 	.CLK(WrClk),
 	.CLEAR(\fifo_inst/reset_w [1]),
 	.Q(\fifo_inst/wptr [1])
@@ -272,6 +352,13 @@ DFFC \fifo_inst/wptr_0_s0  (
 	.Q(\fifo_inst/wptr [0])
 );
 defparam \fifo_inst/wptr_0_s0 .INIT=1'b0;
+DFFC \fifo_inst/Equal.wbin_1_s0  (
+	.D(\fifo_inst/Equal.wbinnext [1]),
+	.CLK(WrClk),
+	.CLEAR(\fifo_inst/reset_w [1]),
+	.Q(\fifo_inst/Equal.wbin [1])
+);
+defparam \fifo_inst/Equal.wbin_1_s0 .INIT=1'b0;
 DFFC \fifo_inst/Equal.wbin_0_s0  (
 	.D(\fifo_inst/Equal.wbinnext_0_7 ),
 	.CLK(WrClk),
@@ -294,16 +381,16 @@ DFFP \fifo_inst/reset_r_1_s0  (
 );
 defparam \fifo_inst/reset_r_1_s0 .INIT=1'b1;
 DFFC \fifo_inst/wfull_val1_s0  (
-	.D(\fifo_inst/wfull_val_7 ),
+	.D(\fifo_inst/wfull_val ),
 	.CLK(WrClk),
 	.CLEAR(\fifo_inst/reset_w [1]),
 	.Q(\fifo_inst/wfull_val1_2 )
 );
 defparam \fifo_inst/wfull_val1_s0 .INIT=1'b0;
 DFFP \fifo_inst/wfull_val1_s1  (
-	.D(\fifo_inst/wfull_val_7 ),
+	.D(\fifo_inst/wfull_val ),
 	.CLK(WrClk),
-	.PRESET(\fifo_inst/n217_4 ),
+	.PRESET(\fifo_inst/n255_6 ),
 	.Q(\fifo_inst/wfull_val1_3 )
 );
 defparam \fifo_inst/wfull_val1_s1 .INIT=1'b1;
@@ -317,23 +404,23 @@ defparam \fifo_inst/Full_s0 .INIT=1'b0;
 DFFP \fifo_inst/Full_s1  (
 	.D(\fifo_inst/wfull_val1 ),
 	.CLK(WrClk),
-	.PRESET(\fifo_inst/n217_4 ),
+	.PRESET(\fifo_inst/n255_6 ),
 	.Q(\fifo_inst/Full_2 )
 );
 defparam \fifo_inst/Full_s1 .INIT=1'b1;
 SDPB \fifo_inst/Equal.mem_Equal.mem_0_0_s  (
 	.CLKA(WrClk),
-	.CEA(\fifo_inst/n20_5 ),
+	.CEA(\fifo_inst/n21_5 ),
 	.RESETA(GND),
 	.CLKB(RdClk),
-	.CEB(\fifo_inst/n26_4 ),
+	.CEB(\fifo_inst/n27_4 ),
 	.RESETB(\fifo_inst/reset_r [1]),
 	.OCE(GND),
 	.BLKSELA({GND, GND, GND}),
 	.BLKSELB({GND, GND, GND}),
 	.DI({GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, Data[15:0]}),
-	.ADA({GND, GND, GND, GND, GND, GND, GND, GND, GND, \fifo_inst/Equal.wbin [0], GND, GND, VCC, VCC}),
-	.ADB({GND, GND, GND, GND, GND, GND, GND, GND, GND, \fifo_inst/rbin_num_next [0], GND, GND, GND, GND}),
+	.ADA({GND, GND, GND, GND, GND, GND, GND, GND, \fifo_inst/Equal.wbin [1:0], GND, GND, VCC, VCC}),
+	.ADB({GND, GND, GND, GND, GND, GND, GND, GND, \fifo_inst/rbin_num_next [1:0], GND, GND, GND, GND}),
 	.DO({\fifo_inst/DO [31:16], Q[15:0]})
 );
 defparam \fifo_inst/Equal.mem_Equal.mem_0_0_s .READ_MODE=1'b0;
@@ -342,6 +429,24 @@ defparam \fifo_inst/Equal.mem_Equal.mem_0_0_s .BIT_WIDTH_1=16;
 defparam \fifo_inst/Equal.mem_Equal.mem_0_0_s .RESET_MODE="ASYNC";
 defparam \fifo_inst/Equal.mem_Equal.mem_0_0_s .BLK_SEL_0=3'b000;
 defparam \fifo_inst/Equal.mem_Equal.mem_0_0_s .BLK_SEL_1=3'b000;
+ALU \fifo_inst/n94_s0  (
+	.I0(\fifo_inst/Equal.rgraynext [0]),
+	.I1(\fifo_inst/Equal.rq2_wptr [0]),
+	.I3(GND),
+	.CIN(GND),
+	.COUT(\fifo_inst/n94_3 ),
+	.SUM(\fifo_inst/n94_1_SUM )
+);
+defparam \fifo_inst/n94_s0 .ALU_MODE=3;
+ALU \fifo_inst/n95_s0  (
+	.I0(\fifo_inst/Equal.rgraynext [1]),
+	.I1(\fifo_inst/Equal.rq2_wptr [1]),
+	.I3(GND),
+	.CIN(\fifo_inst/n94_3 ),
+	.COUT(\fifo_inst/n95_3 ),
+	.SUM(\fifo_inst/n95_1_SUM )
+);
+defparam \fifo_inst/n95_s0 .ALU_MODE=3;
 INV \fifo_inst/n4_s2  (
 	.I(RdClk),
 	.O(\fifo_inst/n4_6 )

src/src/WrapFifoChain/FifoShReg16/FifoShReg16_tmp.v

@@ -4,7 +4,7 @@
 //Tool Version: V1.9.9.03 (64-bit)
 //Part Number: GW1N-UV9QN88C6/I5
 //Device: GW1N-9
-//Created Time: Thu Nov 28 11:58:21 2024
+//Created Time: Wed Dec 11 18:12:33 2024
 
 //Change the instance name and port connections to the signal names
 //--------Copy here to design--------

src/src/WrapFifoChain/FifoShReg16/temp/FIFOHS/FifoShReg16.vg

@@ -1,7 +1,7 @@
 //
 //Written by GowinSynthesis
 //Tool Version "V1.9.9.03 (64-bit)"
-//Thu Nov 28 11:58:21 2024
+//Wed Dec 11 18:12:33 2024
 
 //Source file index table:
 //file0 "\C:/Gowin/Gowin_V1.9.9.03_x64/IDE/ipcore/FIFO_HS/data/fifo_hs.v"
@@ -17,129 +17,165 @@
 `pragma protect encoding=(enctype="base64", line_length=76, bytes=256)
 `pragma protect key_keyowner="GOWIN",key_keyname="GWK2023-09",key_method="rsa"
 `pragma protect key_block
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-vn+qjfDch5LzEIV4t4Lf3yywUW4CXFBNDdMUGQ==
+EdSuByY19m9xPKm75w2J/zRa6NbzCqoA9BI9ggApZOOkGbJv5LxV3TEZZOau0Iz2+6DR9Bn5Vma5
+r5t95Z5EpSpLzzeqFp+g5uwIzZ9ViT3pOCOHwwtf5Lwr2NYvRLfSLU4Ts/6TWhm/0ttZuSQ8gioV
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+Hm2Xkf+uANO3DlQK2V3Wlb9A49ozYunCBMYfEzpRntAfXhApEYBlqiUCDq/tfFex+kPqdPmOyscR
+GR4X2fnd5l3q7jAUMgo+jjDHE8W5vdph2o9ztA==
 
-`pragma protect encoding=(enctype="base64", line_length=76, bytes=6368)
+`pragma protect encoding=(enctype="base64", line_length=76, bytes=8432)
 `pragma protect data_keyowner="default-ip-vendor"
 `pragma protect data_keyname="default-ip-key"
 `pragma protect data_method="aes128-cfb"
 `pragma protect data_block
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 `pragma protect end_protected
 module FifoShReg16 (
   Data,

src/src/WrapFifoChain/FifoShReg16/temp/FIFOHS/FifoShReg16_syn_resource.html

@@ -31,9 +31,9 @@ table td.label { width: 20%; white-space: nowrap; min-width: 20px; background-co
 </tr>
 <tr>
 <td class="label">FifoShReg16 (C:/Gowin/Gowin_V1.9.9.03_x64/IDE/ipcore/FIFO_HS/data/fifo_hs_top.v)</td>
-<td align = "center">19</td>
-<td align = "center">-</td>
-<td align = "center">18</td>
+<td align = "center">25</td>
+<td align = "center">2</td>
+<td align = "center">23</td>
 <td align = "center">-</td>
 <td align = "center">1</td>
 <td align = "center">-</td>

src/src/WrapFifoChain/FifoShReg16/temp/FIFOHS/FifoShReg16_syn_rsc.xml

@@ -1,2 +1,2 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<Module name="FifoShReg16" Register="19" Lut="18" Bsram="1" T_Register="19(19)" T_Lut="18(18)" T_Bsram="1(1)"/>
+<Module name="FifoShReg16" Register="25" Alu="2" Lut="23" Bsram="1" T_Register="25(25)" T_Alu="2(2)" T_Lut="23(23)" T_Bsram="1(1)"/>

src/src/WrapFifoChain/FifoShReg16/temp/FIFOHS/FifoShReg16_tmp.v

@@ -4,7 +4,7 @@
 //Tool Version: V1.9.9.03 (64-bit)
 //Part Number: GW1N-UV9QN88C6/I5
 //Device: GW1N-9
-//Created Time: Thu Nov 28 11:58:21 2024
+//Created Time: Wed Dec 11 18:12:33 2024
 
 //Change the instance name and port connections to the signal names
 //--------Copy here to design--------

src/src/WrapFifoChain/FifoShReg16/temp/FIFOHS/fifo_parameter.v

@@ -1,6 +1,6 @@
-parameter WDEPTH = 2;
-parameter ASIZE = 1;
+parameter WDEPTH = 4;
+parameter ASIZE = 2;
 parameter WDSIZE = 16;
-parameter RDEPTH = 2;
-parameter RASIZE = 1;
+parameter RDEPTH = 4;
+parameter RASIZE = 2;
 parameter RDSIZE = 16;

src/src/WrapFifoChain/FifoShReg8/FifoShReg8.ipc

@@ -25,11 +25,11 @@ OutputRegistersSelected=false
 REG=false
 ReadDataNum=false
 ReadDataWidth=8
-ReadDepth=2
+ReadDepth=4
 ResetSynchronization=true
 SSRAM=false
 StandardFIFO=false
 Synthesis_tool=GowinSynthesis
 WriteDataNum=false
 WriteDataWidth=8
-WriteDepth=2
+WriteDepth=4

src/src/WrapFifoChain/FifoShReg8/FifoShReg8.v

@@ -1,7 +1,7 @@
 //
 //Written by GowinSynthesis
 //Tool Version "V1.9.9.03 (64-bit)"
-//Thu Nov 28 11:57:53 2024
+//Wed Dec 11 18:11:52 2024
 
 //Source file index table:
 //file0 "\C:/Gowin/Gowin_V1.9.9.03_x64/IDE/ipcore/FIFO_HS/data/fifo_hs.v"
@@ -17,130 +17,166 @@
 `pragma protect encoding=(enctype="base64", line_length=76, bytes=256)
 `pragma protect key_keyowner="GOWIN",key_keyname="GWK2023-09",key_method="rsa"
 `pragma protect key_block
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+OLpao6UIV38xaT8octF89mJf2L4h+lH6BpXlpQ==
 
-`pragma protect encoding=(enctype="base64", line_length=76, bytes=6400)
+`pragma protect encoding=(enctype="base64", line_length=76, bytes=8448)
 `pragma protect data_keyowner="default-ip-vendor"
 `pragma protect data_keyname="default-ip-key"
 `pragma protect data_method="aes128-cfb"
 `pragma protect data_block
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 `pragma protect end_protected
 module FifoShReg8 (
   Data,

src/src/WrapFifoChain/FifoShReg8/FifoShReg8.vo

@@ -2,7 +2,7 @@
 //All rights reserved.
 //File Title: Post-PnR Simulation Model file
 //Tool Version: V1.9.9.03 (64-bit)
-//Created Time: Thu Nov 28 11:57:54 2024
+//Created Time: Wed Dec 11 18:11:53 2024
 
 `timescale 100 ps/100 ps
 module FifoShReg8(
@@ -36,34 +36,39 @@ wire Reset;
 wire VCC;
 wire WrClk;
 wire WrEn;
-wire \fifo_inst/n20_5 ;
-wire \fifo_inst/n26_4 ;
-wire \fifo_inst/n177_4 ;
-wire \fifo_inst/rempty_val ;
-wire \fifo_inst/wfull_val_7 ;
+wire \fifo_inst/n21_5 ;
+wire \fifo_inst/n27_4 ;
 wire \fifo_inst/wfull_val1 ;
 wire \fifo_inst/wfull_val1_0 ;
 wire \fifo_inst/Full_1 ;
 wire \fifo_inst/Equal.wbinnext_0_7 ;
-wire \fifo_inst/rempty_val_8 ;
+wire \fifo_inst/wfull_val_4 ;
+wire \fifo_inst/wfull_val_5 ;
+wire \fifo_inst/n215_6 ;
+wire \fifo_inst/wfull_val ;
+wire \fifo_inst/rempty_val ;
 wire \fifo_inst/wfull_val1_2 ;
 wire \fifo_inst/wfull_val1_3 ;
 wire \fifo_inst/Full_1_2 ;
 wire \fifo_inst/Full_2 ;
+wire \fifo_inst/n62_1_SUM ;
+wire \fifo_inst/n62_3 ;
+wire \fifo_inst/n63_1_SUM ;
+wire \fifo_inst/n63_3 ;
 wire \fifo_inst/n4_6 ;
 wire \fifo_inst/n9_6 ;
-wire [0:0] \fifo_inst/Equal.rgraynext ;
-wire [0:0] \fifo_inst/Equal.wgraynext ;
-wire [1:0] \fifo_inst/rbin_num_next ;
-wire [1:1] \fifo_inst/Equal.wbinnext ;
+wire [1:0] \fifo_inst/Equal.rgraynext ;
+wire [1:0] \fifo_inst/Equal.wgraynext ;
+wire [2:0] \fifo_inst/rbin_num_next ;
+wire [2:1] \fifo_inst/Equal.wbinnext ;
 wire [1:0] \fifo_inst/reset_r ;
 wire [1:0] \fifo_inst/reset_w ;
-wire [1:0] \fifo_inst/rbin_num ;
-wire [1:0] \fifo_inst/Equal.rq1_wptr ;
-wire [1:0] \fifo_inst/Equal.rq2_wptr ;
-wire [0:0] \fifo_inst/rptr ;
-wire [1:0] \fifo_inst/wptr ;
-wire [0:0] \fifo_inst/Equal.wbin ;
+wire [2:0] \fifo_inst/rbin_num ;
+wire [2:0] \fifo_inst/Equal.rq1_wptr ;
+wire [2:0] \fifo_inst/Equal.rq2_wptr ;
+wire [1:0] \fifo_inst/rptr ;
+wire [2:0] \fifo_inst/wptr ;
+wire [1:0] \fifo_inst/Equal.wbin ;
 wire [31:8] \fifo_inst/DO ;
 VCC VCC_cZ (
   .V(VCC)
@@ -74,57 +79,51 @@ GND GND_cZ (
 GSR GSR (
 	.GSRI(VCC)
 );
-LUT4 \fifo_inst/n20_s1  (
+LUT4 \fifo_inst/n21_s1  (
 	.I0(\fifo_inst/Full_2 ),
 	.I1(\fifo_inst/Full_1_2 ),
 	.I2(\fifo_inst/Full_1 ),
 	.I3(WrEn),
-	.F(\fifo_inst/n20_5 )
+	.F(\fifo_inst/n21_5 )
 );
-defparam \fifo_inst/n20_s1 .INIT=16'h5300;
-LUT3 \fifo_inst/n26_s1  (
+defparam \fifo_inst/n21_s1 .INIT=16'h5300;
+LUT3 \fifo_inst/n27_s1  (
 	.I0(RdEn),
 	.I1(Empty),
 	.I2(\fifo_inst/rempty_val ),
-	.F(\fifo_inst/n26_4 )
+	.F(\fifo_inst/n27_4 )
 );
-defparam \fifo_inst/n26_s1 .INIT=8'h0E;
+defparam \fifo_inst/n27_s1 .INIT=8'h0E;
 LUT3 \fifo_inst/Equal.rgraynext_0_s0  (
-	.I0(\fifo_inst/rbin_num [0]),
-	.I1(\fifo_inst/rbin_num_next [0]),
+	.I0(\fifo_inst/rbin_num_next [0]),
+	.I1(\fifo_inst/rbin_num [0]),
 	.I2(\fifo_inst/rbin_num [1]),
 	.F(\fifo_inst/Equal.rgraynext [0])
 );
 defparam \fifo_inst/Equal.rgraynext_0_s0 .INIT=8'h1E;
+LUT4 \fifo_inst/Equal.rgraynext_1_s0  (
+	.I0(\fifo_inst/rbin_num_next [0]),
+	.I1(\fifo_inst/rbin_num [0]),
+	.I2(\fifo_inst/rbin_num [1]),
+	.I3(\fifo_inst/rbin_num [2]),
+	.F(\fifo_inst/Equal.rgraynext [1])
+);
+defparam \fifo_inst/Equal.rgraynext_1_s0 .INIT=16'h0BF4;
 LUT3 \fifo_inst/Equal.wgraynext_0_s0  (
-	.I0(\fifo_inst/Equal.wbin [0]),
-	.I1(\fifo_inst/n20_5 ),
-	.I2(\fifo_inst/wptr [1]),
+	.I0(\fifo_inst/n21_5 ),
+	.I1(\fifo_inst/Equal.wbin [0]),
+	.I2(\fifo_inst/Equal.wbin [1]),
 	.F(\fifo_inst/Equal.wgraynext [0])
 );
 defparam \fifo_inst/Equal.wgraynext_0_s0 .INIT=8'h1E;
-LUT2 \fifo_inst/n177_s1  (
-	.I0(\fifo_inst/reset_w [1]),
-	.I1(\fifo_inst/wfull_val_7 ),
-	.F(\fifo_inst/n177_4 )
-);
-defparam \fifo_inst/n177_s1 .INIT=4'h4;
-LUT4 \fifo_inst/rempty_val_s3  (
-	.I0(\fifo_inst/Equal.rq2_wptr [1]),
-	.I1(\fifo_inst/rempty_val_8 ),
-	.I2(\fifo_inst/Equal.rq2_wptr [0]),
-	.I3(\fifo_inst/rbin_num_next [0]),
-	.F(\fifo_inst/rempty_val )
-);
-defparam \fifo_inst/rempty_val_s3 .INIT=16'h4221;
-LUT4 \fifo_inst/wfull_val_s3  (
-	.I0(\fifo_inst/wptr [0]),
-	.I1(\fifo_inst/wptr [1]),
-	.I2(\fifo_inst/rbin_num [1]),
-	.I3(\fifo_inst/rptr [0]),
-	.F(\fifo_inst/wfull_val_7 )
-);
-defparam \fifo_inst/wfull_val_s3 .INIT=16'h1428;
+LUT4 \fifo_inst/Equal.wgraynext_1_s0  (
+	.I0(\fifo_inst/n21_5 ),
+	.I1(\fifo_inst/Equal.wbin [0]),
+	.I2(\fifo_inst/Equal.wbin [1]),
+	.I3(\fifo_inst/wptr [2]),
+	.F(\fifo_inst/Equal.wgraynext [1])
+);
+defparam \fifo_inst/Equal.wgraynext_1_s0 .INIT=16'h07F8;
 LUT3 \fifo_inst/wfull_val1_s9  (
 	.I0(\fifo_inst/wfull_val1_3 ),
 	.I1(\fifo_inst/wfull_val1_2 ),
@@ -132,13 +131,14 @@ LUT3 \fifo_inst/wfull_val1_s9  (
 	.F(\fifo_inst/wfull_val1 )
 );
 defparam \fifo_inst/wfull_val1_s9 .INIT=8'hAC;
-LUT3 \fifo_inst/wfull_val1_s10  (
-	.I0(\fifo_inst/wfull_val_7 ),
-	.I1(\fifo_inst/wfull_val1_0 ),
-	.I2(\fifo_inst/reset_w [1]),
+LUT4 \fifo_inst/wfull_val1_s10  (
+	.I0(\fifo_inst/wfull_val_4 ),
+	.I1(\fifo_inst/wfull_val_5 ),
+	.I2(\fifo_inst/wfull_val1_0 ),
+	.I3(\fifo_inst/reset_w [1]),
 	.F(\fifo_inst/wfull_val1_0 )
 );
-defparam \fifo_inst/wfull_val1_s10 .INIT=8'h0E;
+defparam \fifo_inst/wfull_val1_s10 .INIT=16'h00F8;
 LUT3 \fifo_inst/Full_d_s  (
 	.I0(\fifo_inst/Full_2 ),
 	.I1(\fifo_inst/Full_1_2 ),
@@ -146,13 +146,14 @@ LUT3 \fifo_inst/Full_d_s  (
 	.F(Full)
 );
 defparam \fifo_inst/Full_d_s .INIT=8'hAC;
-LUT3 \fifo_inst/Full_s8  (
-	.I0(\fifo_inst/wfull_val_7 ),
-	.I1(\fifo_inst/Full_1 ),
-	.I2(\fifo_inst/reset_w [1]),
+LUT4 \fifo_inst/Full_s8  (
+	.I0(\fifo_inst/wfull_val_4 ),
+	.I1(\fifo_inst/wfull_val_5 ),
+	.I2(\fifo_inst/Full_1 ),
+	.I3(\fifo_inst/reset_w [1]),
 	.F(\fifo_inst/Full_1 )
 );
-defparam \fifo_inst/Full_s8 .INIT=8'h0E;
+defparam \fifo_inst/Full_s8 .INIT=16'h00F8;
 LUT3 \fifo_inst/rbin_num_next_0_s5  (
 	.I0(Empty),
 	.I1(RdEn),
@@ -160,34 +161,78 @@ LUT3 \fifo_inst/rbin_num_next_0_s5  (
 	.F(\fifo_inst/rbin_num_next [0])
 );
 defparam \fifo_inst/rbin_num_next_0_s5 .INIT=8'hB4;
-LUT3 \fifo_inst/rbin_num_next_1_s2  (
+LUT3 \fifo_inst/rbin_num_next_1_s5  (
 	.I0(\fifo_inst/rbin_num_next [0]),
 	.I1(\fifo_inst/rbin_num [0]),
 	.I2(\fifo_inst/rbin_num [1]),
 	.F(\fifo_inst/rbin_num_next [1])
 );
-defparam \fifo_inst/rbin_num_next_1_s2 .INIT=8'hB4;
+defparam \fifo_inst/rbin_num_next_1_s5 .INIT=8'hB4;
+LUT4 \fifo_inst/rbin_num_next_2_s2  (
+	.I0(\fifo_inst/rbin_num_next [0]),
+	.I1(\fifo_inst/rbin_num [0]),
+	.I2(\fifo_inst/rbin_num [1]),
+	.I3(\fifo_inst/rbin_num [2]),
+	.F(\fifo_inst/rbin_num_next [2])
+);
+defparam \fifo_inst/rbin_num_next_2_s2 .INIT=16'hBF40;
 LUT2 \fifo_inst/Equal.wbinnext_0_s3  (
-	.I0(\fifo_inst/Equal.wbin [0]),
-	.I1(\fifo_inst/n20_5 ),
+	.I0(\fifo_inst/n21_5 ),
+	.I1(\fifo_inst/Equal.wbin [0]),
 	.F(\fifo_inst/Equal.wbinnext_0_7 )
 );
 defparam \fifo_inst/Equal.wbinnext_0_s3 .INIT=4'h6;
-LUT3 \fifo_inst/Equal.wbinnext_1_s2  (
-	.I0(\fifo_inst/Equal.wbin [0]),
-	.I1(\fifo_inst/n20_5 ),
-	.I2(\fifo_inst/wptr [1]),
+LUT3 \fifo_inst/Equal.wbinnext_1_s3  (
+	.I0(\fifo_inst/n21_5 ),
+	.I1(\fifo_inst/Equal.wbin [0]),
+	.I2(\fifo_inst/Equal.wbin [1]),
 	.F(\fifo_inst/Equal.wbinnext [1])
 );
-defparam \fifo_inst/Equal.wbinnext_1_s2 .INIT=8'h78;
-LUT4 \fifo_inst/rempty_val_s4  (
-	.I0(\fifo_inst/Equal.rq2_wptr [0]),
-	.I1(\fifo_inst/Equal.rq2_wptr [1]),
-	.I2(\fifo_inst/rbin_num [1]),
-	.I3(\fifo_inst/rbin_num [0]),
-	.F(\fifo_inst/rempty_val_8 )
+defparam \fifo_inst/Equal.wbinnext_1_s3 .INIT=8'h78;
+LUT4 \fifo_inst/Equal.wbinnext_2_s2  (
+	.I0(\fifo_inst/n21_5 ),
+	.I1(\fifo_inst/Equal.wbin [0]),
+	.I2(\fifo_inst/Equal.wbin [1]),
+	.I3(\fifo_inst/wptr [2]),
+	.F(\fifo_inst/Equal.wbinnext [2])
+);
+defparam \fifo_inst/Equal.wbinnext_2_s2 .INIT=16'h7F80;
+LUT2 \fifo_inst/wfull_val_s1  (
+	.I0(\fifo_inst/wptr [2]),
+	.I1(\fifo_inst/rbin_num [2]),
+	.F(\fifo_inst/wfull_val_4 )
+);
+defparam \fifo_inst/wfull_val_s1 .INIT=4'h6;
+LUT4 \fifo_inst/wfull_val_s2  (
+	.I0(\fifo_inst/wptr [0]),
+	.I1(\fifo_inst/rptr [0]),
+	.I2(\fifo_inst/wptr [1]),
+	.I3(\fifo_inst/rptr [1]),
+	.F(\fifo_inst/wfull_val_5 )
+);
+defparam \fifo_inst/wfull_val_s2 .INIT=16'h0990;
+LUT4 \fifo_inst/n215_s2  (
+	.I0(\fifo_inst/wptr [2]),
+	.I1(\fifo_inst/rbin_num [2]),
+	.I2(\fifo_inst/reset_w [1]),
+	.I3(\fifo_inst/wfull_val_5 ),
+	.F(\fifo_inst/n215_6 )
+);
+defparam \fifo_inst/n215_s2 .INIT=16'h0600;
+LUT3 \fifo_inst/wfull_val_s3  (
+	.I0(\fifo_inst/wptr [2]),
+	.I1(\fifo_inst/rbin_num [2]),
+	.I2(\fifo_inst/wfull_val_5 ),
+	.F(\fifo_inst/wfull_val )
+);
+defparam \fifo_inst/wfull_val_s3 .INIT=8'h60;
+LUT3 \fifo_inst/rempty_val_s2  (
+	.I0(\fifo_inst/rbin_num_next [2]),
+	.I1(\fifo_inst/Equal.rq2_wptr [2]),
+	.I2(\fifo_inst/n63_3 ),
+	.F(\fifo_inst/rempty_val )
 );
-defparam \fifo_inst/rempty_val_s4 .INIT=16'h871E;
+defparam \fifo_inst/rempty_val_s2 .INIT=8'h09;
 DFFP \fifo_inst/reset_r_0_s0  (
 	.D(GND),
 	.CLK(\fifo_inst/n4_6 ),
@@ -209,6 +254,13 @@ DFFP \fifo_inst/reset_w_0_s0  (
 	.Q(\fifo_inst/reset_w [0])
 );
 defparam \fifo_inst/reset_w_0_s0 .INIT=1'b1;
+DFFC \fifo_inst/rbin_num_2_s0  (
+	.D(\fifo_inst/rbin_num_next [2]),
+	.CLK(RdClk),
+	.CLEAR(\fifo_inst/reset_r [1]),
+	.Q(\fifo_inst/rbin_num [2])
+);
+defparam \fifo_inst/rbin_num_2_s0 .INIT=1'b0;
 DFFC \fifo_inst/rbin_num_1_s0  (
 	.D(\fifo_inst/rbin_num_next [1]),
 	.CLK(RdClk),
@@ -223,6 +275,13 @@ DFFC \fifo_inst/rbin_num_0_s0  (
 	.Q(\fifo_inst/rbin_num [0])
 );
 defparam \fifo_inst/rbin_num_0_s0 .INIT=1'b0;
+DFFC \fifo_inst/Equal.rq1_wptr_2_s0  (
+	.D(\fifo_inst/wptr [2]),
+	.CLK(RdClk),
+	.CLEAR(\fifo_inst/reset_r [1]),
+	.Q(\fifo_inst/Equal.rq1_wptr [2])
+);
+defparam \fifo_inst/Equal.rq1_wptr_2_s0 .INIT=1'b0;
 DFFC \fifo_inst/Equal.rq1_wptr_1_s0  (
 	.D(\fifo_inst/wptr [1]),
 	.CLK(RdClk),
@@ -237,6 +296,13 @@ DFFC \fifo_inst/Equal.rq1_wptr_0_s0  (
 	.Q(\fifo_inst/Equal.rq1_wptr [0])
 );
 defparam \fifo_inst/Equal.rq1_wptr_0_s0 .INIT=1'b0;
+DFFC \fifo_inst/Equal.rq2_wptr_2_s0  (
+	.D(\fifo_inst/Equal.rq1_wptr [2]),
+	.CLK(RdClk),
+	.CLEAR(\fifo_inst/reset_r [1]),
+	.Q(\fifo_inst/Equal.rq2_wptr [2])
+);
+defparam \fifo_inst/Equal.rq2_wptr_2_s0 .INIT=1'b0;
 DFFC \fifo_inst/Equal.rq2_wptr_1_s0  (
 	.D(\fifo_inst/Equal.rq1_wptr [1]),
 	.CLK(RdClk),
@@ -251,6 +317,13 @@ DFFC \fifo_inst/Equal.rq2_wptr_0_s0  (
 	.Q(\fifo_inst/Equal.rq2_wptr [0])
 );
 defparam \fifo_inst/Equal.rq2_wptr_0_s0 .INIT=1'b0;
+DFFC \fifo_inst/rptr_1_s0  (
+	.D(\fifo_inst/Equal.rgraynext [1]),
+	.CLK(RdClk),
+	.CLEAR(\fifo_inst/reset_r [1]),
+	.Q(\fifo_inst/rptr [1])
+);
+defparam \fifo_inst/rptr_1_s0 .INIT=1'b0;
 DFFC \fifo_inst/rptr_0_s0  (
 	.D(\fifo_inst/Equal.rgraynext [0]),
 	.CLK(RdClk),
@@ -258,8 +331,15 @@ DFFC \fifo_inst/rptr_0_s0  (
 	.Q(\fifo_inst/rptr [0])
 );
 defparam \fifo_inst/rptr_0_s0 .INIT=1'b0;
+DFFC \fifo_inst/wptr_2_s0  (
+	.D(\fifo_inst/Equal.wbinnext [2]),
+	.CLK(WrClk),
+	.CLEAR(\fifo_inst/reset_w [1]),
+	.Q(\fifo_inst/wptr [2])
+);
+defparam \fifo_inst/wptr_2_s0 .INIT=1'b0;
 DFFC \fifo_inst/wptr_1_s0  (
-	.D(\fifo_inst/Equal.wbinnext [1]),
+	.D(\fifo_inst/Equal.wgraynext [1]),
 	.CLK(WrClk),
 	.CLEAR(\fifo_inst/reset_w [1]),
 	.Q(\fifo_inst/wptr [1])
@@ -272,6 +352,13 @@ DFFC \fifo_inst/wptr_0_s0  (
 	.Q(\fifo_inst/wptr [0])
 );
 defparam \fifo_inst/wptr_0_s0 .INIT=1'b0;
+DFFC \fifo_inst/Equal.wbin_1_s0  (
+	.D(\fifo_inst/Equal.wbinnext [1]),
+	.CLK(WrClk),
+	.CLEAR(\fifo_inst/reset_w [1]),
+	.Q(\fifo_inst/Equal.wbin [1])
+);
+defparam \fifo_inst/Equal.wbin_1_s0 .INIT=1'b0;
 DFFC \fifo_inst/Equal.wbin_0_s0  (
 	.D(\fifo_inst/Equal.wbinnext_0_7 ),
 	.CLK(WrClk),
@@ -294,16 +381,16 @@ DFFP \fifo_inst/reset_r_1_s0  (
 );
 defparam \fifo_inst/reset_r_1_s0 .INIT=1'b1;
 DFFC \fifo_inst/wfull_val1_s0  (
-	.D(\fifo_inst/wfull_val_7 ),
+	.D(\fifo_inst/wfull_val ),
 	.CLK(WrClk),
 	.CLEAR(\fifo_inst/reset_w [1]),
 	.Q(\fifo_inst/wfull_val1_2 )
 );
 defparam \fifo_inst/wfull_val1_s0 .INIT=1'b0;
 DFFP \fifo_inst/wfull_val1_s1  (
-	.D(\fifo_inst/wfull_val_7 ),
+	.D(\fifo_inst/wfull_val ),
 	.CLK(WrClk),
-	.PRESET(\fifo_inst/n177_4 ),
+	.PRESET(\fifo_inst/n215_6 ),
 	.Q(\fifo_inst/wfull_val1_3 )
 );
 defparam \fifo_inst/wfull_val1_s1 .INIT=1'b1;
@@ -317,23 +404,23 @@ defparam \fifo_inst/Full_s0 .INIT=1'b0;
 DFFP \fifo_inst/Full_s1  (
 	.D(\fifo_inst/wfull_val1 ),
 	.CLK(WrClk),
-	.PRESET(\fifo_inst/n177_4 ),
+	.PRESET(\fifo_inst/n215_6 ),
 	.Q(\fifo_inst/Full_2 )
 );
 defparam \fifo_inst/Full_s1 .INIT=1'b1;
 SDPB \fifo_inst/Equal.mem_Equal.mem_0_0_s  (
 	.CLKA(WrClk),
-	.CEA(\fifo_inst/n20_5 ),
+	.CEA(\fifo_inst/n21_5 ),
 	.RESETA(GND),
 	.CLKB(RdClk),
-	.CEB(\fifo_inst/n26_4 ),
+	.CEB(\fifo_inst/n27_4 ),
 	.RESETB(\fifo_inst/reset_r [1]),
 	.OCE(GND),
 	.BLKSELA({GND, GND, GND}),
 	.BLKSELB({GND, GND, GND}),
 	.DI({GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, Data[7:0]}),
-	.ADA({GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, \fifo_inst/Equal.wbin [0], GND, GND, GND}),
-	.ADB({GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, \fifo_inst/rbin_num_next [0], GND, GND, GND}),
+	.ADA({GND, GND, GND, GND, GND, GND, GND, GND, GND, \fifo_inst/Equal.wbin [1:0], GND, GND, GND}),
+	.ADB({GND, GND, GND, GND, GND, GND, GND, GND, GND, \fifo_inst/rbin_num_next [1:0], GND, GND, GND}),
 	.DO({\fifo_inst/DO [31:8], Q[7:0]})
 );
 defparam \fifo_inst/Equal.mem_Equal.mem_0_0_s .READ_MODE=1'b0;
@@ -342,6 +429,24 @@ defparam \fifo_inst/Equal.mem_Equal.mem_0_0_s .BIT_WIDTH_1=8;
 defparam \fifo_inst/Equal.mem_Equal.mem_0_0_s .RESET_MODE="ASYNC";
 defparam \fifo_inst/Equal.mem_Equal.mem_0_0_s .BLK_SEL_0=3'b000;
 defparam \fifo_inst/Equal.mem_Equal.mem_0_0_s .BLK_SEL_1=3'b000;
+ALU \fifo_inst/n62_s0  (
+	.I0(\fifo_inst/Equal.rgraynext [0]),
+	.I1(\fifo_inst/Equal.rq2_wptr [0]),
+	.I3(GND),
+	.CIN(GND),
+	.COUT(\fifo_inst/n62_3 ),
+	.SUM(\fifo_inst/n62_1_SUM )
+);
+defparam \fifo_inst/n62_s0 .ALU_MODE=3;
+ALU \fifo_inst/n63_s0  (
+	.I0(\fifo_inst/Equal.rgraynext [1]),
+	.I1(\fifo_inst/Equal.rq2_wptr [1]),
+	.I3(GND),
+	.CIN(\fifo_inst/n62_3 ),
+	.COUT(\fifo_inst/n63_3 ),
+	.SUM(\fifo_inst/n63_1_SUM )
+);
+defparam \fifo_inst/n63_s0 .ALU_MODE=3;
 INV \fifo_inst/n4_s2  (
 	.I(RdClk),
 	.O(\fifo_inst/n4_6 )

src/src/WrapFifoChain/FifoShReg8/FifoShReg8_tmp.v

@@ -4,7 +4,7 @@
 //Tool Version: V1.9.9.03 (64-bit)
 //Part Number: GW1N-UV9QN88C6/I5
 //Device: GW1N-9
-//Created Time: Thu Nov 28 11:57:53 2024
+//Created Time: Wed Dec 11 18:11:52 2024
 
 //Change the instance name and port connections to the signal names
 //--------Copy here to design--------

src/src/WrapFifoChain/FifoShReg8/temp/FIFOHS/FifoShReg8.vg

@@ -1,7 +1,7 @@
 //
 //Written by GowinSynthesis
 //Tool Version "V1.9.9.03 (64-bit)"
-//Thu Nov 28 11:57:53 2024
+//Wed Dec 11 18:11:52 2024
 
 //Source file index table:
 //file0 "\C:/Gowin/Gowin_V1.9.9.03_x64/IDE/ipcore/FIFO_HS/data/fifo_hs.v"
@@ -17,130 +17,166 @@
 `pragma protect encoding=(enctype="base64", line_length=76, bytes=256)
 `pragma protect key_keyowner="GOWIN",key_keyname="GWK2023-09",key_method="rsa"
 `pragma protect key_block
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+OLpao6UIV38xaT8octF89mJf2L4h+lH6BpXlpQ==
 
-`pragma protect encoding=(enctype="base64", line_length=76, bytes=6400)
+`pragma protect encoding=(enctype="base64", line_length=76, bytes=8448)
 `pragma protect data_keyowner="default-ip-vendor"
 `pragma protect data_keyname="default-ip-key"
 `pragma protect data_method="aes128-cfb"
 `pragma protect data_block
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 `pragma protect end_protected
 module FifoShReg8 (
   Data,

src/src/WrapFifoChain/FifoShReg8/temp/FIFOHS/FifoShReg8_syn_resource.html

@@ -31,9 +31,9 @@ table td.label { width: 20%; white-space: nowrap; min-width: 20px; background-co
 </tr>
 <tr>
 <td class="label">FifoShReg8 (C:/Gowin/Gowin_V1.9.9.03_x64/IDE/ipcore/FIFO_HS/data/fifo_hs_top.v)</td>
-<td align = "center">19</td>
-<td align = "center">-</td>
-<td align = "center">18</td>
+<td align = "center">25</td>
+<td align = "center">2</td>
+<td align = "center">23</td>
 <td align = "center">-</td>
 <td align = "center">1</td>
 <td align = "center">-</td>

src/src/WrapFifoChain/FifoShReg8/temp/FIFOHS/FifoShReg8_syn_rsc.xml

@@ -1,2 +1,2 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<Module name="FifoShReg8" Register="19" Lut="18" Bsram="1" T_Register="19(19)" T_Lut="18(18)" T_Bsram="1(1)"/>
+<Module name="FifoShReg8" Register="25" Alu="2" Lut="23" Bsram="1" T_Register="25(25)" T_Alu="2(2)" T_Lut="23(23)" T_Bsram="1(1)"/>

src/src/WrapFifoChain/FifoShReg8/temp/FIFOHS/FifoShReg8_tmp.v

@@ -4,7 +4,7 @@
 //Tool Version: V1.9.9.03 (64-bit)
 //Part Number: GW1N-UV9QN88C6/I5
 //Device: GW1N-9
-//Created Time: Thu Nov 28 11:57:53 2024
+//Created Time: Wed Dec 11 18:11:52 2024
 
 //Change the instance name and port connections to the signal names
 //--------Copy here to design--------

src/src/WrapFifoChain/FifoShReg8/temp/FIFOHS/fifo_parameter.v

@@ -1,6 +1,6 @@
-parameter WDEPTH = 2;
-parameter ASIZE = 1;
+parameter WDEPTH = 4;
+parameter ASIZE = 2;
 parameter WDSIZE = 8;
-parameter RDEPTH = 2;
-parameter RASIZE = 1;
+parameter RDEPTH = 4;
+parameter RASIZE = 2;
 parameter RDSIZE = 8;