Добавлен флаг FifoTxEmpty, синхронный с WrClock. Исправлена ошибка в SPIm, QuadSPIm

src/src/DataFifo/DataFifoWrapper.v

@@ -28,6 +28,7 @@ module DataFifoWrapper
 	input ToFifoTxReadVal_i,
 
 	output	ToSpiVal_o,
+	output EmptyFlagTx_o,
 	output [CmdRegWidth-1:0]	TxFifoCtrlReg_o,
 	output [CmdRegWidth-1:0]	RxFifoCtrlReg_o,
 	output	[CmdRegWidth-1:0]	ToSpiData_o,
@@ -49,14 +50,20 @@ module DataFifoWrapper
 
 	wire [7:0] rxFifoUpDnCnt;
 	wire [7:0] txFifoUpDnCnt;
+
+	(* dont_touch = "true" *) wire emptyFlagTxForDsp;
+
+	//  (* dont_touch = "true" *)wire [6:0] wrDataCnt;
+	//  (* dont_touch = "true" *)wire [6:0] rdDataCnt;
 	
 //================================================================================
 //	ASSIGNMENTS
 //================================================================================
 	assign	ToSpiVal_o	=	1'b1;
 	assign DataFromRxFifo_o = dataFromRxFifo;
+	assign EmptyFlagTx_o = emptyFlagTx;
 
-	assign TxFifoCtrlReg_o = {16'h0, txFifoUpDnCnt,5'h0,emptyFlagTx,fullFlagTx, FifoTxRst_i};
+	assign TxFifoCtrlReg_o = {16'h0, txFifoUpDnCnt,5'h0,emptyFlagTxForDsp,fullFlagTx, FifoTxRst_i};
 	assign RxFifoCtrlReg_o = {16'h0, rxFifoUpDnCnt,5'h0,emptyFlagRx,fullFlagRx, FifoRxRst_i};
 //================================================================================
 //	LOCALPARAMS
@@ -66,9 +73,7 @@ module DataFifoWrapper
 //	CODING
 //================================================================================
 
-	FifoCtrl #(
-		.STAGES		(STAGES)
-	)FifoCtrl_inst (
+	FifoCtrl FifoCtrl_inst (
 		.ToFifoTxWriteVal_i	(ToFifoVal_i),
 		.ToFifoTxReadVal_i (ToFifoTxReadVal_i),
 		.ToFifoRxWriteVal_i	(ToFifoRxWriteVal_i),
@@ -83,6 +88,7 @@ module DataFifoWrapper
 		.FifoRxRstRdPtr_i	(FifoRxRstRdPtr_i),
 		.FifoTxEmpty_i		(emptyFlagTx),
 		.FifoRxFull_i		(fullFlagRx),
+		.EmptyFlagTxForDsp_o(emptyFlagTxForDsp),
 		.FifoRxEmpty_i		(emptyFlagRx),
 		.FifoTxWrClock_i	(WrClk_i),
 		.FifoTxRdClock_i	(RdClk_i),
@@ -95,6 +101,10 @@ module DataFifoWrapper
 		.FifoRxWriteEn_o	(rxFifoWrEn),
 		.FifoRxReadEn_o		(rxFifoRdEn)
 	
+	
+	
+	
+	
 	);
 	
 	
@@ -110,7 +120,6 @@ module DataFifoWrapper
 		.dout		(ToSpiData_o),
 		.full		(fullFlagTx), 
 		.empty		(emptyFlagTx)
-	
 	);
 	
 	DataFifoRx	DataFifoRx

src/src/DataFifo/DataOutMux.v

@@ -11,6 +11,7 @@ module DataOutMux#(
     input SmcAre_i,
     input [AddrRegWidth-1:0] Addr_i,
     input [AddrRegWidth-1:0] ToRegMapAddr_i,
+    input RequestToFifo_i,
     input ToFifoVal_i,
     input [CmdRegWidth/2-1:0] DataFromRegMap_i,
     input [CmdRegWidth-1:0] DataFromRxFifo1_i,
@@ -51,7 +52,7 @@ module DataOutMux#(
     assign dataFromRxFifo[6] = DataFromRxFifo7_i;
     
     assign dataFromRegMap = DataFromRegMap_i;
-    assign AnsData_o = (ToRegMapAddr_i)?dataFromRegMap:dataFromRxFifoR;
+    assign AnsData_o = (!RequestToFifo_i)?dataFromRegMap:dataFromRxFifoR;
     
     
     always @(posedge Clk_i) begin 
@@ -67,7 +68,9 @@ module DataOutMux#(
             end
         end
     end
-  
+    
+    
+    
     always @(*) begin
         if (Rst_i) begin
             dataFromRxFifoR1 = 0;

src/src/DataFifo/FifoCtrl.v

@@ -41,6 +41,8 @@ module FifoCtrl #(
     output  [7:0] RxFifoUpDnCnt_o,
     output  [7:0] TxFifoUpDnCnt_o,
 
+    output EmptyFlagTxForDsp_o,
+
     output FifoTxWriteEn_o,
     output FifoTxReadEn_o,
     output FifoRxWriteEn_o,
@@ -59,10 +61,11 @@ module FifoCtrl #(
     (* dont_touch = "true" *)reg [7:0] rxFifoWrPtr;
     (* dont_touch = "true" *)reg [7:0] rxFifoRdPtr;
     
-    (* dont_touch = "true" *) reg [7:0] rxFifoUpDnCnt;
-    (* dont_touch = "true" *) reg [7:0] txFifoUpDnCnt;
+    (* dont_touch = "true" *)reg [7:0] rxFifoUpDnCnt;
+    (* dont_touch = "true" *)reg [7:0] txFifoUpDnCnt;
     
-    reg [1:0] readEnCnt;    
+    reg [1:0] readEnCnt;
+    reg emptyFlagTxForDsp;    
     
     
     
@@ -77,6 +80,7 @@ module FifoCtrl #(
 
     wire [7:0] rxFifoWrPtrSync;
     wire [7:0] txFifoWrPtrSync;
+    wire [7:0] txFifoRdPtrSync;
 
     wire rxFifoRstSync;
 
@@ -95,13 +99,15 @@ module FifoCtrl #(
     assign RxFifoUpDnCnt_o = rxFifoUpDnCnt;
     assign TxFifoUpDnCnt_o = txFifoUpDnCnt;
     
+
+    assign EmptyFlagTxForDsp_o = emptyFlagTxForDsp;
     
     // //================================================================================
     
 
     RxFifoPtrSync #(
         .WIDTH(8),
-        .STAGES(STAGES)
+        .STAGES(3)
     )
     rxFifoPtrSync (
         .ClkFast_i(FifoRxWrClock_i),
@@ -110,17 +116,40 @@ module FifoCtrl #(
         .RxFifoWrPtr_o(rxFifoWrPtrSync)
     );
 
+    // TxFifoPtrSync #(
+    //     .WIDTH(8),
+    //     .STAGES(3)
+    // )
+    // txFifoPtrSync (
+    //     .ClkFast_i(FifoTxWrClock_i),
+    //     .ClkSlow_i(FifoTxRdClock_i),
+    //     .TxFifoWrPtr_i(txFifoWrPtr),
+    //     .TxFifoWrPtr_o(txFifoWrPtrSync)
+    // );
+
+    // RxFifoRstSync #(
+    //     .WIDTH(1),
+    //     .STAGES(3)
+    // )
+    // rxFifoRstSync (
+    //     .ClkFast_i(FifoRxWrClock_i),
+    //     .ClkSlow_i(FifoRxRdClock_i),
+    //     .RxFifoRst_i(FifoRxRst_i),
+    //     .RxFifoRst_o(rxFifoRstSync)
+    // );
+
+
     TxFifoPtrSync #(
         .WIDTH(8),
-        .STAGES(STAGES)
+        .STAGES(3)
     )
     txFifoPtrSync (
-        .ClkFast_i(FifoTxWrClock_i),
-        .ClkSlow_i(FifoTxRdClock_i),
-        .TxFifoWrPtr_i(txFifoWrPtr),
-        .TxFifoWrPtr_o(txFifoWrPtrSync)
+        .ClkFast_i(FifoTxRdClock_i),
+        .ClkSlow_i(FifoTxWrClock_i),
+        .TxFifoWrPtr_i(txFifoRdPtr),
+        .TxFifoWrPtr_o(txFifoRdPtrSync)
     );
-    
+
     
     always @(posedge FifoRxRdClock_i) begin 
         if (FifoRxRstRdPtr_i) begin 
@@ -233,17 +262,41 @@ module FifoCtrl #(
         end
     end
     
-    always @(posedge FifoTxRdClock_i) begin 
+    always @(posedge FifoTxWrClock_i) begin 
         if (FifoTxRst_i) begin 
             txFifoUpDnCnt <= 8'h0;
         end
         else begin 
-            txFifoUpDnCnt <= txFifoWrPtrSync - txFifoRdPtr;
+            txFifoUpDnCnt <= txFifoWrPtr - txFifoRdPtrSync;
         end
     end
     
     
-    
+    // always @(posedge FifoTxWrClock_i) begin 
+    //     if (FifoTxRstWrPtr_i) begin 
+    //         emptyFlagTxForDsp <= 1'b1;
+    //     end
+    //     else begin 
+    //         if (txFifoWrPtr == txFifoRdPtr) begin 
+    //             emptyFlagTxForDsp <= 1'b1;
+    //         end
+    //         else begin 
+    //             emptyFlagTxForDsp <= 1'b0;
+    //         end
+    //     end
+    // end
+
+    always @(*) begin
+        if (txFifoUpDnCnt == 8'h0) begin
+            emptyFlagTxForDsp <= 1'b1;
+        end
+        else begin
+            emptyFlagTxForDsp <= 1'b0;
+        end
+    end
+
+
+
     
     
     // //================================================================================

src/src/MMCM/MmcmWrapper.v

@@ -1,8 +1,8 @@
 
 module MmcmWrapper 
 #(
-	parameter	SpiNum	=	7,
-   parameter	STAGES   =	3
+	parameter	SpiNum	=	7
+   parameter   STAGES   =  3
 )
 (
    input	Clk_i,
@@ -103,7 +103,10 @@ wire [SpiNum-1:0] spiClk;
    //================================================================================
    //	CODING
    //================================================================================
- 
+   
+   
+   
+      
    genvar i;
    
    generate
@@ -152,6 +155,10 @@ wire [SpiNum-1:0] spiClk;
    
    endgenerate
    
+   
+   
+   
+   
    ClkDiv ClkDiv_inst
     (
      // Clock out ports

src/src/Mux/DataMuxer.v

@@ -55,6 +55,8 @@ module DataMuxer
 	input	[CmdRegWidth-1:0]	SmcData_i,
     input	[AddrRegWidth-1:0]	SmcAddr_i,
 
+	output	RequestToFifo_o,
+
 	output	reg	ToRegMapVal_o,
 	output	reg	[CmdRegWidth-1:0]	ToRegMapData_o,
     output	reg	[AddrRegWidth-1:0]	ToRegMapAddr_o,
@@ -78,7 +80,7 @@ module DataMuxer
 //================================================================================
 //	ASSIGNMENTS
 //================================================================================
-
+	assign	RequestToFifo_o	=	requestToFifo;
 //================================================================================
 //	LOCALPARAMS
 //================================================================================

src/src/QuadSPI/QuadSPIm.v

@@ -3,6 +3,7 @@ module QuadSPIm(
     input Clk_i,
     input Rst_i,
     input Start_i,
+    input EmptyFlag_i,
     input ClockPhase_i,
     input [31:0] SpiData_i,
     input SpiDataVal_i,
@@ -83,19 +84,19 @@ module QuadSPIm(
     end
     
     
-    always @(posedge Clk_i) begin 
-        if (Rst_i) begin 
-            trCnt <= 1'b0;
-        end
-        else begin 
-            if ( ssCnt == (ssNum + Lead_i + Lag_i)) begin 
-                trCnt <= trCnt + 1'b1;
-            end
-            else if (oldDataFlag) begin 
-                trCnt <= 1'b0;
-            end
-        end
-    end
+    // always @(posedge Clk_i) begin 
+    //     if (Rst_i) begin 
+    //         trCnt <= 1'b0;
+    //     end
+    //     else begin 
+    //         if ( ssCnt == (ssNum + Lead_i + Lag_i)) begin 
+    //             trCnt <= trCnt + 1'b1;
+    //         end
+    //         else if (oldDataFlag) begin 
+    //             trCnt <= 1'b0;
+    //         end
+    //     end
+    // end
     
     
     
@@ -348,7 +349,7 @@ module QuadSPIm(
                         Mosi0_i = (!ss&& (ssCnt <= ssNum+Lag_i && ssCnt > Lag_i))? (mosiReg0[5]):1'b0;
                         Mosi1_i = (!ss&& (ssCnt <= ssNum+Lag_i && ssCnt > Lag_i))? (mosiReg1[5]):1'b0;
                         Mosi2_i = (!ss&& (ssCnt <= ssNum+Lag_i && ssCnt > Lag_i))? (mosiReg2[5]):1'b0;
-                        Mosi3_i = (!ss&& (ssCnt < ssNum+Lag_i && ssCnt > Lag_i))? (mosiReg3[5]):1'b0;
+                        Mosi3_i = (!ss&& (ssCnt <= ssNum+Lag_i && ssCnt > Lag_i))? (mosiReg3[5]):1'b0;
                     end
                     3 : begin
                         Mosi0_i = (!ss&& (ssCnt <= ssNum+Lag_i && ssCnt > Lag_i))? (mosiReg0[7]):1'b0;
@@ -458,7 +459,7 @@ module QuadSPIm(
             oldDataFlag = 1'b0;
         end
         else begin 
-            if (spiDataR == SpiData_i) begin 
+            if (spiDataR == SpiData_i && (SpiData_i != 0) || EmptyFlag_i ) begin 
                 oldDataFlag = 1'b1;
             end
             else begin 
@@ -474,7 +475,7 @@ module QuadSPIm(
             startFlag = 1'b0;
         end
         else begin 
-            if (Start_i&& !stopFlag && SpiData_i != 0 && !oldDataFlag ) begin 
+            if (Start_i && !stopFlag && !EmptyFlag_i  && !oldDataFlag ) begin 
                 startFlag = 1'b1;
             end
             else begin 

src/src/QuadSPI/QuadSPIs.v

@@ -10,7 +10,7 @@ module QuadSPIs (
     input Mosi3_i,
 
     input [1:0] WidthSel_i,
-    input SelSt_i,
+    input SELST_i,
     input EndianSel_i,
    
 
@@ -67,7 +67,7 @@ always @(*) begin
         shiftReg2M = 8'h0;
     end
     else begin
-        if (EndianSel_i) begin  
+        if (!EndianSel_i) begin  
             case(WidthSel_i)  
                  0: begin 
                     addrRegM   = addrReg  [1:0];
@@ -132,8 +132,8 @@ always @(posedge Clk_i) begin
         Data_o <= 24'h0;
     end
     else begin
-        if (EndianSel_i) begin 
-            if (SelSt_i) begin  
+        if (!EndianSel_i) begin 
+            if (SELST_i) begin  
                 if (ssReg && !ssRegR) begin 
                     Data_o <= {shiftReg0M, shiftReg1M, shiftReg2M};
                 end
@@ -145,7 +145,7 @@ always @(posedge Clk_i) begin
             end
         end
         else begin 
-            if (SelSt_i) begin  
+            if (SELST_i) begin  
                 if (ssReg && !ssRegR) begin 
                     Data_o <= {shiftReg2M, shiftReg1M, shiftReg0M};
                 end
@@ -164,7 +164,7 @@ always @(posedge Clk_i) begin
         Addr_o <= 8'h0;
     end
     else begin
-        if (SelSt_i) begin 
+        if (SELST_i) begin 
             if (ssReg && !ssRegR) begin 
                 Addr_o <= addrRegM;
             end
@@ -185,7 +185,7 @@ always @(posedge Sck_i) begin
         shiftReg0 <= 8'h0;
     end
     else begin
-        if (SelSt_i) begin   
+        if (SELST_i) begin   
             if (!Ss_i) begin 
                 shiftReg0 <= {shiftReg0[6:0], Mosi1_i};
             end
@@ -210,7 +210,7 @@ always @(posedge Sck_i ) begin
         shiftReg1 <= 8'h0;
     end
     else begin
-        if (SelSt_i) begin   
+        if (SELST_i) begin   
             if (!Ss_i) begin 
                 shiftReg1 <= {shiftReg1[6:0], Mosi2_i};
             end
@@ -235,7 +235,7 @@ always @(posedge Sck_i ) begin
         shiftReg2 <= 8'h0;
     end
     else begin
-        if (SelSt_i) begin   
+        if (SELST_i) begin   
             if (!Ss_i) begin 
                 shiftReg2 <= {shiftReg2[6:0], Mosi3_i};
             end
@@ -260,7 +260,7 @@ always @(posedge Sck_i or posedge Rst_i ) begin
         addrReg <= 8'h0;
     end
     else begin
-        if (SelSt_i) begin 
+        if (SELST_i) begin 
             if (!Ss_i) begin 
                 addrReg <={addrReg[6:0], Mosi0_i};
             end
@@ -284,7 +284,7 @@ always @(posedge Sck_i or posedge Rst_i) begin
         addrRegLSB <= 8'h0;
     end
     else begin 
-        if (SelSt_i) begin 
+        if (SELST_i) begin 
             if (!Ss_i) begin 
                 addrRegLSB <= {Mosi3_i, addrRegLSB[7:1]};
             end
@@ -308,7 +308,7 @@ always @(posedge Sck_i or posedge Rst_i) begin
         shiftReg0LSB <= 8'h0;
     end
     else begin
-        if (SelSt_i) begin   
+        if (SELST_i) begin   
             if (!Ss_i) begin 
                 shiftReg0LSB <= {Mosi0_i, shiftReg0LSB[7:1]};
             end
@@ -332,7 +332,7 @@ always @(posedge Sck_i or posedge Rst_i) begin
         shiftReg1LSB <= 8'h0;
     end
     else begin
-        if (SelSt_i) begin   
+        if (SELST_i) begin   
             if (!Ss_i) begin 
                 shiftReg1LSB <= {Mosi1_i, shiftReg1LSB[7:1]};
             end
@@ -357,7 +357,7 @@ always @(posedge Sck_i or posedge Rst_i) begin
         shiftReg2LSB <= 8'h0;
     end
     else begin
-        if (SelSt_i) begin   
+        if (SELST_i) begin   
             if (!Ss_i) begin 
                 shiftReg2LSB <= {Mosi2_i, shiftReg2LSB[7:1]};
             end
@@ -378,7 +378,7 @@ end
 
 
 always @(posedge Clk_i) begin
-    if (SelSt_i) begin 
+    if (SELST_i) begin 
         if (ssReg && !ssRegR) begin 
             Val_o <= 1'b1;
         end

src/src/SpiR/SPIm.v

@@ -2,6 +2,7 @@ module SPIm (
     input Clk_i,
     input Rst_i,
     input Start_i,
+    input EmptyFlag_i,
     input ClockPhase_i,
     input [31:0] SpiData_i,
     input SelSt_i,
@@ -99,7 +100,7 @@ module SPIm (
             oldDataFlag = 1'b0;
         end
         else begin 
-            if (spiDataR == SpiData_i) begin 
+            if (spiDataR == SpiData_i && (SpiData_i != 0) || EmptyFlag_i) begin 
                 oldDataFlag = 1'b1;
             end
             else begin 
@@ -418,7 +419,7 @@ module SPIm (
             startFlag = 1'b0;
         end
         else begin 
-            if (Start_i&& !stopFlag && SpiData_i != 0 && !oldDataFlag ) begin 
+            if (Start_i && !stopFlag && !EmptyFlag_i  && !oldDataFlag  ) begin 
                 startFlag = 1'b1;
             end
             else begin 

src/src/Top/S5443_3Top.v

@@ -24,8 +24,8 @@ module S5443_3Top
 #(
     parameter CmdRegWidth = 32,
     parameter AddrRegWidth = 12,
-    parameter STAGES = 2,
-    parameter SpiNum = 7
+    parameter STAGES = 3,
+    parameter SpiNum = 1
 
 )
 (
@@ -279,6 +279,12 @@ module S5443_3Top
     
     wire smcValComb; 
     wire	[CmdRegWidth/2-1:0]	ansData;
+
+    wire requestToFifo;
+
+    wire [SpiNum-1: 0] emptyFlagTx;
+
+    wire [SpiNum-1:0] spiEn;
     //================================================================================
     //  ASSIGNMENTS
     //================================================================================
@@ -294,20 +300,41 @@ module S5443_3Top
     assign Mosi1_io[6] =(SpiDir_o[6])?mosi1[6]:1'bz;
     assign Mosi2_o = mosi2;
     assign Mosi3_o = mosi3;
-    assign Ss_o[0] = (assel[0])? ((chipSelFpga[0])? ssMuxed[0]:~ssMuxed[0]):chipSelFpga[0];
-    assign Ss_o[1] = (assel[1])? ((chipSelFpga[1])? ssMuxed[1]:~ssMuxed[1]):chipSelFpga[1];
-    assign Ss_o[2] = (assel[2])? ((chipSelFpga[2])? ssMuxed[2]:~ssMuxed[2]):chipSelFpga[2];
-    assign Ss_o[3] = (assel[3])? ((chipSelFpga[3])? ssMuxed[3]:~ssMuxed[3]):chipSelFpga[3];
-    assign Ss_o[4] = (assel[4])? ((chipSelFpga[4])? ssMuxed[4]:~ssMuxed[4]):chipSelFpga[4];
-    assign Ss_o[5] = (assel[5])? ((chipSelFpga[5])? ssMuxed[5]:~ssMuxed[5]):chipSelFpga[5];
-    assign Ss_o[6] = (assel[6])? ((chipSelFpga[6])? ssMuxed[6]:~ssMuxed[6]):chipSelFpga[6];
-    assign SsFlash_o[0] = (assel[0])?(chipSelFlash[0]? ssMuxed[0]:~ssMuxed[0]):chipSelFlash[0];
-    assign SsFlash_o[1] = (assel[1])?(chipSelFlash[1]? ssMuxed[1]:~ssMuxed[1]):chipSelFlash[1];
-    assign SsFlash_o[2] = (assel[2])?(chipSelFlash[2]? ssMuxed[2]:~ssMuxed[2]):chipSelFlash[2];
-    assign SsFlash_o[3] = (assel[3])?(chipSelFlash[3]? ssMuxed[3]:~ssMuxed[3]):chipSelFlash[3];
-    assign SsFlash_o[4] = (assel[4])?(chipSelFlash[4]? ssMuxed[4]:~ssMuxed[4]):chipSelFlash[4];
-    assign SsFlash_o[5] = (assel[5])?(chipSelFlash[5]? ssMuxed[5]:~ssMuxed[5]):chipSelFlash[5];
-    assign SsFlash_o[6] = (assel[6])?(chipSelFlash[6]? ssMuxed[6]:~ssMuxed[6]):chipSelFlash[6];
+    // assign Ss_o[0] = (assel[0])? ((chipSelFpga[0])? ssMuxed[0]:~ssMuxed[0]):chipSelFpga[0];
+    // assign Ss_o[1] = (assel[1])? ((chipSelFpga[1])? ssMuxed[1]:~ssMuxed[1]):chipSelFpga[1];
+    // assign Ss_o[2] = (assel[2])? ((chipSelFpga[2])? ssMuxed[2]:~ssMuxed[2]):chipSelFpga[2];
+    // assign Ss_o[3] = (assel[3])? ((chipSelFpga[3])? ssMuxed[3]:~ssMuxed[3]):chipSelFpga[3];
+    // assign Ss_o[4] = (assel[4])? ((chipSelFpga[4])? ssMuxed[4]:~ssMuxed[4]):chipSelFpga[4];
+    // assign Ss_o[5] = (assel[5])? ((chipSelFpga[5])? ssMuxed[5]:~ssMuxed[5]):chipSelFpga[5];
+    // assign Ss_o[6] = (assel[6])? ((chipSelFpga[6])? ssMuxed[6]:~ssMuxed[6]):chipSelFpga[6];
+
+    assign Ss_o[0] = (assel[0]) ? ssMuxed[0] : chipSelFpga[0];
+    assign Ss_o[1] = (assel[1]) ? ssMuxed[1] : chipSelFpga[1];
+    assign Ss_o[2] = (assel[2]) ? ssMuxed[2] : chipSelFpga[2];
+    assign Ss_o[3] = (assel[3]) ? ssMuxed[3] : chipSelFpga[3];
+    assign Ss_o[4] = (assel[4]) ? ssMuxed[4] : chipSelFpga[4];
+    assign Ss_o[5] = (assel[5]) ? ssMuxed[5] : chipSelFpga[5];
+    assign Ss_o[6] = (assel[6]) ? ssMuxed[6] : chipSelFpga[6];
+
+
+    // assign SsFlash_o[0] = (assel[0])?(chipSelFlash[0]? ssMuxed[0]:~ssMuxed[0]):chipSelFlash[0];
+    // assign SsFlash_o[1] = (assel[1])?(chipSelFlash[1]? ssMuxed[1]:~ssMuxed[1]):chipSelFlash[1];
+    // assign SsFlash_o[2] = (assel[2])?(chipSelFlash[2]? ssMuxed[2]:~ssMuxed[2]):chipSelFlash[2];
+    // assign SsFlash_o[3] = (assel[3])?(chipSelFlash[3]? ssMuxed[3]:~ssMuxed[3]):chipSelFlash[3];
+    // assign SsFlash_o[4] = (assel[4])?(chipSelFlash[4]? ssMuxed[4]:~ssMuxed[4]):chipSelFlash[4];
+    // assign SsFlash_o[5] = (assel[5])?(chipSelFlash[5]? ssMuxed[5]:~ssMuxed[5]):chipSelFlash[5];
+    // assign SsFlash_o[6] = (assel[6])?(chipSelFlash[6]? ssMuxed[6]:~ssMuxed[6]):chipSelFlash[6];
+
+    assign SsFlash_o[0] = (assel[0]) ? ssMuxed[0] : chipSelFlash[0];
+    assign SsFlash_o[1] = (assel[1]) ? ssMuxed[1] : chipSelFlash[1];
+    assign SsFlash_o[2] = (assel[2]) ? ssMuxed[2] : chipSelFlash[2];
+    assign SsFlash_o[3] = (assel[3]) ? ssMuxed[3] : chipSelFlash[3];
+    assign SsFlash_o[4] = (assel[4]) ? ssMuxed[4] : chipSelFlash[4];
+    assign SsFlash_o[5] = (assel[5]) ? ssMuxed[5] : chipSelFlash[5];
+    assign SsFlash_o[6] = (assel[6]) ? ssMuxed[6] : chipSelFlash[6];
+
+
+
     assign Sck_o = sckMuxed;
     
     assign widthSel[0] = spi0CtrlRR[6:5];
@@ -317,6 +344,15 @@ module S5443_3Top
     assign widthSel[4] = spi4CtrlRR[6:5];
     assign widthSel[5] = spi5CtrlRR[6:5];
     assign widthSel[6] = spi6CtrlRR[6:5];
+
+    assign spiEn[0] = spi0CtrlRR[0];
+    assign spiEn[1] = spi1CtrlRR[0];
+    assign spiEn[2] = spi2CtrlRR[0];
+    assign spiEn[3] = spi3CtrlRR[0];
+    assign spiEn[4] = spi4CtrlRR[0];
+    assign spiEn[5] = spi5CtrlRR[0];
+    assign spiEn[6] = spi6CtrlRR[0];
+
     
     assign spiMode[0] = spi0CtrlRR[7];
     assign spiMode[1] = spi1CtrlRR[7];
@@ -578,6 +614,7 @@ module S5443_3Top
         .Clk_i(gclk),
         .Addr_i(addrExt),
         .ToRegMapAddr_i(toRegMapAddr),
+        .RequestToFifo_i(requestToFifo),
         .FifoRxRst_i(fifoRxRstRdPtr[0]),
         .DataFromRegMap_i(ansData),
         .SmcAre_i(SmcAre_i),
@@ -606,7 +643,7 @@ module S5443_3Top
     	.SmcVal_i(smcValComb),
     	.SmcData_i(SmcData_io),
         .SmcAddr_i(addrExt),
-    
+        .RequestToFifo_o(requestToFifo),
     	.ToRegMapVal_o(toRegMapVal),
     	.ToRegMapData_o(toRegMapData),
         .ToRegMapAddr_o(toRegMapAddr),
@@ -872,6 +909,7 @@ module S5443_3Top
 
     			.TxFifoCtrlReg_o(txFifoCtrlReg[i]),
                 .RxFifoCtrlReg_o(rxFifoCtrlReg[i]),
+                .EmptyFlagTx_o(emptyFlagTx[i]),
     			.ToSpiVal_o(toSpiVal[i]),
                 .DataFromRxFifo_o(dataFromRxFifo[i]),
     			.ToSpiData_o(toSpiData[i])
@@ -880,7 +918,8 @@ module S5443_3Top
             SPIm SPIm_inst (
                 .Clk_i(spiClkBus[i]),
                 .Start_i(spiTxEnSync[i]),
-                .Rst_i(initRstGen[i]| spiMode[i]),
+                .Rst_i(initRstGen[i]| spiMode[i] | !spiEn[i]),
+                .EmptyFlag_i(emptyFlagTx[i]),
                 .SpiData_i(toSpiData[i]),
                 .Sck_o(sckR[i]),
                 .Ss_o(ssR[i]),
@@ -912,7 +951,8 @@ module S5443_3Top
             QuadSPIm QuadSPIm_inst (
                 .Clk_i(spiClkBus[i]),
                 .Start_i(spiTxEnSync[i]),
-                .Rst_i(initRstGen[i]| !spiMode[i]),
+                .Rst_i(initRstGen[i]| !spiMode[i] | !spiEn[i]),
+                .EmptyFlag_i(emptyFlagTx[i]),
     			.SpiDataVal_i(toSpiVal),
                 .SpiData_i(toSpiData[i]),
                 .Sck_o(sckQ[i]),