Repo init

script/recreate.tcl

@@ -0,0 +1,775 @@
+#*****************************************************************************************
+# Vivado (TM) v2020.2 (64-bit)
+#
+# recreate.tcl: Tcl script for re-creating project 'S5443v3'
+#
+# Generated by Vivado on Tue Feb 13 12:12:33 +0700 2024
+# IP Build 3064653 on Wed Nov 18 14:17:31 MST 2020
+#
+# This file contains the Vivado Tcl commands for re-creating the project to the state*
+# when this script was generated. In order to re-create the project, please source this
+# file in the Vivado Tcl Shell.
+#
+# * Note that the runs in the created project will be configured the same way as the
+#   original project, however they will not be launched automatically. To regenerate the
+#   run results please launch the synthesis/implementation runs as needed.
+#
+#*****************************************************************************************
+# NOTE: In order to use this script for source control purposes, please make sure that the
+#       following files are added to the source control system:-
+#
+# 1. This project restoration tcl script (recreate.tcl) that was generated.
+#
+# 2. The following source(s) files that were local or imported into the original project.
+#    (Please see the '$orig_proj_dir' and '$origin_dir' variable setting below at the start of the script)
+#
+#
+# 3. The following remote source files that were added to the original project:-
+#
+#    "C:/S5443v3/src/src/CDC/CDC.v"
+#    "C:/S5443v3/src/src/MMCM/ClkCh.v"
+#    "C:/S5443v3/src/src/MMCM/ClkDivSync.v"
+#    "C:/S5443v3/src/src/MMCM/ClkGen.v"
+#    "C:/S5443v3/src/src/MMCM/ClkOutMMCM.v"
+#    "C:/S5443v3/src/src/DataFifo/DataFifoWrapper.v"
+#    "C:/S5443v3/src/src/Mux/DataMuxer.v"
+#    "C:/S5443v3/src/src/DataFifo/DataOutMux.v"
+#    "C:/S5443v3/src/src/DataFifo/FifoCtrl.v"
+#    "C:/S5443v3/src/src/InitRst/InitRst.v"
+#    "C:/S5443v3/src/src/MMCM/MmcmWrapper.v"
+#    "C:/S5443v3/src/src/QuadSPI/QuadSPIm.v"
+#    "C:/S5443v3/src/src/RegMap/RegMap.v"
+#    "C:/S5443v3/src/src/DataFifo/RxFifoPtrSync.v"
+#    "C:/S5443v3/src/src/SpiR/SPIm.v"
+#    "C:/S5443v3/src/src/SpiR/SPIs.v"
+#    "C:/S5443v3/src/src/CDC/Sync1bit.v"
+#    "C:/S5443v3/src/src/DataFifo/TxFifoPtrsync.v"
+#    "C:/S5443v3/src/src/Top/S5443_3Top.v"
+#    "C:/S5443v3/src/src/DataFifo/DataMuxer � �����.v"
+#    "C:/S5443v3/src/src/QuadSPI/QuadSPIs.v"
+#    "C:/S5443v3/src/src/DataFifo/RxFifoRstSync.v"
+#    "C:/S5443v3/src/constr/S5443_3.xdc"
+#
+#*****************************************************************************************
+
+# Check file required for this script exists
+proc checkRequiredFiles { origin_dir} {
+  set status true
+  foreach ifile $files {
+    if { ![file isfile $ifile] } {
+      puts " Could not find local file $ifile "
+      set status false
+    }
+  }
+
+  set files [list \
+   "C:/S5443v3/src/src/CDC/CDC.v" \
+   "C:/S5443v3/src/src/MMCM/ClkCh.v" \
+   "C:/S5443v3/src/src/MMCM/ClkDivSync.v" \
+   "C:/S5443v3/src/src/MMCM/ClkGen.v" \
+   "C:/S5443v3/src/src/MMCM/ClkOutMMCM.v" \
+   "C:/S5443v3/src/src/DataFifo/DataFifoWrapper.v" \
+   "C:/S5443v3/src/src/Mux/DataMuxer.v" \
+   "C:/S5443v3/src/src/DataFifo/DataOutMux.v" \
+   "C:/S5443v3/src/src/DataFifo/FifoCtrl.v" \
+   "C:/S5443v3/src/src/InitRst/InitRst.v" \
+   "C:/S5443v3/src/src/MMCM/MmcmWrapper.v" \
+   "C:/S5443v3/src/src/QuadSPI/QuadSPIm.v" \
+   "C:/S5443v3/src/src/RegMap/RegMap.v" \
+   "C:/S5443v3/src/src/DataFifo/RxFifoPtrSync.v" \
+   "C:/S5443v3/src/src/SpiR/SPIm.v" \
+   "C:/S5443v3/src/src/SpiR/SPIs.v" \
+   "C:/S5443v3/src/src/CDC/Sync1bit.v" \
+   "C:/S5443v3/src/src/DataFifo/TxFifoPtrsync.v" \
+   "C:/S5443v3/src/src/Top/S5443_3Top.v" \
+   "C:/S5443v3/src/src/DataFifo/DataMuxer � �����.v" \
+   "C:/S5443v3/src/src/QuadSPI/QuadSPIs.v" \
+   "C:/S5443v3/src/src/DataFifo/RxFifoRstSync.v" \
+   "C:/S5443v3/src/constr/S5443_3.xdc" \
+  ]
+  foreach ifile $files {
+    if { ![file isfile $ifile] } {
+      puts " Could not find remote file $ifile "
+      set status false
+    }
+  }
+
+  return $status
+}
+# Set the reference directory for source file relative paths (by default the value is script directory path)
+set origin_dir "C:/"
+
+# Use origin directory path location variable, if specified in the tcl shell
+if { [info exists ::origin_dir_loc] } {
+  set origin_dir $::origin_dir_loc
+}
+
+# Set the project name
+set _xil_proj_name_ "S5443v3"
+
+# Use project name variable, if specified in the tcl shell
+if { [info exists ::user_project_name] } {
+  set _xil_proj_name_ $::user_project_name
+}
+
+variable script_file
+set script_file "recreate.tcl"
+
+# Help information for this script
+proc print_help {} {
+  variable script_file
+  puts "\nDescription:"
+  puts "Recreate a Vivado project from this script. The created project will be"
+  puts "functionally equivalent to the original project for which this script was"
+  puts "generated. The script contains commands for creating a project, filesets,"
+  puts "runs, adding/importing sources and setting properties on various objects.\n"
+  puts "Syntax:"
+  puts "$script_file"
+  puts "$script_file -tclargs \[--origin_dir <path>\]"
+  puts "$script_file -tclargs \[--project_name <name>\]"
+  puts "$script_file -tclargs \[--help\]\n"
+  puts "Usage:"
+  puts "Name                   Description"
+  puts "-------------------------------------------------------------------------"
+  puts "\[--origin_dir <path>\]  Determine source file paths wrt this path. Default"
+  puts "                       origin_dir path value is \".\", otherwise, the value"
+  puts "                       that was set with the \"-paths_relative_to\" switch"
+  puts "                       when this script was generated.\n"
+  puts "\[--project_name <name>\] Create project with the specified name. Default"
+  puts "                       name is the name of the project from where this"
+  puts "                       script was generated.\n"
+  puts "\[--help\]               Print help information for this script"
+  puts "-------------------------------------------------------------------------\n"
+  exit 0
+}
+
+if { $::argc > 0 } {
+  for {set i 0} {$i < $::argc} {incr i} {
+    set option [string trim [lindex $::argv $i]]
+    switch -regexp -- $option {
+      "--origin_dir"   { incr i; set origin_dir [lindex $::argv $i] }
+      "--project_name" { incr i; set _xil_proj_name_ [lindex $::argv $i] }
+      "--help"         { print_help }
+      default {
+        if { [regexp {^-} $option] } {
+          puts "ERROR: Unknown option '$option' specified, please type '$script_file -tclargs --help' for usage info.\n"
+          return 1
+        }
+      }
+    }
+  }
+}
+
+# Set the directory path for the original project from where this script was exported
+set orig_proj_dir "[file normalize "$origin_dir/S5443v3_PROJ"]"
+
+# Check for paths and files needed for project creation
+set validate_required 0
+if { $validate_required } {
+  if { [checkRequiredFiles $origin_dir] } {
+    puts "Tcl file $script_file is valid. All files required for project creation is accesable. "
+  } else {
+    puts "Tcl file $script_file is not valid. Not all files required for project creation is accesable. "
+    return
+  }
+}
+
+# Create project
+create_project ${_xil_proj_name_} ./${_xil_proj_name_} -part xc7s25csga225-2
+
+# Set the directory path for the new project
+set proj_dir [get_property directory [current_project]]
+
+# Set project properties
+set obj [current_project]
+set_property -name "default_lib" -value "xil_defaultlib" -objects $obj
+set_property -name "enable_vhdl_2008" -value "1" -objects $obj
+set_property -name "ip_cache_permissions" -value "read write" -objects $obj
+set_property -name "ip_output_repo" -value "$proj_dir/${_xil_proj_name_}.cache/ip" -objects $obj
+set_property -name "mem.enable_memory_map_generation" -value "1" -objects $obj
+set_property -name "part" -value "xc7s25csga225-2" -objects $obj
+set_property -name "sim.central_dir" -value "$proj_dir/${_xil_proj_name_}.ip_user_files" -objects $obj
+set_property -name "sim.ip.auto_export_scripts" -value "1" -objects $obj
+set_property -name "xpm_libraries" -value "XPM_CDC XPM_MEMORY" -objects $obj
+
+# Create 'sources_1' fileset (if not found)
+if {[string equal [get_filesets -quiet sources_1] ""]} {
+  create_fileset -srcset sources_1
+}
+
+# Set 'sources_1' fileset object
+set obj [get_filesets sources_1]
+set files [list \
+ [file normalize "${origin_dir}/S5443v3/src/src/CDC/CDC.v"] \
+ [file normalize "${origin_dir}/S5443v3/src/src/MMCM/ClkCh.v"] \
+ [file normalize "${origin_dir}/S5443v3/src/src/MMCM/ClkDivSync.v"] \
+ [file normalize "${origin_dir}/S5443v3/src/src/MMCM/ClkGen.v"] \
+ [file normalize "${origin_dir}/S5443v3/src/src/MMCM/ClkOutMMCM.v"] \
+ [file normalize "${origin_dir}/S5443v3/src/src/DataFifo/DataFifoWrapper.v"] \
+ [file normalize "${origin_dir}/S5443v3/src/src/Mux/DataMuxer.v"] \
+ [file normalize "${origin_dir}/S5443v3/src/src/DataFifo/DataOutMux.v"] \
+ [file normalize "${origin_dir}/S5443v3/src/src/DataFifo/FifoCtrl.v"] \
+ [file normalize "${origin_dir}/S5443v3/src/src/InitRst/InitRst.v"] \
+ [file normalize "${origin_dir}/S5443v3/src/src/MMCM/MmcmWrapper.v"] \
+ [file normalize "${origin_dir}/S5443v3/src/src/QuadSPI/QuadSPIm.v"] \
+ [file normalize "${origin_dir}/S5443v3/src/src/RegMap/RegMap.v"] \
+ [file normalize "${origin_dir}/S5443v3/src/src/DataFifo/RxFifoPtrSync.v"] \
+ [file normalize "${origin_dir}/S5443v3/src/src/SpiR/SPIm.v"] \
+ [file normalize "${origin_dir}/S5443v3/src/src/SpiR/SPIs.v"] \
+ [file normalize "${origin_dir}/S5443v3/src/src/CDC/Sync1bit.v"] \
+ [file normalize "${origin_dir}/S5443v3/src/src/DataFifo/TxFifoPtrsync.v"] \
+ [file normalize "${origin_dir}/S5443v3/src/src/Top/S5443_3Top.v"] \
+ [file normalize "${origin_dir}/S5443v3/src/src/QuadSPI/QuadSPIs.v"] \
+ [file normalize "${origin_dir}/S5443v3/src/src/DataFifo/RxFifoRstSync.v"] \
+]
+add_files -norecurse -fileset $obj $files
+
+# Set 'sources_1' fileset file properties for remote files
+# None
+
+# Set 'sources_1' fileset file properties for local files
+# None
+
+# Set 'sources_1' fileset properties
+set obj [get_filesets sources_1]
+set_property -name "top" -value "S5443_3Top" -objects $obj
+
+# Set 'sources_1' fileset object
+set obj [get_filesets sources_1]
+
+# Set 'sources_1' fileset file properties for remote files
+# None
+
+
+
+# Set 'sources_1' fileset file properties for remote files
+# None
+
+
+# Set 'sources_1' fileset object
+set obj [get_filesets sources_1]
+
+# Set 'sources_1' fileset file properties for remote files
+# None
+
+
+
+
+# Create 'constrs_1' fileset (if not found)
+if {[string equal [get_filesets -quiet constrs_1] ""]} {
+  create_fileset -constrset constrs_1
+}
+
+# Set 'constrs_1' fileset object
+set obj [get_filesets constrs_1]
+
+# Add/Import constrs file and set constrs file properties
+set file "[file normalize "$origin_dir/S5443v3/src/constr/S5443_3.xdc"]"
+set file_added [add_files -norecurse -fileset $obj [list $file]]
+set file "$origin_dir/S5443v3/src/constr/S5443_3.xdc"
+set file [file normalize $file]
+set file_obj [get_files -of_objects [get_filesets constrs_1] [list "*$file"]]
+set_property -name "file_type" -value "XDC" -objects $file_obj
+
+# Set 'constrs_1' fileset properties
+set obj [get_filesets constrs_1]
+set_property -name "target_part" -value "xc7s25csga225-2" -objects $obj
+
+# Create 'sim_1' fileset (if not found)
+if {[string equal [get_filesets -quiet sim_1] ""]} {
+  create_fileset -simset sim_1
+}
+
+# Set 'sim_1' fileset object
+set obj [get_filesets sim_1]
+# Empty (no sources present)
+
+# Set 'sim_1' fileset properties
+set obj [get_filesets sim_1]
+set_property -name "hbs.configure_design_for_hier_access" -value "1" -objects $obj
+set_property -name "top" -value "S5443_3Top" -objects $obj
+set_property -name "top_lib" -value "xil_defaultlib" -objects $obj
+
+# Set 'utils_1' fileset object
+set obj [get_filesets utils_1]
+# Empty (no sources present)
+
+# Set 'utils_1' fileset properties
+set obj [get_filesets utils_1]
+
+# Create 'synth_1' run (if not found)
+if {[string equal [get_runs -quiet synth_1] ""]} {
+    create_run -name synth_1 -part xc7s25csga225-2 -flow {Vivado Synthesis 2020} -strategy "Vivado Synthesis Defaults" -report_strategy {No Reports} -constrset constrs_1
+} else {
+  set_property strategy "Vivado Synthesis Defaults" [get_runs synth_1]
+  set_property flow "Vivado Synthesis 2020" [get_runs synth_1]
+}
+set obj [get_runs synth_1]
+set_property set_report_strategy_name 1 $obj
+set_property report_strategy {Vivado Synthesis Default Reports} $obj
+set_property set_report_strategy_name 0 $obj
+# Create 'synth_1_synth_report_utilization_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs synth_1] synth_1_synth_report_utilization_0] "" ] } {
+  create_report_config -report_name synth_1_synth_report_utilization_0 -report_type report_utilization:1.0 -steps synth_design -runs synth_1
+}
+set obj [get_report_configs -of_objects [get_runs synth_1] synth_1_synth_report_utilization_0]
+if { $obj != "" } {
+
+}
+set obj [get_runs synth_1]
+set_property -name "part" -value "xc7s25csga225-2" -objects $obj
+set_property -name "auto_incremental_checkpoint.directory" -value "$proj_dir/project_1.srcs/utils_1/imports/synth_1" -objects $obj
+set_property -name "strategy" -value "Vivado Synthesis Defaults" -objects $obj
+set_property -name "steps.synth_design.args.flatten_hierarchy" -value "none" -objects $obj
+
+# set the current synth run
+current_run -synthesis [get_runs synth_1]
+
+# Create 'impl_1' run (if not found)
+if {[string equal [get_runs -quiet impl_1] ""]} {
+    create_run -name impl_1 -part xc7s25csga225-2 -flow {Vivado Implementation 2020} -strategy "Vivado Implementation Defaults" -report_strategy {No Reports} -constrset constrs_1 -parent_run synth_1
+} else {
+  set_property strategy "Vivado Implementation Defaults" [get_runs impl_1]
+  set_property flow "Vivado Implementation 2020" [get_runs impl_1]
+}
+set obj [get_runs impl_1]
+set_property set_report_strategy_name 1 $obj
+set_property report_strategy {Vivado Implementation Default Reports} $obj
+set_property set_report_strategy_name 0 $obj
+# Create 'impl_1_init_report_timing_summary_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_init_report_timing_summary_0] "" ] } {
+  create_report_config -report_name impl_1_init_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps init_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_init_report_timing_summary_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "0" -objects $obj
+set_property -name "options.max_paths" -value "10" -objects $obj
+
+}
+# Create 'impl_1_opt_report_drc_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_drc_0] "" ] } {
+  create_report_config -report_name impl_1_opt_report_drc_0 -report_type report_drc:1.0 -steps opt_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_drc_0]
+if { $obj != "" } {
+
+}
+# Create 'impl_1_opt_report_timing_summary_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_timing_summary_0] "" ] } {
+  create_report_config -report_name impl_1_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps opt_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_timing_summary_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "0" -objects $obj
+set_property -name "options.max_paths" -value "10" -objects $obj
+
+}
+# Create 'impl_1_power_opt_report_timing_summary_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_power_opt_report_timing_summary_0] "" ] } {
+  create_report_config -report_name impl_1_power_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps power_opt_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_power_opt_report_timing_summary_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "0" -objects $obj
+set_property -name "options.max_paths" -value "10" -objects $obj
+
+}
+# Create 'impl_1_place_report_io_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_io_0] "" ] } {
+  create_report_config -report_name impl_1_place_report_io_0 -report_type report_io:1.0 -steps place_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_io_0]
+if { $obj != "" } {
+
+}
+# Create 'impl_1_place_report_utilization_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_utilization_0] "" ] } {
+  create_report_config -report_name impl_1_place_report_utilization_0 -report_type report_utilization:1.0 -steps place_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_utilization_0]
+if { $obj != "" } {
+
+}
+# Create 'impl_1_place_report_control_sets_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_control_sets_0] "" ] } {
+  create_report_config -report_name impl_1_place_report_control_sets_0 -report_type report_control_sets:1.0 -steps place_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_control_sets_0]
+if { $obj != "" } {
+set_property -name "options.verbose" -value "1" -objects $obj
+
+}
+# Create 'impl_1_place_report_incremental_reuse_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_0] "" ] } {
+  create_report_config -report_name impl_1_place_report_incremental_reuse_0 -report_type report_incremental_reuse:1.0 -steps place_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "0" -objects $obj
+
+}
+# Create 'impl_1_place_report_incremental_reuse_1' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_1] "" ] } {
+  create_report_config -report_name impl_1_place_report_incremental_reuse_1 -report_type report_incremental_reuse:1.0 -steps place_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_1]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "0" -objects $obj
+
+}
+# Create 'impl_1_place_report_timing_summary_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_timing_summary_0] "" ] } {
+  create_report_config -report_name impl_1_place_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps place_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_timing_summary_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "0" -objects $obj
+set_property -name "options.max_paths" -value "10" -objects $obj
+
+}
+# Create 'impl_1_post_place_power_opt_report_timing_summary_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_post_place_power_opt_report_timing_summary_0] "" ] } {
+  create_report_config -report_name impl_1_post_place_power_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps post_place_power_opt_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_post_place_power_opt_report_timing_summary_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "0" -objects $obj
+set_property -name "options.max_paths" -value "10" -objects $obj
+
+}
+# Create 'impl_1_phys_opt_report_timing_summary_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_phys_opt_report_timing_summary_0] "" ] } {
+  create_report_config -report_name impl_1_phys_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps phys_opt_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_phys_opt_report_timing_summary_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "0" -objects $obj
+set_property -name "options.max_paths" -value "10" -objects $obj
+
+}
+# Create 'impl_1_route_report_drc_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_drc_0] "" ] } {
+  create_report_config -report_name impl_1_route_report_drc_0 -report_type report_drc:1.0 -steps route_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_drc_0]
+if { $obj != "" } {
+
+}
+# Create 'impl_1_route_report_methodology_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_methodology_0] "" ] } {
+  create_report_config -report_name impl_1_route_report_methodology_0 -report_type report_methodology:1.0 -steps route_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_methodology_0]
+if { $obj != "" } {
+
+}
+# Create 'impl_1_route_report_power_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_power_0] "" ] } {
+  create_report_config -report_name impl_1_route_report_power_0 -report_type report_power:1.0 -steps route_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_power_0]
+if { $obj != "" } {
+
+}
+# Create 'impl_1_route_report_route_status_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_route_status_0] "" ] } {
+  create_report_config -report_name impl_1_route_report_route_status_0 -report_type report_route_status:1.0 -steps route_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_route_status_0]
+if { $obj != "" } {
+
+}
+# Create 'impl_1_route_report_timing_summary_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_timing_summary_0] "" ] } {
+  create_report_config -report_name impl_1_route_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps route_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_timing_summary_0]
+if { $obj != "" } {
+set_property -name "options.max_paths" -value "10" -objects $obj
+
+}
+# Create 'impl_1_route_report_incremental_reuse_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_incremental_reuse_0] "" ] } {
+  create_report_config -report_name impl_1_route_report_incremental_reuse_0 -report_type report_incremental_reuse:1.0 -steps route_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_incremental_reuse_0]
+if { $obj != "" } {
+
+}
+# Create 'impl_1_route_report_clock_utilization_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_clock_utilization_0] "" ] } {
+  create_report_config -report_name impl_1_route_report_clock_utilization_0 -report_type report_clock_utilization:1.0 -steps route_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_clock_utilization_0]
+if { $obj != "" } {
+
+}
+# Create 'impl_1_route_report_bus_skew_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_bus_skew_0] "" ] } {
+  create_report_config -report_name impl_1_route_report_bus_skew_0 -report_type report_bus_skew:1.1 -steps route_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_bus_skew_0]
+if { $obj != "" } {
+set_property -name "options.warn_on_violation" -value "1" -objects $obj
+
+}
+# Create 'impl_1_post_route_phys_opt_report_timing_summary_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_timing_summary_0] "" ] } {
+  create_report_config -report_name impl_1_post_route_phys_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps post_route_phys_opt_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_timing_summary_0]
+if { $obj != "" } {
+set_property -name "options.max_paths" -value "10" -objects $obj
+set_property -name "options.warn_on_violation" -value "1" -objects $obj
+
+}
+# Create 'impl_1_post_route_phys_opt_report_bus_skew_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_bus_skew_0] "" ] } {
+  create_report_config -report_name impl_1_post_route_phys_opt_report_bus_skew_0 -report_type report_bus_skew:1.1 -steps post_route_phys_opt_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_bus_skew_0]
+if { $obj != "" } {
+set_property -name "options.warn_on_violation" -value "1" -objects $obj
+
+}
+set obj [get_runs impl_1]
+set_property -name "part" -value "xc7s25csga225-2" -objects $obj
+set_property -name "auto_incremental_checkpoint.directory" -value "$proj_dir/project_1.srcs/utils_1/imports/impl_1" -objects $obj
+set_property -name "strategy" -value "Vivado Implementation Defaults" -objects $obj
+set_property -name "steps.write_bitstream.args.bin_file" -value "1" -objects $obj
+set_property -name "steps.write_bitstream.args.readback_file" -value "0" -objects $obj
+set_property -name "steps.write_bitstream.args.verbose" -value "0" -objects $obj
+
+# set the current impl run
+current_run -implementation [get_runs impl_1]
+
+puts "INFO: Project created:${_xil_proj_name_}"
+# Create 'drc_1' gadget (if not found)
+if {[string equal [get_dashboard_gadgets  [ list "drc_1" ] ] ""]} {
+create_dashboard_gadget -name {drc_1} -type drc
+}
+set obj [get_dashboard_gadgets [ list "drc_1" ] ]
+set_property -name "reports" -value "impl_1#impl_1_route_report_drc_0" -objects $obj
+
+# Create 'methodology_1' gadget (if not found)
+if {[string equal [get_dashboard_gadgets  [ list "methodology_1" ] ] ""]} {
+create_dashboard_gadget -name {methodology_1} -type methodology
+}
+set obj [get_dashboard_gadgets [ list "methodology_1" ] ]
+set_property -name "reports" -value "impl_1#impl_1_route_report_methodology_0" -objects $obj
+
+# Create 'power_1' gadget (if not found)
+if {[string equal [get_dashboard_gadgets  [ list "power_1" ] ] ""]} {
+create_dashboard_gadget -name {power_1} -type power
+}
+set obj [get_dashboard_gadgets [ list "power_1" ] ]
+set_property -name "reports" -value "impl_1#impl_1_route_report_power_0" -objects $obj
+
+# Create 'timing_1' gadget (if not found)
+if {[string equal [get_dashboard_gadgets  [ list "timing_1" ] ] ""]} {
+create_dashboard_gadget -name {timing_1} -type timing
+}
+set obj [get_dashboard_gadgets [ list "timing_1" ] ]
+set_property -name "reports" -value "impl_1#impl_1_route_report_timing_summary_0" -objects $obj
+
+# Create 'utilization_1' gadget (if not found)
+if {[string equal [get_dashboard_gadgets  [ list "utilization_1" ] ] ""]} {
+create_dashboard_gadget -name {utilization_1} -type utilization
+}
+set obj [get_dashboard_gadgets [ list "utilization_1" ] ]
+set_property -name "reports" -value "synth_1#synth_1_synth_report_utilization_0" -objects $obj
+set_property -name "run.step" -value "synth_design" -objects $obj
+set_property -name "run.type" -value "synthesis" -objects $obj
+
+# Create 'utilization_2' gadget (if not found)
+if {[string equal [get_dashboard_gadgets  [ list "utilization_2" ] ] ""]} {
+create_dashboard_gadget -name {utilization_2} -type utilization
+}
+set obj [get_dashboard_gadgets [ list "utilization_2" ] ]
+set_property -name "reports" -value "impl_1#impl_1_place_report_utilization_0" -objects $obj
+
+move_dashboard_gadget -name {utilization_1} -row 0 -col 0
+move_dashboard_gadget -name {power_1} -row 1 -col 0
+move_dashboard_gadget -name {drc_1} -row 2 -col 0
+move_dashboard_gadget -name {timing_1} -row 0 -col 1
+move_dashboard_gadget -name {utilization_2} -row 1 -col 1
+move_dashboard_gadget -name {methodology_1} -row 2 -col 1
+
+##################################################################
+# CHECK VIVADO VERSION
+##################################################################
+
+set scripts_vivado_version 2020.2
+set current_vivado_version [version -short]
+
+if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
+  catch {common::send_msg_id "IPS_TCL-100" "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_ip_tcl to create an updated script."}
+  return 1
+}
+
+##################################################################
+# START
+##################################################################
+
+# To test this script, run the following commands from Vivado Tcl console:
+# source recreateIp.tcl
+# If there is no project opened, this script will create a
+# project, but make sure you do not have an existing project
+# <./S5443v3_PROJ/S5443v3.xpr> in the current working folder.
+
+set list_projs [get_projects -quiet]
+if { $list_projs eq "" } {
+  create_project S5443v3 S5443v3_PROJ -part xc7s25csga225-2
+  set_property target_language Verilog [current_project]
+  set_property simulator_language Verilog [current_project]
+}
+
+##################################################################
+# CHECK IPs
+##################################################################
+
+set bCheckIPs 1
+set bCheckIPsPassed 1
+if { $bCheckIPs == 1 } {
+  set list_check_ips { xilinx.com:ip:clk_wiz:6.0 xilinx.com:ip:fifo_generator:13.2 }
+  set list_ips_missing ""
+  common::send_msg_id "IPS_TCL-1001" "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ."
+
+  foreach ip_vlnv $list_check_ips {
+  set ip_obj [get_ipdefs -all $ip_vlnv]
+  if { $ip_obj eq "" } {
+    lappend list_ips_missing $ip_vlnv
+    }
+  }
+
+  if { $list_ips_missing ne "" } {
+    catch {common::send_msg_id "IPS_TCL-105" "ERROR" "The following IPs are not found in the IP Catalog:\n  $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." }
+    set bCheckIPsPassed 0
+  }
+}
+
+if { $bCheckIPsPassed != 1 } {
+  common::send_msg_id "IPS_TCL-102" "WARNING" "Will not continue with creation of design due to the error(s) above."
+  return 1
+}
+
+##################################################################
+# CREATE IP ClkDiv
+##################################################################
+
+set ClkDiv [create_ip -name clk_wiz -vendor xilinx.com -library ip -version 6.0 -module_name ClkDiv]
+
+set_property -dict { 
+  CONFIG.PRIM_IN_FREQ {123.000}
+  CONFIG.CLKIN1_JITTER_PS {81.30000000000001}
+  CONFIG.CLKOUT2_USED {true}
+  CONFIG.CLKOUT3_USED {true}
+  CONFIG.CLKOUT4_USED {true}
+  CONFIG.CLKOUT5_USED {true}
+  CONFIG.CLKOUT6_USED {true}
+  CONFIG.CLKOUT7_USED {true}
+  CONFIG.NUM_OUT_CLKS {7}
+  CONFIG.CLKOUT2_REQUESTED_OUT_FREQ {80.000}
+  CONFIG.CLKOUT3_REQUESTED_OUT_FREQ {70.000}
+  CONFIG.CLKOUT4_REQUESTED_OUT_FREQ {60.000}
+  CONFIG.CLKOUT5_REQUESTED_OUT_FREQ {50.000}
+  CONFIG.CLKOUT6_REQUESTED_OUT_FREQ {40.000}
+  CONFIG.CLKOUT7_REQUESTED_OUT_FREQ {30.000}
+  CONFIG.MMCM_DIVCLK_DIVIDE {1}
+  CONFIG.MMCM_CLKFBOUT_MULT_F {9.750}
+  CONFIG.MMCM_CLKIN1_PERIOD {8.130}
+  CONFIG.MMCM_CLKOUT0_DIVIDE_F {12.000}
+  CONFIG.MMCM_CLKOUT1_DIVIDE {15}
+  CONFIG.MMCM_CLKOUT2_DIVIDE {17}
+  CONFIG.MMCM_CLKOUT3_DIVIDE {20}
+  CONFIG.MMCM_CLKOUT4_DIVIDE {24}
+  CONFIG.MMCM_CLKOUT5_DIVIDE {30}
+  CONFIG.MMCM_CLKOUT6_DIVIDE {40}
+  CONFIG.CLKOUT1_JITTER {112.035}
+  CONFIG.CLKOUT1_PHASE_ERROR {85.478}
+  CONFIG.CLKOUT2_JITTER {116.822}
+  CONFIG.CLKOUT2_PHASE_ERROR {85.478}
+  CONFIG.CLKOUT3_JITTER {119.640}
+  CONFIG.CLKOUT3_PHASE_ERROR {85.478}
+  CONFIG.CLKOUT4_JITTER {123.604}
+  CONFIG.CLKOUT4_PHASE_ERROR {85.478}
+  CONFIG.CLKOUT5_JITTER {128.250}
+  CONFIG.CLKOUT5_PHASE_ERROR {85.478}
+  CONFIG.CLKOUT6_JITTER {134.251}
+  CONFIG.CLKOUT6_PHASE_ERROR {85.478}
+  CONFIG.CLKOUT7_JITTER {142.568}
+  CONFIG.CLKOUT7_PHASE_ERROR {85.478}
+} [get_ips ClkDiv]
+
+set_property -dict { 
+  GENERATE_SYNTH_CHECKPOINT {1}
+} $ClkDiv
+
+##################################################################
+
+##################################################################
+# CREATE IP DataFifoRx
+##################################################################
+
+set DataFifoRx [create_ip -name fifo_generator -vendor xilinx.com -library ip -version 13.2 -module_name DataFifoRx]
+
+set_property -dict { 
+  CONFIG.Fifo_Implementation {Independent_Clocks_Builtin_FIFO}
+  CONFIG.Performance_Options {First_Word_Fall_Through}
+  CONFIG.Input_Data_Width {32}
+  CONFIG.Input_Depth {512}
+  CONFIG.Output_Data_Width {32}
+  CONFIG.Output_Depth {512}
+  CONFIG.Reset_Type {Asynchronous_Reset}
+  CONFIG.Use_Dout_Reset {false}
+  CONFIG.Data_Count_Width {9}
+  CONFIG.Write_Data_Count_Width {9}
+  CONFIG.Read_Data_Count_Width {9}
+  CONFIG.Read_Clock_Frequency {123}
+  CONFIG.Write_Clock_Frequency {100}
+  CONFIG.Full_Threshold_Assert_Value {503}
+  CONFIG.Full_Threshold_Negate_Value {502}
+  CONFIG.Empty_Threshold_Assert_Value {6}
+  CONFIG.Empty_Threshold_Negate_Value {7}
+} [get_ips DataFifoRx]
+
+set_property -dict { 
+  GENERATE_SYNTH_CHECKPOINT {1}
+} $DataFifoRx
+
+##################################################################
+
+##################################################################
+# CREATE IP DataFifoTx
+##################################################################
+
+set DataFifoTx [create_ip -name fifo_generator -vendor xilinx.com -library ip -version 13.2 -module_name DataFifoTx]
+
+set_property -dict { 
+  CONFIG.Fifo_Implementation {Independent_Clocks_Builtin_FIFO}
+  CONFIG.Performance_Options {First_Word_Fall_Through}
+  CONFIG.Input_Data_Width {32}
+  CONFIG.Input_Depth {512}
+  CONFIG.Output_Data_Width {32}
+  CONFIG.Output_Depth {512}
+  CONFIG.Reset_Type {Asynchronous_Reset}
+  CONFIG.Use_Dout_Reset {false}
+  CONFIG.Valid_Flag {true}
+  CONFIG.Write_Acknowledge_Flag {true}
+  CONFIG.Data_Count_Width {9}
+  CONFIG.Write_Data_Count_Width {9}
+  CONFIG.Read_Data_Count_Width {9}
+  CONFIG.Read_Clock_Frequency {5}
+  CONFIG.Write_Clock_Frequency {123}
+  CONFIG.Full_Threshold_Assert_Value {408}
+  CONFIG.Full_Threshold_Negate_Value {407}
+  CONFIG.Empty_Threshold_Assert_Value {6}
+  CONFIG.Empty_Threshold_Negate_Value {7}
+} [get_ips DataFifoTx]
+
+set_property -dict { 
+  GENERATE_SYNTH_CHECKPOINT {1}
+} $DataFifoTx
+
+##################################################################
+

src/src/CDC/CDC.v

@@ -0,0 +1,331 @@
+module CDC #(
+    parameter WIDTH = 32,
+    parameter STAGES = 3,
+    parameter SpiNum = 7
+
+
+
+)
+(
+    input ClkFast_i,
+    input [SpiNum-1:0] ClkSlow_i,
+
+    input [WIDTH-1:0] Spi0Ctrl_i,
+    input [WIDTH-1:0] Spi0CsCtrl_i,
+    input [WIDTH-1:0] Spi0CsDelay_i,
+    input [WIDTH-1:0] Spi0TxFifoCtrl_i,
+    input [WIDTH-1:0] Spi0RxFifoCtrl_i,
+
+    input [WIDTH-1:0] Spi1Ctrl_i,
+    input [WIDTH-1:0] Spi1CsCtrl_i,
+    input [WIDTH-1:0] Spi1CsDelay_i,
+    input [WIDTH-1:0] Spi1TxFifoCtrl_i,
+    input [WIDTH-1:0] Spi1RxFifoCtrl_i,
+
+    input [WIDTH-1:0] Spi2Ctrl_i,
+    input [WIDTH-1:0] Spi2CsCtrl_i,
+    input [WIDTH-1:0] Spi2CsDelay_i,
+    input [WIDTH-1:0] Spi2TxFifoCtrl_i,
+    input [WIDTH-1:0] Spi2RxFifoCtrl_i,
+
+    input [WIDTH-1:0] Spi3Ctrl_i,
+    input [WIDTH-1:0] Spi3CsCtrl_i,
+    input [WIDTH-1:0] Spi3CsDelay_i,
+    input [WIDTH-1:0] Spi3TxFifoCtrl_i,
+    input [WIDTH-1:0] Spi3RxFifoCtrl_i,
+
+    input [WIDTH-1:0] Spi4Ctrl_i,
+    input [WIDTH-1:0] Spi4CsCtrl_i,
+    input [WIDTH-1:0] Spi4CsDelay_i,
+    input [WIDTH-1:0] Spi4TxFifoCtrl_i,
+    input [WIDTH-1:0] Spi4RxFifoCtrl_i,
+
+    input [WIDTH-1:0] Spi5Ctrl_i,
+    input [WIDTH-1:0] Spi5CsCtrl_i,
+    input [WIDTH-1:0] Spi5CsDelay_i,
+    input [WIDTH-1:0] Spi5TxFifoCtrl_i,
+    input [WIDTH-1:0] Spi5RxFifoCtrl_i,
+
+    input [WIDTH-1:0] Spi6Ctrl_i,
+    input [WIDTH-1:0] Spi6CsCtrl_i,
+    input [WIDTH-1:0] Spi6CsDelay_i,
+    input [WIDTH-1:0] Spi6TxFifoCtrl_i,
+    input [WIDTH-1:0] Spi6RxFifoCtrl_i,
+
+    output [WIDTH-1:0] Spi0Ctrl_o,
+    output [WIDTH-1:0] Spi0CsCtrl_o,
+    output [WIDTH-1:0] Spi0CsDelay_o,
+    output [WIDTH-1:0] Spi0TxFifoCtrl_o,
+    output [WIDTH-1:0] Spi0RxFifoCtrl_o,
+
+    output [WIDTH-1:0] Spi1Ctrl_o,
+    output [WIDTH-1:0] Spi1CsCtrl_o,
+    output [WIDTH-1:0] Spi1CsDelay_o,
+    output [WIDTH-1:0] Spi1TxFifoCtrl_o,
+    output [WIDTH-1:0] Spi1RxFifoCtrl_o,
+
+    output [WIDTH-1:0] Spi2Ctrl_o,
+    output [WIDTH-1:0] Spi2CsCtrl_o,
+    output [WIDTH-1:0] Spi2CsDelay_o,
+    output [WIDTH-1:0] Spi2TxFifoCtrl_o,
+    output [WIDTH-1:0] Spi2RxFifoCtrl_o,
+
+    output [WIDTH-1:0] Spi3Ctrl_o,
+    output [WIDTH-1:0] Spi3CsCtrl_o,
+    output [WIDTH-1:0] Spi3CsDelay_o,
+    output [WIDTH-1:0] Spi3TxFifoCtrl_o,
+    output [WIDTH-1:0] Spi3RxFifoCtrl_o,
+
+    output [WIDTH-1:0] Spi4Ctrl_o,
+    output [WIDTH-1:0] Spi4CsCtrl_o,
+    output [WIDTH-1:0] Spi4CsDelay_o,
+    output [WIDTH-1:0] Spi4TxFifoCtrl_o,
+    output [WIDTH-1:0] Spi4RxFifoCtrl_o,
+
+    output [WIDTH-1:0] Spi5Ctrl_o,
+    output [WIDTH-1:0] Spi5CsCtrl_o,
+    output [WIDTH-1:0] Spi5CsDelay_o,
+    output [WIDTH-1:0] Spi5TxFifoCtrl_o,
+    output [WIDTH-1:0] Spi5RxFifoCtrl_o,
+    
+    output [WIDTH-1:0] Spi6Ctrl_o,
+    output [WIDTH-1:0] Spi6CsCtrl_o,
+    output [WIDTH-1:0] Spi6CsDelay_o,
+    output [WIDTH-1:0] Spi6TxFifoCtrl_o,
+    output [WIDTH-1:0] Spi6RxFifoCtrl_o
+    
+);
+
+//lauch registers 
+reg [WIDTH-1:0] spi0Ctrl;
+reg [WIDTH-1:0] spi0CsCtrl;
+reg [WIDTH-1:0] spi0CsDelay;
+reg [WIDTH-1:0] spi0TxFifoCtrl;
+reg [WIDTH-1:0] spi0RxFifoCtrl;
+
+reg [WIDTH-1:0] spi1Ctrl;
+reg [WIDTH-1:0] spi1CsCtrl;
+reg [WIDTH-1:0] spi1CsDelay;
+reg [WIDTH-1:0] spi1TxFifoCtrl;
+reg [WIDTH-1:0] spi1RxFifoCtrl;
+
+reg [WIDTH-1:0] spi2Ctrl;
+reg [WIDTH-1:0] spi2CsCtrl;
+reg [WIDTH-1:0] spi2CsDelay;
+reg [WIDTH-1:0] spi2TxFifoCtrl;
+reg [WIDTH-1:0] spi2RxFifoCtrl;
+
+reg [WIDTH-1:0] spi3Ctrl;
+reg [WIDTH-1:0] spi3CsCtrl;
+reg [WIDTH-1:0] spi3CsDelay;
+reg [WIDTH-1:0] spi3TxFifoCtrl;
+reg [WIDTH-1:0] spi3RxFifoCtrl;
+
+reg [WIDTH-1:0] spi4Ctrl;
+reg [WIDTH-1:0] spi4CsCtrl;
+reg [WIDTH-1:0] spi4CsDelay;
+reg [WIDTH-1:0] spi4TxFifoCtrl;
+reg [WIDTH-1:0] spi4RxFifoCtrl;
+
+reg [WIDTH-1:0] spi5Ctrl;
+reg [WIDTH-1:0] spi5CsCtrl;
+reg [WIDTH-1:0] spi5CsDelay;
+reg [WIDTH-1:0] spi5TxFifoCtrl;
+reg [WIDTH-1:0] spi5RxFifoCtrl;
+
+reg [WIDTH-1:0] spi6Ctrl;
+reg [WIDTH-1:0] spi6CsCtrl;
+reg [WIDTH-1:0] spi6CsDelay;
+reg [WIDTH-1:0] spi6TxFifoCtrl;
+reg [WIDTH-1:0] spi6RxFifoCtrl;
+
+// capture registers
+(* ASYNC_REG = "TRUE" *)reg [STAGES*WIDTH-1:0] spi0Ctrl_c;
+(* ASYNC_REG = "TRUE" *)reg [STAGES*WIDTH-1:0] spi0CsCtrl_c;
+(* ASYNC_REG = "TRUE" *)reg [STAGES*WIDTH-1:0] spi0CsDelay_c;
+(* ASYNC_REG = "TRUE" *)reg [STAGES*WIDTH-1:0] spi0TxFifoCtrl_c;
+(* ASYNC_REG = "TRUE" *)reg [STAGES*WIDTH-1:0] spi0RxFifoCtrl_c;
+
+(*ASYNC_REG = "TRUE"*)reg [STAGES*WIDTH-1:0]   spi1Ctrl_c;
+(*ASYNC_REG = "TRUE"*)reg [STAGES*WIDTH-1:0]   spi1CsCtrl_c;
+(*ASYNC_REG = "TRUE"*)reg [STAGES*WIDTH-1:0]   spi1CsDelay_c;
+(*ASYNC_REG = "TRUE"*)reg [STAGES*WIDTH-1:0]   spi1TxFifoCtrl_c;
+(*ASYNC_REG = "TRUE"*)reg [STAGES*WIDTH-1:0]   spi1RxFifoCtrl_c;
+
+(*ASYNC_REG = "TRUE"*)reg [STAGES*WIDTH-1:0]   spi2Ctrl_c;
+(*ASYNC_REG = "TRUE"*)reg [STAGES*WIDTH-1:0]   spi2CsCtrl_c;
+(*ASYNC_REG = "TRUE"*)reg [STAGES*WIDTH-1:0]   spi2CsDelay_c;
+(*ASYNC_REG = "TRUE"*)reg [STAGES*WIDTH-1:0]   spi2TxFifoCtrl_c;
+(*ASYNC_REG = "TRUE"*)reg [STAGES*WIDTH-1:0]   spi2RxFifoCtrl_c;
+
+(*ASYNC_REG = "TRUE"*)reg [STAGES*WIDTH-1:0]   spi3Ctrl_c;
+(*ASYNC_REG = "TRUE"*)reg [STAGES*WIDTH-1:0]   spi3CsCtrl_c;
+(*ASYNC_REG = "TRUE"*)reg [STAGES*WIDTH-1:0]   spi3CsDelay_c;
+(*ASYNC_REG = "TRUE"*)reg [STAGES*WIDTH-1:0]   spi3TxFifoCtrl_c;
+(*ASYNC_REG = "TRUE"*)reg [STAGES*WIDTH-1:0]   spi3RxFifoCtrl_c;
+
+(*ASYNC_REG = "TRUE"*)reg [STAGES*WIDTH-1:0]   spi4Ctrl_c;
+(*ASYNC_REG = "TRUE"*)reg [STAGES*WIDTH-1:0]   spi4CsCtrl_c;
+(*ASYNC_REG = "TRUE"*)reg [STAGES*WIDTH-1:0]   spi4CsDelay_c;
+(*ASYNC_REG = "TRUE"*)reg [STAGES*WIDTH-1:0]   spi4TxFifoCtrl_c;
+(*ASYNC_REG = "TRUE"*)reg [STAGES*WIDTH-1:0]   spi4RxFifoCtrl_c;
+
+(*ASYNC_REG = "TRUE"*)reg [STAGES*WIDTH-1:0]   spi5Ctrl_c;
+(*ASYNC_REG = "TRUE"*)reg [STAGES*WIDTH-1:0]   spi5CsCtrl_c;
+(*ASYNC_REG = "TRUE"*)reg [STAGES*WIDTH-1:0]   spi5CsDelay_c;
+(*ASYNC_REG = "TRUE"*)reg [STAGES*WIDTH-1:0]   spi5TxFifoCtrl_c;
+(*ASYNC_REG = "TRUE"*)reg [STAGES*WIDTH-1:0]   spi5RxFifoCtrl_c;
+
+(*ASYNC_REG = "TRUE"*)reg [STAGES*WIDTH-1:0]   spi6Ctrl_c;
+(*ASYNC_REG = "TRUE"*)reg [STAGES*WIDTH-1:0]   spi6CsCtrl_c;
+(*ASYNC_REG = "TRUE"*)reg [STAGES*WIDTH-1:0]   spi6CsDelay_c;
+(*ASYNC_REG = "TRUE"*)reg [STAGES*WIDTH-1:0]   spi6TxFifoCtrl_c;
+(*ASYNC_REG = "TRUE"*)reg [STAGES*WIDTH-1:0]   spi6RxFifoCtrl_c;
+
+//SPI0
+assign Spi0Ctrl_o = spi0Ctrl_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];
+assign Spi0CsDelay_o = spi0CsDelay_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];
+assign Spi0CsCtrl_o = spi0CsCtrl_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];
+assign Spi0TxFifoCtrl_o = spi0TxFifoCtrl_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];
+assign Spi0RxFifoCtrl_o = spi0RxFifoCtrl_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];
+//SPI1
+assign Spi1Ctrl_o = spi1Ctrl_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];
+assign Spi1CsDelay_o = spi1CsDelay_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];
+assign Spi1CsCtrl_o = spi1CsCtrl_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];
+assign Spi1TxFifoCtrl_o = spi1TxFifoCtrl_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];
+assign Spi1RxFifoCtrl_o = spi1RxFifoCtrl_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];
+//SPI2
+assign Spi2Ctrl_o = spi2Ctrl_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];
+assign Spi2CsDelay_o = spi2CsDelay_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];
+assign Spi2CsCtrl_o = spi2CsCtrl_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];
+assign Spi2TxFifoCtrl_o = spi2TxFifoCtrl_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];
+assign Spi2RxFifoCtrl_o = spi2RxFifoCtrl_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];
+//SPI3
+assign Spi3Ctrl_o = spi3Ctrl_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];
+assign Spi3CsDelay_o = spi3CsDelay_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];
+assign Spi3CsCtrl_o = spi3CsCtrl_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];
+assign Spi3TxFifoCtrl_o = spi3TxFifoCtrl_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];
+assign Spi3RxFifoCtrl_o = spi3RxFifoCtrl_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];
+//SPI4
+assign Spi4Ctrl_o = spi4Ctrl_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];
+assign Spi4CsDelay_o = spi4CsDelay_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];
+assign Spi4CsCtrl_o = spi4CsCtrl_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];
+assign Spi4TxFifoCtrl_o = spi4TxFifoCtrl_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];
+assign Spi4RxFifoCtrl_o = spi4RxFifoCtrl_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];
+//SPI5
+assign Spi5Ctrl_o = spi5Ctrl_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];
+assign Spi5CsDelay_o = spi5CsDelay_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];
+assign Spi5CsCtrl_o = spi5CsCtrl_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];
+assign Spi5TxFifoCtrl_o = spi5TxFifoCtrl_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];
+assign Spi5RxFifoCtrl_o = spi5RxFifoCtrl_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];
+//SPI6
+assign Spi6Ctrl_o = spi6Ctrl_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];
+assign Spi6CsDelay_o = spi6CsDelay_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];
+assign Spi6CsCtrl_o = spi6CsCtrl_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];
+assign Spi6TxFifoCtrl_o = spi6TxFifoCtrl_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];
+assign Spi6RxFifoCtrl_o = spi6RxFifoCtrl_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];
+
+
+always @(posedge ClkFast_i) begin
+    spi0Ctrl <= Spi0Ctrl_i;
+    spi0CsDelay <= Spi0CsDelay_i;
+    spi0CsCtrl <= Spi0CsCtrl_i;
+    spi0TxFifoCtrl <= Spi0TxFifoCtrl_i;
+    spi0RxFifoCtrl <= Spi0RxFifoCtrl_i;
+    spi1Ctrl <= Spi1Ctrl_i;
+    spi1CsDelay <= Spi1CsDelay_i;
+    spi1CsCtrl <= Spi1CsCtrl_i;
+    spi1TxFifoCtrl <= Spi1TxFifoCtrl_i;
+    spi1RxFifoCtrl <= Spi1RxFifoCtrl_i;
+    spi2Ctrl <= Spi2Ctrl_i;
+    spi2CsDelay <= Spi2CsDelay_i;
+    spi2CsCtrl <= Spi2CsCtrl_i;
+    spi2TxFifoCtrl <= Spi2TxFifoCtrl_i;
+    spi2RxFifoCtrl <= Spi2RxFifoCtrl_i;
+    spi3Ctrl <= Spi3Ctrl_i;
+    spi3CsDelay <= Spi3CsDelay_i;
+    spi3CsCtrl <= Spi3CsCtrl_i;
+    spi3TxFifoCtrl <= Spi3TxFifoCtrl_i;
+    spi3RxFifoCtrl <= Spi3RxFifoCtrl_i;
+    spi4Ctrl <= Spi4Ctrl_i;
+    spi4CsDelay <= Spi4CsDelay_i;
+    spi4CsCtrl <= Spi4CsCtrl_i;
+    spi4TxFifoCtrl <= Spi4TxFifoCtrl_i;
+    spi4RxFifoCtrl <= Spi4RxFifoCtrl_i;
+    spi5Ctrl <= Spi5Ctrl_i;
+    spi5CsDelay <= Spi5CsDelay_i;
+    spi5CsCtrl <= Spi5CsCtrl_i;
+    spi5TxFifoCtrl <= Spi5TxFifoCtrl_i;
+    spi5RxFifoCtrl <= Spi5RxFifoCtrl_i;
+    spi6Ctrl <= Spi6Ctrl_i;
+    spi6CsDelay <= Spi6CsDelay_i;
+    spi6CsCtrl <= Spi6CsCtrl_i;
+    spi6TxFifoCtrl <= Spi6TxFifoCtrl_i;
+    spi6RxFifoCtrl <= Spi6RxFifoCtrl_i;
+end
+
+
+
+
+
+always @(posedge ClkSlow_i[0]) begin 
+    spi0Ctrl_c <= {spi0Ctrl_c[(STAGES-1)*WIDTH-1:0],spi0Ctrl};
+    spi0CsDelay_c <= {spi0CsDelay_c[(STAGES-1)*WIDTH-1:0],spi0CsDelay};
+    spi0CsCtrl_c <= {spi0CsCtrl_c[(STAGES-1)*WIDTH-1:0],spi0CsCtrl};
+    spi0TxFifoCtrl_c <= {spi0TxFifoCtrl_c[(STAGES-1)*WIDTH-1:0],spi0TxFifoCtrl};
+    spi0RxFifoCtrl_c <= {spi0RxFifoCtrl_c[(STAGES-1)*WIDTH-1:0],spi0RxFifoCtrl};
+end
+
+always@(posedge ClkSlow_i[1]) begin 
+    spi1Ctrl_c <= {spi1Ctrl_c[(STAGES-1)*WIDTH-1:0],spi1Ctrl};
+    spi1CsDelay_c <= {spi1CsDelay_c[(STAGES-1)*WIDTH-1:0],spi1CsDelay};
+    spi1CsCtrl_c <= {spi1CsCtrl_c[(STAGES-1)*WIDTH-1:0],spi1CsCtrl};
+    spi1TxFifoCtrl_c <= {spi1TxFifoCtrl_c[(STAGES-1)*WIDTH-1:0],spi1TxFifoCtrl};
+    spi1RxFifoCtrl_c <= {spi1RxFifoCtrl_c[(STAGES-1)*WIDTH-1:0],spi1RxFifoCtrl};
+end
+
+always@(posedge ClkSlow_i[2]) begin 
+    spi2Ctrl_c <= {spi2Ctrl_c[(STAGES-1)*WIDTH-1:0],spi2Ctrl};
+    spi2CsDelay_c <= {spi2CsDelay_c[(STAGES-1)*WIDTH-1:0],spi2CsDelay};
+    spi2CsCtrl_c <= {spi2CsCtrl_c[(STAGES-1)*WIDTH-1:0],spi2CsCtrl};
+    spi2TxFifoCtrl_c <= {spi2TxFifoCtrl_c[(STAGES-1)*WIDTH-1:0],spi2TxFifoCtrl};
+    spi2RxFifoCtrl_c <= {spi2RxFifoCtrl_c[(STAGES-1)*WIDTH-1:0],spi2RxFifoCtrl};
+end
+
+always@(posedge ClkSlow_i[3]) begin 
+    spi3Ctrl_c <= {spi3Ctrl_c[(STAGES-1)*WIDTH-1:0],spi3Ctrl};
+    spi3CsDelay_c <= {spi3CsDelay_c[(STAGES-1)*WIDTH-1:0],spi3CsDelay};
+    spi3CsCtrl_c <= {spi3CsCtrl_c[(STAGES-1)*WIDTH-1:0],spi3CsCtrl};
+    spi3TxFifoCtrl_c <= {spi3TxFifoCtrl_c[(STAGES-1)*WIDTH-1:0],spi3TxFifoCtrl};
+    spi3RxFifoCtrl_c <= {spi3RxFifoCtrl_c[(STAGES-1)*WIDTH-1:0],spi3RxFifoCtrl};
+end
+
+always@(posedge ClkSlow_i[4]) begin 
+    spi4Ctrl_c <= {spi4Ctrl_c[(STAGES-1)*WIDTH-1:0],spi4Ctrl};
+    spi4CsDelay_c <= {spi4CsDelay_c[(STAGES-1)*WIDTH-1:0],spi4CsDelay};
+    spi4CsCtrl_c <= {spi4CsCtrl_c[(STAGES-1)*WIDTH-1:0],spi4CsCtrl};
+    spi4TxFifoCtrl_c <= {spi4TxFifoCtrl_c[(STAGES-1)*WIDTH-1:0],spi4TxFifoCtrl};
+    spi4RxFifoCtrl_c <= {spi4RxFifoCtrl_c[(STAGES-1)*WIDTH-1:0],spi4RxFifoCtrl};
+end
+
+always@(posedge ClkSlow_i[5]) begin 
+    spi5Ctrl_c <= {spi5Ctrl_c[(STAGES-1)*WIDTH-1:0],spi5Ctrl};
+    spi5CsDelay_c <= {spi5CsDelay_c[(STAGES-1)*WIDTH-1:0],spi5CsDelay};
+    spi5CsCtrl_c <= {spi5CsCtrl_c[(STAGES-1)*WIDTH-1:0],spi5CsCtrl};
+    spi5TxFifoCtrl_c <= {spi5TxFifoCtrl_c[(STAGES-1)*WIDTH-1:0],spi5TxFifoCtrl};
+    spi5RxFifoCtrl_c <= {spi5RxFifoCtrl_c[(STAGES-1)*WIDTH-1:0],spi5RxFifoCtrl};
+end
+
+always@(posedge ClkSlow_i[6]) begin 
+    spi6Ctrl_c <= {spi6Ctrl_c[(STAGES-1)*WIDTH-1:0],spi6Ctrl};
+    spi6CsDelay_c <= {spi6CsDelay_c[(STAGES-1)*WIDTH-1:0],spi6CsDelay};
+    spi6CsCtrl_c <= {spi6CsCtrl_c[(STAGES-1)*WIDTH-1:0],spi6CsCtrl};
+    spi6TxFifoCtrl_c <= {spi6TxFifoCtrl_c[(STAGES-1)*WIDTH-1:0],spi6TxFifoCtrl};
+    spi6RxFifoCtrl_c <= {spi6RxFifoCtrl_c[(STAGES-1)*WIDTH-1:0],spi6RxFifoCtrl};
+end
+
+
+
+
+
+endmodule

src/src/CDC/Sync1bit.v

@@ -0,0 +1,47 @@
+module Sync1bit #(
+    parameter WIDTH = 1,
+    parameter STAGES = 3
+
+
+
+)
+(
+    input ClkFast_i,
+    input ClkSlow_i,
+    input TxEn_i,
+    input RstReg_i,
+
+    output [WIDTH-1:0] TxEn_o,
+    output [WIDTH-1:0] RstReg_o
+
+);
+//lauch registers 
+reg spiTxEnReg;
+reg rstReg;
+// capture registers
+(* ASYNC_REG = "TRUE" *) reg [STAGES*WIDTH-1:0] spiTxEnReg_c;
+(* ASYNC_REG = "TRUE" *) reg [STAGES*WIDTH-1:0] rstReg_c;
+
+assign TxEn_o = spiTxEnReg_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];
+assign RstReg_o = rstReg_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];
+
+
+always @(posedge ClkFast_i) begin
+    spiTxEnReg <= TxEn_i;
+    rstReg <= RstReg_i;
+end
+
+
+
+
+
+always @(posedge ClkSlow_i) begin 
+    spiTxEnReg_c <= {spiTxEnReg_c[(STAGES-1)*WIDTH-1:0], spiTxEnReg};
+    rstReg_c <= {rstReg_c[(STAGES-1)*WIDTH-1:0], rstReg};
+end
+
+
+
+
+
+endmodule

src/src/DataFifo/DataFifoWrapper.v

@@ -0,0 +1,129 @@
+
+module DataFifoWrapper 
+#(
+    parameter	CmdRegWidth	=	32,
+    parameter	AddrRegWidth=	12,
+	parameter	STAGES		=	3,
+	
+	parameter	FifoNum	=	7
+)
+(
+    input	WrClk_i,
+	input	RdClk_i,
+    input	FifoRxRst_i,
+	input	FifoTxRst_i,
+	input	FifoTxRstWrPtr_i,
+	input	FifoRxRstRdPtr_i,
+	input   SmcAre_i,
+	input	SmcAwe_i,
+	input	[AddrRegWidth-1:0]	SmcAddr_i,
+	input   [7:0] TxFifoWrdCnt_i,
+	input   [7:0] RxFifoWrdCnt_i,
+
+	input	ToFifoVal_i,
+	input	[CmdRegWidth-1:0]	ToFifoData_i,
+	input   [CmdRegWidth-1:0]	ToFifoRxData_i,
+	input   ToFifoRxWriteVal_i,                   
+	
+	input ToFifoTxReadVal_i,
+
+	output	ToSpiVal_o,
+	output [CmdRegWidth-1:0]	TxFifoCtrlReg_o,
+	output [CmdRegWidth-1:0]	RxFifoCtrlReg_o,
+	output	[CmdRegWidth-1:0]	ToSpiData_o,
+	output  [CmdRegWidth-1:0]   DataFromRxFifo_o
+);
+//================================================================================
+//	REG/WIRE
+//================================================================================
+	wire [CmdRegWidth-1:0]	dataFromRxFifo;
+	wire fullFlagRx;
+	wire emptyFlagRx;
+	wire fullFlagTx;
+	wire emptyFlagTx;
+
+	wire txFifoWrEn;
+	wire txFifoRdEn;
+	wire rxFifoWrEn;
+	wire rxFifoRdEn;
+
+	wire [7:0] rxFifoUpDnCnt;
+	wire [7:0] txFifoUpDnCnt;
+	
+//================================================================================
+//	ASSIGNMENTS
+//================================================================================
+	assign	ToSpiVal_o	=	1'b1;
+	assign DataFromRxFifo_o = dataFromRxFifo;
+
+	assign TxFifoCtrlReg_o = {16'h0, txFifoUpDnCnt,5'h0,emptyFlagTx,fullFlagTx, FifoTxRst_i};
+	assign RxFifoCtrlReg_o = {16'h0, rxFifoUpDnCnt,5'h0,emptyFlagRx,fullFlagRx, FifoRxRst_i};
+//================================================================================
+//	LOCALPARAMS
+//================================================================================
+
+//================================================================================
+//	CODING
+//================================================================================
+
+	FifoCtrl #(
+		.STAGES		(STAGES)
+	)FifoCtrl_inst (
+		.ToFifoTxWriteVal_i	(ToFifoVal_i),
+		.ToFifoTxReadVal_i (ToFifoTxReadVal_i),
+		.ToFifoRxWriteVal_i	(ToFifoRxWriteVal_i),
+		.ToFifoRxReadVal_i	(!SmcAre_i),
+		.SmcAddr_i			(SmcAddr_i),
+		.TxFifoWrdCnt_i		(TxFifoWrdCnt_i),
+		.RxFifoWrdCnt_i		(RxFifoWrdCnt_i),
+		.FifoTxFull_i		(fullFlagTx),
+		.FifoTxRst_i		(FifoTxRst_i),
+		.FifoRxRst_i		(FifoRxRst_i),
+		.FifoTxRstWrPtr_i	(FifoTxRstWrPtr_i),
+		.FifoRxRstRdPtr_i	(FifoRxRstRdPtr_i),
+		.FifoTxEmpty_i		(emptyFlagTx),
+		.FifoRxFull_i		(fullFlagRx),
+		.FifoRxEmpty_i		(emptyFlagRx),
+		.FifoTxWrClock_i	(WrClk_i),
+		.FifoTxRdClock_i	(RdClk_i),
+		.FifoRxWrClock_i	(RdClk_i),
+		.FifoRxRdClock_i	(WrClk_i),
+		.RxFifoUpDnCnt_o	(rxFifoUpDnCnt),
+		.TxFifoUpDnCnt_o	(txFifoUpDnCnt),
+		.FifoTxWriteEn_o	(txFifoWrEn),
+		.FifoTxReadEn_o		(txFifoRdEn),
+		.FifoRxWriteEn_o	(rxFifoWrEn),
+		.FifoRxReadEn_o		(rxFifoRdEn)
+	
+	);
+	
+	
+	
+	DataFifoTx	DataFifoTx
+	( 
+		.wr_clk		(WrClk_i), 
+		.rd_clk		(RdClk_i), 
+		.rst		(FifoTxRst_i),
+		.din		(ToFifoData_i), 
+		.wr_en		(txFifoWrEn), 
+		.rd_en		(txFifoRdEn), 
+		.dout		(ToSpiData_o),
+		.full		(fullFlagTx), 
+		.empty		(emptyFlagTx)
+	
+	);
+	
+	DataFifoRx	DataFifoRx
+	( 
+		.wr_clk		(RdClk_i), 
+		.rd_clk		(WrClk_i),
+		.rst		(FifoRxRst_i), 
+		.din		(ToFifoRxData_i), 
+		.wr_en		(rxFifoWrEn), 
+		.rd_en		(rxFifoRdEn), 
+		.dout		(dataFromRxFifo), 
+		.full		(fullFlagRx), 
+		.empty		(emptyFlagRx)
+	);
+	
+	endmodule

src/src/DataFifo/DataOutMux.v

@@ -0,0 +1,165 @@
+module DataOutMux#(
+    parameter	CmdRegWidth	=	32,
+    parameter	AddrRegWidth=	12
+
+
+
+) (
+    input Rst_i,
+    input FifoRxRst_i,
+    input Clk_i,
+    input SmcAre_i,
+    input [AddrRegWidth-1:0] Addr_i,
+    input [AddrRegWidth-1:0] ToRegMapAddr_i,
+    input ToFifoVal_i,
+    input [CmdRegWidth/2-1:0] DataFromRegMap_i,
+    input [CmdRegWidth-1:0] DataFromRxFifo1_i,
+    input [CmdRegWidth-1:0] DataFromRxFifo2_i,
+    input [CmdRegWidth-1:0] DataFromRxFifo3_i,
+    input [CmdRegWidth-1:0] DataFromRxFifo4_i,
+    input [CmdRegWidth-1:0] DataFromRxFifo5_i,
+    input [CmdRegWidth-1:0] DataFromRxFifo6_i,
+    input [CmdRegWidth-1:0] DataFromRxFifo7_i,
+
+    output [CmdRegWidth/2-1:0] AnsData_o
+
+);
+
+
+    wire [0:31] dataFromRxFifo [6:0];
+    wire [15:0] dataFromRegMap;
+    
+    reg [15:0] dataFromRxFifoR;
+    reg [1:0] readEnCnt;
+    
+    (* dont_touch = "true" *)reg [CmdRegWidth/2-1:0] dataFromRxFifoR1;
+    reg [CmdRegWidth-1:0] dataFromRxFifoR2;
+    reg [CmdRegWidth-1:0] dataFromRxFifoR3;
+    reg [CmdRegWidth-1:0] dataFromRxFifoR4;
+    reg [CmdRegWidth-1:0] dataFromRxFifoR5;
+    reg [CmdRegWidth-1:0] dataFromRxFifoR6;
+    reg [CmdRegWidth-1:0] dataFromRxFifoR7;
+    
+    
+    
+    assign dataFromRxFifo[0] = DataFromRxFifo1_i;
+    assign dataFromRxFifo[1] = DataFromRxFifo2_i;
+    assign dataFromRxFifo[2] = DataFromRxFifo3_i;
+    assign dataFromRxFifo[3] = DataFromRxFifo4_i;
+    assign dataFromRxFifo[4] = DataFromRxFifo5_i;
+    assign dataFromRxFifo[5] = DataFromRxFifo6_i;
+    assign dataFromRxFifo[6] = DataFromRxFifo7_i;
+    
+    assign dataFromRegMap = DataFromRegMap_i;
+    assign AnsData_o = (ToRegMapAddr_i)?dataFromRegMap:dataFromRxFifoR;
+    
+    
+    always @(posedge Clk_i) begin 
+        if (FifoRxRst_i) begin 
+            readEnCnt <= 1'b0;
+        end
+        else begin 
+            if (!SmcAre_i) begin 
+                readEnCnt <= readEnCnt + 1'b1;
+            end
+            else begin 
+                readEnCnt <= 1'b0;
+            end
+        end
+    end
+  
+    always @(*) begin
+        if (Rst_i) begin
+            dataFromRxFifoR1 = 0;
+            dataFromRxFifoR2 = 0;
+            dataFromRxFifoR3 = 0;
+            dataFromRxFifoR4 = 0;
+            dataFromRxFifoR5 = 0;
+            dataFromRxFifoR6 = 0;
+            dataFromRxFifoR7 = 0;
+        end
+        else begin
+            if (!SmcAre_i && readEnCnt < 1 ) begin  
+                case(Addr_i) 
+                    12'h1c : begin
+                        dataFromRxFifoR1 = DataFromRxFifo1_i[31:16];
+                    end
+                    12'h6c : begin
+                        dataFromRxFifoR2 = DataFromRxFifo2_i;
+                    end
+                    12'h10c : begin
+                        dataFromRxFifoR3 = DataFromRxFifo3_i;
+                    end
+                    12'h15c : begin
+                        dataFromRxFifoR4 = DataFromRxFifo4_i;
+                    end
+                    12'h1ac : begin
+                        dataFromRxFifoR5 = DataFromRxFifo5_i;
+                    end
+                    12'h1fc : begin
+                        dataFromRxFifoR6 = DataFromRxFifo6_i;
+                    end
+                    12'h24c : begin
+                        dataFromRxFifoR7 = DataFromRxFifo7_i;
+                    end
+                endcase
+            end
+        end
+    end
+    
+    
+    
+    always @(*) begin 
+            case (Addr_i)  
+                12'h1c: begin 
+                    dataFromRxFifoR = DataFromRxFifo1_i[15:0];
+                end
+                12'h1e: begin
+                    dataFromRxFifoR = dataFromRxFifoR1;
+                end 
+                12'h6c: begin 
+                    dataFromRxFifoR =  DataFromRxFifo2_i[15:0];
+                end
+                12'h6e: begin 
+                    dataFromRxFifoR = dataFromRxFifoR2[31:16];
+                end
+                12'h10c: begin 
+                    dataFromRxFifoR =  DataFromRxFifo3_i[15:0];
+                end
+                12'h10e: begin 
+                    dataFromRxFifoR = dataFromRxFifoR3[31:16];
+                end
+                12'h15c: begin 
+                    dataFromRxFifoR =  DataFromRxFifo4_i[15:0];
+                end
+                12'h15e: begin 
+                    dataFromRxFifoR = dataFromRxFifoR4[31:16];
+                end
+                12'h1ac: begin 
+                    dataFromRxFifoR =  DataFromRxFifo5_i[15:0];
+                end
+                12'h1ae: begin 
+                    dataFromRxFifoR = dataFromRxFifoR5[31:16];
+                end
+                12'h1fc: begin 
+                    dataFromRxFifoR =  DataFromRxFifo6_i[15:0];
+                end
+                12'h1fe: begin 
+                    dataFromRxFifoR = dataFromRxFifoR6[31:16];
+                end
+                12'h24c: begin 
+                    dataFromRxFifoR =  DataFromRxFifo7_i[15:0];
+                end
+                12'h24e: begin 
+                    dataFromRxFifoR = dataFromRxFifoR7[31:16];
+                end
+                default: begin
+                    dataFromRxFifoR = 16'h0;
+                end
+            endcase
+        end
+    
+    
+    
+    
+    endmodule

src/src/DataFifo/FifoCtrl.v

@@ -0,0 +1,251 @@
+module FifoCtrl #(
+    parameter Fifo0ReadMsbAddr		= 12'h0+12'd28,
+	parameter Fifo1ReadMsbAddr		= 12'h50+12'd28,
+	parameter Fifo2ReadMsbAddr		= 12'hf0+12'd28,
+	parameter Fifo3ReadMsbAddr		= 12'h140+12'd28,
+	parameter Fifo4ReadMsbAddr		= 12'h190+12'd28,
+	parameter Fifo5ReadMsbAddr		= 12'h1e0+12'd28,
+	parameter Fifo6ReadMsbAddr		= 12'h230+12'd28,
+    parameter STAGES = 3
+
+
+
+
+)(
+    input ToFifoTxWriteVal_i,
+    input ToFifoTxReadVal_i,
+    input ToFifoRxWriteVal_i,
+    input ToFifoRxReadVal_i,
+
+    input FifoTxFull_i,
+    input FifoTxEmpty_i,
+    input FifoRxFull_i,
+    input FifoRxEmpty_i,
+    input [11:0] SmcAddr_i,
+
+    input   [7:0] TxFifoWrdCnt_i,
+    input   [7:0] RxFifoWrdCnt_i,
+
+    input FifoTxWrClock_i,
+    input FifoTxRdClock_i,
+    input FifoRxWrClock_i,
+    input FifoRxRdClock_i,
+
+    input FifoTxRst_i,
+    input FifoRxRst_i,
+
+    input FifoTxRstWrPtr_i,
+    input FifoRxRstRdPtr_i,
+
+
+    output  [7:0] RxFifoUpDnCnt_o,
+    output  [7:0] TxFifoUpDnCnt_o,
+
+    output FifoTxWriteEn_o,
+    output FifoTxReadEn_o,
+    output FifoRxWriteEn_o,
+    output FifoRxReadEn_o
+
+);
+
+
+    reg fifoTxWriteEn;
+    reg fifoTxReadEn;
+    reg fifoRxWriteEn;
+    reg fifoRxReadEn;
+    
+    (* dont_touch = "true" *)reg [7:0] txFifoWrPtr;
+    (* dont_touch = "true" *)reg [7:0] txFifoRdPtr;
+    (* dont_touch = "true" *)reg [7:0] rxFifoWrPtr;
+    (* dont_touch = "true" *)reg [7:0] rxFifoRdPtr;
+    
+    (* dont_touch = "true" *) reg [7:0] rxFifoUpDnCnt;
+    (* dont_touch = "true" *) reg [7:0] txFifoUpDnCnt;
+    
+    reg [1:0] readEnCnt;    
+    
+    
+    
+    wire	requestToFifo0	=(SmcAddr_i == Fifo0ReadMsbAddr)?1'b1:1'b0;
+    wire	requestToFifo1	=(SmcAddr_i == Fifo1ReadMsbAddr)?1'b1:1'b0;
+    wire	requestToFifo2	=(SmcAddr_i == Fifo2ReadMsbAddr)?1'b1:1'b0;
+    wire	requestToFifo3	=(SmcAddr_i == Fifo3ReadMsbAddr)?1'b1:1'b0;
+    wire	requestToFifo4	=(SmcAddr_i == Fifo4ReadMsbAddr)?1'b1:1'b0;
+    wire	requestToFifo5	=(SmcAddr_i == Fifo5ReadMsbAddr)?1'b1:1'b0;
+    wire	requestToFifo6	=(SmcAddr_i == Fifo6ReadMsbAddr)?1'b1:1'b0;
+    wire	requestToFifo   =(requestToFifo0|requestToFifo1|requestToFifo2|requestToFifo3|requestToFifo4|requestToFifo5|requestToFifo6)?1'b1:1'b0;
+
+    wire [7:0] rxFifoWrPtrSync;
+    wire [7:0] txFifoWrPtrSync;
+
+    wire rxFifoRstSync;
+
+    
+    
+    
+    // //================================================================================
+    // //	ASSIGNMENTS
+    
+    assign FifoTxWriteEn_o = fifoTxWriteEn;
+    assign FifoTxReadEn_o = fifoTxReadEn;
+    assign FifoRxWriteEn_o = fifoRxWriteEn;
+    assign FifoRxReadEn_o = fifoRxReadEn;
+    
+    
+    assign RxFifoUpDnCnt_o = rxFifoUpDnCnt;
+    assign TxFifoUpDnCnt_o = txFifoUpDnCnt;
+    
+    
+    // //================================================================================
+    
+
+    RxFifoPtrSync #(
+        .WIDTH(8),
+        .STAGES(STAGES)
+    )
+    rxFifoPtrSync (
+        .ClkFast_i(FifoRxWrClock_i),
+        .ClkSlow_i(FifoRxRdClock_i),
+        .RxFifoWrPtr_i(rxFifoWrPtr),
+        .RxFifoWrPtr_o(rxFifoWrPtrSync)
+    );
+
+    TxFifoPtrSync #(
+        .WIDTH(8),
+        .STAGES(STAGES)
+    )
+    txFifoPtrSync (
+        .ClkFast_i(FifoTxWrClock_i),
+        .ClkSlow_i(FifoTxRdClock_i),
+        .TxFifoWrPtr_i(txFifoWrPtr),
+        .TxFifoWrPtr_o(txFifoWrPtrSync)
+    );
+    
+    
+    always @(posedge FifoRxRdClock_i) begin 
+        if (FifoRxRstRdPtr_i) begin 
+            readEnCnt <= 1'b0;
+        end
+        else begin 
+            if (ToFifoRxReadVal_i) begin 
+                readEnCnt <= readEnCnt + 1'b1;
+            end
+            else begin 
+                readEnCnt <= 1'b0;
+            end
+        end
+    end
+    
+    
+    
+    always @(posedge FifoTxWrClock_i) begin 
+        if (ToFifoTxWriteVal_i && !FifoTxFull_i) begin 
+            fifoTxWriteEn <= 1'b1;
+        end
+        else begin 
+            fifoTxWriteEn <= 1'b0;
+        end
+    end
+    
+    
+    always @(posedge FifoTxRdClock_i ) begin 
+        if (ToFifoTxReadVal_i && !FifoTxEmpty_i) begin 
+            fifoTxReadEn <= 1'b1;
+        end
+        else begin 
+            fifoTxReadEn <= 1'b0;
+        end
+    end
+    
+    
+    always @(posedge FifoRxWrClock_i) begin 
+        if (ToFifoRxWriteVal_i && !FifoRxFull_i) begin 
+            fifoRxWriteEn <= 1'b1;
+        end
+        else begin 
+            fifoRxWriteEn <= 1'b0;
+        end
+    end
+    
+    
+    always @(posedge FifoRxRdClock_i) begin 
+        if (ToFifoRxReadVal_i && !FifoRxEmpty_i && requestToFifo && readEnCnt < 1 ) begin 
+            fifoRxReadEn <= 1'b1;
+        end
+        else begin 
+            fifoRxReadEn <= 1'b0;
+        end
+    end
+    
+    
+    always @(posedge FifoTxWrClock_i ) begin 
+        if (FifoTxRstWrPtr_i) begin 
+            txFifoWrPtr <= 8'h0;
+        end
+        else begin 
+            if (fifoTxWriteEn  ) begin 
+                txFifoWrPtr <= txFifoWrPtr + 1'b1;
+            end
+        end
+    end
+    
+    always @(posedge FifoTxRdClock_i ) begin 
+        if (FifoTxRst_i) begin 
+            txFifoRdPtr <= 8'h0;
+        end
+        else begin 
+            if (fifoTxReadEn ) begin 
+                txFifoRdPtr <= txFifoRdPtr + 1'b1;
+            end
+        end
+    end
+    
+    
+    always @(posedge FifoRxWrClock_i) begin 
+        if (FifoRxRst_i) begin 
+            rxFifoWrPtr <= 8'h0;
+        end
+        else begin
+            if (fifoRxWriteEn ) begin 
+                rxFifoWrPtr <= rxFifoWrPtr + 1'b1;
+            end
+        end
+    end
+    
+    always @(posedge FifoRxRdClock_i) begin 
+        if (FifoRxRstRdPtr_i) begin 
+            rxFifoRdPtr <= 8'h0;
+        end
+        else begin 
+            if (fifoRxReadEn ) begin 
+                rxFifoRdPtr <= rxFifoRdPtr + 1'b1;
+            end
+        end
+    end
+    
+    
+    always @(posedge FifoRxRdClock_i) begin 
+        if (FifoRxRstRdPtr_i) begin 
+            rxFifoUpDnCnt <= 8'h0;
+        end
+        else begin 
+            rxFifoUpDnCnt <= rxFifoWrPtrSync - rxFifoRdPtr;
+        end
+    end
+    
+    always @(posedge FifoTxRdClock_i) begin 
+        if (FifoTxRst_i) begin 
+            txFifoUpDnCnt <= 8'h0;
+        end
+        else begin 
+            txFifoUpDnCnt <= txFifoWrPtrSync - txFifoRdPtr;
+        end
+    end
+    
+    
+    
+    
+    
+    // //================================================================================
+    
+    endmodule

src/src/DataFifo/RxFifoPtrSync.v

@@ -0,0 +1,47 @@
+module RxFifoPtrSync #(
+    parameter WIDTH = 8,
+    parameter STAGES = 3
+
+
+
+)
+(
+    input ClkFast_i,
+    input ClkSlow_i,
+    input [WIDTH-1:0] RxFifoWrPtr_i,
+
+    output [WIDTH-1:0] RxFifoWrPtr_o
+);
+
+
+
+
+//lauch registers 
+reg [WIDTH-1:0] rxFifoWrPtrReg;
+
+
+// capture registers
+(* ASYNC_REG = "TRUE" *) reg [STAGES*WIDTH-1:0] rxFifoWrPtrReg_c;
+
+
+
+assign RxFifoWrPtr_o = rxFifoWrPtrReg_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];
+
+
+always @(posedge ClkFast_i) begin
+    rxFifoWrPtrReg <= RxFifoWrPtr_i;
+end
+
+
+
+
+
+always @(posedge ClkSlow_i) begin
+    rxFifoWrPtrReg_c <= {rxFifoWrPtrReg_c[(STAGES-1)*WIDTH-1:0], rxFifoWrPtrReg};
+end
+
+
+
+
+
+endmodule

src/src/DataFifo/RxFifoRstSync.v

@@ -0,0 +1,45 @@
+module RxFifoRstSync #(
+    parameter WIDTH = 1,
+    parameter STAGES = 3
+
+
+
+)
+(
+    input ClkFast_i,
+    input ClkSlow_i,
+    input [WIDTH-1:0] RxFifoRst_i,
+
+    output [WIDTH-1:0] RxFifoRst_o
+);
+
+
+
+
+
+//lauch registers 
+reg [WIDTH-1:0] rxFifoRstReg;
+
+
+// capture registers
+(* ASYNC_REG = "TRUE" *) reg [STAGES*WIDTH-1:0] rxFifoRstReg_c;
+
+
+assign RxFifoWrPtr_o = rxFifoWrPtrReg_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];
+
+
+
+always @(posedge ClkFast_i) begin
+    rxFifoRstReg <= RxFifoRst_i;
+end
+
+
+always @(posedge ClkSlow_i) begin
+    rxFifoRstReg_c <= {rxFifoRstReg_c[(STAGES-1)*WIDTH-1:0], rxFifoRstReg};
+end
+
+
+
+
+
+endmodule

src/src/DataFifo/TxFifoPtrsync.v

@@ -0,0 +1,44 @@
+module TxFifoPtrSync #(
+    parameter WIDTH = 8,
+    parameter STAGES = 3
+
+
+
+)
+(
+    input ClkFast_i,
+    input ClkSlow_i,
+    input [WIDTH-1:0] TxFifoWrPtr_i,
+
+    output [WIDTH-1:0] TxFifoWrPtr_o
+);
+
+//lauch registers 
+reg [WIDTH-1:0] txFifoWrPtrReg;
+
+
+// capture registers
+(* ASYNC_REG = "TRUE" *) reg [STAGES*WIDTH-1:0] txFifoWrPtrReg_c;
+
+
+
+assign TxFifoWrPtr_o = txFifoWrPtrReg_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];
+
+
+always @(posedge ClkFast_i) begin
+    txFifoWrPtrReg <= TxFifoWrPtr_i;
+end
+
+
+
+
+
+always @(posedge ClkSlow_i) begin
+    txFifoWrPtrReg_c <= {txFifoWrPtrReg_c[(STAGES-1)*WIDTH-1:0], txFifoWrPtrReg};
+end
+
+
+
+
+
+endmodule

src/src/InitRst/InitRst.v

@@ -0,0 +1,104 @@
+module InitRst (
+    clk_i,
+    signal_o
+);
+
+//================================================================================
+//
+//  FUNCTIONS
+//
+//================================================================================
+
+    function integer bit_num;
+        input integer value;
+        begin
+            bit_num = 0;
+            while (value > 0) begin
+                value   = value >> 1;
+                bit_num = bit_num + 1;
+            end
+        end
+    endfunction
+
+//================================================================================
+//
+//  PARAMETER/LOCALPARAM
+//
+//================================================================================
+
+    parameter   DELAY_VALUE     = 20;
+    localparam  DELAY_CNT_W     = bit_num(DELAY_VALUE);
+
+//================================================================================
+//
+//  PORTS
+//
+//================================================================================
+
+    input           clk_i;
+    output  reg     signal_o;
+
+//================================================================================
+//
+//  STATE MACHINE STATES
+//
+//================================================================================
+
+    localparam      SM_RST_S    = 1'b0;
+    localparam      SM_DONE_S   = 1'b1;
+
+//================================================================================
+//
+//  REG/WIRE
+//
+//================================================================================
+
+    reg                         curr_state  = SM_RST_S;
+    reg     [DELAY_CNT_W-1:0]   delay_cnt   = {DELAY_CNT_W{1'b0}};
+    reg                         delay_flag  = 1'b0;
+
+    reg                         next_state;
+    reg     [DELAY_CNT_W-1:0]   delay_cnt_next	=	{DELAY_CNT_W{1'b0}};
+    reg                         signal_next;
+
+//================================================================================
+//
+//  CODING
+//
+//================================================================================
+
+initial begin
+    curr_state  = SM_RST_S;
+    delay_cnt   = {DELAY_CNT_W{1'b0}};
+    signal_o    = 1'b1;
+    delay_flag  = 1'b0;
+end
+
+always @(posedge clk_i) begin
+    curr_state  <= next_state;
+    delay_cnt   <= delay_cnt_next;
+    signal_o    <= signal_next;
+    delay_flag  <= delay_cnt > (DELAY_VALUE - 1);
+end
+
+always @(*) begin
+    next_state      = SM_RST_S;
+    delay_cnt_next  = delay_cnt;
+    signal_next     = 1'b1;
+    case(curr_state)
+        SM_RST_S    : begin
+            if (delay_flag) begin
+                next_state      = SM_DONE_S;
+            end else begin
+                next_state      = SM_RST_S;
+                delay_cnt_next  = delay_cnt + {{(DELAY_CNT_W-1){1'b0}}, 1'b1};
+            end
+        end
+        SM_DONE_S   : begin
+            signal_next = 1'b0;
+            next_state  = SM_DONE_S;
+        end
+    endcase
+end
+
+endmodule

src/src/MMCM/ClkCh.v

@@ -0,0 +1,53 @@
+module ClkCh (
+    input Rst_i,
+    input clkCh,
+    input clkOutMMCM,
+    input clkMan,
+
+    output SpiClk_o
+
+
+
+);
+
+
+reg spiClkReg;
+
+wire spiClk;
+
+assign spiClk = spiClkReg;
+
+
+
+always @(*) begin 
+    if (Rst_i) begin 
+        spiClkReg = 0;
+    end
+    else begin 
+        if (clkCh) begin 
+            spiClkReg = clkOutMMCM;
+        end
+        else begin 
+            spiClkReg = clkMan;
+        end
+    end
+end
+
+
+
+BUFG BUFG_inst (
+   .O(SpiClk_o), // 1-bit output: Clock output
+   .I(spiClk)  // 1-bit input: Clock input
+);
+
+
+
+
+
+
+
+
+endmodule
+
+
+

src/src/MMCM/ClkDivSync.v

@@ -0,0 +1,44 @@
+module ClkDivSync #(
+    parameter WIDTH = 4,
+    parameter STAGES = 3
+
+
+
+)
+(
+    input ClkFast_i,
+    input ClkSlow_i,
+    input [WIDTH-1:0] ClkDiv_i,
+
+    output [WIDTH-1:0] ClkDiv_o
+);
+
+
+//lauch registers 
+reg [WIDTH-1:0] clkDivReg;
+
+// capture registers
+(* ASYNC_REG = "TRUE" *) reg [STAGES*WIDTH-1:0] clkDivReg_c;
+
+
+assign ClkDiv_o = clkDivReg_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];
+
+
+
+always @(posedge ClkFast_i) begin
+    clkDivReg <= ClkDiv_i;
+end
+
+
+
+
+
+always @(posedge ClkSlow_i) begin
+    clkDivReg_c <= {clkDivReg_c[(STAGES-1)*WIDTH-1:0], clkDivReg};
+end
+
+
+
+
+
+endmodule

src/src/MMCM/ClkGen.v

@@ -0,0 +1,36 @@
+module ClkGen (
+  input Clk_i,
+  input [3:0] ClkDiv_i,
+  input Rst_i,
+  output Clk_o
+);
+
+reg [16:0] cnt;
+
+reg clk;
+wire clk_o;
+
+
+always @(posedge Clk_i) begin 
+    if (Rst_i) begin 
+        cnt <= 0;
+    end
+    else begin 
+        if (cnt >= ClkDiv_i-1) begin 
+            cnt <= 0;
+        end
+        else begin 
+            cnt <= cnt + 1;
+        end
+    end
+end
+
+assign Clk_o = (cnt < ClkDiv_i/2) ? 1 : 0;
+
+
+
+
+
+
+
+endmodule

src/src/MMCM/ClkGen_tb.v

@@ -0,0 +1,47 @@
+`timescale 1ns / 1ps
+module ClkGen_tb();
+
+
+
+
+
+
+reg Clk_i;
+reg Rst_i;
+
+reg [3:0] clkDiv_i;
+
+
+
+
+
+
+always #(1.667/2) Clk_i = ~Clk_i;
+
+
+
+
+ClkGenGowin ClkGen_inst (
+    .Clk_i(Clk_i), 
+    .Rst_i(Rst_i), 
+    .Clk75_o(),
+    .Clk40_o(),
+    .Clk30_o(),
+    .Clk5_o()
+);
+
+
+
+initial begin 
+    Clk_i = 0;
+    Rst_i = 1;
+    clkDiv_i = 3;
+    #1000;
+    Rst_i = 0;
+
+end
+
+
+
+
+endmodule

src/src/MMCM/ClkGen_tb.v.bak

@@ -0,0 +1,46 @@
+module ClkGen_tb();
+
+
+
+
+
+
+reg Clk_i;
+reg Rst_i;
+
+reg [3:0] clkDiv_i;
+
+
+
+
+
+
+always #(1.667/2) Clk_i = ~Clk_i;
+
+
+
+
+ClkGenGowin ClkGen_inst (
+    .Clk_i(Clk_i), 
+    .Rst_i(Rst_i), 
+    .Clk75_o(),
+    .Clk40_o(),
+    .Clk30_o(),
+    .Clk5_o()
+);
+
+
+
+initial begin 
+    Clk_i = 0;
+    Rst_i = 1;
+    clkDiv_i = 3;
+    #1000;
+    Rst_i = 0;
+
+end
+
+
+
+
+endmodule

src/src/MMCM/ClkOutMMCM.v

@@ -0,0 +1,55 @@
+module clkOutMMCM(
+input Rst_i,
+input [2:0]clkNum,
+input clk0out,
+input clk1out,
+input clk2out,
+input clk3out,
+input clk4out,
+input clk5out,
+input clk6out, 
+
+output   ClkOutMMCM_o
+
+);
+
+
+reg clkOutMMCMReg;
+
+wire clkOutMMCM;
+
+assign clkOutMMCM = clkOutMMCMReg;
+
+
+always @(*) begin 
+    if (Rst_i) begin 
+        clkOutMMCMReg = 0;
+    end
+    else begin 
+        case (clkNum) 
+            0: clkOutMMCMReg = clk0out;
+            1: clkOutMMCMReg = clk1out;
+            2: clkOutMMCMReg = clk2out;
+            3: clkOutMMCMReg = clk3out;
+            4: clkOutMMCMReg = clk4out;
+            5: clkOutMMCMReg = clk5out;
+            6: clkOutMMCMReg = clk6out;
+            default: clkOutMMCMReg = 0;
+        endcase
+    end
+end
+
+
+
+
+BUFG BUFG_inst (
+   .O(ClkOutMMCM_o), // 1-bit output: Clock output
+   .I(clkOutMMCM)  // 1-bit input: Clock input
+);
+
+
+
+
+
+
+endmodule

src/src/MMCM/MmcmWrapper.v

@@ -0,0 +1,176 @@
+
+module MmcmWrapper 
+#(
+	parameter	SpiNum	=	7,
+   parameter	STAGES   =	3
+)
+(
+   input	Clk_i,
+   input	Rst_i,
+   input Rst80_i,
+   input [7:0] BaudRate0_i,
+   input [7:0] BaudRate1_i,
+   input [7:0] BaudRate2_i,
+   input [7:0] BaudRate3_i,
+   input [7:0] BaudRate4_i,
+   input [7:0] BaudRate5_i,
+   input [7:0] BaudRate6_i,
+
+
+   output   Clk80_o,
+	output 	[SpiNum-1:0]	SpiClk_o
+   
+);
+//================================================================================
+//	REG/WIRE
+//================================================================================
+	
+wire    clk0out;
+wire    clk1out;
+wire    clk2out;
+wire    clk3out;
+wire    clk4out;
+wire    clk5out;
+wire    clk6out;
+wire    locked;
+
+wire [SpiNum-1:0] clkOutMMCM;
+
+
+wire [SpiNum-1:0] clkMan;
+
+wire [0:2] clkNum [SpiNum-1:0];
+wire [0:3] clkDiv [SpiNum-1:0];
+wire [0:3] clkDivSync [SpiNum-1:0];
+wire [SpiNum-1:0] clkCh; 
+wire [SpiNum-1:0] spiClk;
+
+
+
+//================================================================================
+//	ASSIGNMENTS
+//================================================================================
+	// assign SpiClk_o[0]	=	clk1out;
+   // assign SpiClk_o[1]	=	clk2out;
+   // assign SpiClk_o[2]	=	clk3out;
+   // assign SpiClk_o[3]	=	clk4out;
+   // assign SpiClk_o[4]	=	clk5out;
+   // assign SpiClk_o[5]	=	clk6out;
+   // assign SpiClk_o[6]	=	clk7out;
+
+   assign clkNum[0] = BaudRate0_i[7:5];
+   assign clkNum[1] = BaudRate1_i[7:5];
+   assign clkNum[2] = BaudRate2_i[7:5];
+   assign clkNum[3] = BaudRate3_i[7:5];
+   assign clkNum[4] = BaudRate4_i[7:5];
+   assign clkNum[5] = BaudRate5_i[7:5];
+   assign clkNum[6] = BaudRate6_i[7:5];
+
+   assign clkDiv[0] = BaudRate0_i[3:0];
+   assign clkDiv[1] = BaudRate1_i[3:0];
+   assign clkDiv[2] = BaudRate2_i[3:0];
+   assign clkDiv[3] = BaudRate3_i[3:0];
+   assign clkDiv[4] = BaudRate4_i[3:0];
+   assign clkDiv[5] = BaudRate5_i[3:0];
+   assign clkDiv[6] = BaudRate6_i[3:0];
+
+   assign clkCh[0] = BaudRate0_i[4];
+   assign clkCh[1] = BaudRate1_i[4];
+   assign clkCh[2] = BaudRate2_i[4];
+   assign clkCh[3] = BaudRate3_i[4];
+   assign clkCh[4] = BaudRate4_i[4];
+   assign clkCh[5] = BaudRate5_i[4];
+   assign clkCh[6] = BaudRate6_i[4];
+
+   assign SpiClk_o[0] = spiClk[0];
+   assign SpiClk_o[1] = spiClk[1];
+   assign SpiClk_o[2] = spiClk[2];
+   assign SpiClk_o[3] = spiClk[3];
+   assign SpiClk_o[4] = spiClk[4];
+   assign SpiClk_o[5] = spiClk[5];
+   assign SpiClk_o[6] = spiClk[6];
+
+   assign Clk100_o = clk0out;
+   assign Clk80_o = clk1out;
+
+
+
+   //================================================================================
+   //	LOCALPARAMS
+   //================================================================================
+   
+   
+   //================================================================================
+   //	CODING
+   //================================================================================
+ 
+   genvar i;
+   
+   generate
+      for (i=0; i < SpiNum; i = i +1) begin : ClkGen
+         ClkGen ClkGen_inst (
+            .Clk_i(clk1out),
+            .ClkDiv_i(clkDivSync[i]),
+            .Rst_i(Rst80_i),
+            .Clk_o(clkMan[i])
+         );
+
+         ClkDivSync #(
+            .WIDTH(4),
+            .STAGES(STAGES)
+         )(
+            .ClkFast_i(Clk_i),
+            .ClkSlow_i(clk1out),
+            .ClkDiv_i(clkDiv[i]),
+            .ClkDiv_o(clkDivSync[i])
+
+         );
+         
+
+         clkOutMMCM clkOutMMCM_inst (
+            .Rst_i(Rst_i),
+            .clkNum(clkNum[i]),
+            .clk0out(clk0out),
+            .clk1out(clk1out),
+            .clk2out(clk2out),
+            .clk3out(clk3out),
+            .clk4out(clk4out),
+            .clk5out(clk5out),
+            .clk6out(clk6out),
+            .ClkOutMMCM_o(clkOutMMCM[i])
+         );
+   
+         ClkCh ClkCh_inst (
+            .Rst_i(Rst_i),
+            .clkCh(clkCh[i]),
+            .clkOutMMCM(clkOutMMCM[i]),
+            .clkMan(clkMan[i]),
+            .SpiClk_o(spiClk[i])
+         );
+      end
+   
+   
+   endgenerate
+   
+   ClkDiv ClkDiv_inst
+    (
+     // Clock out ports
+     .clk_out1(clk0out),     //100 MHz
+     .clk_out2(clk1out),     // 80 MHz
+     .clk_out3(clk2out),     // 70 MHz
+     .clk_out4(clk3out),     // 60MHz
+     .clk_out5(clk4out),     // 50MHz
+   //   .clk_out6(clk5out),     // 40MHz
+     .clk_out7(clk6out),     // 30MHz 
+     // Status and control signals
+     .reset(Rst_i), // input reset
+     .locked(locked),       // output locked
+    // Clock in ports
+     .clk_in1(Clk_i));      // input clk_in1
+   
+   
+      
+   
+   
+   
+   endmodule

src/src/Mux/DataMuxer.v

@@ -0,0 +1,174 @@
+
+module DataMuxer 
+#(
+    parameter	CmdRegWidth	=	16,
+    parameter	AddrRegWidth=	12,
+	
+	parameter	FifoNum	=	7,
+	
+	// parameter	Fifo0WriteLsbAddr	=	12'h0+12'h24,
+	// parameter	Fifo0WriteMsbAddr	=	12'h0+12'h26,
+	// parameter	Fifo1WriteLsbAddr	=	12'h50+12'h24,
+	// parameter	Fifo2WriteMsbAddr	=	12'hF0+12'h26,
+	// parameter	Fifo3WriteLsbAddr	=	12'h140+12'h24,
+	// parameter	Fifo4WriteMsbAddr	=	12'h190+12'h26,
+	// parameter	Fifo5WriteLsbAddr	=	12'h1e0+12'h24,
+	// parameter	Fifo6WriteMsbAddr	=	12'h230+12'h26
+	
+	parameter	Fifo0WriteLsbAddr	=	12'h0+12'd24,
+	parameter	Fifo0WriteMsbAddr	=	12'h0+12'd26,
+	parameter	Fifo1WriteLsbAddr	=	12'h50+12'd24,
+	parameter	Fifo1WriteMsbAddr	=	12'h50+12'd26,
+	parameter	Fifo2WriteLsbAddr	=	12'hf0+12'd24,
+	parameter	Fifo2WriteMsbAddr	=	12'hf0+12'd26,
+	parameter	Fifo3WriteLsbAddr	=	12'h140+12'd24,
+	parameter	Fifo3WriteMsbAddr	=	12'h140+12'd26,
+	parameter	Fifo4WriteLsbAddr	=	12'h190+12'd24,
+	parameter	Fifo4WriteMsbAddr	=	12'h190+12'd26,
+	parameter	Fifo5WriteLsbAddr	=	12'h1e0+12'd24,
+	parameter	Fifo5WriteMsbAddr	=	12'h1e0+12'd26,
+	parameter	Fifo6WriteLsbAddr	=	12'h230+12'd24,
+	parameter	Fifo6WriteMsbAddr	=	12'h230+12'd26,
+
+	parameter Fifo0ReadLsbAddr		= 12'h0+12'd28,
+	parameter Fifo0ReadMsbAddr		= 12'h0+12'd30,
+	parameter Fifo1ReadLsbAddr		= 12'h50+12'd28,
+	parameter Fifo1ReadMsbAddr		= 12'h50+12'd30,
+	parameter Fifo2ReadLsbAddr		= 12'hf0+12'd28,
+	parameter Fifo2ReadMsbAddr		= 12'hf0+12'd30,
+	parameter Fifo3ReadLsbAddr		= 12'h140+12'd28,
+	parameter Fifo3ReadMsbAddr		= 12'h140+12'd30,
+	parameter Fifo4ReadLsbAddr		= 12'h190+12'd28,
+	parameter Fifo4ReadMsbAddr		= 12'h190+12'd30,
+	parameter Fifo5ReadLsbAddr		= 12'h1e0+12'd28,
+	parameter Fifo5ReadMsbAddr		= 12'h1e0+12'd30,
+	parameter Fifo6ReadLsbAddr		= 12'h230+12'd28,
+	parameter Fifo6ReadMsbAddr		= 12'h230+12'd30
+
+
+)
+(
+    input	Clk_i,
+    input	Rst_i,
+
+	input	SmcVal_i,
+	input	[CmdRegWidth-1:0]	SmcData_i,
+    input	[AddrRegWidth-1:0]	SmcAddr_i,
+
+	output	reg	ToRegMapVal_o,
+	output	reg	[CmdRegWidth-1:0]	ToRegMapData_o,
+    output	reg	[AddrRegWidth-1:0]	ToRegMapAddr_o,
+	
+	output	reg	[FifoNum-1:0]	ToFifoVal_o,
+	output	reg	[CmdRegWidth*2*FifoNum-1:0]	ToFifoData_o
+	
+);
+//================================================================================
+//	REG/WIRE
+//================================================================================
+	wire	requestToFifo0	=((SmcAddr_i==Fifo0WriteLsbAddr||SmcAddr_i==Fifo0WriteMsbAddr)|| (SmcAddr_i==Fifo0ReadLsbAddr||SmcAddr_i==Fifo0ReadMsbAddr));
+	wire	requestToFifo1	=((SmcAddr_i==Fifo1WriteLsbAddr||SmcAddr_i==Fifo1WriteMsbAddr)|| (SmcAddr_i==Fifo1ReadLsbAddr||SmcAddr_i==Fifo1ReadMsbAddr));
+	wire	requestToFifo2	=((SmcAddr_i==Fifo2WriteLsbAddr||SmcAddr_i==Fifo2WriteMsbAddr)|| (SmcAddr_i==Fifo2ReadLsbAddr||SmcAddr_i==Fifo2ReadMsbAddr));
+	wire	requestToFifo3	=((SmcAddr_i==Fifo3WriteLsbAddr||SmcAddr_i==Fifo3WriteMsbAddr)|| (SmcAddr_i==Fifo3ReadLsbAddr||SmcAddr_i==Fifo3ReadMsbAddr));
+	wire	requestToFifo4	=((SmcAddr_i==Fifo4WriteLsbAddr||SmcAddr_i==Fifo4WriteMsbAddr)|| (SmcAddr_i==Fifo4ReadLsbAddr||SmcAddr_i==Fifo4ReadMsbAddr));
+	wire	requestToFifo5	=((SmcAddr_i==Fifo5WriteLsbAddr||SmcAddr_i==Fifo5WriteMsbAddr)|| (SmcAddr_i==Fifo5ReadLsbAddr||SmcAddr_i==Fifo5ReadMsbAddr));
+	wire	requestToFifo6	=((SmcAddr_i==Fifo6WriteLsbAddr||SmcAddr_i==Fifo6WriteMsbAddr)|| (SmcAddr_i==Fifo6ReadLsbAddr||SmcAddr_i==Fifo6ReadMsbAddr));
+	
+	wire	requestToFifo	=	(requestToFifo0|requestToFifo1|requestToFifo2|requestToFifo3|requestToFifo4|requestToFifo5|requestToFifo6);
+//================================================================================
+//	ASSIGNMENTS
+//================================================================================
+
+//================================================================================
+//	LOCALPARAMS
+//================================================================================
+
+//================================================================================
+//	CODING
+//================================================================================
+
+	always	@(posedge	Clk_i	or	posedge	Rst_i)	begin
+		if	(Rst_i)	begin
+			ToRegMapVal_o	<=	1'b0;
+			ToRegMapData_o	<=	16'h0;
+			ToRegMapAddr_o	<=	12'h0;
+			
+			ToFifoVal_o		<=	7'h0;
+			ToFifoData_o	<=	0;
+		end	else	begin
+			if	(requestToFifo)	begin	
+				case(SmcAddr_i)	
+					Fifo0WriteLsbAddr:	begin
+										ToFifoVal_o[0]	<=	1'b0;
+										ToFifoData_o[CmdRegWidth*0+:CmdRegWidth]	<=	SmcData_i;
+									end
+					Fifo0WriteMsbAddr:	begin
+										ToFifoVal_o[0]	<=	SmcVal_i;
+										ToFifoData_o[CmdRegWidth*1+:CmdRegWidth]	<=	SmcData_i;
+									end
+									
+					Fifo1WriteLsbAddr:	begin
+										ToFifoVal_o[1]	<=	1'b0;
+										ToFifoData_o[CmdRegWidth*2+:CmdRegWidth]	<=	SmcData_i;
+									end
+					Fifo1WriteMsbAddr:	begin
+										ToFifoVal_o[1]	<=	SmcVal_i;
+										ToFifoData_o[CmdRegWidth*3+:CmdRegWidth]	<=	SmcData_i;
+									end
+									
+					Fifo2WriteLsbAddr:	begin
+										ToFifoVal_o[2]	<=	1'b0;
+										ToFifoData_o[CmdRegWidth*4+:CmdRegWidth]	<=	SmcData_i;
+									end
+					Fifo2WriteMsbAddr:	begin
+										ToFifoVal_o[2]	<=	SmcVal_i;
+										ToFifoData_o[CmdRegWidth*5+:CmdRegWidth]	<=	SmcData_i;
+									end
+									
+					Fifo3WriteLsbAddr:	begin
+										ToFifoVal_o[3]	<=	1'b0;
+										ToFifoData_o[CmdRegWidth*6+:CmdRegWidth]	<=	SmcData_i;
+									end
+					Fifo3WriteMsbAddr:	begin
+										ToFifoVal_o[3]	<=	SmcVal_i;
+										ToFifoData_o[CmdRegWidth*7+:CmdRegWidth]	<=	SmcData_i;
+									end
+									
+					Fifo4WriteLsbAddr:	begin
+										ToFifoVal_o[4]	<=	1'b0;
+										ToFifoData_o[CmdRegWidth*8+:CmdRegWidth]	<=	SmcData_i;
+									end
+					Fifo4WriteMsbAddr:	begin
+										ToFifoVal_o[4]	<=	SmcVal_i;
+										ToFifoData_o[CmdRegWidth*9+:CmdRegWidth]	<=	SmcData_i;
+									end
+									
+					Fifo5WriteLsbAddr:	begin
+										ToFifoVal_o[5]	<=	1'b0;
+										ToFifoData_o[CmdRegWidth*10+:CmdRegWidth]	<=	SmcData_i;
+									end
+					Fifo5WriteMsbAddr:	begin
+										ToFifoVal_o[5]	<=	SmcVal_i;
+										ToFifoData_o[CmdRegWidth*11+:CmdRegWidth]	<=	SmcData_i;
+									end
+									
+					Fifo6WriteLsbAddr:	begin
+										ToFifoVal_o[6]	<=	1'b0;
+										ToFifoData_o[CmdRegWidth*12+:CmdRegWidth]	<=	SmcData_i;
+									end
+					Fifo6WriteMsbAddr:	begin
+										ToFifoVal_o[6]	<=	SmcVal_i;
+										ToFifoData_o[CmdRegWidth*13+:CmdRegWidth]	<=	SmcData_i;
+									end
+				endcase
+				ToRegMapAddr_o	<=	0;
+			end	else	begin
+				ToRegMapVal_o	<=	SmcVal_i;
+				ToFifoVal_o		<=	7'h0;
+				ToRegMapData_o	<=	SmcData_i;
+				ToRegMapAddr_o	<=	SmcAddr_i;
+				ToFifoData_o	<=	0;
+			end
+		end
+	end
+	endmodule

src/src/QuadSPI/QuadSPIm.v.bak

@@ -0,0 +1,744 @@
+
+module QuadSPIm(
+    input Clk_i,
+    input Rst_i,
+    input Start_i,
+    input CPHA_i,
+    input [31:0] SPIdata,
+    input SpiDataVal_i,
+    input SELST_i,
+    input [1:0] WidthSel_i,
+    input  LAG_i,
+    input  LEAD_i,
+    input EndianSel_i,
+    input [5:0] Stop_i,
+    input PulsePol_i,   
+    output reg Mosi0_i,
+    output reg Mosi1_i,
+    output reg Mosi2_i,
+    output reg Mosi3_i,
+    output reg  Sck_o,
+    output reg Val_o,
+    output Ss_o 
+);
+//================================================================================
+//  REG/WIRE
+//================================================================================
+    reg startFlag;
+    reg startR;
+    reg [31:0] trCnt;
+
+    reg valReg;
+    reg lineBusy;
+    reg [5:0] ssCnt;
+    reg ss;
+    reg ssR;
+    reg [31:0] spiDataR;
+    reg oldDataFlag;
+    reg [7:0] mosiReg0;
+    reg [7:0] mosiReg1;
+    reg [7:0] mosiReg2;
+    reg [7:0] mosiReg3;
+    reg [3:0] ssNum;
+    reg [2:0] delayCnt;
+    reg stopFlag;
+//================================================================================
+//  ASSIGNMENTS
+//================================================================================
+
+    assign Ss_o = ss; 
+//================================================================================
+//  CODING
+//================================================================================	
+
+
+    always @(*) begin 
+        if (Start_i) begin 
+            Val_o = valReg;
+        end
+        else begin 
+            Val_o = 1'b0;
+        end
+    end
+    
+    
+    
+    always @(*) begin 
+        if (SELST_i) begin 
+            if (!ss) begin 
+                lineBusy = 1'b1;
+            end
+            else begin 
+                lineBusy = 1'b0;
+            end
+        end
+        else begin 
+            if (ss) begin 
+                lineBusy = 1'b1;
+            end
+            else begin 
+                lineBusy = 1'b0;
+            end
+        end
+    end
+    
+    
+    always @(posedge Clk_i) begin 
+        if (Rst_i) begin 
+            trCnt <= 1'b0;
+        end
+        else begin 
+            if ( ssCnt == (ssNum + LEAD_i + LAG_i)) begin 
+                trCnt <= trCnt + 1'b1;
+            end
+            else if (oldDataFlag) begin 
+                trCnt <= 1'b0;
+            end
+        end
+    end
+    
+    
+    
+    always @(posedge Clk_i) begin 
+        if (Rst_i) begin 
+            delayCnt <= 1'b0;
+        end
+        else begin 
+            if (stopFlag &&delayCnt < Stop_i) begin 
+                delayCnt <= delayCnt + 1'b1;
+            end
+            else begin 
+                delayCnt <= 1'b0;
+            end
+        end
+    end
+    
+    always @(posedge Clk_i) begin 
+        if (Rst_i) begin 
+            stopFlag <= 1'b0;
+        end
+        else begin
+            if (SELST_i) begin 
+                if (ss && !ssR) begin 
+                    stopFlag <= 1'b1;
+                end
+                else if ( delayCnt == Stop_i) begin 
+                    stopFlag <= 1'b0;
+                end
+            end
+            else begin 
+                if (!ss && ssR) begin 
+                    stopFlag <= 1'b1;
+                end
+                else if (delayCnt == Stop_i) begin 
+                    stopFlag <= 1'b0;
+                end
+            end
+        end
+    end
+    
+    
+    
+    always @(*) begin
+        if (SELST_i) begin 
+            if (PulsePol_i) begin 
+                if (CPHA_i) begin
+                    if (LEAD_i == 0) begin 
+                        if (!ss && (ssCnt <= ssNum+LAG_i+LEAD_i && ssCnt > LAG_i) ) begin 
+                            Sck_o = ~(~Clk_i);
+                        end
+                        else begin 
+                            Sck_o = 1'b0;
+                        end
+                    end
+                    else begin 
+                        if (!ss && (ssCnt < ssNum+LAG_i+LEAD_i && ssCnt > LAG_i)) begin 
+                            Sck_o = ~(~Clk_i);
+                        end
+                        else begin 
+                            Sck_o = 1'b0;
+                        end
+                    end
+                end
+                else begin
+                    if (LEAD_i == 0) begin 
+                        if (!ss && (ssCnt <= ssNum+LAG_i+LEAD_i && ssCnt > LAG_i) ) begin 
+                            Sck_o = ~(Clk_i);
+                        end
+                        else begin 
+                            Sck_o = 1'b0;
+                        end
+                    end
+                    else begin 
+                        if (!ss && (ssCnt < ssNum + LAG_i + LEAD_i && ssCnt > LAG_i)) begin 
+                            Sck_o = ~(Clk_i);
+                        end
+                        else begin 
+                            Sck_o = 1'b0;
+                        end
+                    end
+                end
+            end
+            else begin 
+                if (CPHA_i) begin
+                    if (LEAD_i == 0) begin  
+                        if (!ss && (ssCnt <= ssNum+LAG_i+LEAD_i && ssCnt > LAG_i) ) begin 
+                            Sck_o = ~(Clk_i);
+                        end
+                        else begin 
+                            Sck_o = 1'b0;
+                        end
+                    end
+                    else begin 
+                        if (!ss && (ssCnt <ssNum + LAG_i + LAG_i && ssCnt > LAG_i)) begin 
+                            Sck_o = ~(Clk_i);
+                        end
+                        else begin 
+                            Sck_o = 1'b0;
+                        end
+                    end
+                end 
+                else begin
+                    if (LEAD_i == 0) begin 
+                        if (!ss && (ssCnt <= ssNum+LAG_i+LEAD_i && ssCnt > LAG_i) ) begin 
+                            Sck_o = ~(~Clk_i);
+                        end
+                        else begin 
+                            Sck_o = 1'b0;
+                        end
+                    end
+                    else begin 
+                        if (!ss && (ssCnt < ssNum + LAG_i + LEAD_i && ssCnt > LAG_i)) begin 
+                            Sck_o = ~(~Clk_i);
+                        end
+                        else begin 
+                            Sck_o = 1'b0;
+                        end
+                    end
+                end
+            end
+        end
+        else begin 
+              if (PulsePol_i) begin 
+                if (CPHA_i) begin
+                    if (LEAD_i == 0) begin 
+                        if (ss && (ssCnt <= ssNum+LAG_i+LEAD_i && ssCnt > LAG_i) ) begin 
+                            Sck_o = ~(~Clk_i);
+                        end
+                        else begin 
+                            Sck_o = 1'b0;
+                        end
+                    end
+                    else begin 
+                        if (ss && (ssCnt < ssNum+LAG_i+LEAD_i && ssCnt > LAG_i)) begin 
+                            Sck_o = ~(~Clk_i);
+                        end
+                        else begin 
+                            Sck_o = 1'b0;
+                        end
+                    end
+                end
+                else begin
+                    if (LEAD_i == 0) begin 
+                        if (ss && (ssCnt <= ssNum+LAG_i+LEAD_i && ssCnt > LAG_i) ) begin 
+                            Sck_o = ~(Clk_i);
+                        end
+                        else begin 
+                            Sck_o = 1'b0;
+                        end
+                    end
+                    else begin 
+                        if (ss && (ssCnt < ssNum + LAG_i + LEAD_i && ssCnt > LAG_i)) begin 
+                            Sck_o = ~(Clk_i);
+                        end
+                        else begin 
+                            Sck_o = 1'b0;
+                        end
+                    end
+                end
+            end
+            else begin 
+                if (CPHA_i) begin
+                    if (LEAD_i == 0) begin  
+                        if (ss && (ssCnt <= ssNum+LAG_i+LEAD_i && ssCnt > LAG_i) ) begin 
+                            Sck_o = ~(Clk_i);
+                        end
+                        else begin 
+                            Sck_o = 1'b0;
+                        end
+                    end
+                    else begin 
+                        if (ss && (ssCnt <ssNum + LAG_i + LAG_i && ssCnt > LAG_i)) begin 
+                            Sck_o = ~(Clk_i);
+                        end
+                        else begin 
+                            Sck_o = 1'b0;
+                        end
+                    end
+                end 
+                else begin
+                    if (LEAD_i == 0) begin 
+                        if (ss && (ssCnt <= ssNum+LAG_i+LEAD_i && ssCnt > LAG_i) ) begin 
+                            Sck_o = ~(~Clk_i);
+                        end
+                        else begin 
+                            Sck_o = 1'b0;
+                        end
+                    end
+                    else begin 
+                        if (ss && (ssCnt < ssNum + LAG_i + LEAD_i && ssCnt > LAG_i)) begin 
+                            Sck_o = ~(~Clk_i);
+                        end
+                        else begin 
+                            Sck_o = 1'b0;
+                        end
+                    end
+                end
+            end
+        end
+            
+    end
+    
+    
+    always @(*) begin
+        if (SELST_i) begin 
+            if (EndianSel_i) begin 
+                case (WidthSel_i) 
+                    0 : begin 
+                        Mosi0_i = (!ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i) ) ? (mosiReg3[0]):1'b0;
+                        Mosi1_i = (!ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i)) ? (mosiReg3[0]):1'b0;
+                        Mosi2_i = (!ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i)) ? (mosiReg1[0]):1'b0;
+                        Mosi3_i = (!ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i)) ? (mosiReg0[0]):1'b0;
+                    end
+                    1 : begin 
+                        Mosi0_i = (!ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i)) ? (mosiReg3[0]):1'b0;
+                        Mosi1_i = (!ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i)) ? (mosiReg2[0]):1'b0;
+                        Mosi2_i = (!ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i)) ? (mosiReg1[0]):1'b0;
+                        Mosi3_i = (!ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i)) ? (mosiReg0[0]):1'b0;
+                    end
+                    2 : begin 
+                        Mosi0_i = (!ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i)) ? (mosiReg3[0]):1'b0;
+                        Mosi1_i = (!ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i)) ? (mosiReg2[0]):1'b0;
+                        Mosi2_i = (!ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i)) ? (mosiReg1[0]):1'b0;
+                        Mosi3_i = (!ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i)) ? (mosiReg0[0]):1'b0;
+                    end
+                    3 : begin 
+                        Mosi0_i = (!ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i)) ? (mosiReg3[0]):1'b0;
+                        Mosi1_i = (!ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i)) ? (mosiReg2[0]):1'b0;
+                        Mosi2_i = (!ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i)) ? (mosiReg1[0]):1'b0;
+                        Mosi3_i = (!ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i)) ? (mosiReg0[0]):1'b0;
+                    end
+                endcase
+            end
+            else begin 
+                case (WidthSel_i)
+                    0 : begin
+                        Mosi0_i = (!ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg0[1]):1'b0;
+                        Mosi1_i = (!ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg1[1]):1'b0;
+                        Mosi2_i = (!ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg2[1]):1'b0;
+                        Mosi3_i = (!ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg3[1]):1'b0;
+                    end
+                    1 : begin
+                        Mosi0_i = (!ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg0[3]):1'b0;
+                        Mosi1_i = (!ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg1[3]):1'b0;
+                        Mosi2_i = (!ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg2[3]):1'b0;
+                        Mosi3_i = (!ss&& (ssCnt <= ssNum+LAG_i && ssCnt >LAG_i))? (mosiReg3[3]):1'b0;
+                    end
+                    2 : begin
+                        Mosi0_i = (!ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg0[5]):1'b0;
+                        Mosi1_i = (!ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg1[5]):1'b0;
+                        Mosi2_i = (!ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg2[5]):1'b0;
+                        Mosi3_i = (!ss&& (ssCnt < ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg3[5]):1'b0;
+                    end
+                    3 : begin
+                        Mosi0_i = (!ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg0[7]):1'b0;
+                        Mosi1_i = (!ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg1[7]):1'b0;
+                        Mosi2_i = (!ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg2[7]):1'b0;
+                        Mosi3_i = (!ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg3[7]):1'b0;
+                    end
+                endcase
+            end
+        end
+        else begin 
+            if (EndianSel_i) begin 
+                case (WidthSel_i) 
+                    0 : begin 
+                        Mosi0_i = (ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i) )?(mosiReg3[0]):1'b0;
+                        Mosi1_i = (ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i)) ? (mosiReg2[0]):1'b0;
+                        Mosi2_i = (ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i)) ? (mosiReg1[0]):1'b0;
+                        Mosi3_i = (ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i)) ? (mosiReg0[0]):1'b0;
+                    end
+                    1 : begin 
+                        Mosi0_i = (ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i)) ? (mosiReg3[0]):1'b0;
+                        Mosi1_i = (ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i)) ? (mosiReg2[0]):1'b0;
+                        Mosi2_i = (ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i)) ? (mosiReg1[0]):1'b0;
+                        Mosi3_i = (ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i)) ? (mosiReg0[0]):1'b0;
+                    end
+                    2 : begin
+                        Mosi0_i = (ss && (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i)) ? (mosiReg3[0]):1'b0;
+                        Mosi1_i = (ss && (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i)) ? (mosiReg2[0]):1'b0;
+                        Mosi2_i = (ss && (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i)) ? (mosiReg1[0]):1'b0;
+                        Mosi3_i = (ss && (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i)) ? (mosiReg0[0]):1'b0;
+                    end
+                    3 : begin 
+                        Mosi0_i = (ss && (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i)) ? (mosiReg3[0]):1'b0;
+                        Mosi1_i = (ss && (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i)) ? (mosiReg2[0]):1'b0;
+                        Mosi2_i = (ss && (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i)) ? (mosiReg1[0]):1'b0;
+                        Mosi3_i = (ss && (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i)) ? (mosiReg0[0]):1'b0;
+                    end
+                endcase
+            end
+            else begin 
+                case (WidthSel_i)
+                    0 : begin
+                        Mosi0_i = (ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg0[1]):1'b0;
+                        Mosi1_i = (ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg1[1]):1'b0;
+                        Mosi2_i = (ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg2[1]):1'b0;
+                        Mosi3_i = (ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg3[1]):1'b0;
+                    end
+                    1 : begin
+                        Mosi0_i = (ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg0[3]):1'b0;
+                        Mosi1_i = (ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg1[3]):1'b0;
+                        Mosi2_i = (ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg2[3]):1'b0;
+                        Mosi3_i = (ss&& (ssCnt <= ssNum+LAG_i && ssCnt >LAG_i))? (mosiReg3[3]):1'b0;
+                    end
+                    2 : begin
+                        Mosi0_i = (ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg0[5]):1'b0;
+                        Mosi1_i = (ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg1[5]):1'b0;
+                        Mosi2_i = (ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg2[5]):1'b0;
+                        Mosi3_i = (ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg3[5]):1'b0;
+                    end
+                    3 : begin
+                        Mosi0_i = (ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg0[7]):1'b0;
+                        Mosi1_i = (ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg1[7]):1'b0;
+                        Mosi2_i = (ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg2[7]):1'b0;
+                        Mosi3_i = (ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg3[7]):1'b0;
+                    end
+                endcase
+            end
+        end
+    end
+    
+    
+    
+    always @(posedge Clk_i) begin
+        ssR <= ss;
+    end
+    
+    
+    always @(*) begin
+        if (SELST_i) begin 
+            if (ss && !ssR) begin 
+                valReg = 1'b1;
+            end
+            else begin 
+                valReg = 1'b0;
+            end
+        end
+        else begin 
+            if (!ss&& ssR) begin 
+                valReg = 1'b1;
+            end
+            else begin 
+                valReg = 1'b0;
+            end
+        end
+    end
+    
+    
+    always @(posedge Clk_i) begin
+        if (valReg) begin  
+            spiDataR <= SPIdata;
+        end
+    end
+    
+    
+    always @(*) begin 
+        if (Rst_i) begin 
+            oldDataFlag = 1'b0;
+        end
+        else begin 
+            if (spiDataR == SPIdata) begin 
+                oldDataFlag = 1'b1;
+            end
+            else begin 
+                oldDataFlag = 1'b0;
+            end
+        end
+    end
+    
+    
+    
+    always @(*) begin 
+        if (Rst_i) begin 
+            startFlag = 1'b0;
+        end
+        else begin 
+            if (Start_i&& !stopFlag && SPIdata != 0 && !oldDataFlag ) begin 
+                startFlag = 1'b1;
+            end
+            else begin 
+                startFlag = 1'b0;
+            end
+        end
+    end
+    
+    always @(*) begin 
+        if (Rst_i) begin 
+            ssNum = 1'b0;
+        end
+        else begin 
+            case (WidthSel_i) 
+                0 : begin 
+                    ssNum = 2;
+                end
+                1 : begin 
+                    ssNum = 4;
+                end
+                2 : begin 
+                    ssNum = 6;
+                end
+                3 : begin 
+                    ssNum = 8;
+                end
+            endcase
+        end
+    end
+    
+    
+    always @(negedge Clk_i) begin 
+        if (Rst_i) begin 
+            ssCnt <= 1'b0;
+        end
+        else if (ssCnt < (ssNum+LAG_i+LEAD_i)  && startFlag  ) begin 
+            ssCnt <= ssCnt + 1'b1;
+        end
+        else begin
+            if (ssCnt == ssNum-1 || !startFlag) begin 
+                ssCnt <= 1'b0;
+            end
+        end
+    end
+    
+    
+    
+    
+    always @(posedge Clk_i) begin
+        if (SELST_i) begin  
+            if (Rst_i) begin 
+                ss <= 1'b1;
+            end
+            else begin 
+                if (ssCnt < (ssNum+LAG_i+LEAD_i)  && startFlag ) begin 
+                    ss <= 1'b0;
+                end
+                else begin 
+                    ss <= 1'b1;
+                end
+            end
+        end
+        else begin 
+            if (Rst_i) begin 
+                ss <= 1'b0;
+            end
+            else begin 
+                if (ssCnt < (ssNum+LAG_i+LEAD_i)  && startFlag ) begin 
+                    ss <= 1'b1;
+                end
+                else begin 
+                    ss <= 1'b0;
+                end
+            end
+        end
+    end
+    
+    
+    always @(negedge Clk_i) begin 
+        if (Rst_i) begin 
+            mosiReg0 <= SPIdata[31:24];
+        end
+        else begin
+            if (!EndianSel_i) begin 
+                if (SELST_i) begin 
+                    if (!ssR && (ssCnt > LAG_i && ssCnt < ssNum + LAG_i + LEAD_i)) begin
+                        mosiReg0 <= { mosiReg0[6:0],1'b0 };
+                    end
+                    else begin 
+                        mosiReg0 <= SPIdata[31:24];
+                    end
+                end
+                else begin 
+                    if (ssR&& (ssCnt > LAG_i && ssCnt < ssNum + LAG_i + LEAD_i)) begin
+                        mosiReg0 <= { mosiReg0[6:0],1'b0 };
+                    end
+                    else begin 
+                        mosiReg0 <= SPIdata[31:24];
+                    end
+                end
+            end
+            else begin 
+                if (SELST_i) begin 
+                    if (!ssR&& (ssCnt > LAG_i && ssCnt < ssNum + LAG_i + LEAD_i)) begin
+                        mosiReg0 <= {1'b0, mosiReg0[7:1] };
+                    end
+                    else begin 
+                        mosiReg0 <= SPIdata[31:24];
+                    end
+                end
+                else begin 
+                    if (ssR&& (ssCnt > LAG_i && ssCnt < ssNum + LAG_i + LEAD_i)) begin
+                        mosiReg0 <= {1'b0, mosiReg0[7:1] };
+                    end
+                    else begin 
+                        mosiReg0 <= SPIdata[31:24];
+                    end
+                end
+            end
+        end
+    end
+    
+    always @(negedge Clk_i) begin 
+        if (Rst_i) begin 
+            mosiReg1 <= SPIdata[23:16];
+        end
+        else begin
+            if (!EndianSel_i) begin 
+                if (SELST_i) begin 
+                    if (!ssR&& (ssCnt > LAG_i && ssCnt < ssNum + LAG_i + LEAD_i)) begin
+                        mosiReg1 <= { mosiReg1[6:0],1'b0 };
+                    end
+                    else begin 
+                        mosiReg1 <= SPIdata[23:16];
+                    end
+                end
+                else begin 
+                    if (ssR&& (ssCnt > LAG_i && ssCnt < ssNum + LAG_i + LEAD_i)) begin
+                        mosiReg1 <= { mosiReg1[6:0],1'b0 };
+                    end
+                    else begin 
+                        mosiReg1 <= SPIdata[23:16];
+                    end
+                end
+            end
+            else begin 
+                if (SELST_i) begin 
+                    if (!ssR&& (ssCnt > LAG_i && ssCnt < ssNum + LAG_i + LEAD_i)) begin
+                        mosiReg1 <= {1'b0, mosiReg1[7:1] };
+                    end
+                    else begin 
+                        mosiReg1 <= SPIdata[23:16];
+                    end
+                end
+                else begin 
+                    if (ssR&& (ssCnt > LAG_i && ssCnt < ssNum + LAG_i + LEAD_i)) begin
+                        mosiReg1 <= {1'b0, mosiReg1[7:1] };
+                    end
+                    else begin 
+                        mosiReg1 <= SPIdata[23:16];
+                    end
+                end
+            end
+        end
+    end
+    
+    always @(negedge Clk_i) begin 
+        if (Rst_i) begin 
+            mosiReg2 <= SPIdata[15:8];
+        end
+        else begin
+            if (!EndianSel_i) begin
+                if (SELST_i) begin  
+                    if (!ssR&& (ssCnt > LAG_i && ssCnt < ssNum + LAG_i + LEAD_i)) begin
+                        mosiReg2 <= { mosiReg2[6:0],1'b0 };
+                    end
+                    else begin 
+                        mosiReg2 <= SPIdata[15:8];
+                    end
+                end
+                else begin 
+                    if (ssR&& (ssCnt > LAG_i && ssCnt < ssNum + LAG_i + LEAD_i)) begin
+                        mosiReg2 <= { mosiReg2[6:0],1'b0 };
+                    end
+                    else begin 
+                        mosiReg2 <= SPIdata[15:8];
+                    end
+                end
+            end
+            else begin 
+                if (SELST_i) begin 
+                    if (!ssR&& (ssCnt > LAG_i && ssCnt < ssNum + LAG_i + LEAD_i)) begin
+                        mosiReg2 <= {1'b0, mosiReg2[7:1] };
+                    end
+                    else begin 
+                        mosiReg2 <= SPIdata[15:8];
+                    end
+                end
+                else begin 
+                    if (ssR&& (ssCnt > LAG_i && ssCnt < ssNum + LAG_i + LEAD_i)) begin
+                        mosiReg2 <= {1'b0, mosiReg2[7:1] };
+                    end
+                    else begin 
+                        mosiReg2 <= SPIdata[15:8];
+                    end
+                end
+            end
+        end
+    end
+    
+    always @(negedge Clk_i) begin 
+        if (Rst_i) begin 
+            mosiReg3 <= SPIdata[7:0];
+        end
+        else begin
+            if (!EndianSel_i) begin 
+                if (SELST_i) begin 
+                    if (!ssR&& (ssCnt > LAG_i && ssCnt < ssNum + LAG_i + LEAD_i)) begin
+                        mosiReg3 <= { mosiReg3[6:0],1'b0 };
+                    end
+                    else begin 
+                        mosiReg3 <= SPIdata[7:0];
+                    end
+                end
+                else begin 
+                    if (ssR&& (ssCnt > LAG_i && ssCnt < ssNum + LAG_i + LEAD_i)) begin
+                        mosiReg3 <= { mosiReg3[6:0],1'b0 };
+                    end
+                    else begin 
+                        mosiReg3 <= SPIdata[7:0];
+                    end
+                end
+            end
+            else begin 
+                if (SELST_i) begin 
+                    if (!ssR&& (ssCnt > LAG_i && ssCnt < ssNum + LAG_i + LEAD_i)) begin
+                        mosiReg3 <= {1'b0, mosiReg3[7:1] };
+                    end
+                    else begin 
+                        mosiReg3 <= SPIdata[7:0];
+                    end
+                end
+                else begin 
+                    if (ssR&& (ssCnt > LAG_i && ssCnt < ssNum + LAG_i + LEAD_i)) begin
+                        mosiReg3 <= {1'b0, mosiReg3[7:1] };
+                    end
+                    else begin 
+                        mosiReg3 <= SPIdata[7:0];
+                    end
+                end
+            end
+        end
+    end
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    endmodule

src/src/QuadSPI/QuadSPIs.v

@@ -0,0 +1,402 @@
+module QuadSPIs (
+    input Clk_i,
+    input Rst_i,
+
+    input Sck_i,
+    input Ss_i,
+    input Mosi0_i,
+    input Mosi1_i,
+    input Mosi2_i,
+    input Mosi3_i,
+
+    input [1:0] WidthSel_i,
+    input SelSt_i,
+    input EndianSel_i,
+   
+
+    output reg [23:0] Data_o,
+    output reg [7:0] Addr_o,
+      output [31:0] DataToRxFifo_o,
+    output reg Val_o
+);
+
+//================================================================================
+//	REG/WIRE
+//================================================================================
+
+reg ssReg;
+reg ssRegR; 
+reg SckReg; 
+reg [7:0] addrReg;
+reg [7:0] shiftReg0;
+reg [7:0] shiftReg1;
+reg [7:0] shiftReg2;
+
+reg [7:0] addrRegLSB;
+reg [7:0] shiftReg0LSB;
+reg [7:0] shiftReg1LSB;
+reg [7:0] shiftReg2LSB;
+
+reg [7:0] shiftReg0M;
+reg [7:0] shiftReg1M;
+reg [7:0] shiftReg2M;
+reg [7:0] addrRegM;
+
+
+//===============================================================================
+//  ASSIGNMENTS
+
+
+assign DataToRxFifo_o = {Addr_o, Data_o};
+
+//================================================================================
+//	CODING
+//================================================================================
+
+always	@(posedge	Clk_i)	begin
+	ssReg	<=	Ss_i;
+	ssRegR	<=	ssReg;
+end
+
+
+always @(*) begin 
+    if (Rst_i) begin
+        addrRegM = 8'h0; 
+        shiftReg0M = 8'h0;
+        shiftReg1M = 8'h0;
+        shiftReg2M = 8'h0;
+    end
+    else begin
+        if (EndianSel_i) begin  
+            case(WidthSel_i)  
+                 0: begin 
+                    addrRegM   = addrReg  [1:0];
+                    shiftReg0M = shiftReg0[1:0];
+                    shiftReg1M = shiftReg1[1:0];
+                    shiftReg2M = shiftReg2[1:0];
+                end
+                1: begin 
+                    addrRegM   = addrReg  [3:0];
+                    shiftReg0M = shiftReg0[3:0];
+                    shiftReg1M = shiftReg1[3:0];
+                    shiftReg2M = shiftReg2[3:0];
+                end
+                2: begin 
+                    addrRegM   = addrReg  [5:0];
+                    shiftReg0M = shiftReg0[5:0];
+                    shiftReg1M = shiftReg1[5:0];
+                    shiftReg2M = shiftReg2[5:0];
+                end
+                3: begin 
+                    addrRegM   = addrReg  [7:0];
+                    shiftReg0M = shiftReg0[7:0];
+                    shiftReg1M = shiftReg1[7:0];
+                    shiftReg2M = shiftReg2[7:0];
+                end
+            endcase
+        end
+        else begin 
+            case(WidthSel_i) 
+                    0: begin 
+                        addrRegM   = addrRegLSB[1:0];
+                        shiftReg0M = shiftReg0LSB[1:0];
+                        shiftReg1M = shiftReg1LSB[1:0];
+                        shiftReg2M = shiftReg2LSB[1:0];
+                    end
+                    1: begin 
+                        addrRegM   = addrRegLSB[3:0];
+                        shiftReg0M = shiftReg0LSB[3:0];
+                        shiftReg1M = shiftReg1LSB[3:0];
+                        shiftReg2M = shiftReg2LSB[3:0];
+                    end
+                    2: begin 
+                        addrRegM   = addrRegLSB[5:0];
+                        shiftReg0M = shiftReg0LSB[5:0];
+                        shiftReg1M = shiftReg1LSB[5:0];
+                        shiftReg2M = shiftReg2LSB[5:0];
+                    end
+                    3: begin 
+                        addrRegM   = addrRegLSB[7:0];
+                        shiftReg0M = shiftReg0LSB[7:0];
+                        shiftReg1M = shiftReg1LSB[7:0];
+                        shiftReg2M = shiftReg2LSB[7:0];
+                    end
+            endcase
+        end
+    end
+end
+
+
+always @(posedge Clk_i) begin 
+    if (Rst_i) begin 
+        Data_o <= 24'h0;
+    end
+    else begin
+        if (EndianSel_i) begin 
+            if (SelSt_i) begin  
+                if (ssReg && !ssRegR) begin 
+                    Data_o <= {shiftReg0M, shiftReg1M, shiftReg2M};
+                end
+            end
+            else begin 
+                if (!ssReg && ssRegR) begin 
+                    Data_o <= {shiftReg0M, shiftReg1M, shiftReg2M};
+                end
+            end
+        end
+        else begin 
+            if (SelSt_i) begin  
+                if (ssReg && !ssRegR) begin 
+                    Data_o <= {shiftReg2M, shiftReg1M, shiftReg0M};
+                end
+            end
+            else begin 
+                if (!ssReg && ssRegR) begin 
+                    Data_o <= {shiftReg2M, shiftReg1M, shiftReg0M};
+                end
+            end
+        end
+    end
+end
+
+always @(posedge Clk_i) begin 
+    if (Rst_i) begin 
+        Addr_o <= 8'h0;
+    end
+    else begin
+        if (SelSt_i) begin 
+            if (ssReg && !ssRegR) begin 
+                Addr_o <= addrRegM;
+            end
+        end
+        else begin 
+            if (!ssReg && ssRegR) begin 
+                Addr_o <= addrRegM;
+            end
+        end
+    end
+end
+
+
+
+
+always @(posedge Sck_i) begin 
+    if (Rst_i) begin 
+        shiftReg0 <= 8'h0;
+    end
+    else begin
+        if (SelSt_i) begin   
+            if (!Ss_i) begin 
+                shiftReg0 <= {shiftReg0[6:0], Mosi1_i};
+            end
+            else begin 
+                shiftReg0 <= 8'h0;
+            end
+        end
+        else begin 
+            if (Ss_i) begin 
+                shiftReg0 <= {shiftReg0[6:0], Mosi1_i};
+            end
+            else begin 
+                shiftReg0<= 8'h0;
+            end
+        end
+    end
+end
+
+
+always @(posedge Sck_i ) begin 
+    if (Rst_i) begin 
+        shiftReg1 <= 8'h0;
+    end
+    else begin
+        if (SelSt_i) begin   
+            if (!Ss_i) begin 
+                shiftReg1 <= {shiftReg1[6:0], Mosi2_i};
+            end
+            else begin 
+                shiftReg1 <= 8'h0;
+            end
+        end
+        else begin 
+            if (Ss_i) begin 
+                shiftReg1 <= {shiftReg1[6:0], Mosi2_i};
+            end
+            else begin 
+                shiftReg1 <= 8'h0;
+            end
+        end
+    end
+end
+
+
+always @(posedge Sck_i ) begin 
+    if (Rst_i) begin 
+        shiftReg2 <= 8'h0;
+    end
+    else begin
+        if (SelSt_i) begin   
+            if (!Ss_i) begin 
+                shiftReg2 <= {shiftReg2[6:0], Mosi3_i};
+            end
+            else begin 
+                shiftReg2 <= 8'h0;
+            end
+        end
+        else begin 
+            if (Ss_i) begin 
+                shiftReg2 <= {shiftReg2[6:0], Mosi3_i};
+            end
+            else begin 
+                shiftReg2 <= 8'h0;
+            end
+        end
+    end
+end
+
+
+always @(posedge Sck_i or posedge Rst_i ) begin 
+    if (Rst_i) begin 
+        addrReg <= 8'h0;
+    end
+    else begin
+        if (SelSt_i) begin 
+            if (!Ss_i) begin 
+                addrReg <={addrReg[6:0], Mosi0_i};
+            end
+            else begin 
+                addrReg <= 8'h0;
+            end
+        end
+        else begin 
+            if (Ss_i) begin 
+                addrReg <= {addrReg[6:0], Mosi0_i};
+            end
+            else begin 
+                addrReg <= 8'h0;
+            end
+        end
+    end
+end
+
+always @(posedge Sck_i or posedge Rst_i) begin
+    if (Rst_i) begin 
+        addrRegLSB <= 8'h0;
+    end
+    else begin 
+        if (SelSt_i) begin 
+            if (!Ss_i) begin 
+                addrRegLSB <= {Mosi3_i, addrRegLSB[7:1]};
+            end
+            else begin 
+                addrRegLSB <= 8'h0;
+            end
+        end
+        else begin 
+            if (Ss_i) begin 
+                addrRegLSB <= {Mosi3_i, addrRegLSB[7:1]};
+            end
+            else begin 
+                addrRegLSB <= 8'h0;
+            end
+        end
+    end
+end
+
+always @(posedge Sck_i or posedge Rst_i) begin 
+    if (Rst_i) begin 
+        shiftReg0LSB <= 8'h0;
+    end
+    else begin
+        if (SelSt_i) begin   
+            if (!Ss_i) begin 
+                shiftReg0LSB <= {Mosi0_i, shiftReg0LSB[7:1]};
+            end
+            else begin 
+                shiftReg0LSB <= 8'h0;
+            end
+        end
+        else begin 
+            if (Ss_i) begin 
+                shiftReg0LSB <= {Mosi0_i, shiftReg0LSB[7:1]};
+            end
+            else begin 
+                shiftReg0LSB <= 8'h0;
+            end
+        end
+    end
+end
+
+always @(posedge Sck_i or posedge Rst_i) begin 
+    if (Rst_i) begin 
+        shiftReg1LSB <= 8'h0;
+    end
+    else begin
+        if (SelSt_i) begin   
+            if (!Ss_i) begin 
+                shiftReg1LSB <= {Mosi1_i, shiftReg1LSB[7:1]};
+            end
+            else begin 
+                shiftReg1LSB <= 8'h0;
+            end
+        end
+        else begin 
+            if (Ss_i) begin 
+                shiftReg1LSB <= {Mosi1_i, shiftReg1LSB[7:1]};
+            end
+            else begin 
+                shiftReg1LSB <= 8'h0;
+            end
+        end
+    end
+end
+
+
+always @(posedge Sck_i or posedge Rst_i) begin 
+    if (Rst_i) begin 
+        shiftReg2LSB <= 8'h0;
+    end
+    else begin
+        if (SelSt_i) begin   
+            if (!Ss_i) begin 
+                shiftReg2LSB <= {Mosi2_i, shiftReg2LSB[7:1]};
+            end
+            else begin 
+                shiftReg2LSB <= 8'h0;
+            end
+        end
+        else begin 
+            if (Ss_i) begin 
+                shiftReg2LSB <= {Mosi2_i, shiftReg2LSB[7:1]};
+            end
+            else begin 
+                shiftReg2LSB <= 8'h0;
+            end
+        end
+    end
+end
+
+
+always @(posedge Clk_i) begin
+    if (SelSt_i) begin 
+        if (ssReg && !ssRegR) begin 
+            Val_o <= 1'b1;
+        end
+        else begin 
+            Val_o <= 1'b0;
+        end
+    end
+    else begin 
+        if (!ssReg&& ssRegR) begin 
+            Val_o <= 1'b1;
+        end
+        else begin 
+            Val_o <= 1'b0;
+        end
+    end
+end
+
+
+
+
+endmodule

src/src/SpiR/SPIm.v

@@ -0,0 +1,535 @@
+module SPIm (
+    input Clk_i,
+    input Rst_i,
+    input Start_i,
+    input ClockPhase_i,
+    input [31:0] SpiData_i,
+    input SelSt_i,
+    input [1:0] WidthSel_i,
+    input  Lag_i,
+    input  Lead_i,
+    input EndianSel_i,
+    input [5:0] Stop_i,
+    input PulsePol_i,
+
+
+    output reg Mosi0_o,
+    output reg Sck_o,
+    output  Ss_o,
+    output reg  Val_o
+);
+
+
+//================================================================================
+//	REG/WIRE
+//================================================================================
+
+    reg startFlag;
+    reg startR;
+    reg [31:0] trCnt;
+    reg valReg;
+    reg valToRxFifo1;
+    reg lineBusy;
+    reg [5:0] ssCnt;
+    reg Ss;
+    reg [31:0]spiDataR;
+    reg oldDataFlag;
+    
+    reg ssR;
+    reg SSR;
+    reg [31:0] mosiReg0;
+    reg [5:0] ssNum;
+    reg [2:0] delayCnt;
+    reg stopFlag;
+    
+    wire ssPol = SelSt_i ? Ss : ~Ss;
+    
+    
+    //================================================================================
+    //  ASSIGNMENTS
+    //================================================================================
+    
+    
+    assign Ss_o = ssPol; 
+    
+    //================================================================================
+    //	CODING
+    //================================================================================
+    
+    always @(*) begin 
+        if (Start_i) begin  
+            Val_o = valReg;
+        end
+        else begin 
+            Val_o = 1'b0;
+        end
+    end
+    
+    
+    always @(*) begin 
+        if (SelSt_i) begin 
+            if (!Ss_o) begin 
+                lineBusy = 1'b1;
+            end
+            else begin 
+                lineBusy = 1'b0;
+            end
+        end
+        else begin 
+            if (Ss_o) begin 
+                lineBusy = 1'b1;
+            end
+            else begin 
+                lineBusy = 1'b0;
+            end
+        end
+    end
+    
+    
+    
+    always @(posedge Clk_i) begin
+        if (valReg) begin  
+            spiDataR <= SpiData_i;
+        end
+    end
+    
+    
+    always @(*) begin 
+        if (Rst_i) begin 
+            oldDataFlag = 1'b0;
+        end
+        else begin 
+            if (spiDataR == SpiData_i) begin 
+                oldDataFlag = 1'b1;
+            end
+            else begin 
+                oldDataFlag = 1'b0;
+            end
+        end
+    end
+    
+    
+    always @(posedge Clk_i) begin 
+        startR <= Start_i;
+    end
+    
+    always @(*) begin 
+        if (Rst_i) begin 
+            valToRxFifo1 = 1'b0;
+        end
+        else begin 
+            if (Start_i && !startR) begin 
+                valToRxFifo1 = 1'b1;
+            end
+            else begin 
+                valToRxFifo1 = 1'b0;
+            end
+        end
+    end
+    
+    always @(negedge Clk_i) begin 
+        if (Rst_i) begin 
+            delayCnt <= 1'b0;
+        end
+        else begin 
+            if (stopFlag &&delayCnt < Stop_i) begin 
+                delayCnt <= delayCnt + 1'b1;
+            end
+            else begin 
+                delayCnt <= 1'b0;
+            end
+        end
+    end
+    
+    always @(posedge Clk_i) begin 
+        if (Rst_i) begin 
+            stopFlag <= 1'b0;
+        end
+        else begin
+            if (SelSt_i) begin 
+                if (ssPol && !ssR) begin 
+                    stopFlag <= 1'b1;
+                end
+                else if ( delayCnt == Stop_i) begin 
+                    stopFlag <= 1'b0;
+                end
+            end
+            else begin 
+                if (!ssPol && ssR) begin 
+                    stopFlag <= 1'b1;
+                end
+                else if (delayCnt == Stop_i) begin 
+                    stopFlag <= 1'b0;
+                end
+            end
+        end
+    end
+    
+    
+    
+    
+    always @(*) begin
+        if (SelSt_i) begin 
+            if (PulsePol_i) begin 
+                if (ClockPhase_i) begin
+                    if (Lead_i == 0) begin 
+                        if (!Ss && (ssCnt <= ssNum+Lag_i+Lead_i && ssCnt > Lag_i) ) begin 
+                            Sck_o = ~(~Clk_i);
+                        end
+                        else begin 
+                            Sck_o = 1'b0;
+                        end
+                    end
+                    else begin 
+                        if (!Ss && (ssCnt < ssNum+Lag_i+Lead_i && ssCnt > Lag_i)) begin 
+                            Sck_o = ~(~Clk_i);
+                        end
+                        else begin 
+                            Sck_o = 1'b0;
+                        end
+                    end
+                end
+                else begin
+                    if (Lead_i == 0) begin 
+                        if (!Ss && (ssCnt <= ssNum+Lag_i+Lead_i && ssCnt > Lag_i) ) begin 
+                            Sck_o = ~(Clk_i);
+                        end
+                        else begin 
+                            Sck_o = 1'b0;
+                        end
+                    end
+                    else begin 
+                        if (!Ss && (ssCnt < ssNum + Lag_i + Lead_i && ssCnt > Lag_i)) begin 
+                            Sck_o = ~(Clk_i);
+                        end
+                        else begin 
+                            Sck_o = 1'b0;
+                        end
+                    end
+                end
+            end
+            else begin 
+                if (ClockPhase_i) begin
+                    if (Lead_i == 0) begin  
+                        if (!Ss && (ssCnt <= ssNum+Lag_i+Lead_i && ssCnt > Lag_i) ) begin 
+                            Sck_o = ~(Clk_i);
+                        end
+                        else begin 
+                            Sck_o = 1'b0;
+                        end
+                    end
+                    else begin 
+                        if (!Ss && (ssCnt <ssNum + Lag_i + Lag_i && ssCnt > Lag_i)) begin 
+                            Sck_o = ~(Clk_i);
+                        end
+                        else begin 
+                            Sck_o = 1'b0;
+                        end
+                    end
+                end 
+                else begin
+                    if (Lead_i == 0) begin 
+                        if (!Ss && (ssCnt <= ssNum+Lag_i+Lead_i && ssCnt > Lag_i) ) begin 
+                            Sck_o = ~(~Clk_i);
+                        end
+                        else begin 
+                            Sck_o = 1'b0;
+                        end
+                    end
+                    else begin 
+                        if (!Ss && (ssCnt < ssNum + Lag_i + Lead_i && ssCnt > Lag_i)) begin 
+                            Sck_o = ~(~Clk_i);
+                        end
+                        else begin 
+                            Sck_o = 1'b0;
+                        end
+                    end
+                end
+            end
+        end
+        else begin 
+              if (PulsePol_i) begin 
+                if (ClockPhase_i) begin
+                    if (Lead_i == 0) begin 
+                        if (ssPol && (ssCnt <= ssNum+Lag_i+Lead_i && ssCnt > Lag_i) ) begin 
+                            Sck_o = ~(~Clk_i);
+                        end
+                        else begin 
+                            Sck_o = 1'b0;
+                        end
+                    end
+                    else begin 
+                        if (ssPol && (ssCnt < ssNum+Lag_i+Lead_i && ssCnt > Lag_i)) begin 
+                            Sck_o = ~(~Clk_i);
+                        end
+                        else begin 
+                            Sck_o = 1'b0;
+                        end
+                    end
+                end
+                else begin
+                    if (Lead_i == 0) begin 
+                        if (ssPol && (ssCnt <= ssNum+Lag_i+Lead_i && ssCnt > Lag_i) ) begin 
+                            Sck_o = ~(Clk_i);
+                        end
+                        else begin 
+                            Sck_o = 1'b0;
+                        end
+                    end
+                    else begin 
+                        if (ssPol && (ssCnt < ssNum + Lag_i + Lead_i && ssCnt > Lag_i)) begin 
+                            Sck_o = ~(Clk_i);
+                        end
+                        else begin 
+                            Sck_o = 1'b0;
+                        end
+                    end
+                end
+            end
+            else begin 
+                if (ClockPhase_i) begin
+                    if (Lead_i == 0) begin  
+                        if (ssPol && (ssCnt <= ssNum+Lag_i+Lead_i && ssCnt > Lag_i) ) begin 
+                            Sck_o = ~(Clk_i);
+                        end
+                        else begin 
+                            Sck_o = 1'b0;
+                        end
+                    end
+                    else begin 
+                        if (ssPol && (ssCnt <ssNum + Lag_i + Lag_i && ssCnt > Lag_i)) begin 
+                            Sck_o = ~(Clk_i);
+                        end
+                        else begin 
+                            Sck_o = 1'b0;
+                        end
+                    end
+                end 
+                else begin
+                    if (Lead_i == 0) begin 
+                        if (ssPol && (ssCnt <= ssNum+Lag_i+Lead_i && ssCnt > Lag_i) ) begin 
+                            Sck_o = ~(~Clk_i);
+                        end
+                        else begin 
+                            Sck_o = 1'b0;
+                        end
+                    end
+                    else begin 
+                        if (ssPol && (ssCnt < ssNum + Lag_i + Lead_i && ssCnt > Lag_i)) begin 
+                            Sck_o = ~(~Clk_i);
+                        end
+                        else begin 
+                            Sck_o = 1'b0;
+                        end
+                    end
+                end
+            end
+        end
+            
+    end
+    
+    
+    always @(*) begin
+        if (Rst_i) begin 
+            Mosi0_o = 1'b0;
+        end
+        else begin
+            if (SelSt_i) begin 
+                if (!EndianSel_i) begin 
+                    case (WidthSel_i)  
+                        0 : begin
+                            Mosi0_o = (!Ss&& (ssCnt <= ssNum+Lag_i && ssCnt > Lag_i))? (mosiReg0[7]):1'b0;
+                        end
+                        1 : begin
+                            Mosi0_o = (!Ss&& (ssCnt <= ssNum+Lag_i && ssCnt > Lag_i))? (mosiReg0[15]):1'b0;
+                        end
+                        2 : begin
+                            Mosi0_o = (!Ss&& (ssCnt <= ssNum+Lag_i && ssCnt > Lag_i))? (mosiReg0[23]):1'b0;
+                        end
+                        3 : begin
+                            Mosi0_o = (!Ss&& (ssCnt <= ssNum+Lag_i && ssCnt > Lag_i))? (mosiReg0[31]):1'b0;
+                        end
+                    endcase
+                end
+                else begin 
+                    case (WidthSel_i)  
+                        0 : begin
+                            Mosi0_o = (!Ss&& (ssCnt <= ssNum+Lag_i && ssCnt > Lag_i))? (mosiReg0[0]):1'b0;
+                        end
+                        1 : begin
+                            Mosi0_o = (!Ss&& (ssCnt <= ssNum+Lag_i && ssCnt > Lag_i))? (mosiReg0[0]):1'b0;
+                        end
+                        2 : begin
+                            Mosi0_o = (!Ss&& (ssCnt <= ssNum+Lag_i && ssCnt > Lag_i))? (mosiReg0[0]):1'b0;
+                        end
+                        3 : begin
+                            Mosi0_o = (!Ss&& (ssCnt <= ssNum+Lag_i && ssCnt > Lag_i))? (mosiReg0[0]):1'b0;
+                        end
+                    endcase
+                end
+            end
+            else begin 
+                if (!EndianSel_i) begin 
+                    case (WidthSel_i)  
+                        0 : begin
+                            Mosi0_o = (ssPol&& (ssCnt <= ssNum+Lag_i && ssCnt > Lag_i))? (mosiReg0[7]):1'b0;
+                        end
+                        1 : begin
+                            Mosi0_o = (ssPol&& (ssCnt <= ssNum+Lag_i && ssCnt > Lag_i))? (mosiReg0[15]):1'b0;
+                        end
+                        2 : begin
+                            Mosi0_o = (ssPol&& (ssCnt <= ssNum+Lag_i && ssCnt > Lag_i))? (mosiReg0[23]):1'b0;
+                        end
+                        3 : begin
+                            Mosi0_o = (ssPol&& (ssCnt <= ssNum+Lag_i && ssCnt > Lag_i))? (mosiReg0[31]):1'b0;
+                        end
+                    endcase
+                end
+                else begin 
+                    case (WidthSel_i)  
+                        0 : begin
+                            Mosi0_o = (ssPol&& (ssCnt <= ssNum+Lag_i && ssCnt > Lag_i))? (mosiReg0[0]):1'b0;
+                        end
+                        1 : begin
+                            Mosi0_o = (ssPol&& (ssCnt <= ssNum+Lag_i && ssCnt > Lag_i))? (mosiReg0[0]):1'b0;
+                        end
+                        2 : begin
+                            Mosi0_o = (ssPol&& (ssCnt <= ssNum+Lag_i && ssCnt > Lag_i))? (mosiReg0[0]):1'b0;
+                        end
+                        3 : begin
+                            Mosi0_o = (ssPol&& (ssCnt <= ssNum+Lag_i && ssCnt > Lag_i))? (mosiReg0[0]):1'b0;
+                        end
+                    endcase
+                end
+            end
+        end
+    end
+    
+    
+    
+    always @(posedge Clk_i) begin
+        ssR <= ssPol;
+        SSR <= Ss;
+    end
+    
+    
+    always @(*) begin 
+        if (Rst_i) begin 
+            startFlag = 1'b0;
+        end
+        else begin 
+            if (Start_i&& !stopFlag && SpiData_i != 0 && !oldDataFlag ) begin 
+                startFlag = 1'b1;
+            end
+            else begin 
+                startFlag = 1'b0;
+            end
+        end
+    end
+    
+    always @(*) begin
+        if (SelSt_i) begin 
+            if (Ss_o && !ssR) begin 
+                valReg = 1'b1;
+            end
+            else begin 
+                valReg = 1'b0;
+            end
+        end
+        else begin 
+            if (!Ss_o&& ssR) begin 
+                valReg = 1'b1;
+            end
+            else begin 
+                valReg = 1'b0;
+            end
+        end
+    end
+    
+    
+    always @(*) begin 
+        if (Rst_i) begin 
+            ssNum = 1'b0;
+        end
+        else begin 
+            case (WidthSel_i) 
+                0 : begin 
+                    ssNum = 8;
+                end
+                1 : begin 
+                    ssNum = 16;
+                end
+                2 : begin 
+                    ssNum = 24;
+                end
+                3 : begin 
+                    ssNum = 32;
+                end
+            endcase
+        end
+    end
+    
+    
+    always @(negedge Clk_i) begin 
+        if (Rst_i) begin 
+            ssCnt <= 1'b0;
+        end
+        else if (ssCnt <= (ssNum+Lag_i+Lead_i)  && startFlag  ) begin 
+            ssCnt <= ssCnt + 1'b1;
+        end
+        else begin
+            if (ssCnt == ssNum-1 || !startFlag) begin 
+                ssCnt <= 1'b0;
+            end
+        end
+    end
+    
+    
+    
+    
+    always @(negedge Clk_i) begin 
+        if (Rst_i) begin 
+            Ss <= 1'b1;
+        end
+        else begin 
+            if (ssCnt <= (ssNum+Lag_i+Lead_i)  && startFlag ) begin 
+                Ss <= 1'b0;
+            end
+            else begin 
+                Ss <= 1'b1;
+            end
+        end
+    end
+    
+    
+    always @(negedge Clk_i) begin 
+        if (Rst_i) begin 
+            mosiReg0 <= SpiData_i[31:0];
+        end
+        else begin
+            if (!EndianSel_i) begin 
+                if (!SSR && (ssCnt > Lag_i && ssCnt < ssNum + Lag_i + Lead_i)) begin
+                    mosiReg0 <= mosiReg0 << 1;
+                end
+                else begin 
+                    mosiReg0 <= SpiData_i[31:0];
+                end
+            end
+            else begin 
+                if (!SSR && (ssCnt > Lag_i && ssCnt < ssNum + Lag_i + Lead_i)) begin
+                    mosiReg0 <= mosiReg0 >> 1;
+                end
+                else begin 
+                    mosiReg0 <= SpiData_i[31:0];
+                end
+            end
+        end
+    end
+    
+    
+    
+    
+    
+    
+    
+    endmodule

src/src/SpiR/SPIm_tb.v

@@ -0,0 +1,149 @@
+`timescale 1ns/1ps
+
+module tb_SPIm;
+
+    // Parameters
+    parameter CLK_PERIOD = 8.13; // Clock period in ns
+
+    // Inputs
+    reg Clk_i;
+    reg Rst_i;
+    reg Start_i;
+    reg CPHA_i;
+    reg [31:0] SPIdata;
+	reg SpiDataVal_i;
+    reg SelSt_i;
+    reg [1:0] WidthSel_i;
+    reg Lag_i;
+    reg Lead_i;
+    reg EndianSel_i;
+    reg [5:0] Stop_i;
+    reg PulsePol_i;
+
+    // Outputs
+    wire Mosi0_o;
+    wire Mosi1_o;
+    wire Mosi2_o;
+    wire Mosi3_o;
+    wire Sck_o;
+    wire Ss_o;
+    wire Val_o;
+
+    SPIm SPIm_inst (
+        .Clk_i(Clk_i), 
+        .Rst_i(Rst_i), 
+        .Start_i(Start_i), 
+        .ClockPhase_i(CPHA_i), 
+        .SpiData_i(SPIdata),
+        .SelSt_i(SelSt_i),
+        .WidthSel_i(WidthSel_i),
+        .Lag_i(Lag_i),
+        .Lead_i(Lead_i),
+        .EndianSel_i(EndianSel_i),
+        .Stop_i(Stop_i),
+        .PulsePol_i(PulsePol_i),
+        .Mosi0_o(Mosi0_o),
+        .Sck_o(Sck_o),
+        .Ss_o(Ss_o),
+        .Val_o(Val_o)
+    );
+
+
+    SPIs SPIs_inst (
+        .Clk_i(Clk_i), 
+        .Rst_i(Rst_i), 
+        .Sck_i(Sck_o), 
+        .Ss_i(Ss_o), 
+        .Mosi0_i(Mosi0_o), 
+        .WidthSel_i(WidthSel_i), 
+        .EndianSel_i(EndianSel_i),
+        .SelSt_i(SelSt_i), 
+        .Data_o(), 
+        .Addr_o(), 
+        .DataToRxFifo_o(), 
+        .Val_o()
+    );
+
+
+    // QuadSPIm QuadSPIm_inst (
+    //     .Clk_i(Clk_i),
+    //     .Rst_i(Rst_i),
+    //     .Start_i(Start_i),
+    //     .ClockPhase_i(CPHA_i),
+    //     .SpiData_i(SPIdata),
+    //     .SpiDataVal_i(SpiDataVal_i),
+    //     .SelSt_i(SelSt_i),
+    //     .WidthSel_i(WidthSel_i),
+    //     .Lag_i(Lag_i),
+    //     .Lead_i(Lead_i),
+    //     .EndianSel_i(EndianSel_i),
+    //     .Stop_i(Stop_i),
+    //     .PulsePol_i(PulsePol_i),
+    //     .Mosi0_i(Mosi0_o),
+    //     .Mosi1_i(Mosi1_o),
+    //     .Mosi2_i(Mosi2_o),
+    //     .Mosi3_i(Mosi3_o),
+    //     .Sck_o(Sck_o),
+    //     .Ss_o(Ss_o),
+    //     .Val_o(Val_o)
+    // );
+
+
+
+    // QuadSPIs QuadSPIs_inst (
+    //     .Clk_i(Clk_i),
+    //     .Rst_i(Rst_i),
+    //     .Sck_i(Sck_o),
+    //     .Ss_i(Ss_o),
+    //     .Mosi0_i(Mosi0_o),
+    //     .Mosi1_i(Mosi1_o),
+    //     .Mosi2_i(Mosi2_o),
+    //     .Mosi3_i(Mosi3_o),
+    //     .WidthSel_i(WidthSel_i),
+    //     .EndianSel_i(EndianSel_i),
+    //     .SelSt_i(SelSt_i),
+    //     .Data_o(),
+    //     .Addr_o(),
+    //     .DataToRxFifo_o(),
+    //     .Val_o()
+    // );
+
+    // Clock generation
+    always #(CLK_PERIOD/2) Clk_i = ~Clk_i;
+
+    // Initial setup and test sequence
+    initial begin
+        // Initialize Inputs
+        Clk_i = 0;
+        Rst_i = 1;
+        Start_i = 0;
+        CPHA_i = 0;
+		SpiDataVal_i = 0;
+        SPIdata = 32'h00000000;
+        SelSt_i = 1;//0:High, 1:Low
+        WidthSel_i = 3; // Full 32-bit width
+        Lag_i = 0;
+        Lead_i = 0;
+        EndianSel_i = 0; // 0:MSB first, 1:lsb first
+        Stop_i = 6'd0;
+        PulsePol_i = 0;
+
+        // Reset the system
+        #(CLK_PERIOD*10) Rst_i = 0;
+        #(CLK_PERIOD*2) Start_i = 1; // Start SPI transaction
+        #(CLK_PERIOD*10)SPIdata =  {16'h2,16'h1};
+        //    #(CLK_PERIOD*10)SPIdata =  32'haa;
+
+    
+        #(CLK_PERIOD*100);
+           SPIdata = {1'h0, 7'h2a, 24'd10};
+
+        // EndianSel_i = 1; // LSB first
+        // SPIdata = {1'h0, 7'h2a, 8'haa,8'h00,8'haa}; 
+        // #(CLK_PERIOD*2) Start_i = 0; 
+        // #(CLK_PERIOD) Start_i = 1;
+
+      
+    end
+
+endmodule

src/src/SpiR/SPIs.v

@@ -0,0 +1,178 @@
+module SPIs (
+    input Clk_i,
+    input Rst_i,
+
+    input Sck_i,
+    input Ss_i,
+    input Mosi0_i,
+    input [1:0] WidthSel_i,
+    input EndianSel_i,
+    input SelSt_i,
+   
+
+    output reg [23:0] Data_o,
+    output reg [7:0] Addr_o,
+    output [31:0] DataToRxFifo_o,
+    output reg Val_o
+);
+
+//================================================================================
+//	REG/WIRE
+//================================================================================
+
+    reg ssReg;
+    reg ssRegR;  
+    reg [31:0] shiftReg;
+    
+    reg [31:0] shiftRegM; 
+ 
+
+//===============================================================================
+//  ASSIGNMENTS
+
+
+    assign DataToRxFifo_o = {Addr_o, Data_o};
+
+//================================================================================
+//	CODING
+//================================================================================
+
+    always	@(posedge	Clk_i)	begin
+    	ssReg	<=	Ss_i;
+    	ssRegR	<=	ssReg;
+    end
+
+
+    always @(*) begin 
+        if (Rst_i) begin
+          shiftRegM = 32'h0;
+        end
+        else begin 
+            case(WidthSel_i)  
+                 0: begin 
+                    shiftRegM = shiftReg[7:0];
+                end
+                1: begin 
+                    shiftRegM = shiftReg[15:0];
+                end
+                2: begin 
+                    shiftRegM = shiftReg[23:0];
+                end
+                3: begin 
+                    shiftRegM = shiftReg[31:0];
+                end
+            endcase
+        end
+    end
+
+
+
+    always @(posedge Clk_i) begin 
+        if (Rst_i) begin 
+            Data_o <= 24'h0;
+        end
+        else begin
+            if (SelSt_i) begin  
+                if (ssReg && !ssRegR) begin 
+                    Data_o <= shiftRegM;
+                end
+            end
+            else begin 
+                if (!ssReg && ssRegR) begin 
+                    Data_o <= shiftRegM[23:0];
+                end
+            end
+        end
+    end
+
+    always @(posedge Clk_i) begin 
+        if (Rst_i) begin 
+            Addr_o <= 8'h0;
+        end
+        else begin
+            if (SelSt_i) begin 
+                if (ssReg && !ssRegR) begin 
+                    Addr_o <= shiftRegM[31:24];
+                end
+            end
+            else begin 
+                if (!ssReg && ssRegR) begin 
+                    Addr_o <= shiftRegM[31:24];
+                end
+            end
+        end
+    end
+
+
+
+
+    always @(posedge Sck_i or posedge Rst_i) begin 
+        if (Rst_i) begin 
+            shiftReg<= 32'h0;
+        end
+        else begin
+            if (!EndianSel_i) begin 
+                if (SelSt_i) begin   
+                    if (!Ss_i) begin 
+                        shiftReg<= {shiftReg[30:0], Mosi0_i};
+                    end
+                    else begin 
+                        shiftReg<= 32'h0;
+                    end
+                end
+                else begin 
+                    if (Ss_i) begin 
+                        shiftReg<= {shiftReg[30:0], Mosi0_i};
+                    end
+                    else begin 
+                        shiftReg<= 32'h0;
+                    end
+                end
+            end
+            else begin 
+                if (SelSt_i) begin   
+                    if (!Ss_i) begin 
+                        shiftReg<= {Mosi0_i, shiftReg[31:1]};
+                    end
+                    else begin 
+                        shiftReg<= 32'h0;
+                    end
+                end
+                else begin 
+                    if (Ss_i) begin 
+                        shiftReg<= {Mosi0_i, shiftReg[31:1]};
+                    end
+                    else begin 
+                        shiftReg<= 32'h0;
+                    end
+                end
+            end
+        end
+    end
+
+
+
+
+    always @(posedge Clk_i) begin
+        if (SelSt_i) begin 
+            if (ssReg && !ssRegR) begin 
+                Val_o <= 1'b1;
+            end
+            else begin 
+                Val_o <= 1'b0;
+            end
+        end
+        else begin 
+            if (!ssReg&& ssRegR) begin 
+                Val_o <= 1'b1;
+            end
+            else begin 
+                Val_o <= 1'b0;
+            end
+        end
+    end
+
+
+
+
+    endmodule

src/src/Top/S5443_3Top.v

@@ -0,0 +1,950 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 10/30/2023 11:24:31 AM
+// Design Name: 
+// Module Name: S5443_3Top
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module S5443_3Top 
+#(
+    parameter CmdRegWidth = 32,
+    parameter AddrRegWidth = 12,
+    parameter STAGES = 2,
+    parameter SpiNum = 7
+
+)
+(
+    input Clk123_i,
+    input [AddrRegWidth-2:0] SmcAddr_i,
+    inout [CmdRegWidth/2-1:0] SmcData_io,
+    
+    input SmcAwe_i,
+    input SmcAmsN_i,
+	
+    input SmcAre_i,
+    input [1:0] SmcBe_i,
+    input SmcAoe_i,
+    output [SpiNum-1:0] Ld_o,
+
+    output  Led_o,
+   
+    output  [SpiNum-1:0] Mosi0_o, 
+    inout   [SpiNum-1:0] Mosi1_io,//inout: when RSPI mode, input; when QSPI mode output; 
+    output  [SpiNum-1:0] Mosi2_o,
+    output  [SpiNum-1:0] Mosi3_o,
+    output  [SpiNum-1:0] Ss_o,
+    output  [SpiNum-1:0] SsFlash_o,
+    output  [SpiNum-1:0] Sck_o,
+    output  [SpiNum-1:0] SpiRst_o,
+    output  [SpiNum-1:0] SpiDir_o,
+    output  LD_o
+
+);
+
+//================================================================================
+//  REG/WIRE
+//================================================================================
+    wire clk80;
+    wire [SpiNum-1:0]sckMuxed;
+    wire [AddrRegWidth-1:0] addrExt;
+    wire [SpiNum-1:0] ssMuxed; 
+    wire [SpiNum-1:0]mosi0;
+    wire [SpiNum-1:0]mosi1;
+    wire [SpiNum-1:0]mosi2;
+    wire [SpiNum-1:0]mosi3;
+    wire [SpiNum-1:0] txEn;
+    wire [SpiNum-1:0] spiTxEnSync;
+    wire initRst;
+    wire gclk;
+    wire [0:7] baudRate [SpiNum-1:0];
+    
+    wire [0:31] txFifoCtrlReg [SpiNum-1:0];
+    wire [0:31] rxFifoCtrlReg [SpiNum-1:0];
+    
+    
+    
+    
+    
+    //InitRst
+    
+    wire [SpiNum-1:0] initRstGen;
+    wire rst80;
+
+    //SPI0
+    wire [CmdRegWidth-1:0] spi0Ctrl;
+    wire [CmdRegWidth-1:0] spi0Clk;
+    wire [CmdRegWidth-1:0] spi0CsDelay;
+    wire [CmdRegWidth-1:0] spi0CsCtrl;
+    wire [CmdRegWidth-1:0] spi0TxFifoCtrl;
+    wire [CmdRegWidth-1:0] spi0RxFifoCtrl;
+    wire [CmdRegWidth-1:0] spi0TxFifo;
+    wire [CmdRegWidth-1:0] spi0RxFifo;
+    wire [CmdRegWidth-1:0] spi0TxFifoCtrlReg;
+    wire [CmdRegWidth-1:0] spi0RxFifoCtrlReg;
+    
+    wire [CmdRegWidth-1:0] spi0CtrlRR;
+    wire [CmdRegWidth-1:0] spi0ClkRR;
+    wire [CmdRegWidth-1:0] spi0CsDelayRR;
+    wire [CmdRegWidth-1:0] spi0CsCtrlRR;
+    wire [CmdRegWidth-1:0] spi0TxFifoCtrlRR;
+    wire [CmdRegWidth-1:0] spi0RxFifoCtrlRR;
+    
+    //SPI1
+    wire [CmdRegWidth-1:0] spi1Ctrl;
+    wire [CmdRegWidth-1:0] spi1Clk;
+    wire [CmdRegWidth-1:0] spi1CsDelay;
+    wire [CmdRegWidth-1:0] spi1CsCtrl;
+    wire [CmdRegWidth-1:0] spi1TxFifoCtrl;
+    wire [CmdRegWidth-1:0] spi1RxFifoCtrl;
+    wire [CmdRegWidth-1:0] spi1TxFifoCtrlReg;
+    wire [CmdRegWidth-1:0] spi1RxFifoCtrlReg;
+
+    wire [CmdRegWidth-1:0] spi1CtrlRR;
+    wire [CmdRegWidth-1:0] spi1CsDelayRR;
+    wire [CmdRegWidth-1:0] spi1CsCtrlRR;
+    wire [CmdRegWidth-1:0] spi1TxFifoCtrlRR;
+    wire [CmdRegWidth-1:0] spi1RxFifoCtrlRR;
+
+    //SPI2
+    wire [CmdRegWidth-1:0] spi2Ctrl;
+    wire [CmdRegWidth-1:0] spi2Clk;
+    wire [CmdRegWidth-1:0] spi2CsDelay;
+    wire [CmdRegWidth-1:0] spi2CsCtrl;
+    wire [CmdRegWidth-1:0] spi2TxFifoCtrl;
+    wire [CmdRegWidth-1:0] spi2RxFifoCtrl;
+    wire [CmdRegWidth-1:0] spi2TxFifoCtrlReg;
+    wire [CmdRegWidth-1:0] spi2RxFifoCtrlReg;
+
+    wire [CmdRegWidth-1:0] spi2CtrlRR;
+    wire [CmdRegWidth-1:0] spi2CsDelayRR;
+    wire [CmdRegWidth-1:0] spi2CsCtrlRR;
+    wire [CmdRegWidth-1:0] spi2TxFifoCtrlRR;
+    wire [CmdRegWidth-1:0] spi2RxFifoCtrlRR;
+
+    //SPI3
+    wire [CmdRegWidth-1:0] spi3Ctrl;
+    wire [CmdRegWidth-1:0] spi3Clk;
+    wire [CmdRegWidth-1:0] spi3CsDelay;
+    wire [CmdRegWidth-1:0] spi3CsCtrl;
+    wire [CmdRegWidth-1:0] spi3TxFifoCtrl;
+    wire [CmdRegWidth-1:0] spi3RxFifoCtrl;
+    wire [CmdRegWidth-1:0] spi3TxFifoCtrlReg;
+    wire [CmdRegWidth-1:0] spi3RxFifoCtrlReg;
+
+    wire [CmdRegWidth-1:0] spi3CtrlRR;
+    wire [CmdRegWidth-1:0] spi3ClkRR;
+    wire [CmdRegWidth-1:0] spi3CsDelayRR;
+    wire [CmdRegWidth-1:0] spi3CsCtrlRR;
+    wire [CmdRegWidth-1:0] spi3TxFifoCtrlRR;
+    wire [CmdRegWidth-1:0] spi3RxFifoCtrlRR;
+
+    //SPI4
+    wire [CmdRegWidth-1:0] spi4Ctrl;
+    wire [CmdRegWidth-1:0] spi4Clk;
+    wire [CmdRegWidth-1:0] spi4CsDelay;
+    wire [CmdRegWidth-1:0] spi4CsCtrl;
+    wire [CmdRegWidth-1:0] spi4TxFifoCtrl;
+    wire [CmdRegWidth-1:0] spi4RxFifoCtrl;
+    wire [CmdRegWidth-1:0] spi4TxFifoCtrlReg;
+    wire [CmdRegWidth-1:0] spi4RxFifoCtrlReg;
+
+    wire [CmdRegWidth-1:0] spi4CtrlRR;
+    wire [CmdRegWidth-1:0] spi4ClkRR;
+    wire [CmdRegWidth-1:0] spi4CsDelayRR;
+    wire [CmdRegWidth-1:0] spi4CsCtrlRR;
+    wire [CmdRegWidth-1:0] spi4TxFifoCtrlRR;
+    wire [CmdRegWidth-1:0] spi4RxFifoCtrlRR;
+    
+    //SPI5
+    wire [CmdRegWidth-1:0] spi5Ctrl;
+    wire [CmdRegWidth-1:0] spi5Clk;
+    wire [CmdRegWidth-1:0] spi5CsDelay;
+    wire [CmdRegWidth-1:0] spi5CsCtrl;
+    wire [CmdRegWidth-1:0] spi5TxFifoCtrl;
+    wire [CmdRegWidth-1:0] spi5RxFifoCtrl;
+    wire [CmdRegWidth-1:0] spi5TxFifoCtrlReg;
+    wire [CmdRegWidth-1:0] spi5RxFifoCtrlReg;
+
+    wire [CmdRegWidth-1:0] spi5CtrlRR;
+    wire [CmdRegWidth-1:0] spi5ClkRR;
+    wire [CmdRegWidth-1:0] spi5CsDelayRR;
+    wire [CmdRegWidth-1:0] spi5CsCtrlRR;
+    wire [CmdRegWidth-1:0] spi5TxFifoCtrlRR;
+    wire [CmdRegWidth-1:0] spi5RxFifoCtrlRR;
+
+    //SPI6
+    wire [CmdRegWidth-1:0] spi6Ctrl;
+    wire [CmdRegWidth-1:0] spi6Clk;
+    wire [CmdRegWidth-1:0] spi6CsDelay;
+    wire [CmdRegWidth-1:0] spi6CsCtrl;
+    wire [CmdRegWidth-1:0] spi6TxFifoCtrl;
+    wire [CmdRegWidth-1:0] spi6RxFifoCtrl;
+    wire [CmdRegWidth-1:0] spi6TxFifoCtrlReg;
+    wire [CmdRegWidth-1:0] spi6RxFifoCtrlReg;
+
+    wire [CmdRegWidth-1:0] spi6CtrlRR;
+    wire [CmdRegWidth-1:0] spi6ClkRR;
+    wire [CmdRegWidth-1:0] spi6CsDelayRR;
+    wire [CmdRegWidth-1:0] spi6CsCtrlRR;
+    wire [CmdRegWidth-1:0] spi6TxFifoCtrlRR;
+    wire [CmdRegWidth-1:0] spi6RxFifoCtrlRR;
+
+    
+    
+    wire [CmdRegWidth-1:0] spiTxRxEn;
+    wire [CmdRegWidth-1:0] GPIOA;
+    wire [CmdRegWidth-1:0] GPIOASync;
+    
+    
+    wire	[AddrRegWidth-1:0]	toRegMapAddr;
+    wire	[CmdRegWidth/2-1:0]	toRegMapData;
+    wire	toRegMapVal;
+    
+    wire	[SpiNum-1:0]	toFifoVal;
+    wire	[CmdRegWidth*SpiNum-1:0]	toFifoData;
+    
+    wire	[SpiNum-1:0]	toSpiVal;
+    wire	[0:31]	toSpiData [SpiNum-1:0];
+    
+    wire [0:1] widthSel [SpiNum-1:0];
+    wire [SpiNum-1:0] clockPol;
+    wire [SpiNum-1:0] clockPhase;
+    wire [SpiNum-1:0] endianSel;
+    wire [SpiNum-1:0] selSt;
+    wire [SpiNum-1:0] spiMode;
+    
+    
+    wire [0:5] stopDelay [SpiNum-1:0];
+    wire [SpiNum-1:0] leadx;
+    wire [SpiNum-1:0] lag; 
+    wire [SpiNum-1:0] fifoRxRst;
+    wire [SpiNum-1:0] fifoTxRst;
+    wire [SpiNum-1:0] fifoRxRstRdPtr;
+    wire [SpiNum-1:0] fifoTxRstWrPtr;
+    wire [0:7]  wordCntTx [SpiNum-1:0];
+    wire [0:7]  wordCntRx [SpiNum-1:0];
+    
+    
+    wire [SpiNum-1:0] chipSelFpga;
+    wire [SpiNum-1:0] chipSelFlash;
+    
+    wire [SpiNum-1:0] assel;
+    
+    wire	[SpiNum-1:0]	spiClkBus;
+    wire	[SpiNum-1:0]	spiSyncRst;
+    wire	[AddrRegWidth-1:0]	smcAddr;
+    wire	[CmdRegWidth/2-1:0]	smcData;
+    wire	smcVal;
+    //RxFifo 
+    wire [0:31] dataToRxFifo [SpiNum-1:0];
+    wire [0:7] addrToRxFifo [SpiNum-1:0];
+    wire [SpiNum-1:0] valToRxFifo;
+    wire [SpiNum-1:0] valToTxFifoRead;
+    
+    
+    // SPI mode choice 
+    wire [SpiNum-1:0] sckR; 
+    wire [SpiNum-1:0] ssR;
+    wire [SpiNum-1:0] mosi0R;
+    wire [SpiNum-1:0] valReg;
+    wire [SpiNum-1:0] valToTxR;
+    wire [SpiNum-1:0] valToRxR;
+    wire [0:31] dataToRxFifoR [SpiNum-1:0];
+    
+    
+    wire [SpiNum-1:0] sckQ;
+    wire [SpiNum-1:0] ssQ;
+    wire [SpiNum-1:0] mosi0Q;
+    wire [SpiNum-1:0] valToTxQ;
+    wire [SpiNum-1:0] valToRxQ;
+    wire [0:31] dataToRxFifoQ [SpiNum-1:0];
+    wire [0:31] dataFromRxFifo [SpiNum-1:0];
+    
+    wire [CmdRegWidth/2-1:0] muxedData;
+    
+    wire smcValComb; 
+    wire	[CmdRegWidth/2-1:0]	ansData;
+    //================================================================================
+    //  ASSIGNMENTS
+    //================================================================================
+    assign addrExt = {SmcAddr_i, 1'b0};
+    assign smcValComb = (!SmcAmsN_i && !SmcAwe_i) ? 1'b1 : 1'b0;
+    assign txEn = spiTxRxEn[6:0];
+    assign Mosi1_io[0] =(SpiDir_o[0])?mosi1[0]:1'bz;
+    assign Mosi1_io[1] =(SpiDir_o[1])?mosi1[1]:1'bz;
+    assign Mosi1_io[2] =(SpiDir_o[2])?mosi1[2]:1'bz;
+    assign Mosi1_io[3] =(SpiDir_o[3])?mosi1[3]:1'bz;
+    assign Mosi1_io[4] =(SpiDir_o[4])?mosi1[4]:1'bz;
+    assign Mosi1_io[5] =(SpiDir_o[5])?mosi1[5]:1'bz;
+    assign Mosi1_io[6] =(SpiDir_o[6])?mosi1[6]:1'bz;
+    assign Mosi2_o = mosi2;
+    assign Mosi3_o = mosi3;
+    assign Ss_o[0] = (assel[0])? ((chipSelFpga[0])? ssMuxed[0]:~ssMuxed[0]):chipSelFpga[0];
+    assign Ss_o[1] = (assel[1])? ((chipSelFpga[1])? ssMuxed[1]:~ssMuxed[1]):chipSelFpga[1];
+    assign Ss_o[2] = (assel[2])? ((chipSelFpga[2])? ssMuxed[2]:~ssMuxed[2]):chipSelFpga[2];
+    assign Ss_o[3] = (assel[3])? ((chipSelFpga[3])? ssMuxed[3]:~ssMuxed[3]):chipSelFpga[3];
+    assign Ss_o[4] = (assel[4])? ((chipSelFpga[4])? ssMuxed[4]:~ssMuxed[4]):chipSelFpga[4];
+    assign Ss_o[5] = (assel[5])? ((chipSelFpga[5])? ssMuxed[5]:~ssMuxed[5]):chipSelFpga[5];
+    assign Ss_o[6] = (assel[6])? ((chipSelFpga[6])? ssMuxed[6]:~ssMuxed[6]):chipSelFpga[6];
+    assign SsFlash_o[0] = (assel[0])?(chipSelFlash[0]? ssMuxed[0]:~ssMuxed[0]):chipSelFlash[0];
+    assign SsFlash_o[1] = (assel[1])?(chipSelFlash[1]? ssMuxed[1]:~ssMuxed[1]):chipSelFlash[1];
+    assign SsFlash_o[2] = (assel[2])?(chipSelFlash[2]? ssMuxed[2]:~ssMuxed[2]):chipSelFlash[2];
+    assign SsFlash_o[3] = (assel[3])?(chipSelFlash[3]? ssMuxed[3]:~ssMuxed[3]):chipSelFlash[3];
+    assign SsFlash_o[4] = (assel[4])?(chipSelFlash[4]? ssMuxed[4]:~ssMuxed[4]):chipSelFlash[4];
+    assign SsFlash_o[5] = (assel[5])?(chipSelFlash[5]? ssMuxed[5]:~ssMuxed[5]):chipSelFlash[5];
+    assign SsFlash_o[6] = (assel[6])?(chipSelFlash[6]? ssMuxed[6]:~ssMuxed[6]):chipSelFlash[6];
+    assign Sck_o = sckMuxed;
+    
+    assign widthSel[0] = spi0CtrlRR[6:5];
+    assign widthSel[1] = spi1CtrlRR[6:5];
+    assign widthSel[2] = spi2CtrlRR[6:5];
+    assign widthSel[3] = spi3CtrlRR[6:5];
+    assign widthSel[4] = spi4CtrlRR[6:5];
+    assign widthSel[5] = spi5CtrlRR[6:5];
+    assign widthSel[6] = spi6CtrlRR[6:5];
+    
+    assign spiMode[0] = spi0CtrlRR[7];
+    assign spiMode[1] = spi1CtrlRR[7];
+    assign spiMode[2] = spi2CtrlRR[7];
+    assign spiMode[3] = spi3CtrlRR[7];
+    assign spiMode[4] = spi4CtrlRR[7];
+    assign spiMode[5] = spi5CtrlRR[7];
+    assign spiMode[6] = spi6CtrlRR[7];
+    
+    
+    assign clockPol[0] = spi0CtrlRR[2];
+    assign clockPol[1] = spi1CtrlRR[2];
+    assign clockPol[2] = spi2CtrlRR[2];
+    assign clockPol[3] = spi3CtrlRR[2];
+    assign clockPol[4] = spi4CtrlRR[2];
+    assign clockPol[5] = spi5CtrlRR[2];
+    assign clockPol[6] = spi6CtrlRR[2];
+    
+    assign clockPhase[0] = spi0CtrlRR[1];
+    assign clockPhase[1] = spi1CtrlRR[1];
+    assign clockPhase[2] = spi2CtrlRR[1];
+    assign clockPhase[3] = spi3CtrlRR[1];
+    assign clockPhase[4] = spi4CtrlRR[1];
+    assign clockPhase[5] = spi5CtrlRR[1];
+    assign clockPhase[6] = spi6CtrlRR[1];
+    
+    assign endianSel[0] = spi0CtrlRR[8];
+    assign endianSel[1] = spi1CtrlRR[8];
+    assign endianSel[2] = spi2CtrlRR[8];
+    assign endianSel[3] = spi3CtrlRR[8];
+    assign endianSel[4] = spi4CtrlRR[8];
+    assign endianSel[5] = spi5CtrlRR[8];
+    assign endianSel[6] = spi6CtrlRR[8];
+    
+    assign selSt[0] = spi0CtrlRR[4];
+    assign selSt[1] = spi1CtrlRR[4];
+    assign selSt[2] = spi2CtrlRR[4];
+    assign selSt[3] = spi3CtrlRR[4];
+    assign selSt[4] = spi4CtrlRR[4];
+    assign selSt[5] = spi5CtrlRR[4];
+    assign selSt[6] = spi6CtrlRR[4];
+    
+    assign assel[0] = spi0CtrlRR[3];
+    assign assel[1] = spi1CtrlRR[3];
+    assign assel[2] = spi2CtrlRR[3];
+    assign assel[3] = spi3CtrlRR[3];
+    assign assel[4] = spi4CtrlRR[3];
+    assign assel[5] = spi5CtrlRR[3];
+    assign assel[6] = spi6CtrlRR[3];
+    
+    assign stopDelay[0] = spi0CsDelayRR[7:2];
+    assign stopDelay[1] = spi1CsDelayRR[7:2];
+    assign stopDelay[2] = spi2CsDelayRR[7:2];
+    assign stopDelay[3] = spi3CsDelayRR[7:2];
+    assign stopDelay[4] = spi4CsDelayRR[7:2];
+    assign stopDelay[5] = spi5CsDelayRR[7:2];
+    assign stopDelay[6] = spi6CsDelayRR[7:2];
+    
+    assign leadx[0] = spi0CsDelayRR[1];
+    assign leadx[1] = spi1CsDelayRR[1];
+    assign leadx[2] = spi2CsDelayRR[1];
+    assign leadx[3] = spi3CsDelayRR[1];
+    assign leadx[4] = spi4CsDelayRR[1];
+    assign leadx[5] = spi5CsDelayRR[1];
+    assign leadx[6] = spi6CsDelayRR[1];
+    
+    assign lag[0] = spi0CsDelayRR[0];
+    assign lag[1] = spi1CsDelayRR[0];
+    assign lag[2] = spi2CsDelayRR[0];
+    assign lag[3] = spi3CsDelayRR[0];
+    assign lag[4] = spi4CsDelayRR[0];
+    assign lag[5] = spi5CsDelayRR[0];
+    assign lag[6] = spi6CsDelayRR[0];
+    
+    assign baudRate[0] = spi0Clk[7:0];
+    assign baudRate[1] = spi1Clk[7:0];
+    assign baudRate[2] = spi2Clk[7:0];
+    assign baudRate[3] = spi3Clk[7:0];
+    assign baudRate[4] = spi4Clk[7:0];
+    assign baudRate[5] = spi5Clk[7:0];
+    assign baudRate[6] = spi6Clk[7:0];
+    
+    
+    assign SpiRst_o[0] = GPIOASync[0];
+    assign SpiRst_o[1] = GPIOASync[1];
+    assign SpiRst_o[2] = GPIOASync[2];
+    assign SpiRst_o[3] = GPIOASync[3];
+    assign SpiRst_o[4] = GPIOASync[4];
+    assign SpiRst_o[5] = GPIOASync[5];
+    assign SpiRst_o[6] = GPIOASync[6];
+    
+    assign fifoRxRstRdPtr[0] = spi0RxFifoCtrl[0];
+    assign fifoRxRstRdPtr[1] = spi1RxFifoCtrl[0];
+    assign fifoRxRstRdPtr[2] = spi2RxFifoCtrl[0];
+    assign fifoRxRstRdPtr[3] = spi3RxFifoCtrl[0];
+    assign fifoRxRstRdPtr[4] = spi4RxFifoCtrl[0];
+    assign fifoRxRstRdPtr[5] = spi5RxFifoCtrl[0];
+    assign fifoRxRstRdPtr[6] = spi6RxFifoCtrl[0];
+    
+    assign fifoRxRst[0] = spi0RxFifoCtrlRR[0];
+    assign fifoRxRst[1] = spi1RxFifoCtrlRR[0];
+    assign fifoRxRst[2] = spi2RxFifoCtrlRR[0];
+    assign fifoRxRst[3] = spi3RxFifoCtrlRR[0];
+    assign fifoRxRst[4] = spi4RxFifoCtrlRR[0];
+    assign fifoRxRst[5] = spi5RxFifoCtrlRR[0];
+    assign fifoRxRst[6] = spi6RxFifoCtrlRR[0];
+    
+    assign fifoTxRstWrPtr[0] = spi0TxFifoCtrl[0];
+    assign fifoTxRstWrPtr[1] = spi1TxFifoCtrl[0];
+    assign fifoTxRstWrPtr[2] = spi2TxFifoCtrl[0];
+    assign fifoTxRstWrPtr[3] = spi3TxFifoCtrl[0];
+    assign fifoTxRstWrPtr[4] = spi4TxFifoCtrl[0];
+    assign fifoTxRstWrPtr[5] = spi5TxFifoCtrl[0];
+    assign fifoTxRstWrPtr[6] = spi6TxFifoCtrl[0];
+    
+    assign fifoTxRst[0] = spi0TxFifoCtrlRR[0];
+    assign fifoTxRst[1] = spi1TxFifoCtrlRR[0];
+    assign fifoTxRst[2] = spi2TxFifoCtrlRR[0];
+    assign fifoTxRst[3] = spi3TxFifoCtrlRR[0];
+    assign fifoTxRst[4] = spi4TxFifoCtrlRR[0];
+    assign fifoTxRst[5] = spi5TxFifoCtrlRR[0];
+    assign fifoTxRst[6] = spi5TxFifoCtrlRR[0];
+    
+    assign Ld_o[0] = GPIOA[16];
+    assign Ld_o[1] = GPIOA[17];
+    assign Ld_o[2] = GPIOA[18];
+    assign Ld_o[3] = GPIOA[19];
+    assign Ld_o[4] = GPIOA[20];
+    assign Ld_o[5] = GPIOA[21];
+    assign Ld_o[6] = GPIOA[22];
+    assign LD_o = Ld_o[0]&Ld_o[1]&Ld_o[2]&Ld_o[3]&Ld_o[4]&Ld_o[5]&Ld_o[6];
+    
+    assign wordCntRx[0] = spi0RxFifoCtrlRR[15:8];
+    assign wordCntRx[1] = spi1RxFifoCtrlRR[15:8];
+    assign wordCntRx[2] = spi2RxFifoCtrlRR[15:8];
+    assign wordCntRx[3] = spi3RxFifoCtrlRR[15:8];
+    assign wordCntRx[4] = spi4RxFifoCtrlRR[15:8];
+    assign wordCntRx[5] = spi5RxFifoCtrlRR[15:8];
+    assign wordCntRx[6] = spi6RxFifoCtrlRR[15:8];
+    
+    assign wordCntTx[0] = spi0TxFifoCtrlRR[15:8];
+    assign wordCntTx[1] = spi1TxFifoCtrlRR[15:8];
+    assign wordCntTx[2] = spi2TxFifoCtrlRR[15:8];
+    assign wordCntTx[3] = spi3TxFifoCtrlRR[15:8];
+    assign wordCntTx[4] = spi4TxFifoCtrlRR[15:8];
+    assign wordCntTx[5] = spi5TxFifoCtrlRR[15:8];
+    assign wordCntTx[6] = spi6TxFifoCtrlRR[15:8];
+    
+    
+    assign chipSelFpga[0] = spi0CsCtrlRR[0];
+    assign chipSelFpga[1] = spi1CsCtrlRR[0];
+    assign chipSelFpga[2] = spi2CsCtrlRR[0];
+    assign chipSelFpga[3] = spi3CsCtrlRR[0];
+    assign chipSelFpga[4] = spi4CsCtrlRR[0];
+    assign chipSelFpga[5] = spi5CsCtrlRR[0];
+    assign chipSelFpga[6] = spi6CsCtrlRR[0];
+    
+    assign chipSelFlash[0] = spi0CsCtrlRR[1];
+    assign chipSelFlash[1] = spi1CsCtrlRR[1];
+    assign chipSelFlash[2] = spi2CsCtrlRR[1];
+    assign chipSelFlash[3] = spi3CsCtrlRR[1];
+    assign chipSelFlash[4] = spi4CsCtrlRR[1];
+    assign chipSelFlash[5] = spi5CsCtrlRR[1];
+    assign chipSelFlash[6] = spi6CsCtrlRR[1];
+    
+    
+    assign ssMuxed[0] = (spiMode[0])? ssQ[0]:ssR[0];
+    assign ssMuxed[1] = (spiMode[1])? ssQ[1]:ssR[1];
+    assign ssMuxed[2] = (spiMode[2])? ssQ[2]:ssR[2];
+    assign ssMuxed[3] = (spiMode[3])? ssQ[3]:ssR[3];
+    assign ssMuxed[4] = (spiMode[4])? ssQ[4]:ssR[4];
+    assign ssMuxed[5] = (spiMode[5])? ssQ[5]:ssR[5];
+    assign ssMuxed[6] = (spiMode[6])? ssQ[6]:ssR[6];
+    
+    assign SpiDir_o[0] = (spiMode[0])? 1'b1 : 1'b0 ;
+    assign SpiDir_o[1] = (spiMode[1])? 1'b1 : 1'b0 ;
+    assign SpiDir_o[2] = (spiMode[2])? 1'b1 : 1'b0 ;
+    assign SpiDir_o[3] = (spiMode[3])? 1'b1 : 1'b0 ;
+    assign SpiDir_o[4] = (spiMode[4])? 1'b1 : 1'b0 ;
+    assign SpiDir_o[5] = (spiMode[5])? 1'b1 : 1'b0 ;
+    assign SpiDir_o[6] = (spiMode[6])? 1'b1 : 1'b0 ;
+    
+    
+    assign sckMuxed[0] =  (spiMode[0])?sckQ[0]:sckR[0];
+    assign sckMuxed[1] =  (spiMode[1])?sckQ[1]:sckR[1];
+    assign sckMuxed[2] =  (spiMode[2])?sckQ[2]:sckR[2];
+    assign sckMuxed[3] =  (spiMode[3])?sckQ[3]:sckR[3];
+    assign sckMuxed[4] =  (spiMode[4])?sckQ[4]:sckR[4];
+    assign sckMuxed[5] =  (spiMode[5])?sckQ[5]:sckR[5];
+    assign sckMuxed[6] =  (spiMode[6])?sckQ[6]:sckR[6];
+    
+    assign mosi0[0] =  (spiMode[0])?mosi0Q[0]:mosi0R[0];
+    assign mosi0[1] =  (spiMode[1])?mosi0Q[1]:mosi0R[1];
+    assign mosi0[2] =  (spiMode[2])?mosi0Q[2]:mosi0R[2];
+    assign mosi0[3] =  (spiMode[3])?mosi0Q[3]:mosi0R[3];
+    assign mosi0[4] =  (spiMode[4])?mosi0Q[4]:mosi0R[4];
+    assign mosi0[5] =  (spiMode[5])?mosi0Q[5]:mosi0R[5];
+    assign mosi0[6] =  (spiMode[6])?mosi0Q[6]:mosi0R[6];
+    
+    assign Mosi0_o[0] = mosi0[0];
+    assign Mosi0_o[1] = mosi0[1];
+    assign Mosi0_o[2] = mosi0[2];
+    assign Mosi0_o[3] = mosi0[3];
+    assign Mosi0_o[4] = mosi0[4];
+    assign Mosi0_o[5] = mosi0[5];
+    assign Mosi0_o[6] = mosi0[6];
+    
+    
+    assign valToTxFifoRead[0] =  (spiMode[0])?valToTxQ[0]:valToTxR[0];
+    assign valToTxFifoRead[1] =  (spiMode[1])?valToTxQ[1]:valToTxR[1];
+    assign valToTxFifoRead[2] =  (spiMode[2])?valToTxQ[2]:valToTxR[2];
+    assign valToTxFifoRead[3] =  (spiMode[3])?valToTxQ[3]:valToTxR[3];
+    assign valToTxFifoRead[4] =  (spiMode[4])?valToTxQ[4]:valToTxR[4];
+    assign valToTxFifoRead[5] =  (spiMode[5])?valToTxQ[5]:valToTxR[5];
+    assign valToTxFifoRead[6] =  (spiMode[6])?valToTxQ[6]:valToTxR[6];
+    
+    assign valToRxFifo[0] = valToRxR[0];
+    assign valToRxFifo[1] = valToRxR[1];
+    assign valToRxFifo[2] = valToRxR[2];
+    assign valToRxFifo[3] = valToRxR[3];
+    assign valToRxFifo[4] = valToRxR[4];
+    assign valToRxFifo[5] = valToRxR[5];
+    assign valToRxFifo[6] = valToRxR[6];
+    
+    assign dataToRxFifo[0] = dataToRxFifoR[0];
+    assign dataToRxFifo[1] = dataToRxFifoR[1];
+    assign dataToRxFifo[2] = dataToRxFifoR[2];
+    assign dataToRxFifo[3] = dataToRxFifoR[3];
+    assign dataToRxFifo[4] = dataToRxFifoR[4];
+    assign dataToRxFifo[5] = dataToRxFifoR[5];
+    assign dataToRxFifo[6] = dataToRxFifoR[6];
+    
+    assign spi0TxFifoCtrlReg = txFifoCtrlReg[0];
+    assign spi1TxFifoCtrlReg = txFifoCtrlReg[1];
+    assign spi2TxFifoCtrlReg = txFifoCtrlReg[2];
+    assign spi3TxFifoCtrlReg = txFifoCtrlReg[3];
+    assign spi4TxFifoCtrlReg = txFifoCtrlReg[4];
+    assign spi5TxFifoCtrlReg = txFifoCtrlReg[5];
+    assign spi6TxFifoCtrlReg = txFifoCtrlReg[6];
+    
+    assign spi0RxFifoCtrlReg = rxFifoCtrlReg[0];
+    assign spi1RxFifoCtrlReg = rxFifoCtrlReg[1];
+    assign spi2RxFifoCtrlReg = rxFifoCtrlReg[2];
+    assign spi3RxFifoCtrlReg = rxFifoCtrlReg[3];
+    assign spi4RxFifoCtrlReg = rxFifoCtrlReg[4];
+    assign spi5RxFifoCtrlReg = rxFifoCtrlReg[5];
+    assign spi6RxFifoCtrlReg = rxFifoCtrlReg[6];
+    
+    
+    
+    assign	SmcData_io	=	(!SmcAre_i && !SmcAoe_i)?muxedData:16'bz;
+    
+    //================================================================================
+    //  CODING
+    //================================================================================	
+    
+    DataOutMux DataOutMuxer
+    (
+        .Clk_i(gclk),
+        .Addr_i(addrExt),
+        .ToRegMapAddr_i(toRegMapAddr),
+        .FifoRxRst_i(fifoRxRstRdPtr[0]),
+        .DataFromRegMap_i(ansData),
+        .SmcAre_i(SmcAre_i),
+        .DataFromRxFifo1_i(dataFromRxFifo[0]),
+        .DataFromRxFifo2_i(dataFromRxFifo[1]),
+        .DataFromRxFifo3_i(dataFromRxFifo[2]),
+        .DataFromRxFifo4_i(dataFromRxFifo[3]),
+        .DataFromRxFifo5_i(dataFromRxFifo[4]),
+        .DataFromRxFifo6_i(dataFromRxFifo[5]),
+        .DataFromRxFifo7_i(dataFromRxFifo[6]),
+        .AnsData_o (muxedData)
+        
+    );
+    
+    BUFG BUFG_inst (
+       .O(gclk), // 1-bit output: Clock output
+       .I(Clk123_i)  // 1-bit input: Clock input
+    );
+    
+    
+    DataMuxer DataMuxer
+    (
+        .Clk_i(gclk),
+        .Rst_i(initRst),
+    
+    	.SmcVal_i(smcValComb),
+    	.SmcData_i(SmcData_io),
+        .SmcAddr_i(addrExt),
+    
+    	.ToRegMapVal_o(toRegMapVal),
+    	.ToRegMapData_o(toRegMapData),
+        .ToRegMapAddr_o(toRegMapAddr),
+    
+    	.ToFifoVal_o(toFifoVal),
+    	.ToFifoData_o(toFifoData)
+    
+    );
+    
+
+    CDC #(
+
+        .WIDTH(CmdRegWidth),
+        .STAGES(STAGES)
+
+    ) synchronizer(
+        .ClkFast_i(gclk),
+        .ClkSlow_i(spiClkBus),
+
+        .Spi0Ctrl_i(spi0Ctrl),
+        .Spi0CsCtrl_i(spi0CsCtrl),
+        .Spi0CsDelay_i(spi0CsDelay),
+        .Spi0TxFifoCtrl_i(spi0TxFifoCtrl),
+        .Spi0RxFifoCtrl_i(spi0RxFifoCtrl),
+
+        .Spi1Ctrl_i(spi1Ctrl),
+        .Spi1CsCtrl_i(spi1CsCtrl),
+        .Spi1CsDelay_i(spi1CsDelay),
+        .Spi1TxFifoCtrl_i(spi1TxFifoCtrl),
+        .Spi1RxFifoCtrl_i(spi1RxFifoCtrl),
+
+        .Spi2Ctrl_i(spi2Ctrl),
+        .Spi2CsCtrl_i(spi2CsCtrl),
+        .Spi2CsDelay_i(spi2CsDelay),
+        .Spi2TxFifoCtrl_i(spi2TxFifoCtrl),
+        .Spi2RxFifoCtrl_i(spi2RxFifoCtrl),
+
+        .Spi3Ctrl_i(spi3Ctrl),
+        .Spi3CsCtrl_i(spi3CsCtrl),
+        .Spi3CsDelay_i(spi3CsDelay),
+        .Spi3TxFifoCtrl_i(spi3TxFifoCtrl),
+        .Spi3RxFifoCtrl_i(spi3RxFifoCtrl),
+
+        .Spi4Ctrl_i(spi4Ctrl),
+        .Spi4CsCtrl_i(spi4CsCtrl),
+        .Spi4CsDelay_i(spi4CsDelay),
+        .Spi4TxFifoCtrl_i(spi4TxFifoCtrl),
+        .Spi4RxFifoCtrl_i(spi4RxFifoCtrl),
+
+        .Spi5Ctrl_i(spi5Ctrl),
+        .Spi5CsCtrl_i(spi5CsCtrl),
+        .Spi5CsDelay_i(spi5CsDelay),
+        .Spi5TxFifoCtrl_i(spi5TxFifoCtrl),
+        .Spi5RxFifoCtrl_i(spi5RxFifoCtrl),
+
+        .Spi6Ctrl_i(spi6Ctrl),
+        .Spi6CsCtrl_i(spi6CsCtrl),
+        .Spi6CsDelay_i(spi6CsDelay),
+        .Spi6TxFifoCtrl_i(spi6TxFifoCtrl),
+        .Spi6RxFifoCtrl_i(spi6RxFifoCtrl),
+
+        .Spi0Ctrl_o(spi0CtrlRR),
+        .Spi0CsCtrl_o(spi0CsCtrlRR),
+        .Spi0CsDelay_o(spi0CsDelayRR),
+        .Spi0TxFifoCtrl_o(spi0TxFifoCtrlRR),
+        .Spi0RxFifoCtrl_o(spi0RxFifoCtrlRR),
+
+        .Spi1Ctrl_o(spi1CtrlRR),
+        .Spi1CsCtrl_o(spi1CsCtrlRR),
+        .Spi1CsDelay_o(spi1CsDelayRR),
+        .Spi1TxFifoCtrl_o(spi1TxFifoCtrlRR),
+        .Spi1RxFifoCtrl_o(spi1RxFifoCtrlRR),
+
+        .Spi2Ctrl_o(spi2CtrlRR),
+        .Spi2CsCtrl_o(spi2CsCtrlRR),
+        .Spi2CsDelay_o(spi2CsDelayRR),
+        .Spi2TxFifoCtrl_o(spi2TxFifoCtrlRR),
+        .Spi2RxFifoCtrl_o(spi2RxFifoCtrlRR),
+
+        .Spi3Ctrl_o(spi3CtrlRR),
+        .Spi3CsCtrl_o(spi3CsCtrlRR),
+        .Spi3CsDelay_o(spi3CsDelayRR),
+        .Spi3TxFifoCtrl_o(spi3TxFifoCtrlRR),
+        .Spi3RxFifoCtrl_o(spi3RxFifoCtrlRR),
+
+        .Spi4Ctrl_o(spi4CtrlRR),
+        .Spi4CsCtrl_o(spi4CsCtrlRR),
+        .Spi4CsDelay_o(spi4CsDelayRR),
+        .Spi4TxFifoCtrl_o(spi4TxFifoCtrlRR),
+        .Spi4RxFifoCtrl_o(spi4RxFifoCtrlRR),
+
+        .Spi5Ctrl_o(spi5CtrlRR),
+        .Spi5CsCtrl_o(spi5CsCtrlRR),
+        .Spi5CsDelay_o(spi5CsDelayRR),
+        .Spi5TxFifoCtrl_o(spi5TxFifoCtrlRR),
+        .Spi5RxFifoCtrl_o(spi5RxFifoCtrlRR),
+
+        .Spi6Ctrl_o(spi6CtrlRR),
+        .Spi6CsCtrl_o(spi6CsCtrlRR),
+        .Spi6CsDelay_o(spi6CsDelayRR),
+        .Spi6TxFifoCtrl_o(spi6TxFifoCtrlRR),
+        .Spi6RxFifoCtrl_o(spi6RxFifoCtrlRR)
+
+    );
+
+
+    RegMap 
+    #(
+        .CmdRegWidth(32),
+        .AddrRegWidth(12)
+    )
+    RegMap_inst 
+    (
+        .Clk_i(gclk),
+        .Rst_i(initRst),
+        .Data_i(toRegMapData),
+        .Addr_i(toRegMapAddr),
+        .Val_i(toRegMapVal),
+        .SmcBe_i(SmcBe_i),
+
+        .TxFifoCtrlReg0_i(spi0TxFifoCtrlReg),
+        .TxFifoCtrlReg1_i(spi1TxFifoCtrlReg),
+        .TxFifoCtrlReg2_i(spi2TxFifoCtrlReg),
+        .TxFifoCtrlReg3_i(spi3TxFifoCtrlReg),
+        .TxFifoCtrlReg4_i(spi4TxFifoCtrlReg),
+        .TxFifoCtrlReg5_i(spi5TxFifoCtrlReg),
+        .TxFifoCtrlReg6_i(spi6TxFifoCtrlReg),
+        .RxFifoCtrlReg0_i(spi0RxFifoCtrlReg),
+        .RxFifoCtrlReg1_i(spi1RxFifoCtrlReg),
+        .RxFifoCtrlReg2_i(spi2RxFifoCtrlReg),
+        .RxFifoCtrlReg3_i(spi3RxFifoCtrlReg),
+        .RxFifoCtrlReg4_i(spi4RxFifoCtrlReg),
+        .RxFifoCtrlReg5_i(spi5RxFifoCtrlReg),
+        .RxFifoCtrlReg6_i(spi6RxFifoCtrlReg),
+
+        //Spi0
+        .Spi0CtrlReg_o(spi0Ctrl),
+        .Spi0ClkReg_o(spi0Clk),
+        .Spi0CsDelayReg_o(spi0CsDelay),
+        .Spi0CsCtrlReg_o(spi0CsCtrl),
+        .Spi0TxFifoCtrlReg_o(spi0TxFifoCtrl),
+        .Spi0RxFifoCtrlReg_o(spi0RxFifoCtrl),
+        //Spi1
+        .Spi1CtrlReg_o(spi1Ctrl),
+        .Spi1ClkReg_o(spi1Clk),
+        .Spi1CsDelayReg_o(spi1CsDelay),
+        .Spi1CsCtrlReg_o(spi1CsCtrl),
+        .Spi1TxFifoCtrlReg_o(spi1TxFifoCtrl),
+        .Spi1RxFifoCtrlReg_o(spi1RxFifoCtrl),
+        //Spi2
+        .Spi2CtrlReg_o(spi2Ctrl),
+        .Spi2ClkReg_o(spi2Clk),
+        .Spi2CsDelayReg_o(spi2CsDelay),
+        .Spi2CsCtrlReg_o(spi2CsCtrl),
+        .Spi2TxFifoCtrlReg_o(spi2TxFifoCtrl),
+        .Spi2RxFifoCtrlReg_o(spi2RxFifoCtrl),
+        //Spi3
+        .Spi3CtrlReg_o(spi3Ctrl),
+        .Spi3ClkReg_o(spi3Clk),
+        .Spi3CsDelayReg_o(spi3CsDelay),
+        .Spi3CsCtrlReg_o(spi3CsCtrl),
+        .Spi3TxFifoCtrlReg_o(spi3TxFifoCtrl),
+        .Spi3RxFifoCtrlReg_o(spi3RxFifoCtrl),
+        //Spi4
+        .Spi4CtrlReg_o(spi4Ctrl),
+        .Spi4ClkReg_o(spi4Clk),
+        .Spi4CsDelayReg_o(spi4CsDelay),
+        .Spi4CsCtrlReg_o(spi4CsCtrl),
+        .Spi4TxFifoCtrlReg_o(spi4TxFifoCtrl),
+        .Spi4RxFifoCtrlReg_o(spi4RxFifoCtrl),
+        //Spi5
+        .Spi5CtrlReg_o(spi5Ctrl),
+        .Spi5ClkReg_o(spi5Clk),
+        .Spi5CsDelayReg_o(spi5CsDelay),
+        .Spi5CsCtrlReg_o(spi5CsCtrl),
+        .Spi5TxFifoCtrlReg_o(spi5TxFifoCtrl),
+        .Spi5RxFifoCtrlReg_o(spi5RxFifoCtrl),
+        //Spi6
+        .Spi6CtrlReg_o(spi6Ctrl),
+        .Spi6ClkReg_o(spi6Clk),
+        .Spi6CsDelayReg_o(spi6CsDelay),
+        .Spi6CsCtrlReg_o(spi6CsCtrl),
+        .Spi6TxFifoCtrlReg_o(spi6TxFifoCtrl),
+        .Spi6RxFifoCtrlReg_o(spi6RxFifoCtrl),
+        .SpiTxRxEnReg_o(spiTxRxEn),
+        .GPIOAReg_o(GPIOA),
+
+        .Led_o(Led_o),
+        .AnsDataReg_o(ansData)
+
+    );
+    
+    MmcmWrapper #(
+        .SpiNum(SpiNum),
+        .STAGES(STAGES) 
+
+    ) MainMmcm
+    (
+    	.Clk_i(gclk),
+    	.Rst_i(initRst),
+        .Rst80_i(rst80),
+        .BaudRate0_i(baudRate[0]),
+        .BaudRate1_i(baudRate[1]),
+        .BaudRate2_i(baudRate[2]),
+        .BaudRate3_i(baudRate[3]),
+        .BaudRate4_i(baudRate[4]),
+        .BaudRate5_i(baudRate[5]),
+        .BaudRate6_i(baudRate[6]),
+        .Clk80_o(clk80),
+    	.SpiClk_o(spiClkBus)
+    );
+    
+    
+    genvar i;
+    
+    generate
+        for  (i = 0; i < SpiNum; i = i + 1) begin: SpiGen
+
+            InitRst InitRst_inst 
+            (
+                .clk_i(spiClkBus[i]),
+                .signal_o(initRstGen[i])
+            );
+
+            Sync1bit#(
+                .WIDTH(1),
+                .STAGES(STAGES)
+
+            )
+            Sync1bit_inst(
+                .ClkFast_i(gclk),
+                .ClkSlow_i(spiClkBus[i]),
+                .TxEn_i(txEn[i]),
+                .RstReg_i(GPIOA[i]),
+                .TxEn_o(spiTxEnSync[i]),
+                .RstReg_o(GPIOASync[i])
+
+            );
+            
+    		DataFifoWrapper #(
+                .STAGES(STAGES)
+                
+            )DataFifoWrapper
+    		(
+    			.WrClk_i(gclk),
+    			.RdClk_i(spiClkBus[i]),
+        
+    			.FifoRxRst_i(fifoRxRst[i]),
+                .FifoTxRst_i(fifoTxRst[i]),
+                .FifoRxRstRdPtr_i(fifoRxRstRdPtr[i]),
+                .FifoTxRstWrPtr_i(fifoTxRstWrPtr[i]),
+
+                .SmcAre_i(SmcAre_i),
+                .SmcAwe_i(SmcAwe_i),
+                .SmcAddr_i(addrExt),
+                .TxFifoWrdCnt_i(wordCntTx[i]),
+                .RxFifoWrdCnt_i(wordCntRx[i]),
+    			.ToFifoVal_i(toFifoVal[i]),
+                .ToFifoRxData_i(dataToRxFifo[i]),
+                .ToFifoRxWriteVal_i(valToRxFifo[i]),
+                .ToFifoTxReadVal_i(valToTxFifoRead[i]),
+    			.ToFifoData_i(toFifoData[32*i+:32]),
+
+    			.TxFifoCtrlReg_o(txFifoCtrlReg[i]),
+                .RxFifoCtrlReg_o(rxFifoCtrlReg[i]),
+    			.ToSpiVal_o(toSpiVal[i]),
+                .DataFromRxFifo_o(dataFromRxFifo[i]),
+    			.ToSpiData_o(toSpiData[i])
+    		);
+    
+            SPIm SPIm_inst (
+                .Clk_i(spiClkBus[i]),
+                .Start_i(spiTxEnSync[i]),
+                .Rst_i(initRstGen[i]| spiMode[i]),
+                .SpiData_i(toSpiData[i]),
+                .Sck_o(sckR[i]),
+                .Ss_o(ssR[i]),
+                .Mosi0_o(mosi0R[i]),
+                .WidthSel_i(widthSel[i]),
+                .PulsePol_i(clockPol[i]),
+                .ClockPhase_i(clockPhase[i]),
+                .EndianSel_i(endianSel[i]),
+                .Lag_i(lag[i]),
+                .Lead_i(leadx[i]),
+                .Stop_i(stopDelay[i]),
+                .SelSt_i(selSt[i]),
+                .Val_o(valToTxR[i])
+    
+            );
+    
+            SPIs SPIs_inst (
+                .Clk_i(spiClkBus[i]),
+                .Rst_i(initRstGen[i]|SpiRst_o[i]| spiMode[i]),
+                .Sck_i(sckR[i]),
+                .Ss_i(ssR[i]),
+                .Mosi0_i(Mosi1_io[i]),
+                .WidthSel_i(widthSel[i]),
+                .SelSt_i(selSt[i]),
+                .DataToRxFifo_o(dataToRxFifoR[i]),
+                .Val_o(valToRxR[i])
+            );
+    
+            QuadSPIm QuadSPIm_inst (
+                .Clk_i(spiClkBus[i]),
+                .Start_i(spiTxEnSync[i]),
+                .Rst_i(initRstGen[i]| !spiMode[i]),
+    			.SpiDataVal_i(toSpiVal),
+                .SpiData_i(toSpiData[i]),
+                .Sck_o(sckQ[i]),
+                .Ss_o(ssQ[i]),
+                .Mosi0_i(mosi0Q[i]),
+                .Mosi1_i(mosi1[i]),
+                .Mosi2_i(mosi2[i]),
+                .Mosi3_i(mosi3[i]),
+                .WidthSel_i(widthSel[i]),
+                .PulsePol_i(clockPol[i]),
+                .ClockPhase_i(clockPhase[i]),
+                .EndianSel_i(endianSel[i]),
+                .Lag_i(lag[i]),
+                .Lead_i(leadx[i]),
+                .Stop_i(stopDelay[i]),
+                .SelSt_i(selSt[i]),
+                .Val_o(valToTxQ[i])
+            );
+        end
+    endgenerate
+    
+    InitRst InitRst_inst
+     (
+        .clk_i(gclk),
+        .signal_o(initRst)
+    );
+
+     InitRst Rst80_inst
+     (
+        .clk_i(clk80),
+        .signal_o(rst80)
+    );
+    
+    
+    endmodule