Init

script/recreate.tcl

@@ -0,0 +1,125 @@
+create_project -name RF_FPGA -dir C:/RF_FPGA_PROJ_Test -pn GW1N-LV9PG256C6/I5 -device_version C -force 
+
+
+add_file -type verilog "/RF_FPGA/src/src/ClkGenGowin/ClkGenGowin.v"
+add_file -type verilog "/RF_FPGA/src/src/ControlUnit/ControlUnit.v"
+add_file -type verilog "/RF_FPGA/src/src/NCO/CordicNco.v"
+add_file -type verilog "/RF_FPGA/src/src/I2C/I2CSM.v"
+add_file -type verilog "/RF_FPGA/src/src/I2C/temp_i2c_master_ver2.v"
+add_file -type verilog "/RF_FPGA/src/src/NCO/CordicRotation.v"
+add_file -type verilog "/RF_FPGA/src/src/QuadSPI/QuadSPIs.v"
+add_file -type verilog "/RF_FPGA/src/src/Top/RFTop.v"
+add_file -type verilog "/RF_FPGA/src/src/SPI/SPIm.v"
+add_file -type verilog "/RF_FPGA/src/src/SPI/SPImDDS.v"
+add_file -type verilog "/RF_FPGA/src/src/SPI/SPIs.v"
+add_file -type verilog "/RF_FPGA/src/src/fifo_top/FifoCtrl.v"
+add_file -type verilog "/RF_FPGA/src/src/fifo_top/DDSFifo/fifo_top/FifoDDS.v"
+add_file -type verilog "/RF_FPGA/src/src/fifo_top/FifoRxRF.v"
+add_file -type verilog "/RF_FPGA/src/src/fifo_top/MAX2870FIFO/fifo_top/FifoMax2870.v"
+add_file -type verilog "/RF_FPGA/src/src/gowin_rpll/gClkGen.v"
+add_file -type verilog "/RF_FPGA/src/src/gowin_rpll/gowin_rpll/ClkGen.v"
+add_file -type verilog "/RF_FPGA/src/src/initRst/InitRst.v"
+add_file -type cst "/RF_FPGA/src/constr/RF_FPGA.cst"
+add_file -type sdc "/RF_FPGA/src/constr/RF_FPGA.sdc"
+
+
+
+
+set_option -synthesis_tool gowinsynthesis
+set_option -output_base_name RF_FPGA
+set_option -top_module RFTop
+set_option -gen_verilog_sim_netlist 1
+
+set_option -print_all_synthesis_warning 0
+set_option -allow_duplicate_modules 0
+set_option -multi_file_compilation_unit 1
+set_option -auto_constraint_io 0
+set_option -default_enum_encoding default
+set_option -compiler_compatible 1
+set_option -disable_io_insertion 0
+set_option -fix_gated_and_generated_clocks 1
+set_option -frequency Auto
+set_option -looplimit 2000
+set_option -maxfan 10000
+set_option -pipe 1
+set_option -resolve_multiple_driver 0
+set_option -resource_sharing 1
+set_option -retiming 0
+set_option -run_prop_extract 1
+set_option -rw_check_on_ram 0
+set_option -supporttypedflt 0
+set_option -symbolic_fsm_compiler 1
+set_option -synthesis_onoff_pragma 0
+set_option -update_models_cp 0
+set_option -write_apr_constraint 1
+set_option -gen_sdf 0
+set_option -gen_io_cst 0
+set_option -vccaux 3.3
+set_option -gen_ibis 0
+set_option -gen_posp 0
+set_option -gen_text_timing_rpt 0
+set_option -gen_verilog_sim_netlist 1
+set_option -gen_vhdl_sim_netlist 0
+set_option -show_init_in_vo 0
+set_option -show_all_warn 0
+set_option -timing_driven 1
+set_option -ireg_in_iob 1
+set_option -oreg_in_iob 1
+set_option -ioreg_in_iob 1
+set_option -replicate_resources 0
+set_option -cst_warn_to_error 1
+set_option -rpt_auto_place_io_info 0
+set_option -correct_hold_violation 1
+set_option -place_option 0
+set_option -route_option 0
+set_option -clock_route_order 0
+set_option -route_maxfan 23
+set_option -use_jtag_as_gpio 0
+set_option -use_sspi_as_gpio 1
+set_option -use_mspi_as_gpio 0
+set_option -use_ready_as_gpio 0
+set_option -use_done_as_gpio 0
+set_option -use_reconfign_as_gpio 0
+set_option -use_mode_as_gpio 0
+set_option -use_i2c_as_gpio 0
+set_option -use_cpu_as_gpio 0
+set_option -power_on_reset_monitor 1
+set_option -bit_format bin
+set_option -bit_crc_check 1
+set_option -bit_compress 0
+set_option -bit_encrypt 0
+set_option -bit_encrypt_key 00000000000000000000000000000000
+set_option -bit_security 1
+set_option -bit_incl_bsram_init 1
+set_option -bg_programming off
+set_option -hotboot 0
+set_option -i2c_slave_addr 00
+set_option -secure_mode 0
+set_option -loading_rate default
+set_option -program_done_bypass 0
+set_option -wakeup_mode 0
+set_option -user_code default
+set_option -unused_pin default
+set_option -multi_boot 1
+set_option -multiboot_address_width 24
+set_option -multiboot_mode normal
+set_option -multiboot_spi_flash_address 00000000
+set_option -mspi_jump 0
+set_option -turn_off_bg 0
+set_option -vccx 3.3
+set_option -seu_handler 0
+set_option -seu_handler_checksum 0
+set_option -seu_handler_mode auto
+set_option -error_detection false
+set_option -error_detection_correction false
+set_option -stop_seu_handler false
+set_option -error_injection false
+set_option -ext_cclk false
+set_option -ext_cclk_div 
+
+
+
+
+
+
+

src/constr/RF_FPGA.cst

@@ -0,0 +1,123 @@
+//Copyright (C)2014-2024 Gowin Semiconductor Corporation.
+//All rights reserved. 
+//File Title: Physical Constraints file
+//Tool Version: V1.9.9.01 (64-bit)
+//Part Number: GW1N-LV9PG256C6/I5
+//Device: GW1N-9
+//Created Time: Wed 03 20 12:43:13 2024
+
+IO_LOC "GPIO_o[17]" D1;
+IO_PORT "GPIO_o[17]" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;
+IO_LOC "GPIO_o[16]" R1;
+IO_PORT "GPIO_o[16]" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;
+IO_LOC "GPIO_o[15]" L1;
+IO_PORT "GPIO_o[15]" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;
+IO_LOC "GPIO_o[14]" K2;
+IO_PORT "GPIO_o[14]" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;
+IO_LOC "GPIO_o[13]" K1;
+IO_PORT "GPIO_o[13]" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;
+IO_LOC "GPIO_o[12]" L2;
+IO_PORT "GPIO_o[12]" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;
+IO_LOC "GPIO_o[11]" A2;
+IO_PORT "GPIO_o[11]" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;
+IO_LOC "GPIO_o[10]" A11;
+IO_PORT "GPIO_o[10]" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;
+IO_LOC "GPIO_o[9]" A14;
+IO_PORT "GPIO_o[9]" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;
+IO_LOC "GPIO_o[8]" A12;
+IO_PORT "GPIO_o[8]" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;
+IO_LOC "GPIO_o[7]" A10;
+IO_PORT "GPIO_o[7]" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;
+IO_LOC "GPIO_o[6]" A13;
+IO_PORT "GPIO_o[6]" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;
+IO_LOC "GPIO_o[5]" R6;
+IO_PORT "GPIO_o[5]" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;
+IO_LOC "GPIO_o[4]" T5;
+IO_PORT "GPIO_o[4]" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;
+IO_LOC "GPIO_o[3]" T6;
+IO_PORT "GPIO_o[3]" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;
+IO_LOC "GPIO_o[2]" J16;
+IO_PORT "GPIO_o[2]" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;
+IO_LOC "GPIO_o[1]" H16;
+IO_PORT "GPIO_o[1]" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;
+IO_LOC "GPIO_o[0]" G16;
+IO_PORT "GPIO_o[0]" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;
+IO_PORT "Mosi0_o[7]" IO_TYPE=LVCMOS33;
+IO_LOC "Mosi0_o[6]" C1;
+IO_PORT "Mosi0_o[6]" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;
+IO_LOC "Mosi0_o[5]" F16;
+IO_PORT "Mosi0_o[5]" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;
+IO_LOC "Mosi0_o[4]" C7;
+IO_PORT "Mosi0_o[4]" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;
+IO_LOC "Mosi0_o[3]" B3;
+IO_PORT "Mosi0_o[3]" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;
+IO_LOC "Mosi0_o[2]" B5;
+IO_PORT "Mosi0_o[2]" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;
+IO_LOC "Mosi0_o[1]" R3;
+IO_PORT "Mosi0_o[1]" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;
+IO_LOC "Mosi0_o[0]" G1;
+IO_PORT "Mosi0_o[0]" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;
+IO_PORT "Sck_o[7]" IO_TYPE=LVCMOS33;
+IO_LOC "Sck_o[6]" C2;
+IO_PORT "Sck_o[6]" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;
+IO_LOC "Sck_o[5]" E16;
+IO_PORT "Sck_o[5]" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;
+IO_LOC "Sck_o[4]" B7;
+IO_PORT "Sck_o[4]" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;
+IO_LOC "Sck_o[3]" A3;
+IO_PORT "Sck_o[3]" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;
+IO_LOC "Sck_o[2]" A5;
+IO_PORT "Sck_o[2]" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;
+IO_LOC "Sck_o[1]" T2;
+IO_PORT "Sck_o[1]" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;
+IO_LOC "Sck_o[0]" G2;
+IO_PORT "Sck_o[0]" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;
+IO_PORT "Ss_o[7]" IO_TYPE=LVCMOS33;
+IO_LOC "Ss_o[6]" D2;
+IO_PORT "Ss_o[6]" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;
+IO_LOC "Ss_o[5]" F15;
+IO_PORT "Ss_o[5]" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;
+IO_LOC "Ss_o[4]" C8;
+IO_PORT "Ss_o[4]" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;
+IO_LOC "Ss_o[3]" B4;
+IO_PORT "Ss_o[3]" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;
+IO_LOC "Ss_o[2]" A4;
+IO_PORT "Ss_o[2]" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;
+IO_LOC "Ss_o[1]" R4;
+IO_PORT "Ss_o[1]" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;
+IO_LOC "Ss_o[0]" F1;
+IO_PORT "Ss_o[0]" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;
+IO_PORT "Clk50_o" IO_TYPE=LVCMOS33;
+IO_PORT "Clk100_o" IO_TYPE=LVCMOS33;
+IO_PORT "Clk600_o" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;
+IO_PORT "Clk5_o" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;
+IO_PORT "Clk20_o" IO_TYPE=LVCMOS33;
+IO_PORT "Clk30_o" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;
+IO_PORT "Clk40_o" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;
+IO_PORT "Clk75_o" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;
+IO_LOC "I2CSck_o" K16;
+IO_PORT "I2CSck_o" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;
+IO_LOC "I2CSda_io" L16;
+IO_PORT "I2CSda_io" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;
+IO_LOC "Mosi1_io" T12;
+IO_PORT "Mosi1_io" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;
+IO_LOC "MisoMax2870_i" B1;
+IO_PORT "MisoMax2870_i" IO_TYPE=LVCMOS33 PULL_MODE=UP BANK_VCCIO=3.3;
+IO_LOC "Miso2_i" T3;
+IO_PORT "Miso2_i" IO_TYPE=LVCMOS33 PULL_MODE=UP BANK_VCCIO=3.3;
+IO_LOC "Miso1_i" F2;
+IO_PORT "Miso1_i" IO_TYPE=LVCMOS33 PULL_MODE=UP BANK_VCCIO=3.3;
+IO_LOC "Ss_i" T9;
+IO_PORT "Ss_i" IO_TYPE=LVCMOS33 PULL_MODE=UP BANK_VCCIO=3.3;
+IO_LOC "Sck_i" T13;
+IO_PORT "Sck_i" IO_TYPE=LVCMOS33 PULL_MODE=UP BANK_VCCIO=3.3;
+IO_LOC "Mosi3_i" T15;
+IO_PORT "Mosi3_i" IO_TYPE=LVCMOS33 PULL_MODE=UP BANK_VCCIO=3.3;
+IO_LOC "Mosi2_i" T14;
+IO_PORT "Mosi2_i" IO_TYPE=LVCMOS33 PULL_MODE=UP BANK_VCCIO=3.3;
+IO_LOC "Mosi0_i" R12;
+IO_PORT "Mosi0_i" IO_TYPE=LVCMOS33 PULL_MODE=UP BANK_VCCIO=3.3;
+IO_LOC "Rst_i" R9;
+IO_PORT "Rst_i" IO_TYPE=LVCMOS33 PULL_MODE=UP BANK_VCCIO=3.3;
+IO_LOC "Clk_i" H11;
+IO_PORT "Clk_i" IO_TYPE=LVCMOS33 PULL_MODE=UP BANK_VCCIO=3.3;

src/constr/RF_FPGA.rao

@@ -0,0 +1,143 @@
+<?xml version="1" encoding="UTF-8"?>
+<GAO_CONFIG>
+    <Version>3.0</Version>
+    <Mode>Standard</Mode>
+    <AoCore index="0" sample_clock="clk100" trig_type="0" storage_depth="1024" window_num="1" capture_amount="1024" implementation="0" trigger_pos="0" module_name="RFTop" force_trigger_by_falling_edge="false" capture_init_data_enabled="false">
+        <SignalList>
+            <Signal capture_enable="true">Clk_i</Signal>
+            <Signal capture_enable="true">Mosi0_i</Signal>
+            <Signal capture_enable="true">Sck_i</Signal>
+            <Signal capture_enable="true">Ss_i</Signal>
+            <Signal capture_enable="true">Ss_o[0]</Signal>
+            <Signal capture_enable="true">Sck_o[0]</Signal>
+            <Signal capture_enable="true">Mosi0_o[0]</Signal>
+            <Bus capture_enable="true" name="configReg1[23:0]">
+                <Signal>configReg1[23]</Signal>
+                <Signal>configReg1[22]</Signal>
+                <Signal>configReg1[21]</Signal>
+                <Signal>configReg1[20]</Signal>
+                <Signal>configReg1[19]</Signal>
+                <Signal>configReg1[18]</Signal>
+                <Signal>configReg1[17]</Signal>
+                <Signal>configReg1[16]</Signal>
+                <Signal>configReg1[15]</Signal>
+                <Signal>configReg1[14]</Signal>
+                <Signal>configReg1[13]</Signal>
+                <Signal>configReg1[12]</Signal>
+                <Signal>configReg1[11]</Signal>
+                <Signal>configReg1[10]</Signal>
+                <Signal>configReg1[9]</Signal>
+                <Signal>configReg1[8]</Signal>
+                <Signal>configReg1[7]</Signal>
+                <Signal>configReg1[6]</Signal>
+                <Signal>configReg1[5]</Signal>
+                <Signal>configReg1[4]</Signal>
+                <Signal>configReg1[3]</Signal>
+                <Signal>configReg1[2]</Signal>
+                <Signal>configReg1[1]</Signal>
+                <Signal>configReg1[0]</Signal>
+            </Bus>
+            <Bus capture_enable="true" name="numOfConfigCmds[1:0]">
+                <Signal>numOfConfigCmds[1]</Signal>
+                <Signal>numOfConfigCmds[0]</Signal>
+            </Bus>
+            <Bus capture_enable="true" name="currState[3:0]">
+                <Signal>currState[3]</Signal>
+                <Signal>currState[2]</Signal>
+                <Signal>currState[1]</Signal>
+                <Signal>currState[0]</Signal>
+            </Bus>
+            <Bus capture_enable="true" name="nextState[3:0]">
+                <Signal>nextState[3]</Signal>
+                <Signal>nextState[2]</Signal>
+                <Signal>nextState[1]</Signal>
+                <Signal>nextState[0]</Signal>
+            </Bus>
+            <Signal capture_enable="true">RorQSPIFlag</Signal>
+            <Bus capture_enable="true" name="deviceID[4:0]">
+                <Signal>deviceID[4]</Signal>
+                <Signal>deviceID[3]</Signal>
+                <Signal>deviceID[2]</Signal>
+                <Signal>deviceID[1]</Signal>
+                <Signal>deviceID[0]</Signal>
+            </Bus>
+            <Bus capture_enable="true" name="dataToRxFifo[23:0]">
+                <Signal>dataToRxFifo[23]</Signal>
+                <Signal>dataToRxFifo[22]</Signal>
+                <Signal>dataToRxFifo[21]</Signal>
+                <Signal>dataToRxFifo[20]</Signal>
+                <Signal>dataToRxFifo[19]</Signal>
+                <Signal>dataToRxFifo[18]</Signal>
+                <Signal>dataToRxFifo[17]</Signal>
+                <Signal>dataToRxFifo[16]</Signal>
+                <Signal>dataToRxFifo[15]</Signal>
+                <Signal>dataToRxFifo[14]</Signal>
+                <Signal>dataToRxFifo[13]</Signal>
+                <Signal>dataToRxFifo[12]</Signal>
+                <Signal>dataToRxFifo[11]</Signal>
+                <Signal>dataToRxFifo[10]</Signal>
+                <Signal>dataToRxFifo[9]</Signal>
+                <Signal>dataToRxFifo[8]</Signal>
+                <Signal>dataToRxFifo[7]</Signal>
+                <Signal>dataToRxFifo[6]</Signal>
+                <Signal>dataToRxFifo[5]</Signal>
+                <Signal>dataToRxFifo[4]</Signal>
+                <Signal>dataToRxFifo[3]</Signal>
+                <Signal>dataToRxFifo[2]</Signal>
+                <Signal>dataToRxFifo[1]</Signal>
+                <Signal>dataToRxFifo[0]</Signal>
+            </Bus>
+            <Signal capture_enable="true">Rst_i</Signal>
+            <Signal capture_enable="true">rstInit</Signal>
+        </SignalList>
+        <Triggers>
+            <Trigger index="0">
+                <SignalList>
+                    <Signal>Ss_i</Signal>
+                </SignalList>
+            </Trigger>
+            <Trigger index="1">
+                <SignalList>
+                    <Signal>Rst_i</Signal>
+                </SignalList>
+            </Trigger>
+            <Trigger index="2"/>
+            <Trigger index="3"/>
+            <Trigger index="4"/>
+            <Trigger index="5"/>
+            <Trigger index="6"/>
+            <Trigger index="7"/>
+            <Trigger index="8"/>
+            <Trigger index="9"/>
+            <Trigger index="10"/>
+            <Trigger index="11"/>
+            <Trigger index="12"/>
+            <Trigger index="13"/>
+            <Trigger index="14"/>
+            <Trigger index="15"/>
+        </Triggers>
+        <MatchUnits>
+            <MatchUnit index="0" enabled="1" match_type="1" counter_enable="0" counter_width="2" counter="2" countinuous="0" func="0" value0="0" value1="0" trigger="0"/>
+            <MatchUnit index="1" enabled="1" match_type="1" counter_enable="0" counter_width="2" counter="2" countinuous="0" func="0" value0="1" value1="0" trigger="1"/>
+            <MatchUnit index="2" enabled="0" match_type="0" counter_enable="0" counter_width="2" counter="2" countinuous="0" func="0" value0="" value1=""/>
+            <MatchUnit index="3" enabled="0" match_type="0" counter_enable="0" counter_width="2" counter="2" countinuous="0" func="0" value0="" value1=""/>
+            <MatchUnit index="4" enabled="0" match_type="0" counter_enable="0" counter_width="2" counter="2" countinuous="0" func="0" value0="" value1=""/>
+            <MatchUnit index="5" enabled="0" match_type="0" counter_enable="0" counter_width="2" counter="2" countinuous="0" func="0" value0="" value1=""/>
+            <MatchUnit index="6" enabled="0" match_type="0" counter_enable="0" counter_width="2" counter="2" countinuous="0" func="0" value0="" value1=""/>
+            <MatchUnit index="7" enabled="0" match_type="0" counter_enable="0" counter_width="2" counter="2" countinuous="0" func="0" value0="" value1=""/>
+            <MatchUnit index="8" enabled="0" match_type="0" counter_enable="0" counter_width="2" counter="2" countinuous="0" func="0" value0="" value1=""/>
+            <MatchUnit index="9" enabled="0" match_type="0" counter_enable="0" counter_width="2" counter="2" countinuous="0" func="0" value0="" value1=""/>
+            <MatchUnit index="10" enabled="0" match_type="0" counter_enable="0" counter_width="2" counter="2" countinuous="0" func="0" value0="" value1=""/>
+            <MatchUnit index="11" enabled="0" match_type="0" counter_enable="0" counter_width="2" counter="2" countinuous="0" func="0" value0="" value1=""/>
+            <MatchUnit index="12" enabled="0" match_type="0" counter_enable="0" counter_width="2" counter="2" countinuous="0" func="0" value0="" value1=""/>
+            <MatchUnit index="13" enabled="0" match_type="0" counter_enable="0" counter_width="2" counter="2" countinuous="0" func="0" value0="" value1=""/>
+            <MatchUnit index="14" enabled="0" match_type="0" counter_enable="0" counter_width="2" counter="2" countinuous="0" func="0" value0="" value1=""/>
+            <MatchUnit index="15" enabled="0" match_type="0" counter_enable="0" counter_width="2" counter="2" countinuous="0" func="0" value0="" value1=""/>
+        </MatchUnits>
+        <Expressions type="Static">
+            <Expression>M0</Expression>
+            <Expression>M1</Expression>
+        </Expressions>
+    </AoCore>
+    <GAO_ID>0010011100001101</GAO_ID>
+</GAO_CONFIG>

src/constr/RF_FPGA.sdc

@@ -0,0 +1,21 @@
+//Copyright (C)2014-2024 GOWIN Semiconductor Corporation.
+//All rights reserved.
+//File Title: Timing Constraints file
+//Tool Version: V1.9.9.01 (64-bit) 
+//Created Time: 2024-03-18 14:44:39
+create_clock -name Clk_i -period 41.667 -waveform {0 20.834} [get_ports {Clk_i}]
+create_clock -name Sck_i -period 10 -waveform {0 5} [get_ports {Sck_i}]
+create_generated_clock -name clk30 -source [get_ports {Clk_i}] -master_clock Clk_i -divide_by 24 -multiply_by 30 [get_ports {Clk30_o}]
+create_generated_clock -name clk40 -source [get_ports {Clk_i}] -master_clock Clk_i -divide_by 24 -multiply_by 40 [get_ports {Clk40_o}]
+create_generated_clock -name clk50 -source [get_ports {Clk_i}] -master_clock Clk_i -divide_by 24 -multiply_by 50 [get_ports {Clk50_o}]
+create_generated_clock -name clk5 -source [get_ports {Clk_i}] -master_clock Clk_i -divide_by 24 -multiply_by 5 [get_ports {Clk5_o}]
+create_generated_clock -name clk360 -source [get_ports {Clk_i}] -master_clock Clk_i -divide_by 24 -multiply_by 360 [get_ports {Clk600_o}]
+create_generated_clock -name clk100 -source [get_ports {Clk_i}] -master_clock Clk_i -divide_by 24 -multiply_by 100 [get_ports {Clk100_o}]
+create_generated_clock -name clk20 -source [get_ports {Clk_i}] -master_clock Clk_i -divide_by 24 -multiply_by 20 [get_ports {Clk20_o}]
+create_generated_clock -name clk75 -source [get_ports {Clk_i}] -master_clock Clk_i -divide_by 24 -multiply_by 72 [get_ports {Clk75_o}]
+set_clock_groups -asynchronous -group [get_clocks {Clk_i Sck_i}]
+report_timing -setup -from_clock [get_clocks {clk100}] -max_paths 100 -max_common_paths 1
+report_timing -setup -from_clock [get_clocks {clk360}] -max_paths 100 -max_common_paths 1
+report_timing -setup -from_clock [get_clocks {clk75}] -max_paths 100 -max_common_paths 1
+report_timing -setup -from_clock [get_clocks {clk50}] -max_paths 100 -max_common_paths 1
+report_timing -setup -from [get_ports {Rst_i}]

src/src/ClkGen/ClkGen.ipc

@@ -0,0 +1,24 @@
+[General]
+ipc_version=4
+file=ClkGen
+module=ClkGen
+target_device=gw1n9c-046
+type=clock_rpll
+version=1.0
+
+[Config]
+CKLOUTD3=false
+CLKFB_SOURCE=0
+CLKIN_FREQ=24
+CLKOUTD=false
+CLKOUTP=false
+CLKOUT_BYPASS=false
+CLKOUT_DIVIDE_DYN=true
+CLKOUT_FREQ=360
+CLKOUT_TOLERANCE=0
+DYNAMIC=true
+LANG=0
+LOCK_EN=false
+MODE_GENERAL=true
+PLL_PWD=false
+RESET_PLL=false

src/src/ClkGen/ClkGen.mod

@@ -0,0 +1,33 @@
+-series GW1N
+-device GW1N-9
+-device_version C
+-package PBGA256
+-part_number GW1N-LV9PG256C6/I5
+
+
+-mod_name ClkGen
+-file_name ClkGen
+-path C:/Users/AnatoliyChigirinskiy/Documents/RF_FPGA/src/ClkGen/
+-type PLL
+-rPll true
+-file_type vlg
+-dev_type GW1N-9C
+-dyn_idiv_sel false
+-idiv_sel 1
+-dyn_fbdiv_sel false
+-fbdiv_sel 15
+-dyn_odiv_sel false
+-odiv_sel 2
+-dyn_da_en true
+-rst_sig false
+-rst_sig_p false
+-fclkin 24
+-clkfb_sel 0
+-en_lock false
+-clkout_bypass false
+-clkout_ft_dir 1
+-en_clkoutp false
+-clkoutp_bypass false
+-en_clkoutd false
+-clkoutd_bypass false
+-en_clkoutd3 false

src/src/ClkGen/ClkGen_tmp.v

@@ -0,0 +1,18 @@
+//Copyright (C)2014-2023 Gowin Semiconductor Corporation.
+//All rights reserved.
+//File Title: Template file for instantiation
+//GOWIN Version: V1.9.9 Beta
+//Part Number: GW1N-LV9PG256C6/I5
+//Device: GW1N-9
+//Device Version: C
+//Created Time: Thu Dec 21 10:35:59 2023
+
+//Change the instance name and port connections to the signal names
+//--------Copy here to design--------
+
+    ClkGen your_instance_name(
+        .clkout(clkout_o), //output clkout
+        .clkin(clkin_i) //input clkin
+    );
+
+//--------Copy end-------------------

src/src/ClkGen/gowin_rpll/gClkGen.ipc

@@ -0,0 +1,24 @@
+[General]
+ipc_version=4
+file=gClkGen
+module=gClkGen
+target_device=gw1n9c-046
+type=clock_rpll
+version=1.0
+
+[Config]
+CKLOUTD3=false
+CLKFB_SOURCE=1
+CLKIN_FREQ=24
+CLKOUTD=false
+CLKOUTP=false
+CLKOUT_BYPASS=false
+CLKOUT_DIVIDE_DYN=true
+CLKOUT_FREQ=100
+CLKOUT_TOLERANCE=0
+DYNAMIC=true
+LANG=0
+LOCK_EN=true
+MODE_GENERAL=true
+PLL_PWD=false
+RESET_PLL=false

src/src/ClkGen/gowin_rpll/gClkGen.mod

@@ -0,0 +1,33 @@
+-series GW1N
+-device GW1N-9
+-device_version C
+-package PBGA256
+-part_number GW1N-LV9PG256C6/I5
+
+
+-mod_name gClkGen
+-file_name gClkGen
+-path C:/Users/AnatoliyChigirinskiy/Documents/RF_FPGA/src/ClkGen/gowin_rpll/
+-type PLL
+-rPll true
+-file_type vlg
+-dev_type GW1N-9C
+-dyn_idiv_sel false
+-idiv_sel 6
+-dyn_fbdiv_sel false
+-fbdiv_sel 25
+-dyn_odiv_sel false
+-odiv_sel 4
+-dyn_da_en true
+-rst_sig false
+-rst_sig_p false
+-fclkin 24
+-clkfb_sel 1
+-en_lock true
+-clkout_bypass false
+-clkout_ft_dir 1
+-en_clkoutp false
+-clkoutp_bypass false
+-en_clkoutd false
+-clkoutd_bypass false
+-en_clkoutd3 false

src/src/ClkGen/gowin_rpll/gClkGen_tmp.v

@@ -0,0 +1,20 @@
+//Copyright (C)2014-2023 Gowin Semiconductor Corporation.
+//All rights reserved.
+//File Title: Template file for instantiation
+//GOWIN Version: V1.9.9 Beta
+//Part Number: GW1N-LV9PG256C6/I5
+//Device: GW1N-9
+//Device Version: C
+//Created Time: Mon Dec 25 15:26:15 2023
+
+//Change the instance name and port connections to the signal names
+//--------Copy here to design--------
+
+    gClkGen your_instance_name(
+        .clkout(clkout_o), //output clkout
+        .lock(lock_o), //output lock
+        .clkin(clkin_i), //input clkin
+        .clkfb(clkfb_i) //input clkfb
+    );
+
+//--------Copy end-------------------

src/src/ClkGenGowin/ClkGenGowin.v

@@ -0,0 +1,113 @@
+module ClkGenGowin (
+  input Clk_i,
+  input Rst_i,
+  output Clk75_o,
+  output Clk50_o,
+  output Clk40_o,
+  output Clk30_o,
+  output Clk5_o
+);
+
+
+localparam Div75MHz = 5;
+localparam Div50MHz = 7;
+localparam Div40MHz = 9;
+localparam Div30MHz = 12;
+localparam Div5MHz = 72;
+
+
+
+reg [16:0] cnt75;
+reg [16:0] cnt50;
+reg [16:0] cnt40;
+reg [16:0] cnt30;
+reg [16:0] cnt5;
+
+reg clk;
+wire clk_o;
+
+
+always @(posedge Clk_i or posedge Rst_i) begin 
+    if (Rst_i) begin 
+        cnt75 <= 0;
+    end
+    else begin 
+        if (cnt75 >= Div75MHz-1) begin 
+            cnt75 <= 0;
+        end
+        else begin 
+            cnt75 <= cnt75 + 1;
+        end
+    end
+end
+
+always @(posedge Clk_i or posedge Rst_i) begin 
+    if (Rst_i) begin 
+        cnt50 <= 0;
+    end
+    else begin 
+        if (cnt50 >= Div50MHz-1) begin 
+            cnt50 <= 0;
+        end
+        else begin 
+            cnt50 <= cnt50 + 1;
+        end
+    end
+end
+
+always @(posedge Clk_i or posedge Rst_i) begin 
+    if (Rst_i) begin 
+        cnt40 <= 0;
+    end
+    else begin 
+        if (cnt40 >= Div40MHz-1) begin 
+            cnt40 <= 0;
+        end
+        else begin 
+            cnt40 <= cnt40 + 1;
+        end
+    end
+end
+
+always @(posedge Clk_i or posedge Rst_i) begin 
+    if (Rst_i) begin 
+        cnt30 <= 0;
+    end
+    else begin 
+        if (cnt30 >= Div30MHz-1) begin 
+            cnt30 <= 0;
+        end
+        else begin 
+            cnt30 <= cnt30 + 1;
+        end
+    end
+end
+
+always @(posedge Clk_i or posedge Rst_i) begin 
+    if (Rst_i) begin 
+        cnt5 <= 0;
+    end
+    else begin 
+        if (cnt5 >= Div5MHz-1) begin 
+            cnt5 <= 0;
+        end
+        else begin 
+            cnt5 <= cnt5 + 1;
+        end
+    end
+end
+
+assign Clk75_o = (cnt75 < Div75MHz/2) ? 1 : 0;
+assign Clk50_o = (cnt50 < Div50MHz/2) ? 1 : 0;
+assign Clk40_o = (cnt40 < Div40MHz/2) ? 1 : 0;
+assign Clk30_o = (cnt30 < Div30MHz/2) ? 1 : 0;
+assign Clk5_o = (cnt5 < Div5MHz/2) ? 1 : 0;
+
+
+
+
+
+
+
+
+endmodule

src/src/ControlUnit/ControlUnit.v

@@ -0,0 +1,114 @@
+module ControlUnit #(
+    parameter Stages = 2,
+    parameter Width = 5,
+    parameter FifoNum = 8
+
+)(
+    input FastClk_i,
+    input [FifoNum-1:0] SlowClk_i,
+    input [Width-1:0] CurrState_i,
+    input Rst_i,
+
+
+
+    output [FifoNum-1:0] LaunchSpiSync_o,
+    output [4:0] CurrStateSync1_o,
+    output [4:0] CurrStateSync2_o,
+    output [4:0] CurrStateSync3_o,
+    output [4:0] CurrStateSync4_o,
+    output [4:0] CurrStateSync5_o
+
+
+
+);
+
+wire [0:2] currStateSync [FifoNum-1:0];
+
+// launch registers 
+reg [Width-1:0] currStateReg;
+
+
+
+
+
+//capture registers
+
+reg [Stages*Width-1:0] currStateReg5Mhz_c;
+reg [Stages*Width-1:0] currStateReg30Mhz_c;
+reg [Stages*Width-1:0] currStateReg40Mhz_c;
+reg [Stages*Width-1:0] currStateReg50Mhz_c;
+reg [Stages*Width-1:0] currStateReg70Mhz_c;
+
+
+
+assign currStateSync[0] = currStateReg5Mhz_c[Stages*Width-1:(Stages-1)*Width];
+assign currStateSync[1] = currStateReg30Mhz_c[Stages*Width-1:(Stages-1)*Width];
+assign currStateSync[2] = currStateReg40Mhz_c[Stages*Width-1:(Stages-1)*Width];
+assign currStateSync[3] = currStateReg50Mhz_c[Stages*Width-1:(Stages-1)*Width];
+assign currStateSync[4] = currStateReg70Mhz_c[Stages*Width-1:(Stages-1)*Width];
+
+assign CurrStateSync1_o = currStateReg5Mhz_c[Stages*Width-1:(Stages-1)*Width];
+assign CurrStateSync2_o = currStateReg30Mhz_c[Stages*Width-1:(Stages-1)*Width];
+assign CurrStateSync3_o = currStateReg40Mhz_c[Stages*Width-1:(Stages-1)*Width];
+assign CurrStateSync4_o = currStateReg50Mhz_c[Stages*Width-1:(Stages-1)*Width];
+assign CurrStateSync5_o = currStateReg70Mhz_c[Stages*Width-1:(Stages-1)*Width];
+
+
+
+assign LaunchSpiSync_o[0] = (!Rst_i) ? 1'b1 : 1'b0;
+assign LaunchSpiSync_o[1] = (!Rst_i) ? 1'b1 : 1'b0;
+assign LaunchSpiSync_o[2] = (!Rst_i) ? 1'b1 : 1'b0;
+assign LaunchSpiSync_o[3] = (!Rst_i) ? 1'b1 : 1'b0;
+assign LaunchSpiSync_o[4] = (!Rst_i) ? 1'b1 : 1'b0;
+assign LaunchSpiSync_o[5] = (!Rst_i) ? 1'b1 : 1'b0;
+assign LaunchSpiSync_o[6] = (!Rst_i) ? 1'b1 : 1'b0;
+
+
+
+always @(posedge FastClk_i) begin 
+    currStateReg <= CurrState_i;
+end
+
+
+always @(posedge SlowClk_i[0]) begin 
+    currStateReg5Mhz_c <= {currStateReg5Mhz_c[(Stages-1)*Width-1:0], currStateReg};
+end
+
+always @(posedge SlowClk_i[1]) begin 
+    currStateReg30Mhz_c <= {currStateReg30Mhz_c[(Stages-1)*Width-1:0], currStateReg};
+end
+
+always @(posedge SlowClk_i[2]) begin 
+    currStateReg40Mhz_c <= {currStateReg40Mhz_c[(Stages-1)*Width-1:0], currStateReg};
+end
+
+always @(posedge SlowClk_i[3]) begin 
+    currStateReg50Mhz_c <= {currStateReg50Mhz_c[(Stages-1)*Width-1:0], currStateReg};
+end
+
+always @(posedge SlowClk_i[4]) begin 
+    currStateReg70Mhz_c <= {currStateReg70Mhz_c[(Stages-1)*Width-1:0], currStateReg};
+end
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+endmodule

src/src/I2C/I2CSM.v

@@ -0,0 +1,80 @@
+module I2CSM (
+	iclk,
+	irst_n,
+	fs_data_rdy,
+	fs_delay_filter,
+	sm_i2c_req,
+	sm_en_i2c_cnt
+	);
+
+
+parameter	IDLE 			= 0;
+parameter	LAUNCH_I2C		= 1; 
+parameter	WAIT_DATA_RDY	= 2; 
+parameter	WAIT_DELAY_CNT	= 3;
+	
+input	wire	iclk;
+input	wire	irst_n;
+input	wire	fs_data_rdy;
+input	wire	fs_delay_filter;
+output	reg		sm_i2c_req;
+output	reg		sm_en_i2c_cnt;
+
+reg	[1:0]	current_state;
+
+always @(posedge iclk or negedge irst_n) begin
+	if(~irst_n) begin
+		current_state <= IDLE;
+	end
+	else begin
+		case(current_state)
+			IDLE : begin
+				current_state <= LAUNCH_I2C;
+			end
+			LAUNCH_I2C : begin
+				current_state <= WAIT_DATA_RDY;
+			end
+			WAIT_DATA_RDY : begin
+				if(fs_data_rdy) begin
+					current_state <= WAIT_DELAY_CNT;
+				end
+				else begin
+					current_state <= WAIT_DATA_RDY;
+				end
+			end
+			WAIT_DELAY_CNT : begin
+				if(fs_delay_filter) begin
+					current_state <= IDLE;
+				end
+				else begin
+					current_state <= WAIT_DELAY_CNT;
+				end
+			end
+		endcase
+	end	
+end
+
+always @(current_state) begin
+	sm_i2c_req		= 1'b0;
+	sm_en_i2c_cnt	= 1'b0;
+	case(current_state)
+		IDLE : begin
+			sm_i2c_req		= 1'b0;
+			sm_en_i2c_cnt	= 1'b0;
+		end
+		LAUNCH_I2C : begin
+			sm_i2c_req 		= 1'b1;
+			sm_en_i2c_cnt	= 1'b0;
+		end
+		WAIT_DATA_RDY : begin
+			sm_i2c_req 		= 1'b0;
+			sm_en_i2c_cnt	= 1'b0;
+		end
+		WAIT_DELAY_CNT : begin
+			sm_i2c_req 	  = 1'b0;
+			sm_en_i2c_cnt = 1'b1;
+		end
+	endcase
+end
+
+endmodule 

src/src/I2C/temp_i2c_master_ver2.v

@@ -0,0 +1,489 @@
+module temp_i2c_master_ver2(
+	i_clk,
+	i_rst_n,
+	i_addr,
+	i_ptr,
+	i_req,
+	o_data,
+	o_data_valid,
+	SCK,
+	SDA
+	);
+parameter	CLK_DIV = 100;
+
+parameter	CLK_DIV_HALF = CLK_DIV/2;
+parameter	CLK_DIV_QUA  = CLK_DIV/4;
+	
+parameter	IDLE 		= 4'd0;	
+parameter	START 		= 4'd1;
+parameter	WR_ADDR		= 4'd2;
+parameter	WR_ADDR_A 	= 4'd3;
+parameter	RD_MSB		= 4'd4;
+parameter	RD_MSB_A	= 4'd5;
+parameter	RD_LSB		= 4'd6;
+parameter	RD_LSB_A	= 4'd7;
+parameter	STOP		= 4'd8;
+parameter	DATA_VAL	= 4'd9;
+input	wire		i_clk;
+input	wire		i_rst_n;
+input	wire[2:0]	i_addr;
+input	wire[1:0]	i_ptr;
+input	wire		i_req;
+output	reg	[15:0]	o_data;
+output	reg			o_data_valid;
+output	wire		SCK;
+inout	wire		SDA;
+
+reg	[3:0]	present_state;
+reg	[3:0]	next_state;
+
+reg		sm_en_clk;
+reg		sm_start;
+reg		sm_transfer;
+reg		sm_rd_tr;
+reg		sm_stop;
+reg		sm_data_valid;
+reg		sm_no_ans;
+//in data buf
+reg	[2:0]	i_addr_reg;
+reg			i_req_reg;
+
+
+reg	[7:0]	data_clk_cnt;
+reg	[7:0]	sck_clk_cnt;
+reg	[7:0]	quad_clk_cnt;
+
+reg			data_clk_reg;
+reg			sck_clk_reg;
+reg			quad_clk_reg;
+
+reg			pos_data_clk;
+reg			pos_data_clk_pipe;
+reg			neg_data_clk;
+
+reg			pos_sck_clk;
+reg			neg_sck_clk;
+
+reg			pos_quad_clk;
+reg			neg_quad_clk;
+
+reg			data_clk_cnt_flag;
+reg			sck_clk_cnt_flag;
+reg			quad_clk_cnt_flag;
+
+reg			en_data_clk_cnt;
+reg			en_sck_clk_cnt;
+
+reg			sck_reg;
+reg			sm_stop_pos_data;
+reg	[7:0]	tx_data_sr;
+reg	[2:0]	tr_bit_cnt;
+reg		en_rd_tr;
+reg		tr_bit_cnt_flag;
+reg		stop_flag;
+reg		rd_data_en;
+reg		sm_en_clk_reg;
+reg		sck_clk_reg_out;
+assign	SCK = sck_clk_reg_out;
+assign	SDA = ~en_rd_tr ? sck_reg : 1'bz;
+
+always @(posedge i_clk or negedge i_rst_n) begin
+	if(!i_rst_n) begin
+		o_data_valid <= 1'b0;
+		sm_en_clk_reg <= 1'b0;
+		sck_clk_reg_out <= 1'b1;
+		en_sck_clk_cnt <= 1'b0;
+	end
+	else begin
+		o_data_valid  <= sm_data_valid;
+		sm_en_clk_reg <= sm_en_clk;
+		en_sck_clk_cnt <= sm_en_clk_reg;
+		sck_clk_reg_out <= sck_clk_reg;
+	end
+end
+
+always @(posedge i_clk or negedge i_rst_n) begin
+	if(!i_rst_n) begin
+		data_clk_reg 	<= 1'b0;
+		sck_clk_reg  	<= 1'b1;
+		quad_clk_reg 	<= 1'b0;	
+		en_data_clk_cnt <= 1'b0;
+		pos_quad_clk	<= 1'b0;
+		neg_quad_clk	<= 1'b0;
+	end
+	else if(!sm_en_clk_reg) begin
+		data_clk_reg 	<= 1'b0;
+		sck_clk_reg  	<= 1'b1;
+		quad_clk_reg 	<= 1'b0;	
+		en_data_clk_cnt <= 1'b0;		
+	end
+	else begin
+		pos_quad_clk <= ~quad_clk_reg & quad_clk_cnt_flag;
+		neg_quad_clk <=  quad_clk_reg & quad_clk_cnt_flag;
+		if(pos_quad_clk) begin
+			en_data_clk_cnt <= 1'b1;
+		end
+		if(data_clk_cnt_flag) begin
+			data_clk_reg <= ~data_clk_reg;
+		end
+		if(sck_clk_cnt_flag) begin
+			sck_clk_reg <= ~sck_clk_reg;
+		end
+		if(quad_clk_cnt_flag) begin
+			quad_clk_reg <= ~quad_clk_reg;
+		end
+	end
+end
+
+always @(posedge i_clk or negedge i_rst_n) begin
+	if(!i_rst_n) begin
+		quad_clk_cnt <= 0;
+	end
+	else if (!sm_en_clk_reg || quad_clk_cnt_flag) begin
+		quad_clk_cnt <= 0;
+	end
+	else begin
+		quad_clk_cnt <= quad_clk_cnt + 1;
+	end
+end
+
+always @(posedge i_clk or negedge i_rst_n) begin
+	if(!i_rst_n) begin
+		sck_clk_cnt <= 0;
+	end
+	else if(!en_sck_clk_cnt || sck_clk_cnt_flag) begin
+		sck_clk_cnt <= 0;
+	end
+	else begin
+		sck_clk_cnt <= sck_clk_cnt + 1;
+	end
+end
+
+always @(posedge i_clk or negedge i_rst_n) begin
+	if(!i_rst_n) begin
+		data_clk_cnt <= 0;
+	end
+	else if(!sm_en_clk_reg || data_clk_cnt_flag) begin
+		data_clk_cnt <= 0;
+	end
+	else if(en_data_clk_cnt) begin
+		data_clk_cnt <= data_clk_cnt + 1;
+	end
+end
+
+always @(posedge i_clk or negedge i_rst_n) begin
+	if(!i_rst_n) begin
+		sm_stop_pos_data <= 1'b0;
+	end
+	else if(!sm_en_clk_reg) begin
+		sm_stop_pos_data <= 1'b0;
+	end
+	else if(sm_stop && pos_data_clk) begin
+		sm_stop_pos_data <= 1'b1;
+	end
+end
+
+always @(posedge i_clk or negedge i_rst_n) begin
+	if(!i_rst_n) begin
+		stop_flag <= 1'b0;
+	end
+	else if(!sm_en_clk_reg) begin
+		stop_flag <= 1'b0;
+	end
+	else if(pos_sck_clk & sm_stop_pos_data) begin
+		stop_flag <= 1'b1;
+	end
+end
+
+always @(posedge i_clk or negedge i_rst_n) begin
+	if(!i_rst_n) begin
+		sck_reg <= 1'b1;
+	end
+	else if(!sm_en_clk_reg || pos_data_clk_pipe && sm_no_ans) begin
+		sck_reg <= 1'b1;
+	end
+	else if((pos_quad_clk && sm_start) || (sm_stop && pos_data_clk_pipe)) begin
+		sck_reg <= 1'b0;
+	end
+	else if(pos_data_clk_pipe) begin
+		sck_reg <= tx_data_sr[7];
+	end
+end
+
+always @(posedge i_clk or negedge i_rst_n) begin
+	if(!i_rst_n) begin
+		rd_data_en <= 1'b0;
+	end
+	else if(pos_data_clk_pipe) begin
+		rd_data_en <= sm_transfer & sm_rd_tr;
+	end
+end
+
+always @(posedge i_clk or negedge i_rst_n) begin
+	if(!i_rst_n) begin
+		o_data <= 16'b0;
+	end
+	else if(rd_data_en & pos_sck_clk) begin
+		o_data <= {o_data[14:0], SDA};
+	end
+end
+
+always @(posedge i_clk or negedge i_rst_n) begin
+	if(!i_rst_n) begin
+		tr_bit_cnt_flag <= 1'b0;
+	end
+	else begin
+		tr_bit_cnt_flag <= &tr_bit_cnt;
+	end
+end
+
+always @(posedge i_clk or negedge i_rst_n) begin
+	if(!i_rst_n) begin
+		en_rd_tr <= 1'b0;
+	end
+	else if(sm_rd_tr && pos_data_clk_pipe) begin
+		en_rd_tr <= 1'b1;
+	end
+	else if(pos_data_clk_pipe) begin
+		en_rd_tr <= 1'b0;
+	end
+end
+
+always @(posedge i_clk or negedge i_rst_n) begin
+	if(!i_rst_n) begin
+		tr_bit_cnt <= 3'b0;
+	end
+	else if(!sm_transfer) begin
+		tr_bit_cnt <= 3'b0;
+	end
+	else if(pos_data_clk) begin
+		tr_bit_cnt <= tr_bit_cnt + 3'b1;
+	end
+end
+
+always @(posedge i_clk or negedge i_rst_n) begin
+	if(!i_rst_n) begin
+		tx_data_sr <= 8'b0;
+	end
+	else if(sm_start) begin
+		tx_data_sr[7:0] <= {4'b1001, i_addr_reg[2:0], 1'b1};
+	end
+	else if(pos_data_clk_pipe) begin
+		tx_data_sr <= tx_data_sr << 1;
+	end
+end
+
+always @(posedge i_clk or negedge i_rst_n) begin
+	if(!i_rst_n) begin
+		data_clk_cnt_flag 		<= 1'b0;
+		quad_clk_cnt_flag 		<= 1'b0;
+		pos_data_clk			<= 1'b0;
+		neg_data_clk			<= 1'b0;
+		pos_data_clk_pipe       <= 1'b0;
+	end
+	else begin
+		data_clk_cnt_flag 		<= (data_clk_cnt == CLK_DIV_HALF-2);
+		quad_clk_cnt_flag 		<= (quad_clk_cnt == CLK_DIV_QUA-2);
+		pos_data_clk 			<= data_clk_cnt_flag & ~data_clk_reg;
+		neg_data_clk 			<= data_clk_cnt_flag &  data_clk_reg;
+		pos_data_clk_pipe       <= pos_data_clk;
+	end
+end
+
+always @(posedge i_clk or negedge i_rst_n) begin
+	if(!i_rst_n) begin
+		sck_clk_cnt_flag 	<= 1'b0;
+		pos_sck_clk			<= 1'b0;
+	end
+	else begin
+		sck_clk_cnt_flag 	<= (sck_clk_cnt == CLK_DIV_HALF-2);
+		pos_sck_clk 		<=  sck_clk_cnt_flag & ~sck_clk_reg;
+	end
+end
+//
+always @(posedge i_clk or negedge i_rst_n) begin
+	if(!i_rst_n) begin
+		i_addr_reg <= 3'b0;
+	end
+	else if(i_req) begin
+		i_addr_reg <= i_addr;
+	end
+end
+
+always @(posedge i_clk or negedge i_rst_n) begin
+	if(!i_rst_n) begin
+		i_req_reg <= 1'b0;
+	end
+	else begin
+		i_req_reg <= i_req;
+	end
+end
+
+always @(posedge i_clk or negedge i_rst_n) begin
+	if(!i_rst_n) begin
+		present_state <= IDLE;
+	end
+	else begin
+		present_state <= next_state;
+	end
+end
+
+always @(present_state or i_req_reg or pos_data_clk or neg_data_clk or tr_bit_cnt_flag or stop_flag) begin
+	sm_en_clk 		= 1'b0;
+	sm_start		= 1'b0;
+	sm_transfer		= 1'b0;
+	sm_rd_tr		= 1'b0;
+	sm_stop     	= 1'b0;
+	sm_data_valid 	= 1'b0;
+	sm_no_ans		= 1'b0;
+	next_state 	= IDLE;
+	case(present_state)
+		IDLE : begin
+			sm_en_clk 		= 1'b0;
+			sm_start		= 1'b0;
+			sm_transfer 	= 1'b0;
+			sm_rd_tr		= 1'b0;
+			sm_stop     	= 1'b0;
+			sm_data_valid 	= 1'b0;
+			sm_no_ans		= 1'b0;
+			if(i_req_reg) begin
+				next_state = START;
+			end
+			else begin
+				next_state 	= present_state;
+			end
+		end
+		START : begin
+			sm_en_clk 		= 1'b1;
+			sm_start  		= 1'b1;
+			sm_transfer 	= 1'b0;
+			sm_rd_tr		= 1'b0;
+			sm_stop     	= 1'b0;
+			sm_data_valid 	= 1'b0;
+			sm_no_ans		= 1'b0;
+			if(pos_data_clk) begin
+				next_state = WR_ADDR;
+			end
+			else begin
+				next_state = START;
+			end
+		end
+		WR_ADDR : begin
+			sm_en_clk 		= 1'b1;
+			sm_start  		= 1'b0;
+			sm_transfer 	= 1'b1;
+			sm_rd_tr		= 1'b0;
+			sm_stop     	= 1'b0;
+			sm_data_valid 	= 1'b0;
+			sm_no_ans		= 1'b0;
+			if(tr_bit_cnt_flag && pos_data_clk) begin
+				next_state = WR_ADDR_A;
+			end
+			else begin 
+				next_state = WR_ADDR;
+			end
+		end
+		WR_ADDR_A : begin
+			sm_en_clk 		= 1'b1;
+			sm_start  		= 1'b0;
+			sm_transfer 	= 1'b0;
+			sm_rd_tr		= 1'b1;
+			sm_stop     	= 1'b0;
+			sm_data_valid 	= 1'b0;
+			sm_no_ans		= 1'b0;
+			if(pos_data_clk) begin
+				next_state = RD_MSB;
+			end
+			else begin
+				next_state = WR_ADDR_A;
+			end
+		end
+		RD_MSB : begin
+			sm_en_clk 		= 1'b1;
+			sm_start  		= 1'b0;
+			sm_transfer 	= 1'b1;
+			sm_rd_tr		= 1'b1;
+			sm_stop     	= 1'b0;
+			sm_data_valid 	= 1'b0;
+			sm_no_ans		= 1'b0;
+			if(pos_data_clk && tr_bit_cnt_flag) begin
+				next_state = RD_MSB_A;
+			end
+			else begin
+				next_state  = RD_MSB;
+			end	
+		end
+		RD_MSB_A : begin
+			sm_en_clk 		= 1'b1;
+			sm_start  		= 1'b0;
+			sm_transfer 	= 1'b0;
+			sm_rd_tr		= 1'b0;//1;
+			sm_stop     	= 1'b0;
+			sm_data_valid 	= 1'b0;
+			sm_no_ans		= 1'b0;
+			if(pos_data_clk) begin
+				next_state = RD_LSB;
+			end
+			else begin
+				next_state  = RD_MSB_A;
+			end	
+		end
+		RD_LSB : begin
+			sm_en_clk 		= 1'b1;
+			sm_start  		= 1'b0;
+			sm_transfer 	= 1'b1;
+			sm_rd_tr		= 1'b1;
+			sm_stop     	= 1'b0;
+			sm_data_valid 	= 1'b0;
+			sm_no_ans		= 1'b0;
+			if(pos_data_clk && tr_bit_cnt_flag) begin
+				next_state = RD_LSB_A;
+			end
+			else begin
+				next_state  = RD_LSB;
+			end	
+		end
+		RD_LSB_A : begin
+			sm_en_clk 		= 1'b1;
+			sm_start  		= 1'b0;
+			sm_transfer 	= 1'b0;
+			sm_rd_tr		= 1'b0;
+			sm_stop     	= 1'b0;
+			sm_data_valid 	= 1'b0;
+			sm_no_ans		= 1'b1;
+			if(pos_data_clk) begin
+				next_state = STOP;
+			end
+			else begin
+				next_state  = RD_LSB_A;
+			end			
+		end
+		STOP : begin
+			sm_en_clk 		= 1'b1;
+			sm_start  		= 1'b0;
+			sm_transfer 	= 1'b0;
+			sm_rd_tr		= 1'b0;
+			sm_stop     	= 1'b1;
+			sm_data_valid 	= 1'b0;
+			sm_no_ans		= 1'b0;
+			if(neg_data_clk) begin
+				next_state = DATA_VAL;
+			end
+			else begin
+				next_state  = STOP;
+			end		
+		end
+		DATA_VAL : begin
+			sm_en_clk 		= 1'b0;
+			sm_start  		= 1'b0;
+			sm_transfer 	= 1'b0;
+			sm_rd_tr		= 1'b0;
+			sm_stop     	= 1'b0;
+			sm_data_valid 	= 1'b1;
+			sm_no_ans		= 1'b0;
+			next_state  	= IDLE;
+		end
+	endcase
+end
+
+endmodule

src/src/NCO/CordicNco.v

@@ -0,0 +1,246 @@
+/*
+    NCO module.
+    The module implements CORDIC algorithm
+*/
+
+module CordicNco 
+#(	parameter                   ODatWidth	= 18,
+	parameter                   PhIncWidth	= 32,
+	parameter                   IterNum		= 10,
+	parameter                   EnSinN		= 0,
+	parameter                   WinTypeW	= 0
+)
+(
+    input	Clk_i,
+    input	Rst_i,
+    input	Val_i,
+    input	[PhIncWidth-1:0]	PhaseInc_i,
+	input	[WinTypeW-1:0]	WinType_i,
+	input	WindVal_i,
+	output	[ODatWidth-1:0]	Wind_o,
+	output	[ODatWidth-1:0]	Sin_o,
+	output	[ODatWidth-1:0]	Cos_o,
+    output	reg	Val_o
+);
+
+//================================================================================
+//  FUNCTIONS
+//================================================================================
+    function integer log2;
+        input integer value;
+        begin
+            log2 = 0;
+            while (value > 1) begin
+                value   = value >> 1;
+                log2    = log2 + 1;
+            end
+        end
+    endfunction
+//================================================================================
+//  LOCALPARAMS
+//================================================================================
+	localparam  [PhIncWidth-1:0]	angle270	= 3<<(PhIncWidth-2);
+	localparam  [PhIncWidth-1:0]	angle180	= 1<<(PhIncWidth-1);
+	localparam  [PhIncWidth-1:0]	angle90		= 1<<(PhIncWidth-2);
+	
+	localparam [17:0] initValue = 18'd78498;
+//================================================================================
+//  REG/WIRE DECLARATIONS
+//================================================================================
+	
+    wire	[PhIncWidth-1:0]	precompAngle[ODatWidth-1:0];   
+    wire	[ODatWidth-1:0]		xPipe[IterNum:0];
+    wire	[ODatWidth-1:0]		yPipe[IterNum:0];
+    wire	[IterNum:0]			valPipe;
+    reg		[PhIncWidth-1:0]	phaseDiffPipe[IterNum-1:0];
+    reg		[2:0]				scwSignPipe[IterNum-1:0];
+
+    reg		[PhIncWidth-1:0]	phaseAcc;
+    reg     [PhIncWidth-1:0]	currPhase;
+    reg		[2:0]				scwSignPrev;
+    reg		[2:0]				scwSign;
+    reg		[2:0]				valSr;
+
+	reg		[ODatWidth-1:0]		sin_o;
+	reg		[ODatWidth-1:0]		cos_o;
+	reg		[ODatWidth-1:0]		wind_o;
+    genvar	g;
+    integer	i;
+	
+	reg		valR;
+//================================================================================
+//  ASSIGNMENTS
+//================================================================================
+    assign	xPipe[0]	=	(Val_i)	?	initValue:xPipe[0];
+    assign	yPipe[0]	=	(Val_i)	?	initValue:yPipe[0];
+    assign	valPipe[0]	=	valSr[2];
+	assign	Wind_o		=	(WindVal_i&&WinType_i==0)	?	wind_o:14'b0;
+
+	assign precompAngle[0] = 32'd536870912;
+	assign precompAngle[1] = 32'd316933406;
+	assign precompAngle[2] = 32'd167458907;
+	assign precompAngle[3] = 32'd85004756;
+	assign precompAngle[4] = 32'd42667331;
+	assign precompAngle[5] = 32'd21354465;
+	assign precompAngle[6] = 32'd10679838;
+	assign precompAngle[7] = 32'd5340245;
+	assign precompAngle[8] = 32'd2670163;
+	assign precompAngle[9] = 32'd1335087;
+	assign precompAngle[10] = 32'd667544;
+	assign precompAngle[11] = 32'd333772;
+	assign precompAngle[12] = 32'd166886;
+	assign precompAngle[13] = 32'd83443;
+	// assign precompAngle[14] = 32'd41722;
+	// assign precompAngle[15] = 32'd20861;
+	// assign precompAngle[16] = 32'd10430;
+	// assign precompAngle[17] = 32'd5215;
+	//assign precompAngle[18] = 32'd2608;
+
+	assign	Sin_o	=	WindVal_i	?	sin_o	:	14'h0;
+	assign	Cos_o	=	WindVal_i	?	cos_o	:	14'h0;
+//================================================================================
+//  CODING
+//================================================================================
+always @(posedge Clk_i) begin
+    if (Rst_i) begin
+        valR	<=	1'b0;
+    end else begin
+		valR	<=	Val_i;
+	end
+end
+
+//  Phase handle logic
+always @(posedge Clk_i) begin
+    if (Rst_i) begin
+        phaseAcc   <= {PhIncWidth{1'b0}};
+    end else if (Val_i) begin
+        phaseAcc   <= phaseAcc + PhaseInc_i;
+    end	else	begin
+		phaseAcc   <= {PhIncWidth{1'b0}};
+	end
+end
+
+always @(posedge Clk_i) begin
+    if (Rst_i) begin
+        currPhase   <= {PhIncWidth{1'b0}};
+        scwSign         <= 3'b0;
+    end else begin
+        if (phaseAcc > angle270) begin
+            currPhase   <= {PhIncWidth{1'b0}} - phaseAcc;
+            scwSign         <= 3'b010;
+        end else if (phaseAcc > angle180) begin
+            currPhase   <= phaseAcc - angle180;
+            scwSign         <= 3'b011;
+        end else if (phaseAcc > angle90) begin
+            currPhase   <= angle180 - phaseAcc;
+            scwSign         <= 3'b001;
+        end else begin
+            currPhase   <= phaseAcc;
+            scwSign         <= 3'b000;
+        end
+    end
+end
+
+//--------------------------------------------------------------------------------
+//  CORDIC pipe
+
+always @(posedge Clk_i) begin
+    if (Rst_i) begin
+        valSr <= 3'b0;
+    end else if	(Val_i)	begin
+        valSr <= {valSr[1:0], Val_i};
+    end	else	begin
+		valSr <= 3'b0;
+	end
+end
+
+always @(posedge Clk_i) begin
+    phaseDiffPipe[0]  <= currPhase - precompAngle[0];
+    scwSignPipe[0]     <= scwSign;
+    for(i=1; i<IterNum; i=i+1) begin
+        scwSignPipe[i] <= scwSignPipe[i-1];
+        if (phaseDiffPipe[i-1][PhIncWidth-1]) begin
+            phaseDiffPipe[i] <= phaseDiffPipe[i-1] + precompAngle[i];
+        end else begin
+            phaseDiffPipe[i] <= phaseDiffPipe[i-1] - precompAngle[i];
+        end
+    end
+end
+
+generate
+    for (g = 0; g < IterNum; g = g + 1) begin : cordic_pipe
+        cordic_rotation #(
+            .ODatWidth	(ODatWidth),
+            .Shift      (g+1)
+        ) cordic_rotation_inst (
+            .Clk_i      (Clk_i),
+            .Rst_i      (Rst_i),
+			.X_i        (xPipe[g]),
+			.Y_i        (yPipe[g]),
+			.Val_i      (valPipe[g]),
+			.Sign_i     (phaseDiffPipe[g][PhIncWidth-1]),
+			.X_o        (xPipe[g+1]),
+			.Y_o        (yPipe[g+1]),
+			.Val_o      (valPipe[g+1])
+		);
+    end
+endgenerate
+
+//--------------------------------------------------------------------------------
+//  Output logic
+
+generate 
+    if (EnSinN) begin
+        always @(posedge Clk_i) begin
+            if (Rst_i) begin
+                sin_o       <= {ODatWidth{1'b0}};
+            end else begin
+                if (scwSignPrev[1]) begin
+                    sin_o   <=  yPipe[IterNum];
+                end else begin
+                    sin_o   <= ~yPipe[IterNum] + {{(ODatWidth-1){1'b0}}, 1'b1};
+                end
+            end
+        end
+    end else begin
+        always @(posedge Clk_i) begin
+            if (Rst_i) begin
+                sin_o       <= {ODatWidth{1'b0}};
+            end else begin
+				if (scwSignPrev[1]) begin
+					sin_o   <= ~yPipe[IterNum] + {{(ODatWidth-1){1'b0}}, 1'b1};
+				end else begin
+					sin_o   <=  yPipe[IterNum];
+				end
+            end
+        end
+		always @(posedge Clk_i) begin
+            if (Rst_i) begin
+                wind_o       <= {ODatWidth{1'b0}};
+            end else begin
+				if (scwSignPrev[2]) begin
+					wind_o   <= ~yPipe[IterNum] + {{(ODatWidth-1){1'b0}}, 1'b1};
+				end else begin
+					wind_o   <=  yPipe[IterNum];
+				end
+            end
+        end
+    end
+endgenerate
+
+always @(posedge Clk_i) begin
+    if (Rst_i) begin
+        cos_o		<= {ODatWidth{1'b0}};
+        scwSignPrev	<= 3'b0;
+        Val_o		<= 1'b0;
+    end else begin
+        if (scwSignPrev[0]) begin
+            cos_o	<= ~xPipe[IterNum] + {{(ODatWidth-1){1'b0}}, 1'b1};
+        end else begin
+            cos_o	<= xPipe[IterNum];
+        end
+		scwSignPrev	<= scwSignPipe[IterNum-1];
+		Val_o		<= valPipe[0];
+    end	
+end
+endmodule

src/src/NCO/CordicRotation.v

@@ -0,0 +1,74 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    10:32:49 05/13/2020 
+// Design Name: 
+// Module Name:    cordic_rotation 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module cordic_rotation 
+#(	parameter   ODatWidth	= 16,
+	parameter   Shift		= 1)
+(
+	input	Clk_i,
+	input	Rst_i,
+
+	input	signed  [ODatWidth-1:0]	X_i,
+	input	signed  [ODatWidth-1:0]	Y_i,
+	input	Val_i,
+	input	Sign_i,
+	output	reg	signed	[ODatWidth-1:0]	X_o,
+	output	reg	signed	[ODatWidth-1:0]	Y_o,
+	output	reg	Val_o
+);
+//================================================================================
+//  REG/WIRE DECLARATIONS
+//================================================================================
+    wire    [ODatWidth-1:0]    shiftedInX;
+    wire    [ODatWidth-1:0]    shiftedInY;
+//================================================================================
+//  ASSIGNMENTS
+//================================================================================
+    assign  shiftedInX    =   X_i >>> Shift;
+    assign  shiftedInY    =   Y_i >>> Shift;
+//================================================================================
+//  CODING
+//================================================================================
+always @(posedge Clk_i) begin
+    if (Rst_i) begin
+        Val_o	<= 1'b0;
+    end else if	(Val_i)	begin
+        Val_o	<= Val_i;
+    end	else	begin
+		Val_o	<=	1'b0;
+	end
+end
+
+always @(posedge Clk_i) begin
+    if (Rst_i) begin
+        X_o   <= {ODatWidth{1'b0}};
+        Y_o   <= {ODatWidth{1'b0}};
+    end else if (Val_i) begin
+        if (Sign_i) begin
+            X_o   <= X_i + shiftedInY;
+            Y_o   <= Y_i - shiftedInX; 
+        end else begin
+            X_o   <= X_i - shiftedInY;
+            Y_o   <= Y_i + shiftedInX;
+        end
+    end
+end
+
+endmodule

src/src/QuadSPI/QuadSPIs.v

@@ -0,0 +1,184 @@
+module QuadSPIs (
+    input Clk_i,
+    input Rst_i,
+
+    input Sck_i,
+    input Ss_i,
+    input Mosi0_i,
+    input Mosi1_i,
+    input Mosi2_i,
+    input Mosi3_i,
+
+    output reg [17:0] Data_o,
+    output reg [7:0] Addr_o,
+    output [23:0] DataToRxFifo_o,
+    output reg RorQSPIFlag_o,
+    output reg Val_o
+);
+
+//================================================================================
+//	REG/WIRE
+//================================================================================
+
+reg ssReg;
+reg ssRegR; 
+reg SckReg; 
+reg [4:0] ssCnt;
+reg [5:0] addrReg;
+reg [5:0] shiftReg0;
+reg [5:0] shiftReg1;
+reg [5:0] shiftReg2;
+
+
+
+
+//===============================================================================
+//  ASSIGNMENTS
+
+
+assign DataToRxFifo_o = {Addr_o, Data_o};
+
+//================================================================================
+//	CODING
+//================================================================================
+
+always	@(posedge	Clk_i)	begin
+	ssReg	<=	Ss_i;
+	ssRegR	<=	ssReg;
+end
+
+
+
+always @(posedge Clk_i) begin 
+    if (Rst_i) begin 
+        Data_o <= 16'h0;
+    end
+    else begin
+        if (ssReg && !ssRegR) begin 
+            Data_o <= {shiftReg0, shiftReg1, shiftReg2};
+         end
+    end
+end
+
+
+
+
+always @(posedge Clk_i) begin 
+    if (Rst_i) begin 
+        Addr_o <= 6'h0;
+    end
+    else begin
+        if (ssReg && !ssRegR) begin 
+            Addr_o <= addrReg;
+        end
+    end
+end
+
+
+always @(posedge Sck_i or posedge Rst_i) begin 
+    if (Rst_i) begin 
+        shiftReg0 <= 6'h0;
+    end
+    else begin  
+        if (!Ss_i) begin 
+            shiftReg0 <= {shiftReg0[4:0], Mosi1_i};
+        end
+        else begin 
+            shiftReg0 <= 8'h0;
+        end
+    end
+end
+
+
+
+always @(posedge Sck_i or posedge Rst_i ) begin 
+    if (Rst_i) begin 
+        shiftReg1 <= 6'h0;
+    end
+    else begin  
+        if (!Ss_i) begin 
+            shiftReg1 <= {shiftReg1[4:0], Mosi2_i};
+        end
+        else begin 
+            shiftReg1 <= 8'h0;
+        end
+    end
+end
+
+
+always @(posedge Sck_i or posedge Rst_i ) begin 
+    if (Rst_i) begin 
+        shiftReg2 <= 6'h0;
+    end
+    else begin  
+        if (!Ss_i) begin 
+            shiftReg2 <= {shiftReg2[4:0], Mosi3_i};
+        end
+        else begin 
+            shiftReg2 <= 6'h0;
+        end
+    end
+end
+
+
+always @(posedge Sck_i or posedge Rst_i ) begin 
+    if (Rst_i) begin 
+        addrReg <= 6'h0;
+    end
+    else begin
+        if (!Ss_i) begin 
+            addrReg <={addrReg[4:0], Mosi0_i};
+        end
+        else begin 
+            addrReg <= 6'h0;
+        end
+    end
+end
+
+
+always @(posedge Clk_i) begin
+    if (ssReg && !ssRegR) begin 
+        Val_o <= 1'b1;
+    end
+    else begin 
+        Val_o <= 1'b0;
+    end
+end
+
+
+always @(posedge Sck_i or posedge Rst_i or posedge Ss_i) begin 
+    if (Rst_i) begin 
+        ssCnt <= 5'd0;
+    end
+    else begin 
+        if (Ss_i) begin 
+            ssCnt <= 5'd0;
+        end
+        else begin 
+            ssCnt <= ssCnt + 1'd1;
+        end
+    end
+end
+
+
+always @(posedge Sck_i) begin 
+    if (Rst_i) begin 
+        RorQSPIFlag_o <= 1'b0;
+    end
+    else begin 
+        if (addrReg[0] == 1 && ssCnt == 1 ) begin
+            RorQSPIFlag_o <= 1'b1;
+        end
+        else if (addrReg[0] != 1 && ssCnt == 1 ) begin 
+            RorQSPIFlag_o <= 1'b0;
+        end
+    end
+end
+
+
+
+
+
+
+
+endmodule

src/src/RAM/RAM.v

@@ -0,0 +1,49 @@
+`include "mem_init.txt"
+module RAM #(
+    parameter mem_init_file = "mem_init.txt"
+
+
+) (
+    input [63:0] Data_i,
+    
+    input [9:0] Addr_i,
+
+    input Clk_i,
+    input Rst_i,
+    input WrEn_i,
+    input RdEn_i,
+
+    output [63:0] Data_o
+
+
+
+);
+
+reg [63:0] mem [1023:0];
+reg [63:0] dataReg;  
+
+
+
+assign Data_o = dataReg;
+
+
+
+always @(posedge Clk_i)
+    if (Rst_i) begin 
+        dataReg <= 64'h0;
+    end
+    else begin 
+        if (!RdEn_i) begin 
+            dataReg <= mem[Addr_i];
+        end
+    end
+
+always @(posedge Clk_i)
+    if (!WrEn_i) begin 
+        mem[Addr_i] <= Data_i;
+    end
+
+
+endmodule
+
+

src/src/SPI/SPIm.v

@@ -0,0 +1,255 @@
+module SPIm (
+    input Clk_i,
+    input Rst_i,
+    input Start_i,
+    input EmptyFlag_i,
+    input [23:0] SpiData_i,
+
+
+    output  Mosi0_o,
+    output  Sck_o,
+    output  Ss_o,
+    output reg  Val_o
+);
+
+//
+// LOCALPARAMS
+
+localparam ssNum = 24; 
+//================================================================================
+//	REG/WIRE
+//================================================================================
+
+    reg startFlag;
+    reg startR;
+    reg lineBusy;
+    reg [31:0] trCnt;
+    reg valReg;
+    reg spiBusy;
+    reg valToRxFifo1;
+    reg [5:0] ssCnt;
+    reg Ss;
+    reg [23:0]spiDataR;
+    reg [23:0]spiDataReg;
+    reg oldDataFlag;
+    
+    reg ssR;
+    reg SSR;
+    reg [23:0] mosiReg0;
+    reg stopFlag;
+    
+    
+    
+    //================================================================================
+    //  ASSIGNMENTS
+    //================================================================================
+    
+    
+    assign Ss_o = Ss;
+    assign Mosi0_o = (!Ss_o && ssCnt <= ssNum) ?mosiReg0[23] : 1'b0;
+    assign Sck_o = (!Ss_o && ssCnt <= ssNum) ? ~Clk_i : 1'b0; 
+    
+    //================================================================================
+    //	CODING
+    //================================================================================
+    
+    always @(*) begin 
+        if (Rst_i) begin 
+            Val_o = 1'b0;
+        end
+        else begin 
+        if (Start_i && trCnt < 1  && Ss_o && SpiData_i == 0 ) begin  
+            Val_o = 1;
+        end
+        else if (Start_i) begin 
+            Val_o <= valReg;
+        end
+        else begin 
+            Val_o <= 1'b0;
+        end
+        end
+    end
+    
+
+    always @(*) begin 
+        if (Rst_i) begin 
+            lineBusy = 1'b0;
+        end
+        else begin 
+            if (Start_i && !Ss_o && SpiData_i != 0) begin 
+                lineBusy = 1'b1;
+            end
+            else begin 
+                lineBusy = 1'b0;
+            end
+        end
+    end
+
+    
+    
+    always @(posedge Clk_i) begin
+        if (valReg) begin  
+            spiDataR <= SpiData_i;
+        end
+    end
+    
+    always @(posedge Clk_i) begin 
+        spiDataReg <= SpiData_i;
+    end
+
+
+    
+    always @(*) begin 
+        if (Rst_i) begin 
+            oldDataFlag = 1'b0;
+        end
+        else begin 
+            if (spiDataR == SpiData_i && (SpiData_i != 0) || EmptyFlag_i) begin 
+                oldDataFlag = 1'b1;
+            end
+            else begin 
+                oldDataFlag = 1'b0;
+            end
+        end
+    end
+    
+    
+    always @(posedge Clk_i) begin 
+        startR <= Start_i;
+    end
+    
+    always @(*) begin 
+        if (Rst_i) begin 
+            valToRxFifo1 = 1'b0;
+        end
+        else begin 
+            if (Start_i && !startR) begin 
+                valToRxFifo1 = 1'b1;
+            end
+            else begin 
+                valToRxFifo1 = 1'b0;
+            end
+        end
+    end
+
+    always @(posedge Clk_i) begin 
+        if (Rst_i) begin 
+            stopFlag <= 1'b0;
+        end
+        else begin
+            if (Ss_o && !SSR) begin 
+                stopFlag <= 1'b1;
+            end
+            else begin
+                stopFlag <= 1'b0;
+            end
+        end
+    end
+
+
+   
+    
+    always @(posedge Clk_i) begin
+        SSR <= Ss;
+    end
+    
+    
+    always @(*) begin 
+        if (Rst_i) begin 
+            startFlag = 1'b0;
+        end
+        else begin 
+            if (Start_i && !stopFlag && !EmptyFlag_i  && !oldDataFlag   ) begin 
+                startFlag = 1'b1;
+            end
+            else begin 
+                startFlag = 1'b0;
+            end
+        end
+    end
+    
+    always @(*) begin
+        if (Rst_i) begin 
+            valReg = 1'b0;
+        end
+        else begin
+            if (Ss_o && !SSR) begin 
+                valReg = 1'b1;
+            end
+            else begin 
+                valReg = 1'b0;
+            end
+        end
+    end
+
+
+    always @(posedge Clk_i) begin 
+        if (Rst_i) begin 
+            trCnt <= 32'd0;
+        end
+        else begin 
+            if (Ss_o && !SSR) begin 
+                trCnt <= trCnt + 1;
+            end
+        end
+    end
+
+
+    
+   
+    
+    
+    always @(posedge Clk_i) begin 
+        if (Rst_i) begin 
+            ssCnt <= 1'b0;
+        end
+        else if (ssCnt <= ssNum  && startFlag  ) begin 
+            ssCnt <= ssCnt + 1'b1;
+        end
+        else begin
+            if (ssCnt == ssNum-1 || !startFlag) begin 
+                ssCnt <= 1'b0;
+            end
+        end
+    end
+    
+    
+    
+    
+    always @(posedge Clk_i) begin 
+        if (Rst_i) begin 
+            Ss <= 1'b1;
+        end
+        else begin 
+            if (ssCnt <= ssNum  && startFlag ) begin 
+                Ss <= 1'b0;
+            end
+            else begin 
+                Ss <= 1'b1;
+            end
+        end
+    end
+    
+    
+    always @(posedge Clk_i) begin 
+        if (Rst_i) begin 
+            mosiReg0 <= SpiData_i[23:0];
+        end
+        else begin 
+            if (!Ss && ( ssCnt < ssNum)) begin
+                mosiReg0 <= mosiReg0 << 1;
+            end
+            else begin 
+                mosiReg0 <= SpiData_i[23:0];
+            end
+        end
+    end
+
+    
+    
+    
+    
+    
+    
+    
+    endmodule

src/src/SPI/SPImDDS.v

@@ -0,0 +1,256 @@
+module SPImDDS#(
+    parameter ssNum = 64
+)(
+    input Clk_i,
+    input Rst_i,
+    input Start_i,
+    input EmptyFlag_i,
+    input [ssNum-1:0] SpiData_i,
+
+
+    output  Mosi0_o,
+    output  Sck_o,
+    output  Ss_o,
+    output reg  Val_o
+);
+
+//
+// LOCALPARAMS
+
+// localparam ssNum = 64; 
+//================================================================================
+//	REG/WIRE
+//================================================================================
+
+    reg startFlag;
+    reg startR;
+    reg lineBusy;
+    reg [31:0] trCnt;
+    reg valReg;
+    reg spiBusy;
+    reg valToRxFifo1;
+    reg [6:0] ssCnt;
+    reg Ss;
+    reg [ssNum-1:0]spiDataR;
+    reg [ssNum-1:0]spiDataReg;
+    reg oldDataFlag;
+    
+    reg ssR;
+    reg SSR;
+    reg [ssNum-1:0] mosiReg0;
+    reg stopFlag;
+    
+    
+    
+    //================================================================================
+    //  ASSIGNMENTS
+    //================================================================================
+    
+    
+    assign Ss_o = Ss;
+    assign Mosi0_o = (!Ss_o && ssCnt <= ssNum) ?mosiReg0[ssNum-1] : 1'b0;
+    assign Sck_o = (!Ss_o && ssCnt <= ssNum) ? Clk_i : 1'b0; 
+    
+    //================================================================================
+    //	CODING
+    //================================================================================
+    
+     always @(*) begin 
+        if (Start_i) begin  
+            Val_o = valReg;
+        end
+        else begin 
+            Val_o = 1'b0;
+        end
+    end
+    
+
+    always @(*) begin 
+        if (Rst_i) begin 
+            lineBusy = 1'b0;
+        end
+        else begin 
+            if (Start_i && !Ss_o && SpiData_i != 0) begin 
+                lineBusy = 1'b1;
+            end
+            else begin 
+                lineBusy = 1'b0;
+            end
+        end
+    end
+
+    
+    
+    always @(posedge Clk_i) begin
+        if (Rst_i) begin 
+            spiDataR <= 0;
+        end
+        else begin
+            if (valReg) begin 
+                spiDataR <= spiDataReg;
+            end
+        end
+    end
+    
+    always @(posedge Clk_i) begin 
+        spiDataReg <= SpiData_i;
+    end
+
+
+    
+    always @(*) begin 
+        if (Rst_i) begin 
+            oldDataFlag = 1'b0;
+        end
+        else begin 
+            if (spiDataR == SpiData_i && (SpiData_i != 0) || EmptyFlag_i) begin 
+                oldDataFlag = 1'b1;
+            end
+            else begin 
+                oldDataFlag = 1'b0;
+            end
+        end
+    end
+    
+    
+    always @(posedge Clk_i) begin 
+        startR <= Start_i;
+    end
+    
+    always @(*) begin 
+        if (Rst_i) begin 
+            valToRxFifo1 = 1'b0;
+        end
+        else begin 
+            if (Start_i && !startR) begin 
+                valToRxFifo1 = 1'b1;
+            end
+            else begin 
+                valToRxFifo1 = 1'b0;
+            end
+        end
+    end
+
+    always @(posedge Clk_i) begin 
+        if (Rst_i) begin 
+            stopFlag <= 1'b0;
+        end
+        else begin
+            if (Ss_o && !SSR) begin 
+                stopFlag <= 1'b1;
+            end
+            else begin
+                stopFlag <= 1'b0;
+            end
+        end
+    end
+
+
+   
+    
+    always @(posedge Clk_i) begin
+        SSR <= Ss;
+    end
+    
+    
+    always @(*) begin 
+        if (Rst_i) begin 
+            startFlag = 1'b0;
+        end
+        else begin 
+            if (Start_i && !stopFlag && !EmptyFlag_i  && !oldDataFlag   ) begin 
+                startFlag = 1'b1;
+            end
+            else begin 
+                startFlag = 1'b0;
+            end
+        end
+    end
+    
+    always @(*) begin
+        if (Rst_i) begin 
+            valReg = 1'b0;
+        end
+        else begin
+            if (Ss_o && !SSR) begin 
+                valReg = 1'b1;
+            end
+            else begin 
+                valReg = 1'b0;
+            end
+        end
+    end
+
+
+    always @(posedge Clk_i) begin 
+        if (Rst_i) begin 
+            trCnt <= 32'd0;
+        end
+        else begin 
+            if (Ss_o && !SSR) begin 
+                trCnt <= trCnt + 1;
+            end
+        end
+    end
+
+
+    
+   
+    
+    
+    always @(negedge Clk_i) begin 
+        if (Rst_i) begin 
+            ssCnt <= 1'b0;
+        end
+        else if (ssCnt <= ssNum  && startFlag  ) begin 
+            ssCnt <= ssCnt + 1'b1;
+        end
+        else begin
+            if (ssCnt == ssNum-1 || !startFlag) begin 
+                ssCnt <= 1'b0;
+            end
+        end
+    end
+    
+    
+    
+    
+    always @(negedge Clk_i) begin 
+        if (Rst_i) begin 
+            Ss <= 1'b1;
+        end
+        else begin 
+            if (ssCnt <= ssNum  && startFlag ) begin 
+                Ss <= 1'b0;
+            end
+            else begin 
+                Ss <= 1'b1;
+            end
+        end
+    end
+    
+    
+    always @(negedge Clk_i) begin 
+        if (Rst_i) begin 
+            mosiReg0 <= SpiData_i[ssNum-1:0];
+        end
+        else begin 
+            if (!Ss && ( ssCnt < ssNum)) begin
+                mosiReg0 <= mosiReg0 << 1;
+            end
+            else begin
+                if (Ss) begin
+                    mosiReg0 <= SpiData_i[ssNum-1:0];
+                end
+            end
+        end
+    end
+
+    
+    
+    
+    
+    
+    
+    
+    endmodule

src/src/SPI/SPIs.v

@@ -0,0 +1,95 @@
+module SPIs (
+    input Clk_i,
+    input Rst_i,
+
+    input Sck_i,
+    input Ss_i,
+    input Mosi0_i,
+
+    output reg [17:0] Data_o,
+    output reg [5:0] Addr_o,
+    output [23:0] DataToRxFifo_o,
+    output reg Val_o
+);
+
+//================================================================================
+//	REG/WIRE
+//================================================================================
+
+    reg ssReg;
+    reg ssRegR;  
+    reg [23:0] shiftReg;
+    
+ 
+
+//===============================================================================
+//  ASSIGNMENTS
+
+
+    assign DataToRxFifo_o = {Addr_o, Data_o};
+
+//================================================================================
+//	CODING
+//================================================================================
+
+    always	@(posedge	Clk_i)	begin
+    	ssReg	<=	Ss_i;
+    	ssRegR	<=	ssReg;
+    end
+
+
+
+
+    always @(posedge Clk_i) begin 
+        if (Rst_i) begin 
+            Data_o <= 18'h0;
+        end
+        else begin
+            if (ssReg && !ssRegR) begin 
+                Data_o <= shiftReg[17:0];
+            end
+        end
+    end
+
+    always @(posedge Clk_i) begin 
+        if (Rst_i) begin 
+            Addr_o <= 8'h0;
+        end
+        else begin 
+            if (ssReg && !ssRegR) begin 
+                Addr_o <= shiftReg[23:18];
+            end
+        end
+    end
+
+
+    always @(posedge Sck_i or posedge Rst_i) begin 
+        if (Rst_i) begin 
+            shiftReg<= 24'h0;
+        end
+        else begin  
+            if (!Ss_i) begin 
+                shiftReg<= {shiftReg[22:0], Mosi0_i};
+            end
+            else begin 
+                shiftReg<= 24'h0;
+            end
+        end
+    end
+    
+        
+
+
+    always @(posedge Clk_i) begin
+        if (ssReg && !ssRegR) begin 
+            Val_o <= 1'b1;
+        end
+        else begin 
+            Val_o <= 1'b0;
+        end
+    end
+
+
+
+
+    endmodule

src/src/Sim/SPIm_tb.v

@@ -0,0 +1,515 @@
+module SPIm_tb (
+    input Clk_i,
+    input Rst_i,
+    input Start_i,
+    input ClockPhase_i,
+    input [31:0] SpiData_i,
+    input SelSt_i,
+    input [1:0] WidthSel_i,
+    input  Lag_i,
+    input  Lead_i,
+    input EndianSel_i,
+    input [5:0] Stop_i,
+    input PulsePol_i,
+
+
+    output reg Mosi0_o,
+    output reg Sck_o,
+    output  Ss_o,
+    output reg  Val_o
+);
+
+
+//================================================================================
+//	REG/WIRE
+//================================================================================
+
+    reg startFlag;
+    reg startR;
+    reg [31:0] trCnt;
+    reg valReg;
+    reg valToRxFifo1;
+    reg [5:0] ssCnt;
+    reg Ss;
+    reg [31:0]spiDataR;
+    reg oldDataFlag;
+    
+    reg ssR;
+    reg SSR;
+    reg [31:0] mosiReg0;
+    reg [5:0] ssNum;
+    reg [2:0] delayCnt;
+    reg stopFlag;
+    
+    wire ssPol = SelSt_i ? Ss : ~Ss;
+    
+    
+    //================================================================================
+    //  ASSIGNMENTS
+    //================================================================================
+    
+    
+    assign Ss_o = ssPol; 
+    
+    //================================================================================
+    //	CODING
+    //================================================================================
+    
+    always @(*) begin 
+        if (Start_i) begin  
+            Val_o = valReg;
+        end
+        else begin 
+            Val_o = 1'b0;
+        end
+    end
+    
+
+    
+    
+    always @(posedge Clk_i) begin
+        if (valReg) begin  
+            spiDataR <= SpiData_i;
+        end
+    end
+    
+    
+    always @(*) begin 
+        if (Rst_i) begin 
+            oldDataFlag = 1'b0;
+        end
+        else begin 
+            if (spiDataR == SpiData_i) begin 
+                oldDataFlag = 1'b1;
+            end
+            else begin 
+                oldDataFlag = 1'b0;
+            end
+        end
+    end
+    
+    
+    always @(posedge Clk_i) begin 
+        startR <= Start_i;
+    end
+    
+    always @(*) begin 
+        if (Rst_i) begin 
+            valToRxFifo1 = 1'b0;
+        end
+        else begin 
+            if (Start_i && !startR) begin 
+                valToRxFifo1 = 1'b1;
+            end
+            else begin 
+                valToRxFifo1 = 1'b0;
+            end
+        end
+    end
+    
+    always @(negedge Clk_i) begin 
+        if (Rst_i) begin 
+            delayCnt <= 1'b0;
+        end
+        else begin 
+            if (stopFlag &&delayCnt < Stop_i) begin 
+                delayCnt <= delayCnt + 1'b1;
+            end
+            else begin 
+                delayCnt <= 1'b0;
+            end
+        end
+    end
+    
+    always @(posedge Clk_i) begin 
+        if (Rst_i) begin 
+            stopFlag <= 1'b0;
+        end
+        else begin
+            if (SelSt_i) begin 
+                if (ssPol && !ssR) begin 
+                    stopFlag <= 1'b1;
+                end
+                else if ( delayCnt == Stop_i) begin 
+                    stopFlag <= 1'b0;
+                end
+            end
+            else begin 
+                if (!ssPol && ssR) begin 
+                    stopFlag <= 1'b1;
+                end
+                else if (delayCnt == Stop_i) begin 
+                    stopFlag <= 1'b0;
+                end
+            end
+        end
+    end
+    
+    
+    
+    
+    always @(*) begin
+        if (SelSt_i) begin 
+            if (PulsePol_i) begin 
+                if (ClockPhase_i) begin
+                    if (Lead_i == 0) begin 
+                        if (!Ss && (ssCnt <= ssNum+Lag_i+Lead_i && ssCnt > Lag_i) ) begin 
+                            Sck_o = ~(~Clk_i);
+                        end
+                        else begin 
+                            Sck_o = 1'b0;
+                        end
+                    end
+                    else begin 
+                        if (!Ss && (ssCnt < ssNum+Lag_i+Lead_i && ssCnt > Lag_i)) begin 
+                            Sck_o = ~(~Clk_i);
+                        end
+                        else begin 
+                            Sck_o = 1'b0;
+                        end
+                    end
+                end
+                else begin
+                    if (Lead_i == 0) begin 
+                        if (!Ss && (ssCnt <= ssNum+Lag_i+Lead_i && ssCnt > Lag_i) ) begin 
+                            Sck_o = ~(Clk_i);
+                        end
+                        else begin 
+                            Sck_o = 1'b0;
+                        end
+                    end
+                    else begin 
+                        if (!Ss && (ssCnt < ssNum + Lag_i + Lead_i && ssCnt > Lag_i)) begin 
+                            Sck_o = ~(Clk_i);
+                        end
+                        else begin 
+                            Sck_o = 1'b0;
+                        end
+                    end
+                end
+            end
+            else begin 
+                if (ClockPhase_i) begin
+                    if (Lead_i == 0) begin  
+                        if (!Ss && (ssCnt <= ssNum+Lag_i+Lead_i && ssCnt > Lag_i) ) begin 
+                            Sck_o = ~(Clk_i);
+                        end
+                        else begin 
+                            Sck_o = 1'b0;
+                        end
+                    end
+                    else begin 
+                        if (!Ss && (ssCnt <ssNum + Lag_i + Lead_i && ssCnt > Lag_i)) begin 
+                            Sck_o = ~(Clk_i);
+                        end
+                        else begin 
+                            Sck_o = 1'b0;
+                        end
+                    end
+                end 
+                else begin
+                    if (Lead_i == 0) begin 
+                        if (!Ss && (ssCnt <= ssNum+Lag_i+Lead_i && ssCnt > Lag_i) ) begin 
+                            Sck_o = ~(~Clk_i);
+                        end
+                        else begin 
+                            Sck_o = 1'b0;
+                        end
+                    end
+                    else begin 
+                        if (!Ss && (ssCnt < ssNum + Lag_i + Lead_i && ssCnt > Lag_i)) begin 
+                            Sck_o = ~(~Clk_i);
+                        end
+                        else begin 
+                            Sck_o = 1'b0;
+                        end
+                    end
+                end
+            end
+        end
+        else begin 
+              if (PulsePol_i) begin 
+                if (ClockPhase_i) begin
+                    if (Lead_i == 0) begin 
+                        if (ssPol && (ssCnt <= ssNum+Lag_i+Lead_i && ssCnt > Lag_i) ) begin 
+                            Sck_o = ~(~Clk_i);
+                        end
+                        else begin 
+                            Sck_o = 1'b0;
+                        end
+                    end
+                    else begin 
+                        if (ssPol && (ssCnt < ssNum+Lag_i+Lead_i && ssCnt > Lag_i)) begin 
+                            Sck_o = ~(~Clk_i);
+                        end
+                        else begin 
+                            Sck_o = 1'b0;
+                        end
+                    end
+                end
+                else begin
+                    if (Lead_i == 0) begin 
+                        if (ssPol && (ssCnt <= ssNum+Lag_i+Lead_i && ssCnt > Lag_i) ) begin 
+                            Sck_o = ~(Clk_i);
+                        end
+                        else begin 
+                            Sck_o = 1'b0;
+                        end
+                    end
+                    else begin 
+                        if (ssPol && (ssCnt < ssNum + Lag_i + Lead_i && ssCnt > Lag_i)) begin 
+                            Sck_o = ~(Clk_i);
+                        end
+                        else begin 
+                            Sck_o = 1'b0;
+                        end
+                    end
+                end
+            end
+            else begin 
+                if (ClockPhase_i) begin
+                    if (Lead_i == 0) begin  
+                        if (ssPol && (ssCnt <= ssNum+Lag_i+Lead_i && ssCnt > Lag_i) ) begin 
+                            Sck_o = ~(Clk_i);
+                        end
+                        else begin 
+                            Sck_o = 1'b0;
+                        end
+                    end
+                    else begin 
+                        if (ssPol && (ssCnt <ssNum + Lag_i + Lead_i && ssCnt > Lag_i)) begin 
+                            Sck_o = ~(Clk_i);
+                        end
+                        else begin 
+                            Sck_o = 1'b0;
+                        end
+                    end
+                end 
+                else begin
+                    if (Lead_i == 0) begin 
+                        if (ssPol && (ssCnt <= ssNum+Lag_i+Lead_i && ssCnt > Lag_i) ) begin 
+                            Sck_o = ~(~Clk_i);
+                        end
+                        else begin 
+                            Sck_o = 1'b0;
+                        end
+                    end
+                    else begin 
+                        if (ssPol && (ssCnt < ssNum + Lag_i + Lead_i && ssCnt > Lag_i)) begin 
+                            Sck_o = ~(~Clk_i);
+                        end
+                        else begin 
+                            Sck_o = 1'b0;
+                        end
+                    end
+                end
+            end
+        end
+            
+    end
+    
+    
+    always @(*) begin
+        if (Rst_i) begin 
+            Mosi0_o = 1'b0;
+        end
+        else begin
+            if (SelSt_i) begin 
+                if (!EndianSel_i) begin 
+                    case (WidthSel_i)  
+                        0 : begin
+                            Mosi0_o = (!Ss&& (ssCnt <= ssNum+Lag_i && ssCnt > Lag_i))? (mosiReg0[7]):1'b0;
+                        end
+                        1 : begin
+                            Mosi0_o = (!Ss&& (ssCnt <= ssNum+Lag_i && ssCnt > Lag_i))? (mosiReg0[15]):1'b0;
+                        end
+                        2 : begin
+                            Mosi0_o = (!Ss&& (ssCnt <= ssNum+Lag_i && ssCnt > Lag_i))? (mosiReg0[23]):1'b0;
+                        end
+                        3 : begin
+                            Mosi0_o = (!Ss&& (ssCnt <= ssNum+Lag_i && ssCnt > Lag_i))? (mosiReg0[31]):1'b0;
+                        end
+                    endcase
+                end
+                else begin 
+                    case (WidthSel_i)  
+                        0 : begin
+                            Mosi0_o = (!Ss&& (ssCnt <= ssNum+Lag_i && ssCnt > Lag_i))? (mosiReg0[0]):1'b0;
+                        end
+                        1 : begin
+                            Mosi0_o = (!Ss&& (ssCnt <= ssNum+Lag_i && ssCnt > Lag_i))? (mosiReg0[0]):1'b0;
+                        end
+                        2 : begin
+                            Mosi0_o = (!Ss&& (ssCnt <= ssNum+Lag_i && ssCnt > Lag_i))? (mosiReg0[0]):1'b0;
+                        end
+                        3 : begin
+                            Mosi0_o = (!Ss&& (ssCnt <= ssNum+Lag_i && ssCnt > Lag_i))? (mosiReg0[0]):1'b0;
+                        end
+                    endcase
+                end
+            end
+            else begin 
+                if (!EndianSel_i) begin 
+                    case (WidthSel_i)  
+                        0 : begin
+                            Mosi0_o = (ssPol&& (ssCnt <= ssNum+Lag_i && ssCnt > Lag_i))? (mosiReg0[7]):1'b0;
+                        end
+                        1 : begin
+                            Mosi0_o = (ssPol&& (ssCnt <= ssNum+Lag_i && ssCnt > Lag_i))? (mosiReg0[15]):1'b0;
+                        end
+                        2 : begin
+                            Mosi0_o = (ssPol&& (ssCnt <= ssNum+Lag_i && ssCnt > Lag_i))? (mosiReg0[23]):1'b0;
+                        end
+                        3 : begin
+                            Mosi0_o = (ssPol&& (ssCnt <= ssNum+Lag_i && ssCnt > Lag_i))? (mosiReg0[31]):1'b0;
+                        end
+                    endcase
+                end
+                else begin 
+                    case (WidthSel_i)  
+                        0 : begin
+                            Mosi0_o = (ssPol&& (ssCnt <= ssNum+Lag_i && ssCnt > Lag_i))? (mosiReg0[0]):1'b0;
+                        end
+                        1 : begin
+                            Mosi0_o = (ssPol&& (ssCnt <= ssNum+Lag_i && ssCnt > Lag_i))? (mosiReg0[0]):1'b0;
+                        end
+                        2 : begin
+                            Mosi0_o = (ssPol&& (ssCnt <= ssNum+Lag_i && ssCnt > Lag_i))? (mosiReg0[0]):1'b0;
+                        end
+                        3 : begin
+                            Mosi0_o = (ssPol&& (ssCnt <= ssNum+Lag_i && ssCnt > Lag_i))? (mosiReg0[0]):1'b0;
+                        end
+                    endcase
+                end
+            end
+        end
+    end
+    
+    
+    
+    always @(posedge Clk_i) begin
+        ssR <= ssPol;
+        SSR <= Ss;
+    end
+    
+    
+    always @(*) begin 
+        if (Rst_i) begin 
+            startFlag = 1'b0;
+        end
+        else begin 
+            if (Start_i&& !stopFlag && SpiData_i != 0 && !oldDataFlag ) begin 
+                startFlag = 1'b1;
+            end
+            else begin 
+                startFlag = 1'b0;
+            end
+        end
+    end
+    
+    always @(posedge Clk_i) begin
+        if (SelSt_i) begin 
+            if (Ss_o && !ssR) begin 
+                valReg = 1'b1;
+            end
+            else begin 
+                valReg = 1'b0;
+            end
+        end
+        else begin 
+            if (!Ss_o&& ssR) begin 
+                valReg = 1'b1;
+            end
+            else begin 
+                valReg = 1'b0;
+            end
+        end
+    end
+    
+    
+    always @(*) begin 
+        if (Rst_i) begin 
+            ssNum = 1'b0;
+        end
+        else begin 
+            case (WidthSel_i) 
+                0 : begin 
+                    ssNum = 8;
+                end
+                1 : begin 
+                    ssNum = 16;
+                end
+                2 : begin 
+                    ssNum = 24;
+                end
+                3 : begin 
+                    ssNum = 32;
+                end
+            endcase
+        end
+    end
+    
+    
+    always @(negedge Clk_i) begin 
+        if (Rst_i) begin 
+            ssCnt <= 1'b0;
+        end
+        else if (ssCnt <= (ssNum+Lag_i+Lead_i)  && startFlag  ) begin 
+            ssCnt <= ssCnt + 1'b1;
+        end
+        else begin
+            if (ssCnt == ssNum-1 || !startFlag) begin 
+                ssCnt <= 1'b0;
+            end
+        end
+    end
+    
+    
+    
+    
+    always @(negedge Clk_i) begin 
+        if (Rst_i) begin 
+            Ss <= 1'b1;
+        end
+        else begin 
+            if (ssCnt <= (ssNum+Lag_i+Lead_i)  && startFlag ) begin 
+                Ss <= 1'b0;
+            end
+            else begin 
+                Ss <= 1'b1;
+            end
+        end
+    end
+    
+    
+    always @(negedge Clk_i) begin 
+        if (Rst_i) begin 
+            mosiReg0 <= SpiData_i[31:0];
+        end
+        else begin
+            if (!EndianSel_i) begin 
+                if (!SSR && (ssCnt > Lag_i && ssCnt < ssNum + Lag_i + Lead_i)) begin
+                    mosiReg0 <= mosiReg0 << 1;
+                end
+                else begin 
+                    mosiReg0 <= SpiData_i[31:0];
+                end
+            end
+            else begin 
+                if (!SSR && (ssCnt > Lag_i && ssCnt < ssNum + Lag_i + Lead_i)) begin
+                    mosiReg0 <= mosiReg0 >> 1;
+                end
+                else begin 
+                    mosiReg0 <= SpiData_i[31:0];
+                end
+            end
+        end
+    end
+    
+    
+    
+    
+    
+    
+    
+    endmodule

src/src/Sim/tb_RF_FPGA.v

@@ -0,0 +1,288 @@
+`timescale 1ns/1ps
+
+module tb_SPIm;
+
+    // Parameters
+    parameter CLK_PERIOD = 8.13; // Clock period in ns
+
+    // Inputs
+    reg Clk_i;
+    reg Clk100;
+    reg Clk20;
+    reg Clk80;
+    reg Clk50;
+    reg Clk24; 
+    reg Rst_i;
+    reg Start_i;
+    reg CPHA_i;
+    reg [31:0] SPIdata;
+	reg SpiDataVal_i;
+    reg SELST_i;
+    reg [1:0] WidthSel_i;
+    reg LAG_i;
+    reg LEAD_i;
+    reg EndianSel_i;
+    reg [5:0] Stop_i;
+    reg PulsePol_i;
+
+    // Outputs
+    wire Mosi0_o;
+    wire Mosi1_o;
+    wire Mosi1_io;
+    wire Mosi2_o;
+    wire Mosi3_o;
+    wire Sck_o;
+    wire Ss_o;
+    wire Val_o;
+
+    wire valR;
+    wire valQ;
+    wire SckR;
+    wire SckQ;
+    wire SsR;
+    wire SsQ;
+    wire mosi0R;
+    wire mosi0Q;
+
+    wire locked;
+    wire rstInit;
+
+    reg [4:0] trCnt;
+    reg [4:0] trCntSync;
+
+    reg start; 
+
+    reg modeSel; 
+
+    assign Val_o = (((modeSel)? trCnt : trCntSync) < 2 ) ? valQ:(modeSel) ? valQ:valR;
+    assign Sck_o = (((modeSel)? trCnt : trCntSync)< 2 ) ? SckQ:(modeSel) ? SckQ:SckR;
+    assign Ss_o = (((modeSel)? trCnt : trCntSync)<2) ? SsQ:(modeSel) ? SsQ:SsR;
+    assign Mosi0_o = (((modeSel)? trCnt : trCntSync)< 2 ) ? mosi0Q:(modeSel) ? mosi0Q:mosi0R;
+    assign Mosi1_io = (modeSel) ? Mosi1_o:1'bz;
+
+
+
+    always @(posedge Clk50) begin 
+        if (Rst_i) begin 
+            trCnt <= 5'd0;
+        end
+        else begin 
+            if (trCnt < 2  && trCntSync < 2 && !modeSel) begin
+                if (valQ) begin 
+                    trCnt <= trCnt + 1;
+                end
+            end
+            else if (trCnt < 7 && modeSel) begin 
+                if (valQ) begin 
+                    trCnt <= trCnt + 1;
+                end
+            end
+            else if (trCntSync >= 2 && !modeSel) begin 
+                trCnt <= 5'd0;
+            end
+        end
+    end
+
+
+
+ always @(posedge Clk20) begin 
+    if (Rst_i) begin 
+        trCntSync <= 5'd0;
+    end
+    else begin
+        if (trCnt >= 2) begin 
+            trCntSync <= trCnt;
+        end
+        else if (Val_o && trCntSync < 7 ) begin 
+            trCntSync <= trCntSync+1;
+        end
+    end
+ end
+
+
+
+
+
+
+    always @(posedge Clk20) begin 
+        if (Rst_i) begin
+            start <= 1'b0;
+        end
+        else begin 
+            if (trCnt >= 2 ) begin 
+                start <= 1'b1;
+            end
+        end
+    end
+
+
+
+
+
+
+    SPIm_tb SPIm_inst (
+        .Clk_i(Clk20), 
+        .Rst_i(Rst_i), 
+        .Start_i(start), 
+        .ClockPhase_i(CPHA_i), 
+        .SpiData_i(SPIdata),
+        .SelSt_i(SELST_i),
+        .WidthSel_i(WidthSel_i),
+        .Lag_i(LAG_i),
+        .Lead_i(LEAD_i),
+        .EndianSel_i(EndianSel_i),
+        .Stop_i(Stop_i),
+        .PulsePol_i(PulsePol_i),
+        .Mosi0_o(mosi0R),
+        .Sck_o(SckR),
+        .Ss_o(SsR),
+        .Val_o(valR)
+    );
+
+
+
+    QuadSPIm QuadSPIm_inst (
+        .Clk_i(Clk100),
+        .Rst_i(Rst_i),
+        .Start_i(Start_i),
+        .ClockPhase_i(CPHA_i),
+        .SpiData_i(SPIdata),
+        .SpiDataVal_i(SpiDataVal_i),
+        .SelSt_i(SELST_i),
+        .WidthSel_i(WidthSel_i),
+        .Lag_i(LAG_i),
+        .Lead_i(LEAD_i),
+        .EndianSel_i(EndianSel_i),
+        .Stop_i(Stop_i),
+        .PulsePol_i(PulsePol_i),
+        .Mosi0_i(mosi0Q),
+        .Mosi1_i(Mosi1_o),
+        .Mosi2_i(Mosi2_o),
+        .Mosi3_i(Mosi3_o),
+        .Sck_o(SckQ),
+        .Ss_o(SsQ),
+        .Val_o(valQ)
+    );
+
+
+
+
+
+
+    RFTop RFTop_inst (
+        .Clk_i(Clk24),
+        .Sck_i(Sck_o),
+        .Ss_i(Ss_o),
+        .Mosi0_i(Mosi0_o),
+        .Mosi1_io(Mosi1_o),
+        .Mosi2_i(Mosi2_o),
+        .Mosi3_i(Mosi3_o),
+        .RstInit_o(rstInit),
+        .Locked_o(locked)
+
+    );
+
+
+
+    // Clock generation
+    always #(CLK_PERIOD/2) Clk_i = ~Clk_i;
+    always #(10/2) Clk100 = ~Clk100;
+    always #(20/2) Clk50 = ~Clk50;
+    always #(12.5/2) Clk80 = ~Clk80;
+    always #(41.67/2) Clk24 = ~Clk24;
+    always #(50/2) Clk20 = ~Clk20;
+
+    // Initial setup and test sequence
+    initial begin
+        // Initialize Inputs
+        Clk_i = 1;
+        Clk100= 1;
+        Clk20 = 1;
+        Clk50 = 1;
+        Clk80 = 1;
+        Clk24 = 1;
+        Rst_i = 1;
+        Start_i = 0;
+        CPHA_i = 0;
+		SpiDataVal_i = 0;
+        modeSel = 0;
+        SELST_i = 1;//0:High, 1:Low
+        WidthSel_i = 2; // 3-32bit, 2-24bit, 1-16bit, 0-8bit
+        LAG_i = 0;
+        LEAD_i = 0;
+        EndianSel_i = 0; // 0:MSB first, 1:lsb first
+        Stop_i = 6'd0;
+        PulsePol_i = 0;
+
+        // Reset the system
+        #(CLK_PERIOD*10) Rst_i = 0;
+        #(CLK_PERIOD*2) Start_i = 1; // Start SPI transaction
+      
+    end
+
+    always @(*) begin
+        if (locked && !rstInit && modeSel)  begin
+            case (trCnt) 
+            0: begin 
+                SPIdata = {8'haa,8'haa,7'haa,1'b0};
+            end
+            1:begin 
+                SPIdata = {1'h0, 7'h2a, 16'd10};
+            end
+            2:begin 
+                SPIdata = {1'h0, 7'h2a, 16'd20};
+            end
+            3:begin 
+                SPIdata = {1'h0, 7'h2a, 16'd30};
+            end
+            4:begin 
+                SPIdata = {1'h0, 7'h2a, 16'd40};
+            end
+            5:begin 
+                SPIdata = {1'h0, 7'h2a, 16'd50};
+            end
+            6:begin 
+                SPIdata = {1'h0, 7'h2a, 16'd60};
+            end
+            7:begin 
+                SPIdata = {1'h0, 7'h2a, 16'd70};
+            end
+        endcase
+        end
+        else if (locked && !rstInit && !modeSel) begin 
+            case (trCnt) 
+            0: begin 
+                SPIdata = 24'h555554;
+            end
+            1:begin 
+                SPIdata = {1'h0, 7'h2a, 16'd10};
+            end
+        endcase
+        case (trCntSync) 
+           2 : begin 
+            SPIdata = {1'h0, 7'h2a, 16'd20};
+            end
+            3 : begin 
+                SPIdata = {1'h0, 7'h2a, 16'd30};
+            end
+            4 : begin 
+                SPIdata = {1'h0, 7'h2a, 16'd40};
+            end
+            5 : begin 
+                SPIdata = {1'h0, 7'h2a, 16'd50};
+            end
+            6 : begin 
+                SPIdata = {1'h0, 7'h2a, 16'd60};
+            end
+            7 : begin 
+                SPIdata = {1'h0, 7'h2a, 16'd70};
+            end
+        endcase
+        end
+        else begin 
+            SPIdata = 24'h0;
+        end
+    end
+
+
+endmodule

src/src/fifo_top/DDSFifo/fifo_top/FifoDDS.ipc

@@ -0,0 +1,30 @@
+[General]
+ipc_version=4
+file=FifoDDS
+module=FifoDDS
+target_device=gw1n9c-046
+type=fifo
+version=3.0
+
+[Config]
+ALEMPTY=0
+ALFULL=0
+COUNT_R=true
+COUNT_W=true
+DEPTH_R=5
+DEPTH_W=5
+ECC=false
+EN_ALEMPTY=false
+EN_ALFULL=false
+FWFT=true
+IMPL=1
+IO_INSERTION=false
+LANG=0
+OUTPUT_REG=false
+RDEN_CTRL=false
+RESET=true
+RESET_SYNC=true
+Read_Write_Check_on_RAM=true
+SIZE_W=72
+STANDARD_FIFO=false
+Synthesis_tool=GowinSynthesis

src/src/fifo_top/DDSFifo/fifo_top/FifoDDS_tmp.v

@@ -0,0 +1,27 @@
+//Copyright (C)2014-2024 Gowin Semiconductor Corporation.
+//All rights reserved.
+//File Title: Template file for instantiation
+//Tool Version: V1.9.9.01 (64-bit)
+//Part Number: GW1N-LV9PG256C6/I5
+//Device: GW1N-9
+//Device Version: C
+//Created Time: Thu Mar 21 09:34:24 2024
+
+//Change the instance name and port connections to the signal names
+//--------Copy here to design--------
+
+	FifoDDS your_instance_name(
+		.Data(Data_i), //input [71:0] Data
+		.Reset(Reset_i), //input Reset
+		.WrClk(WrClk_i), //input WrClk
+		.RdClk(RdClk_i), //input RdClk
+		.WrEn(WrEn_i), //input WrEn
+		.RdEn(RdEn_i), //input RdEn
+		.Wnum(Wnum_o), //output [6:0] Wnum
+		.Rnum(Rnum_o), //output [6:0] Rnum
+		.Q(Q_o), //output [71:0] Q
+		.Empty(Empty_o), //output Empty
+		.Full(Full_o) //output Full
+	);
+
+//--------Copy end-------------------

src/src/fifo_top/DDSFifo/fifo_top/temp/FIFO/FIFO.prj

@@ -0,0 +1,22 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!DOCTYPE gowin-synthesis-project>
+<Project>
+    <Version>beta</Version>
+    <Device id="GW1N-9C" package="PBGA256" speed="6" partNumber="GW1N-LV9PG256C6/I5"/>
+    <FileList>
+        <File path="C:/RF_FPGA/src/src/fifo_top/DDSFifo/fifo_top/temp/FIFO/fifo_define.v" type="verilog"/>
+        <File path="C:/RF_FPGA/src/src/fifo_top/DDSFifo/fifo_top/temp/FIFO/fifo_parameter.v" type="verilog"/>
+        <File path="C:/Gowin/Gowin_V1.9.9.01_x64/IDE/ipcore/FIFO/data/edc.v" type="verilog"/>
+        <File path="C:/Gowin/Gowin_V1.9.9.01_x64/IDE/ipcore/FIFO/data/fifo.v" type="verilog"/>
+        <File path="C:/Gowin/Gowin_V1.9.9.01_x64/IDE/ipcore/FIFO/data/fifo_top.v" type="verilog"/>
+    </FileList>
+    <OptionList>
+        <Option type="disable_insert_pad" value="1"/>
+        <Option type="include_path" value="C:/RF_FPGA/src/src/fifo_top/DDSFifo/fifo_top/temp/FIFO"/>
+        <Option type="output_file" value="FifoDDS.vg"/>
+        <Option type="output_template" value="FifoDDS_tmp.v"/>
+        <Option type="ram_balance" value="1"/>
+        <Option type="ram_rw_check" value="1"/>
+        <Option type="verilog_language" value="sysv-2017"/>
+    </OptionList>
+</Project>

src/src/fifo_top/DDSFifo/fifo_top/temp/FIFO/FifoDDS.log

@@ -0,0 +1,46 @@
+GowinSynthesis start
+Running parser ...
+Analyzing Verilog file 'C:\RF_FPGA\src\src\fifo_top\DDSFifo\fifo_top\temp\FIFO\fifo_define.v'
+Analyzing Verilog file 'C:\RF_FPGA\src\src\fifo_top\DDSFifo\fifo_top\temp\FIFO\fifo_parameter.v'
+Analyzing Verilog file 'C:\Gowin\Gowin_V1.9.9.01_x64\IDE\ipcore\FIFO\data\edc.v'
+Analyzing included file '**'("C:\Gowin\Gowin_V1.9.9.01_x64\IDE\ipcore\FIFO\data\edc.v":14373)
+Back to file '**'("C:\Gowin\Gowin_V1.9.9.01_x64\IDE\ipcore\FIFO\data\edc.v":14373)
+Undeclared symbol '**', assumed default net type '**'("C:\Gowin\Gowin_V1.9.9.01_x64\IDE\ipcore\FIFO\data\edc.v":14373)
+Analyzing Verilog file 'C:\Gowin\Gowin_V1.9.9.01_x64\IDE\ipcore\FIFO\data\fifo.v'
+Analyzing included file '**'("C:\Gowin\Gowin_V1.9.9.01_x64\IDE\ipcore\FIFO\data\fifo.v":553)
+Back to file '**'("C:\Gowin\Gowin_V1.9.9.01_x64\IDE\ipcore\FIFO\data\fifo.v":553)
+Analyzing Verilog file 'C:\Gowin\Gowin_V1.9.9.01_x64\IDE\ipcore\FIFO\data\fifo_top.v'
+Analyzing included file 'fifo_define.v'("C:\Gowin\Gowin_V1.9.9.01_x64\IDE\ipcore\FIFO\data\fifo_top.v":1)
+Back to file 'C:\Gowin\Gowin_V1.9.9.01_x64\IDE\ipcore\FIFO\data\fifo_top.v'("C:\Gowin\Gowin_V1.9.9.01_x64\IDE\ipcore\FIFO\data\fifo_top.v":1)
+Analyzing included file 'fifo_parameter.v'("C:\Gowin\Gowin_V1.9.9.01_x64\IDE\ipcore\FIFO\data\fifo_top.v":56)
+Back to file 'C:\Gowin\Gowin_V1.9.9.01_x64\IDE\ipcore\FIFO\data\fifo_top.v'("C:\Gowin\Gowin_V1.9.9.01_x64\IDE\ipcore\FIFO\data\fifo_top.v":56)
+WARN  (EX2582) : Parameter 'WDEPTH' declared inside compilation unit '$unit_fifo_define_v' shall be treated as localparam("fifo_parameter.v":1)
+WARN  (EX2582) : Parameter 'WDSIZE' declared inside compilation unit '$unit_fifo_define_v' shall be treated as localparam("fifo_parameter.v":2)
+WARN  (EX2582) : Parameter 'RDEPTH' declared inside compilation unit '$unit_fifo_define_v' shall be treated as localparam("fifo_parameter.v":3)
+WARN  (EX2582) : Parameter 'RDSIZE' declared inside compilation unit '$unit_fifo_define_v' shall be treated as localparam("fifo_parameter.v":4)
+WARN  (EX2582) : Parameter 'ASIZE' declared inside compilation unit '$unit_fifo_define_v' shall be treated as localparam("fifo_parameter.v":5)
+WARN  (EX2582) : Parameter 'RASIZE' declared inside compilation unit '$unit_fifo_define_v' shall be treated as localparam("fifo_parameter.v":6)
+Compiling module 'FifoDDS'("C:\Gowin\Gowin_V1.9.9.01_x64\IDE\ipcore\FIFO\data\fifo_top.v":3)
+Compiling module '**'("C:\Gowin\Gowin_V1.9.9.01_x64\IDE\ipcore\FIFO\data\fifo.v":553)
+Extracting RAM for identifier '**'("C:\Gowin\Gowin_V1.9.9.01_x64\IDE\ipcore\FIFO\data\fifo.v":553)
+NOTE  (EX0101) : Current top module is "FifoDDS"
+[5%] Running netlist conversion ...
+Running device independent optimization ...
+[10%] Optimizing Phase 0 completed
+[15%] Optimizing Phase 1 completed
+[25%] Optimizing Phase 2 completed
+Running inference ...
+[30%] Inferring Phase 0 completed
+[40%] Inferring Phase 1 completed
+[50%] Inferring Phase 2 completed
+[55%] Inferring Phase 3 completed
+Running technical mapping ...
+[60%] Tech-Mapping Phase 0 completed
+[65%] Tech-Mapping Phase 1 completed
+[75%] Tech-Mapping Phase 2 completed
+[80%] Tech-Mapping Phase 3 completed
+[90%] Tech-Mapping Phase 4 completed
+[95%] Generate netlist file "C:\RF_FPGA\src\src\fifo_top\DDSFifo\fifo_top\temp\FIFO\FifoDDS.vg" completed
+Generate template file "C:\RF_FPGA\src\src\fifo_top\DDSFifo\fifo_top\temp\FIFO\FifoDDS_tmp.v" completed
+[100%] Generate report file "C:\RF_FPGA\src\src\fifo_top\DDSFifo\fifo_top\temp\FIFO\FifoDDS_syn.rpt.html" completed
+GowinSynthesis finish

src/src/fifo_top/DDSFifo/fifo_top/temp/FIFO/FifoDDS_syn_resource.html

@@ -0,0 +1,44 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html>
+<head>
+<title>Hierarchy Module Resource</title>
+<style type="text/css">
+body { font-family: Verdana, Arial, sans-serif; font-size: 14px; }
+div#main_wrapper{ width: 100%; }
+h1 {text-align: center; }
+h1 {margin-top: 36px; }
+table, th, td { border: 1px solid #aaa; }
+table { border-collapse:collapse; margin-top: 10px; margin-bottom: 20px; width: 100%; }
+th, td { align = "center"; padding: 5px 2px 5px 5px; }
+th { color: #fff; font-weight: bold; background-color: #0084ff; }
+table td.label { width: 20%; white-space: nowrap; min-width: 20px; background-color: #dee8f4; }
+</style>
+</head>
+<body>
+<div id="main_wrapper">
+<div id="content">
+<h1>Hierarchy Module Resource</h1>
+<table>
+<tr>
+<th class="label">MODULE NAME</th>
+<th class="label">REG NUMBER</th>
+<th class="label">ALU NUMBER</th>
+<th class="label">LUT NUMBER</th>
+<th class="label">DSP NUMBER</th>
+<th class="label">BSRAM NUMBER</th>
+<th class="label">SSRAM NUMBER</th>
+</tr>
+<tr>
+<td class="label">FifoDDS (C:/Gowin/Gowin_V1.9.9.01_x64/IDE/ipcore/FIFO/data/fifo_top.v)</td>
+<td align = "center">146</td>
+<td align = "center">21</td>
+<td align = "center">206</td>
+<td align = "center">-</td>
+<td align = "center">-</td>
+<td align = "center">72</td>
+</tr>
+</table>
+</div><!-- content -->
+</div><!-- main_wrapper -->
+</body>
+</html>

src/src/fifo_top/DDSFifo/fifo_top/temp/FIFO/FifoDDS_syn_rsc.xml

@@ -0,0 +1,2 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<Module name="FifoDDS" Register="146" Alu="21" Lut="206" Ssram="72" T_Register="146(146)" T_Alu="21(21)" T_Lut="206(206)" T_Ssram="72(72)"/>

src/src/fifo_top/DDSFifo/fifo_top/temp/FIFO/FifoDDS_tmp.v

@@ -0,0 +1,27 @@
+//Copyright (C)2014-2024 Gowin Semiconductor Corporation.
+//All rights reserved.
+//File Title: Template file for instantiation
+//Tool Version: V1.9.9.01 (64-bit)
+//Part Number: GW1N-LV9PG256C6/I5
+//Device: GW1N-9
+//Device Version: C
+//Created Time: Thu Mar 21 09:34:24 2024
+
+//Change the instance name and port connections to the signal names
+//--------Copy here to design--------
+
+	FifoDDS your_instance_name(
+		.Data(Data_i), //input [71:0] Data
+		.Reset(Reset_i), //input Reset
+		.WrClk(WrClk_i), //input WrClk
+		.RdClk(RdClk_i), //input RdClk
+		.WrEn(WrEn_i), //input WrEn
+		.RdEn(RdEn_i), //input RdEn
+		.Wnum(Wnum_o), //output [6:0] Wnum
+		.Rnum(Rnum_o), //output [6:0] Rnum
+		.Q(Q_o), //output [71:0] Q
+		.Empty(Empty_o), //output Empty
+		.Full(Full_o) //output Full
+	);
+
+//--------Copy end-------------------

src/src/fifo_top/DDSFifo/fifo_top/temp/FIFO/fifo_define.v

@@ -0,0 +1,8 @@
+`define module_name FifoDDS
+`define getname(oriName,tmodule_name) \~oriName.tmodule_name 
+`define DSR_BASED
+`define FWFT
+`define Count_W
+`define Count_R
+`define En_Reset
+`define Reset_Synchronization

src/src/fifo_top/DDSFifo/fifo_top/temp/FIFO/fifo_parameter.v

@@ -0,0 +1,6 @@
+parameter WDEPTH = 64;
+parameter WDSIZE = 72;
+parameter RDEPTH = 64;
+parameter RDSIZE = 72;
+parameter ASIZE = 6;
+parameter RASIZE = 6;

src/src/fifo_top/DDSFifo/fifo_top/temp/FIFO/project.ini

@@ -0,0 +1 @@
+RESOURCE_CHECK=false

src/src/fifo_top/FifoCtrl.v

@@ -0,0 +1,420 @@
+module FifoCtrl#(
+    parameter FifoNum = 8
+)(
+input WrClk_i,
+input Rst_i,
+input[FifoNum-1:0]  RdClk_i,
+input [4:0] CurrState_i,
+input [2:0] DDSFifoCnt_i,
+input [2:0] MAX2870FifoCnt_i,
+input ValToReadFromRxFifo1_i,
+input ValToReadFromRxFifo2_i,
+input ValToReadFromRxFifo3_i,
+input ValToReadFromRxFifo4_i,
+input ValToReadFromRxFifo5_i,
+input ValToReadFromRxFifo6_i,
+input ValToReadFromRxFifo7_i,
+input [4:0] CurrStateSync1_i,
+input [4:0] CurrStateSync2_i,
+input [4:0] CurrStateSync3_i,
+input [4:0] CurrStateSync4_i,
+input [4:0] CurrStateSync5_i,
+input [23:0] DataToRxFifo_i,
+input ValToRxFifo_i,
+
+
+output [FifoNum-1:0] EmptyFlag_o,
+
+output [23:0] DataFromRxFifo1_o,
+output [63:0] DataFromRxFifo2_o,
+output [31:0] DataFromMAX2870Fifo_o,
+output [7:0]  DataFromShRegFifo_o,
+output [15:0] DataFromAttFifo_o,
+output [15:0] DataFromDacFifo_o,
+output [15:0] DataFromPotFifo_o
+
+
+
+);
+
+
+reg     [FifoNum-1:0] rxFifoWrEn;
+reg     [FifoNum-1:0] rxFifoReadEn;
+
+reg     [0:23] dataToRxFifoReg [FifoNum-1:0];
+reg     [23:0] dataToRxFifoReg21;
+reg     [23:0] dataToRxFifoReg22;
+reg     [23:0] dataToRxFifoReg23;
+wire    [71:0] dataToRxFifo2;
+wire    [71:0] dataFromRxFifo2;
+
+reg     [47:0] dataToFifoMax2870Reg;
+wire    [47:0] dataToFifoMax2870;
+wire    [47:0] dataFromMAX2870Fifo;
+
+reg     [1:0] rdEnCnt1;
+reg     [1:0] rdEnCnt2;
+reg     [1:0] rdEnCnt3;
+reg     [1:0] rdEnCnt4;
+reg     [1:0] rdEnCnt5;
+reg     [1:0] rdEnCnt6;
+reg     [1:0] rdEnCnt7;
+
+
+
+wire [FifoNum-1:0] emptyFlag;
+wire [FifoNum-1:0] fullFlag;
+wire [0:23] dataToRxFifo [FifoNum-1:0];
+wire [0:23] dataFromRxFifo [FifoNum-1:0];
+
+
+
+assign dataToRxFifo[0]= dataToRxFifoReg[0];
+assign dataToRxFifo[1]= dataToRxFifoReg[1];
+assign dataToRxFifo[2]= dataToRxFifoReg[2];
+assign dataToRxFifo[3]= dataToRxFifoReg[3];
+assign dataToRxFifo[4]= dataToRxFifoReg[4];
+assign DataFromRxFifo1_o = dataFromRxFifo[0];
+assign DataFromRxFifo2_o = dataFromRxFifo2[71:8];
+assign DataFromMAX2870Fifo_o = dataFromMAX2870Fifo[47-:32];
+assign DataFromShRegFifo_o = dataFromRxFifo[5][0:7];
+assign DataFromAttFifo_o = dataFromRxFifo[4][0:15];
+assign DataFromDacFifo_o = dataFromRxFifo[3][0:15];
+assign DataFromPotFifo_o = dataFromRxFifo[2][0:15];
+
+
+
+
+
+assign dataToRxFifo2 = {dataToRxFifoReg21, dataToRxFifoReg22, dataToRxFifoReg23};
+assign dataToFifoMax2870 = dataToFifoMax2870Reg;
+
+assign EmptyFlag_o = emptyFlag;
+
+integer k; 
+
+always @(posedge WrClk_i) begin 
+    case (CurrState_i)  
+        5'd1 : begin 
+            dataToRxFifoReg[0] <= DataToRxFifo_i;
+        end
+        5'd2 : begin
+            if (DDSFifoCnt_i == 3'h0 ) begin 
+                dataToRxFifoReg21 <= DataToRxFifo_i;
+            end
+            else if (DDSFifoCnt_i == 3'h1) begin 
+                dataToRxFifoReg22 <= DataToRxFifo_i;
+            end
+            else if (DDSFifoCnt_i == 3'h3) begin 
+                dataToRxFifoReg23 <= DataToRxFifo_i;
+            end
+        end
+        5'd3 : begin 
+            dataToRxFifoReg[2] <= DataToRxFifo_i;
+        end
+        5'd4 : begin 
+            dataToRxFifoReg[3] <= DataToRxFifo_i;
+        end
+        5'd5 : begin 
+            dataToRxFifoReg[4] <= DataToRxFifo_i;
+        end
+        5'd6 : begin 
+            dataToRxFifoReg[5] <= DataToRxFifo_i;
+        end
+        5'd7 : begin 
+            case (MAX2870FifoCnt_i) 
+                2'h0 : begin
+                    dataToFifoMax2870Reg[47:24] <= DataToRxFifo_i;
+                end
+                2'h1 : begin
+                    dataToFifoMax2870Reg[23:0] <= DataToRxFifo_i;
+                end 
+                // default: begin 
+                //     dataToFifoMax2870Reg = 0;
+                // end
+            endcase
+        end
+        5'd8 : begin 
+            dataToRxFifoReg[7] <= DataToRxFifo_i;
+        end
+        default: begin 
+            for (k = 0; k < FifoNum; k = k + 1) begin 
+                dataToRxFifoReg[k] <= 0;
+            end
+            dataToRxFifoReg21 <= 0;
+            dataToRxFifoReg22 <= 0;
+            dataToRxFifoReg23 <= 0;
+        end
+    endcase
+end
+
+
+
+always @(posedge WrClk_i) begin 
+    case (CurrState_i) 
+    0 : begin 
+        rxFifoWrEn <= 1'b0;
+    end
+    1: begin 
+        if (!fullFlag[0] && ValToRxFifo_i) begin 
+                rxFifoWrEn[0] <= 1'b1;
+            end
+            else begin 
+                rxFifoWrEn[0] <= 1'b0;
+            end
+    end
+    2: begin 
+        if (!fullFlag[1] && ValToRxFifo_i && DDSFifoCnt_i == 3'h2 ) begin 
+                rxFifoWrEn[1] <= 1'b1;
+            end
+            else begin 
+                rxFifoWrEn[1] <= 1'b0;
+            end
+    end
+    3: begin 
+        if (!fullFlag[2] && ValToRxFifo_i) begin 
+                rxFifoWrEn[2] <= 1'b1;
+            end
+            else begin 
+                rxFifoWrEn[2] <= 1'b0;
+            end
+    end
+    4: begin 
+        if (!fullFlag[3] && ValToRxFifo_i) begin 
+                rxFifoWrEn[3] <= 1'b1;
+            end
+            else begin 
+                rxFifoWrEn[3] <= 1'b0;
+            end
+    end
+    5: begin 
+        if (!fullFlag[4] && ValToRxFifo_i) begin 
+                rxFifoWrEn[4] <= 1'b1;
+            end
+            else begin 
+                rxFifoWrEn[4] <= 1'b0;
+            end
+    end
+    6: begin 
+        if (!fullFlag[5] && ValToRxFifo_i) begin 
+                rxFifoWrEn[5] <= 1'b1;
+            end
+            else begin 
+                rxFifoWrEn[5] <= 1'b0;
+            end
+    end
+    7: begin 
+        if (!fullFlag[6] && ValToRxFifo_i && MAX2870FifoCnt_i == 3'h1) begin 
+                rxFifoWrEn[6] <= 1'b1;
+            end
+            else begin 
+                rxFifoWrEn[6] <= 1'b0;
+            end
+    end
+    default: begin 
+        rxFifoWrEn <= 1'b0;
+    end
+    endcase
+end
+
+always @(posedge RdClk_i[0]) begin
+    if (!emptyFlag[0] && ValToReadFromRxFifo1_i && rdEnCnt1 < 1 ) begin 
+        rxFifoReadEn[0] <= 1'b1;
+    end
+    else if (rdEnCnt1 >= 1 ) begin 
+        rxFifoReadEn[0] <= 1'b0;
+    end
+    else begin 
+        rxFifoReadEn[0] <= 1'b0;
+    end
+end
+
+always @(posedge RdClk_i[1]) begin 
+    if (!emptyFlag[1] && ValToReadFromRxFifo2_i && rdEnCnt2 < 1 ) begin 
+        rxFifoReadEn[1] <= 1'b1;
+    end
+    else if (rdEnCnt2 >= 1 ) begin 
+        rxFifoReadEn[1] <= 1'b0;
+    end
+    else begin 
+        rxFifoReadEn[1] <= 1'b0;
+    end
+end
+
+always @(posedge RdClk_i[2]) begin 
+    if (!emptyFlag[2] && ValToReadFromRxFifo3_i && rdEnCnt3 < 1 ) begin 
+        rxFifoReadEn[2] <= 1'b1;
+    end
+    else if (rdEnCnt3 >= 1 ) begin 
+        rxFifoReadEn[2] <= 1'b0;
+    end
+    else begin 
+        rxFifoReadEn[2] <= 1'b0;
+    end
+end
+
+always @(posedge RdClk_i[3]) begin 
+    if (!emptyFlag[3] && ValToReadFromRxFifo4_i && rdEnCnt4 < 1 ) begin 
+        rxFifoReadEn[3] <= 1'b1;
+    end
+    else if (rdEnCnt4 >= 1 ) begin 
+        rxFifoReadEn[3] <= 1'b0;
+    end
+    else begin 
+        rxFifoReadEn[3] <= 1'b0;
+    end
+end
+
+always @(posedge RdClk_i[4]) begin 
+    if (!emptyFlag[4] && ValToReadFromRxFifo5_i && rdEnCnt5 < 1 ) begin 
+        rxFifoReadEn[4] <= 1'b1;
+    end
+    else if (rdEnCnt5 >= 1 ) begin 
+        rxFifoReadEn[4] <= 1'b0;
+    end
+    else begin 
+        rxFifoReadEn[4] <= 1'b0;
+    end
+end
+
+always @(posedge RdClk_i[5]) begin 
+    if (!emptyFlag[5] && ValToReadFromRxFifo6_i && rdEnCnt6 < 1 ) begin 
+        rxFifoReadEn[5] <= 1'b1;
+    end
+    else if (rdEnCnt6 >= 1 ) begin 
+        rxFifoReadEn[5] <= 1'b0;
+    end
+    else begin 
+        rxFifoReadEn[5] <= 1'b0;
+    end
+end
+
+always @(posedge RdClk_i[6]) begin 
+    if (!emptyFlag[6] && ValToReadFromRxFifo7_i && rdEnCnt7 < 1 ) begin 
+        rxFifoReadEn[6] <= 1'b1;
+    end
+    else if (rdEnCnt7 >= 1 ) begin 
+        rxFifoReadEn[6] <= 1'b0;
+    end
+    else begin 
+        rxFifoReadEn[6] <= 1'b0;
+    end
+end
+
+
+always @(posedge RdClk_i[0]) begin 
+    if (rxFifoReadEn[0]) begin 
+        rdEnCnt1 <= rdEnCnt1 + 1'b1;
+    end
+    else begin 
+        rdEnCnt1 <= 1'b0;
+    end
+end
+
+
+always @(posedge RdClk_i[1]) begin 
+    if (rxFifoReadEn[1]) begin 
+        rdEnCnt2 <= rdEnCnt2 + 1'b1;
+    end
+    else begin 
+        rdEnCnt2 <= 1'b0;
+    end
+end
+
+always @(posedge RdClk_i[2]) begin 
+    if (rxFifoReadEn[2]) begin 
+        rdEnCnt3 <= rdEnCnt3 + 1'b1;
+    end
+    else begin 
+        rdEnCnt3 <= 1'b0;
+    end
+end
+
+always @(posedge RdClk_i[3]) begin 
+    if (rxFifoReadEn[3]) begin 
+        rdEnCnt4 <= rdEnCnt4 + 1'b1;
+    end
+    else begin 
+        rdEnCnt4 <= 1'b0;
+    end
+end
+
+always @(posedge RdClk_i[4]) begin 
+    if (rxFifoReadEn[4]) begin 
+        rdEnCnt5 <= rdEnCnt5 + 1'b1;
+    end
+    else begin 
+        rdEnCnt5 <= 1'b0;
+    end
+end
+
+always @(posedge RdClk_i[5]) begin 
+    if (rxFifoReadEn[5]) begin 
+        rdEnCnt6 <= rdEnCnt6 + 1'b1;
+    end
+    else begin 
+        rdEnCnt6 <= 1'b0;
+    end
+end
+
+always @(posedge RdClk_i[6]) begin 
+    if (rxFifoReadEn[6]) begin 
+        rdEnCnt7 <= rdEnCnt7 + 1'b1;
+    end
+    else begin 
+        rdEnCnt7 <= 1'b0;
+    end
+end
+
+
+genvar i;
+
+generate for (i = 0; i < FifoNum; i = i + 1 ) begin : fifoGen
+    if (i != 1  && i != 6 && i != 7) begin
+        FifoRxRF RxFifoRF (
+            .Data(dataToRxFifo[i]),
+            .Reset(Rst_i),
+            .WrClk(WrClk_i),
+            .RdClk(RdClk_i[i]),
+            .WrEn(rxFifoWrEn[i]),
+            .RdEn(rxFifoReadEn[i]),
+            .Empty(emptyFlag[i]),
+            .Full(fullFlag[i]),
+            .Q(dataFromRxFifo[i])
+        );
+    end
+end 
+endgenerate
+
+
+FifoDDS DDSFifo (
+    .Data(dataToRxFifo2),
+    .Reset(Rst_i),
+    .WrClk(WrClk_i),
+    .RdClk(RdClk_i[1]),
+    .WrEn(rxFifoWrEn[1]),
+    .RdEn(rxFifoReadEn[1]),
+    .Empty(emptyFlag[1]),
+    .Full(fullFlag[1]),
+    .Q(dataFromRxFifo2)
+
+);
+
+
+FifoMax2870 Max2870Fifo (
+    .Data(dataToFifoMax2870),
+    .Reset(Rst_i),
+    .WrClk(WrClk_i),
+    .RdClk(RdClk_i[6]),
+    .WrEn(rxFifoWrEn[6]),
+    .RdEn(rxFifoReadEn[6]),
+    .Empty(emptyFlag[6]),
+    .Full(fullFlag[6]),
+    .Q(dataFromMAX2870Fifo)
+);
+
+
+
+
+
+endmodule

src/src/fifo_top/FifoRxRF.ipc

@@ -0,0 +1,30 @@
+[General]
+ipc_version=4
+file=FifoRxRF
+module=FifoRxRF
+target_device=gw1n9c-046
+type=fifo
+version=3.0
+
+[Config]
+ALEMPTY=0
+ALFULL=0
+COUNT_R=true
+COUNT_W=true
+DEPTH_R=5
+DEPTH_W=5
+ECC=false
+EN_ALEMPTY=false
+EN_ALFULL=false
+FWFT=true
+IMPL=1
+IO_INSERTION=false
+LANG=0
+OUTPUT_REG=false
+RDEN_CTRL=false
+RESET=true
+RESET_SYNC=true
+Read_Write_Check_on_RAM=true
+SIZE_W=24
+STANDARD_FIFO=false
+Synthesis_tool=GowinSynthesis

src/src/fifo_top/FifoRxRF_tmp.v

@@ -0,0 +1,27 @@
+//Copyright (C)2014-2024 Gowin Semiconductor Corporation.
+//All rights reserved.
+//File Title: Template file for instantiation
+//Tool Version: V1.9.9.01 (64-bit)
+//Part Number: GW1N-LV9PG256C6/I5
+//Device: GW1N-9
+//Device Version: C
+//Created Time: Thu Mar 21 09:39:05 2024
+
+//Change the instance name and port connections to the signal names
+//--------Copy here to design--------
+
+	FifoRxRF your_instance_name(
+		.Data(Data_i), //input [23:0] Data
+		.Reset(Reset_i), //input Reset
+		.WrClk(WrClk_i), //input WrClk
+		.RdClk(RdClk_i), //input RdClk
+		.WrEn(WrEn_i), //input WrEn
+		.RdEn(RdEn_i), //input RdEn
+		.Wnum(Wnum_o), //output [6:0] Wnum
+		.Rnum(Rnum_o), //output [6:0] Rnum
+		.Q(Q_o), //output [23:0] Q
+		.Empty(Empty_o), //output Empty
+		.Full(Full_o) //output Full
+	);
+
+//--------Copy end-------------------

src/src/fifo_top/MAX2870FIFO/FifoMax2870.ipc

@@ -0,0 +1,30 @@
+[General]
+ipc_version=4
+file=FifoMax2870
+module=FifoMax2870
+target_device=gw2a55c-005
+type=fifo
+version=3.0
+
+[Config]
+ALEMPTY=0
+ALFULL=0
+COUNT_R=false
+COUNT_W=false
+DEPTH_R=2
+DEPTH_W=2
+ECC=false
+EN_ALEMPTY=false
+EN_ALFULL=false
+FWFT=true
+IMPL=1
+IO_INSERTION=false
+LANG=0
+OUTPUT_REG=false
+RDEN_CTRL=false
+RESET=true
+RESET_SYNC=true
+Read_Write_Check_on_RAM=true
+SIZE_W=48
+STANDARD_FIFO=false
+Synthesis_tool=GowinSynthesis

src/src/fifo_top/MAX2870FIFO/FifoMax2870_tmp.v

@@ -0,0 +1,25 @@
+//Copyright (C)2014-2024 Gowin Semiconductor Corporation.
+//All rights reserved.
+//File Title: Template file for instantiation
+//Tool Version: V1.9.9.01 (64-bit)
+//Part Number: GW2A-LV55PG484C8/I7
+//Device: GW2A-55
+//Device Version: C
+//Created Time: Tue Feb 27 10:41:13 2024
+
+//Change the instance name and port connections to the signal names
+//--------Copy here to design--------
+
+	FifoMax2870 your_instance_name(
+		.Data(Data_i), //input [47:0] Data
+		.Reset(Reset_i), //input Reset
+		.WrClk(WrClk_i), //input WrClk
+		.RdClk(RdClk_i), //input RdClk
+		.WrEn(WrEn_i), //input WrEn
+		.RdEn(RdEn_i), //input RdEn
+		.Q(Q_o), //output [47:0] Q
+		.Empty(Empty_o), //output Empty
+		.Full(Full_o) //output Full
+	);
+
+//--------Copy end-------------------

src/src/fifo_top/MAX2870FIFO/fifo_top/FifoMax2870.ipc

@@ -0,0 +1,30 @@
+[General]
+ipc_version=4
+file=FifoMax2870
+module=FifoMax2870
+target_device=gw1n9c-046
+type=fifo
+version=3.0
+
+[Config]
+ALEMPTY=0
+ALFULL=0
+COUNT_R=false
+COUNT_W=false
+DEPTH_R=5
+DEPTH_W=5
+ECC=false
+EN_ALEMPTY=false
+EN_ALFULL=false
+FWFT=true
+IMPL=1
+IO_INSERTION=false
+LANG=0
+OUTPUT_REG=false
+RDEN_CTRL=false
+RESET=true
+RESET_SYNC=true
+Read_Write_Check_on_RAM=true
+SIZE_W=48
+STANDARD_FIFO=false
+Synthesis_tool=GowinSynthesis

src/src/fifo_top/MAX2870FIFO/fifo_top/FifoMax2870_tmp.v

@@ -0,0 +1,25 @@
+//Copyright (C)2014-2024 Gowin Semiconductor Corporation.
+//All rights reserved.
+//File Title: Template file for instantiation
+//Tool Version: V1.9.9.01 (64-bit)
+//Part Number: GW1N-LV9PG256C6/I5
+//Device: GW1N-9
+//Device Version: C
+//Created Time: Thu Mar 21 09:34:56 2024
+
+//Change the instance name and port connections to the signal names
+//--------Copy here to design--------
+
+	FifoMax2870 your_instance_name(
+		.Data(Data_i), //input [47:0] Data
+		.Reset(Reset_i), //input Reset
+		.WrClk(WrClk_i), //input WrClk
+		.RdClk(RdClk_i), //input RdClk
+		.WrEn(WrEn_i), //input WrEn
+		.RdEn(RdEn_i), //input RdEn
+		.Q(Q_o), //output [47:0] Q
+		.Empty(Empty_o), //output Empty
+		.Full(Full_o) //output Full
+	);
+
+//--------Copy end-------------------

src/src/fifo_top/MAX2870FIFO/fifo_top/temp/FIFO/FIFO.prj

@@ -0,0 +1,22 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!DOCTYPE gowin-synthesis-project>
+<Project>
+    <Version>beta</Version>
+    <Device id="GW1N-9C" package="PBGA256" speed="6" partNumber="GW1N-LV9PG256C6/I5"/>
+    <FileList>
+        <File path="C:/RF_FPGA/src/src/fifo_top/MAX2870FIFO/fifo_top/temp/FIFO/fifo_define.v" type="verilog"/>
+        <File path="C:/RF_FPGA/src/src/fifo_top/MAX2870FIFO/fifo_top/temp/FIFO/fifo_parameter.v" type="verilog"/>
+        <File path="C:/Gowin/Gowin_V1.9.9.01_x64/IDE/ipcore/FIFO/data/edc.v" type="verilog"/>
+        <File path="C:/Gowin/Gowin_V1.9.9.01_x64/IDE/ipcore/FIFO/data/fifo.v" type="verilog"/>
+        <File path="C:/Gowin/Gowin_V1.9.9.01_x64/IDE/ipcore/FIFO/data/fifo_top.v" type="verilog"/>
+    </FileList>
+    <OptionList>
+        <Option type="disable_insert_pad" value="1"/>
+        <Option type="include_path" value="C:/RF_FPGA/src/src/fifo_top/MAX2870FIFO/fifo_top/temp/FIFO"/>
+        <Option type="output_file" value="FifoMax2870.vg"/>
+        <Option type="output_template" value="FifoMax2870_tmp.v"/>
+        <Option type="ram_balance" value="1"/>
+        <Option type="ram_rw_check" value="1"/>
+        <Option type="verilog_language" value="sysv-2017"/>
+    </OptionList>
+</Project>

src/src/fifo_top/MAX2870FIFO/fifo_top/temp/FIFO/FifoMax2870.log

@@ -0,0 +1,46 @@
+GowinSynthesis start
+Running parser ...
+Analyzing Verilog file 'C:\RF_FPGA\src\src\fifo_top\MAX2870FIFO\fifo_top\temp\FIFO\fifo_define.v'
+Analyzing Verilog file 'C:\RF_FPGA\src\src\fifo_top\MAX2870FIFO\fifo_top\temp\FIFO\fifo_parameter.v'
+Analyzing Verilog file 'C:\Gowin\Gowin_V1.9.9.01_x64\IDE\ipcore\FIFO\data\edc.v'
+Analyzing included file '**'("C:\Gowin\Gowin_V1.9.9.01_x64\IDE\ipcore\FIFO\data\edc.v":14373)
+Back to file '**'("C:\Gowin\Gowin_V1.9.9.01_x64\IDE\ipcore\FIFO\data\edc.v":14373)
+Undeclared symbol '**', assumed default net type '**'("C:\Gowin\Gowin_V1.9.9.01_x64\IDE\ipcore\FIFO\data\edc.v":14373)
+Analyzing Verilog file 'C:\Gowin\Gowin_V1.9.9.01_x64\IDE\ipcore\FIFO\data\fifo.v'
+Analyzing included file '**'("C:\Gowin\Gowin_V1.9.9.01_x64\IDE\ipcore\FIFO\data\fifo.v":553)
+Back to file '**'("C:\Gowin\Gowin_V1.9.9.01_x64\IDE\ipcore\FIFO\data\fifo.v":553)
+Analyzing Verilog file 'C:\Gowin\Gowin_V1.9.9.01_x64\IDE\ipcore\FIFO\data\fifo_top.v'
+Analyzing included file 'fifo_define.v'("C:\Gowin\Gowin_V1.9.9.01_x64\IDE\ipcore\FIFO\data\fifo_top.v":1)
+Back to file 'C:\Gowin\Gowin_V1.9.9.01_x64\IDE\ipcore\FIFO\data\fifo_top.v'("C:\Gowin\Gowin_V1.9.9.01_x64\IDE\ipcore\FIFO\data\fifo_top.v":1)
+Analyzing included file 'fifo_parameter.v'("C:\Gowin\Gowin_V1.9.9.01_x64\IDE\ipcore\FIFO\data\fifo_top.v":56)
+Back to file 'C:\Gowin\Gowin_V1.9.9.01_x64\IDE\ipcore\FIFO\data\fifo_top.v'("C:\Gowin\Gowin_V1.9.9.01_x64\IDE\ipcore\FIFO\data\fifo_top.v":56)
+WARN  (EX2582) : Parameter 'WDEPTH' declared inside compilation unit '$unit_fifo_define_v' shall be treated as localparam("fifo_parameter.v":1)
+WARN  (EX2582) : Parameter 'WDSIZE' declared inside compilation unit '$unit_fifo_define_v' shall be treated as localparam("fifo_parameter.v":2)
+WARN  (EX2582) : Parameter 'RDEPTH' declared inside compilation unit '$unit_fifo_define_v' shall be treated as localparam("fifo_parameter.v":3)
+WARN  (EX2582) : Parameter 'RDSIZE' declared inside compilation unit '$unit_fifo_define_v' shall be treated as localparam("fifo_parameter.v":4)
+WARN  (EX2582) : Parameter 'ASIZE' declared inside compilation unit '$unit_fifo_define_v' shall be treated as localparam("fifo_parameter.v":5)
+WARN  (EX2582) : Parameter 'RASIZE' declared inside compilation unit '$unit_fifo_define_v' shall be treated as localparam("fifo_parameter.v":6)
+Compiling module 'FifoMax2870'("C:\Gowin\Gowin_V1.9.9.01_x64\IDE\ipcore\FIFO\data\fifo_top.v":3)
+Compiling module '**'("C:\Gowin\Gowin_V1.9.9.01_x64\IDE\ipcore\FIFO\data\fifo.v":553)
+Extracting RAM for identifier '**'("C:\Gowin\Gowin_V1.9.9.01_x64\IDE\ipcore\FIFO\data\fifo.v":553)
+NOTE  (EX0101) : Current top module is "FifoMax2870"
+[5%] Running netlist conversion ...
+Running device independent optimization ...
+[10%] Optimizing Phase 0 completed
+[15%] Optimizing Phase 1 completed
+[25%] Optimizing Phase 2 completed
+Running inference ...
+[30%] Inferring Phase 0 completed
+[40%] Inferring Phase 1 completed
+[50%] Inferring Phase 2 completed
+[55%] Inferring Phase 3 completed
+Running technical mapping ...
+[60%] Tech-Mapping Phase 0 completed
+[65%] Tech-Mapping Phase 1 completed
+[75%] Tech-Mapping Phase 2 completed
+[80%] Tech-Mapping Phase 3 completed
+[90%] Tech-Mapping Phase 4 completed
+[95%] Generate netlist file "C:\RF_FPGA\src\src\fifo_top\MAX2870FIFO\fifo_top\temp\FIFO\FifoMax2870.vg" completed
+Generate template file "C:\RF_FPGA\src\src\fifo_top\MAX2870FIFO\fifo_top\temp\FIFO\FifoMax2870_tmp.v" completed
+[100%] Generate report file "C:\RF_FPGA\src\src\fifo_top\MAX2870FIFO\fifo_top\temp\FIFO\FifoMax2870_syn.rpt.html" completed
+GowinSynthesis finish

src/src/fifo_top/MAX2870FIFO/fifo_top/temp/FIFO/FifoMax2870_syn_resource.html

@@ -0,0 +1,44 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html>
+<head>
+<title>Hierarchy Module Resource</title>
+<style type="text/css">
+body { font-family: Verdana, Arial, sans-serif; font-size: 14px; }
+div#main_wrapper{ width: 100%; }
+h1 {text-align: center; }
+h1 {margin-top: 36px; }
+table, th, td { border: 1px solid #aaa; }
+table { border-collapse:collapse; margin-top: 10px; margin-bottom: 20px; width: 100%; }
+th, td { align = "center"; padding: 5px 2px 5px 5px; }
+th { color: #fff; font-weight: bold; background-color: #0084ff; }
+table td.label { width: 20%; white-space: nowrap; min-width: 20px; background-color: #dee8f4; }
+</style>
+</head>
+<body>
+<div id="main_wrapper">
+<div id="content">
+<h1>Hierarchy Module Resource</h1>
+<table>
+<tr>
+<th class="label">MODULE NAME</th>
+<th class="label">REG NUMBER</th>
+<th class="label">ALU NUMBER</th>
+<th class="label">LUT NUMBER</th>
+<th class="label">DSP NUMBER</th>
+<th class="label">BSRAM NUMBER</th>
+<th class="label">SSRAM NUMBER</th>
+</tr>
+<tr>
+<td class="label">FifoMax2870 (C:/Gowin/Gowin_V1.9.9.01_x64/IDE/ipcore/FIFO/data/fifo_top.v)</td>
+<td align = "center">108</td>
+<td align = "center">7</td>
+<td align = "center">145</td>
+<td align = "center">-</td>
+<td align = "center">-</td>
+<td align = "center">48</td>
+</tr>
+</table>
+</div><!-- content -->
+</div><!-- main_wrapper -->
+</body>
+</html>

src/src/fifo_top/MAX2870FIFO/fifo_top/temp/FIFO/FifoMax2870_syn_rsc.xml

@@ -0,0 +1,2 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<Module name="FifoMax2870" Register="108" Alu="7" Lut="145" Ssram="48" T_Register="108(108)" T_Alu="7(7)" T_Lut="145(145)" T_Ssram="48(48)"/>

src/src/fifo_top/MAX2870FIFO/fifo_top/temp/FIFO/FifoMax2870_tmp.v

@@ -0,0 +1,25 @@
+//Copyright (C)2014-2024 Gowin Semiconductor Corporation.
+//All rights reserved.
+//File Title: Template file for instantiation
+//Tool Version: V1.9.9.01 (64-bit)
+//Part Number: GW1N-LV9PG256C6/I5
+//Device: GW1N-9
+//Device Version: C
+//Created Time: Thu Mar 21 09:34:56 2024
+
+//Change the instance name and port connections to the signal names
+//--------Copy here to design--------
+
+	FifoMax2870 your_instance_name(
+		.Data(Data_i), //input [47:0] Data
+		.Reset(Reset_i), //input Reset
+		.WrClk(WrClk_i), //input WrClk
+		.RdClk(RdClk_i), //input RdClk
+		.WrEn(WrEn_i), //input WrEn
+		.RdEn(RdEn_i), //input RdEn
+		.Q(Q_o), //output [47:0] Q
+		.Empty(Empty_o), //output Empty
+		.Full(Full_o) //output Full
+	);
+
+//--------Copy end-------------------

src/src/fifo_top/MAX2870FIFO/fifo_top/temp/FIFO/fifo_define.v

@@ -0,0 +1,6 @@
+`define module_name FifoMax2870
+`define getname(oriName,tmodule_name) \~oriName.tmodule_name 
+`define DSR_BASED
+`define FWFT
+`define En_Reset
+`define Reset_Synchronization

src/src/fifo_top/MAX2870FIFO/fifo_top/temp/FIFO/fifo_parameter.v

@@ -0,0 +1,6 @@
+parameter WDEPTH = 64;
+parameter WDSIZE = 48;
+parameter RDEPTH = 64;
+parameter RDSIZE = 48;
+parameter ASIZE = 6;
+parameter RASIZE = 6;

src/src/fifo_top/MAX2870FIFO/fifo_top/temp/FIFO/project.ini

@@ -0,0 +1 @@
+RESOURCE_CHECK=false

src/src/fifo_top/MAX2870FIFO/temp/FIFO/FIFO.prj

@@ -0,0 +1,22 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!DOCTYPE gowin-synthesis-project>
+<Project>
+    <Version>beta</Version>
+    <Device id="GW2A-55C" package="PBGA484" speed="8" partNumber="GW2A-LV55PG484C8/I7"/>
+    <FileList>
+        <File path="C:/Users/AnatoliyChigirinskiy/Documents/RF_FPGA/src/fifo_top/MAX2870FIFO/temp/FIFO/fifo_define.v" type="verilog"/>
+        <File path="C:/Users/AnatoliyChigirinskiy/Documents/RF_FPGA/src/fifo_top/MAX2870FIFO/temp/FIFO/fifo_parameter.v" type="verilog"/>
+        <File path="C:/Gowin/Gowin_V1.9.9.01_x64/IDE/ipcore/FIFO/data/edc.v" type="verilog"/>
+        <File path="C:/Gowin/Gowin_V1.9.9.01_x64/IDE/ipcore/FIFO/data/fifo.v" type="verilog"/>
+        <File path="C:/Gowin/Gowin_V1.9.9.01_x64/IDE/ipcore/FIFO/data/fifo_top.v" type="verilog"/>
+    </FileList>
+    <OptionList>
+        <Option type="disable_insert_pad" value="1"/>
+        <Option type="include_path" value="C:/Users/AnatoliyChigirinskiy/Documents/RF_FPGA/src/fifo_top/MAX2870FIFO/temp/FIFO"/>
+        <Option type="output_file" value="FifoMax2870.vg"/>
+        <Option type="output_template" value="FifoMax2870_tmp.v"/>
+        <Option type="ram_balance" value="1"/>
+        <Option type="ram_rw_check" value="1"/>
+        <Option type="verilog_language" value="sysv-2017"/>
+    </OptionList>
+</Project>

src/src/fifo_top/MAX2870FIFO/temp/FIFO/FifoMax2870.log

@@ -0,0 +1,46 @@
+GowinSynthesis start
+Running parser ...
+Analyzing Verilog file 'C:\Users\AnatoliyChigirinskiy\Documents\RF_FPGA\src\fifo_top\MAX2870FIFO\temp\FIFO\fifo_define.v'
+Analyzing Verilog file 'C:\Users\AnatoliyChigirinskiy\Documents\RF_FPGA\src\fifo_top\MAX2870FIFO\temp\FIFO\fifo_parameter.v'
+Analyzing Verilog file 'C:\Gowin\Gowin_V1.9.9.01_x64\IDE\ipcore\FIFO\data\edc.v'
+Analyzing included file '**'("C:\Gowin\Gowin_V1.9.9.01_x64\IDE\ipcore\FIFO\data\edc.v":14373)
+Back to file '**'("C:\Gowin\Gowin_V1.9.9.01_x64\IDE\ipcore\FIFO\data\edc.v":14373)
+Undeclared symbol '**', assumed default net type '**'("C:\Gowin\Gowin_V1.9.9.01_x64\IDE\ipcore\FIFO\data\edc.v":14373)
+Analyzing Verilog file 'C:\Gowin\Gowin_V1.9.9.01_x64\IDE\ipcore\FIFO\data\fifo.v'
+Analyzing included file '**'("C:\Gowin\Gowin_V1.9.9.01_x64\IDE\ipcore\FIFO\data\fifo.v":553)
+Back to file '**'("C:\Gowin\Gowin_V1.9.9.01_x64\IDE\ipcore\FIFO\data\fifo.v":553)
+Analyzing Verilog file 'C:\Gowin\Gowin_V1.9.9.01_x64\IDE\ipcore\FIFO\data\fifo_top.v'
+Analyzing included file 'fifo_define.v'("C:\Gowin\Gowin_V1.9.9.01_x64\IDE\ipcore\FIFO\data\fifo_top.v":1)
+Back to file 'C:\Gowin\Gowin_V1.9.9.01_x64\IDE\ipcore\FIFO\data\fifo_top.v'("C:\Gowin\Gowin_V1.9.9.01_x64\IDE\ipcore\FIFO\data\fifo_top.v":1)
+Analyzing included file 'fifo_parameter.v'("C:\Gowin\Gowin_V1.9.9.01_x64\IDE\ipcore\FIFO\data\fifo_top.v":56)
+Back to file 'C:\Gowin\Gowin_V1.9.9.01_x64\IDE\ipcore\FIFO\data\fifo_top.v'("C:\Gowin\Gowin_V1.9.9.01_x64\IDE\ipcore\FIFO\data\fifo_top.v":56)
+WARN  (EX2582) : Parameter 'WDEPTH' declared inside compilation unit '$unit_fifo_define_v' shall be treated as localparam("fifo_parameter.v":1)
+WARN  (EX2582) : Parameter 'WDSIZE' declared inside compilation unit '$unit_fifo_define_v' shall be treated as localparam("fifo_parameter.v":2)
+WARN  (EX2582) : Parameter 'RDEPTH' declared inside compilation unit '$unit_fifo_define_v' shall be treated as localparam("fifo_parameter.v":3)
+WARN  (EX2582) : Parameter 'RDSIZE' declared inside compilation unit '$unit_fifo_define_v' shall be treated as localparam("fifo_parameter.v":4)
+WARN  (EX2582) : Parameter 'ASIZE' declared inside compilation unit '$unit_fifo_define_v' shall be treated as localparam("fifo_parameter.v":5)
+WARN  (EX2582) : Parameter 'RASIZE' declared inside compilation unit '$unit_fifo_define_v' shall be treated as localparam("fifo_parameter.v":6)
+Compiling module 'FifoMax2870'("C:\Gowin\Gowin_V1.9.9.01_x64\IDE\ipcore\FIFO\data\fifo_top.v":3)
+Compiling module '**'("C:\Gowin\Gowin_V1.9.9.01_x64\IDE\ipcore\FIFO\data\fifo.v":553)
+Extracting RAM for identifier '**'("C:\Gowin\Gowin_V1.9.9.01_x64\IDE\ipcore\FIFO\data\fifo.v":553)
+NOTE  (EX0101) : Current top module is "FifoMax2870"
+[5%] Running netlist conversion ...
+Running device independent optimization ...
+[10%] Optimizing Phase 0 completed
+[15%] Optimizing Phase 1 completed
+[25%] Optimizing Phase 2 completed
+Running inference ...
+[30%] Inferring Phase 0 completed
+[40%] Inferring Phase 1 completed
+[50%] Inferring Phase 2 completed
+[55%] Inferring Phase 3 completed
+Running technical mapping ...
+[60%] Tech-Mapping Phase 0 completed
+[65%] Tech-Mapping Phase 1 completed
+[75%] Tech-Mapping Phase 2 completed
+[80%] Tech-Mapping Phase 3 completed
+[90%] Tech-Mapping Phase 4 completed
+[95%] Generate netlist file "C:\Users\AnatoliyChigirinskiy\Documents\RF_FPGA\src\fifo_top\MAX2870FIFO\temp\FIFO\FifoMax2870.vg" completed
+Generate template file "C:\Users\AnatoliyChigirinskiy\Documents\RF_FPGA\src\fifo_top\MAX2870FIFO\temp\FIFO\FifoMax2870_tmp.v" completed
+[100%] Generate report file "C:\Users\AnatoliyChigirinskiy\Documents\RF_FPGA\src\fifo_top\MAX2870FIFO\temp\FIFO\FifoMax2870_syn.rpt.html" completed
+GowinSynthesis finish

src/src/fifo_top/MAX2870FIFO/temp/FIFO/FifoMax2870.vg

@@ -0,0 +1,420 @@
+//
+//Written by GowinSynthesis
+//Tool Version "V1.9.9.01 (64-bit)"
+//Tue Feb 27 10:41:13 2024
+
+//Source file index table:
+//file0 "\C:/Users/AnatoliyChigirinskiy/Documents/RF_FPGA/src/fifo_top/MAX2870FIFO/temp/FIFO/fifo_define.v"
+//file1 "\C:/Users/AnatoliyChigirinskiy/Documents/RF_FPGA/src/fifo_top/MAX2870FIFO/temp/FIFO/fifo_parameter.v"
+//file2 "\C:/Gowin/Gowin_V1.9.9.01_x64/IDE/ipcore/FIFO/data/edc.v"
+//file3 "\C:/Gowin/Gowin_V1.9.9.01_x64/IDE/ipcore/FIFO/data/fifo.v"
+//file4 "\C:/Gowin/Gowin_V1.9.9.01_x64/IDE/ipcore/FIFO/data/fifo_top.v"
+`timescale 100 ps/100 ps
+`pragma protect begin_protected
+`pragma protect version="2.3"
+`pragma protect author="default"
+`pragma protect author_info="default"
+`pragma protect encrypt_agent="GOWIN"
+`pragma protect encrypt_agent_info="GOWIN Encrypt Version 2.3"
+
+`pragma protect encoding=(enctype="base64", line_length=76, bytes=256)
+`pragma protect key_keyowner="GOWIN",key_keyname="GWK2023-09",key_method="rsa"
+`pragma protect key_block
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+DeOSOzCqv41W9K4jf+PUOWhiaMnOGOLUBEm5rg==
+
+`pragma protect encoding=(enctype="base64", line_length=76, bytes=19456)
+`pragma protect data_keyowner="default-ip-vendor"
+`pragma protect data_keyname="default-ip-key"
+`pragma protect data_method="aes128-cfb"
+`pragma protect data_block
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+60edcBa/NUESGQ36yqLLJHPE7Q==
+`pragma protect end_protected
+module FifoMax2870 (
+  Data,
+  Reset,
+  WrClk,
+  RdClk,
+  WrEn,
+  RdEn,
+  Q,
+  Empty,
+  Full
+)
+;
+input [47:0] Data;
+input Reset;
+input WrClk;
+input RdClk;
+input WrEn;
+input RdEn;
+output [47:0] Q;
+output Empty;
+output Full;
+wire VCC;
+wire GND;
+  \~fifo.FifoMax2870  fifo_inst (
+    .Reset(Reset),
+    .RdClk(RdClk),
+    .WrClk(WrClk),
+    .WrEn(WrEn),
+    .RdEn(RdEn),
+    .Data(Data[47:0]),
+    .Empty(Empty),
+    .Full(Full),
+    .Q(Q[47:0])
+);
+  VCC VCC_cZ (
+    .V(VCC)
+);
+  GND GND_cZ (
+    .G(GND)
+);
+  GSR GSR (
+    .GSRI(VCC) 
+);
+endmodule /* FifoMax2870 */

src/src/fifo_top/MAX2870FIFO/temp/FIFO/FifoMax2870_syn_resource.html

@@ -0,0 +1,44 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html>
+<head>
+<title>Hierarchy Module Resource</title>
+<style type="text/css">
+body { font-family: Verdana, Arial, sans-serif; font-size: 14px; }
+div#main_wrapper{ width: 100%; }
+h1 {text-align: center; }
+h1 {margin-top: 36px; }
+table, th, td { border: 1px solid #aaa; }
+table { border-collapse:collapse; margin-top: 10px; margin-bottom: 20px; width: 100%; }
+th, td { align = "center"; padding: 5px 2px 5px 5px; }
+th { color: #fff; font-weight: bold; background-color: #0084ff; }
+table td.label { width: 20%; white-space: nowrap; min-width: 20px; background-color: #dee8f4; }
+</style>
+</head>
+<body>
+<div id="main_wrapper">
+<div id="content">
+<h1>Hierarchy Module Resource</h1>
+<table>
+<tr>
+<th class="label">MODULE NAME</th>
+<th class="label">REG NUMBER</th>
+<th class="label">ALU NUMBER</th>
+<th class="label">LUT NUMBER</th>
+<th class="label">DSP NUMBER</th>
+<th class="label">BSRAM NUMBER</th>
+<th class="label">SSRAM NUMBER</th>
+</tr>
+<tr>
+<td class="label">FifoMax2870 (C:/Gowin/Gowin_V1.9.9.01_x64/IDE/ipcore/FIFO/data/fifo_top.v)</td>
+<td align = "center">84</td>
+<td align = "center">4</td>
+<td align = "center">27</td>
+<td align = "center">-</td>
+<td align = "center">-</td>
+<td align = "center">12</td>
+</tr>
+</table>
+</div><!-- content -->
+</div><!-- main_wrapper -->
+</body>
+</html>

src/src/fifo_top/MAX2870FIFO/temp/FIFO/FifoMax2870_syn_rsc.xml

@@ -0,0 +1,2 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<Module name="FifoMax2870" Register="84" Alu="4" Lut="27" Ssram="12" T_Register="84(84)" T_Alu="4(4)" T_Lut="27(27)" T_Ssram="12(12)"/>

src/src/fifo_top/MAX2870FIFO/temp/FIFO/FifoMax2870_tmp.v

@@ -0,0 +1,25 @@
+//Copyright (C)2014-2024 Gowin Semiconductor Corporation.
+//All rights reserved.
+//File Title: Template file for instantiation
+//Tool Version: V1.9.9.01 (64-bit)
+//Part Number: GW2A-LV55PG484C8/I7
+//Device: GW2A-55
+//Device Version: C
+//Created Time: Tue Feb 27 10:41:13 2024
+
+//Change the instance name and port connections to the signal names
+//--------Copy here to design--------
+
+	FifoMax2870 your_instance_name(
+		.Data(Data_i), //input [47:0] Data
+		.Reset(Reset_i), //input Reset
+		.WrClk(WrClk_i), //input WrClk
+		.RdClk(RdClk_i), //input RdClk
+		.WrEn(WrEn_i), //input WrEn
+		.RdEn(RdEn_i), //input RdEn
+		.Q(Q_o), //output [47:0] Q
+		.Empty(Empty_o), //output Empty
+		.Full(Full_o) //output Full
+	);
+
+//--------Copy end-------------------

src/src/fifo_top/MAX2870FIFO/temp/FIFO/fifo_define.v

@@ -0,0 +1,6 @@
+`define module_name FifoMax2870
+`define getname(oriName,tmodule_name) \~oriName.tmodule_name 
+`define DSR_BASED
+`define FWFT
+`define En_Reset
+`define Reset_Synchronization

src/src/fifo_top/MAX2870FIFO/temp/FIFO/fifo_parameter.v

@@ -0,0 +1,6 @@
+parameter WDEPTH = 8;
+parameter WDSIZE = 48;
+parameter RDEPTH = 8;
+parameter RDSIZE = 48;
+parameter ASIZE = 3;
+parameter RASIZE = 3;

src/src/fifo_top/MAX2870FIFO/temp/FIFO/project.ini

@@ -0,0 +1 @@
+RESOURCE_CHECK=false

src/src/fifo_top/temp/FIFO/FIFO.prj

@@ -0,0 +1,22 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!DOCTYPE gowin-synthesis-project>
+<Project>
+    <Version>beta</Version>
+    <Device id="GW1N-9C" package="PBGA256" speed="6" partNumber="GW1N-LV9PG256C6/I5"/>
+    <FileList>
+        <File path="C:/RF_FPGA/src/src/fifo_top/temp/FIFO/fifo_define.v" type="verilog"/>
+        <File path="C:/RF_FPGA/src/src/fifo_top/temp/FIFO/fifo_parameter.v" type="verilog"/>
+        <File path="C:/Gowin/Gowin_V1.9.9.01_x64/IDE/ipcore/FIFO/data/edc.v" type="verilog"/>
+        <File path="C:/Gowin/Gowin_V1.9.9.01_x64/IDE/ipcore/FIFO/data/fifo.v" type="verilog"/>
+        <File path="C:/Gowin/Gowin_V1.9.9.01_x64/IDE/ipcore/FIFO/data/fifo_top.v" type="verilog"/>
+    </FileList>
+    <OptionList>
+        <Option type="disable_insert_pad" value="1"/>
+        <Option type="include_path" value="C:/RF_FPGA/src/src/fifo_top/temp/FIFO"/>
+        <Option type="output_file" value="FifoRxRF.vg"/>
+        <Option type="output_template" value="FifoRxRF_tmp.v"/>
+        <Option type="ram_balance" value="1"/>
+        <Option type="ram_rw_check" value="1"/>
+        <Option type="verilog_language" value="sysv-2017"/>
+    </OptionList>
+</Project>

src/src/fifo_top/temp/FIFO/FifoRxRF.log

@@ -0,0 +1,46 @@
+GowinSynthesis start
+Running parser ...
+Analyzing Verilog file 'C:\RF_FPGA\src\src\fifo_top\temp\FIFO\fifo_define.v'
+Analyzing Verilog file 'C:\RF_FPGA\src\src\fifo_top\temp\FIFO\fifo_parameter.v'
+Analyzing Verilog file 'C:\Gowin\Gowin_V1.9.9.01_x64\IDE\ipcore\FIFO\data\edc.v'
+Analyzing included file '**'("C:\Gowin\Gowin_V1.9.9.01_x64\IDE\ipcore\FIFO\data\edc.v":14373)
+Back to file '**'("C:\Gowin\Gowin_V1.9.9.01_x64\IDE\ipcore\FIFO\data\edc.v":14373)
+Undeclared symbol '**', assumed default net type '**'("C:\Gowin\Gowin_V1.9.9.01_x64\IDE\ipcore\FIFO\data\edc.v":14373)
+Analyzing Verilog file 'C:\Gowin\Gowin_V1.9.9.01_x64\IDE\ipcore\FIFO\data\fifo.v'
+Analyzing included file '**'("C:\Gowin\Gowin_V1.9.9.01_x64\IDE\ipcore\FIFO\data\fifo.v":553)
+Back to file '**'("C:\Gowin\Gowin_V1.9.9.01_x64\IDE\ipcore\FIFO\data\fifo.v":553)
+Analyzing Verilog file 'C:\Gowin\Gowin_V1.9.9.01_x64\IDE\ipcore\FIFO\data\fifo_top.v'
+Analyzing included file 'fifo_define.v'("C:\Gowin\Gowin_V1.9.9.01_x64\IDE\ipcore\FIFO\data\fifo_top.v":1)
+Back to file 'C:\Gowin\Gowin_V1.9.9.01_x64\IDE\ipcore\FIFO\data\fifo_top.v'("C:\Gowin\Gowin_V1.9.9.01_x64\IDE\ipcore\FIFO\data\fifo_top.v":1)
+Analyzing included file 'fifo_parameter.v'("C:\Gowin\Gowin_V1.9.9.01_x64\IDE\ipcore\FIFO\data\fifo_top.v":56)
+Back to file 'C:\Gowin\Gowin_V1.9.9.01_x64\IDE\ipcore\FIFO\data\fifo_top.v'("C:\Gowin\Gowin_V1.9.9.01_x64\IDE\ipcore\FIFO\data\fifo_top.v":56)
+WARN  (EX2582) : Parameter 'WDEPTH' declared inside compilation unit '$unit_fifo_define_v' shall be treated as localparam("fifo_parameter.v":1)
+WARN  (EX2582) : Parameter 'WDSIZE' declared inside compilation unit '$unit_fifo_define_v' shall be treated as localparam("fifo_parameter.v":2)
+WARN  (EX2582) : Parameter 'RDEPTH' declared inside compilation unit '$unit_fifo_define_v' shall be treated as localparam("fifo_parameter.v":3)
+WARN  (EX2582) : Parameter 'RDSIZE' declared inside compilation unit '$unit_fifo_define_v' shall be treated as localparam("fifo_parameter.v":4)
+WARN  (EX2582) : Parameter 'ASIZE' declared inside compilation unit '$unit_fifo_define_v' shall be treated as localparam("fifo_parameter.v":5)
+WARN  (EX2582) : Parameter 'RASIZE' declared inside compilation unit '$unit_fifo_define_v' shall be treated as localparam("fifo_parameter.v":6)
+Compiling module 'FifoRxRF'("C:\Gowin\Gowin_V1.9.9.01_x64\IDE\ipcore\FIFO\data\fifo_top.v":3)
+Compiling module '**'("C:\Gowin\Gowin_V1.9.9.01_x64\IDE\ipcore\FIFO\data\fifo.v":553)
+Extracting RAM for identifier '**'("C:\Gowin\Gowin_V1.9.9.01_x64\IDE\ipcore\FIFO\data\fifo.v":553)
+NOTE  (EX0101) : Current top module is "FifoRxRF"
+[5%] Running netlist conversion ...
+Running device independent optimization ...
+[10%] Optimizing Phase 0 completed
+[15%] Optimizing Phase 1 completed
+[25%] Optimizing Phase 2 completed
+Running inference ...
+[30%] Inferring Phase 0 completed
+[40%] Inferring Phase 1 completed
+[50%] Inferring Phase 2 completed
+[55%] Inferring Phase 3 completed
+Running technical mapping ...
+[60%] Tech-Mapping Phase 0 completed
+[65%] Tech-Mapping Phase 1 completed
+[75%] Tech-Mapping Phase 2 completed
+[80%] Tech-Mapping Phase 3 completed
+[90%] Tech-Mapping Phase 4 completed
+[95%] Generate netlist file "C:\RF_FPGA\src\src\fifo_top\temp\FIFO\FifoRxRF.vg" completed
+Generate template file "C:\RF_FPGA\src\src\fifo_top\temp\FIFO\FifoRxRF_tmp.v" completed
+[100%] Generate report file "C:\RF_FPGA\src\src\fifo_top\temp\FIFO\FifoRxRF_syn.rpt.html" completed
+GowinSynthesis finish

src/src/fifo_top/temp/FIFO/FifoRxRF_syn_resource.html

@@ -0,0 +1,44 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html>
+<head>
+<title>Hierarchy Module Resource</title>
+<style type="text/css">
+body { font-family: Verdana, Arial, sans-serif; font-size: 14px; }
+div#main_wrapper{ width: 100%; }
+h1 {text-align: center; }
+h1 {margin-top: 36px; }
+table, th, td { border: 1px solid #aaa; }
+table { border-collapse:collapse; margin-top: 10px; margin-bottom: 20px; width: 100%; }
+th, td { align = "center"; padding: 5px 2px 5px 5px; }
+th { color: #fff; font-weight: bold; background-color: #0084ff; }
+table td.label { width: 20%; white-space: nowrap; min-width: 20px; background-color: #dee8f4; }
+</style>
+</head>
+<body>
+<div id="main_wrapper">
+<div id="content">
+<h1>Hierarchy Module Resource</h1>
+<table>
+<tr>
+<th class="label">MODULE NAME</th>
+<th class="label">REG NUMBER</th>
+<th class="label">ALU NUMBER</th>
+<th class="label">LUT NUMBER</th>
+<th class="label">DSP NUMBER</th>
+<th class="label">BSRAM NUMBER</th>
+<th class="label">SSRAM NUMBER</th>
+</tr>
+<tr>
+<td class="label">FifoRxRF (C:/Gowin/Gowin_V1.9.9.01_x64/IDE/ipcore/FIFO/data/fifo_top.v)</td>
+<td align = "center">98</td>
+<td align = "center">21</td>
+<td align = "center">110</td>
+<td align = "center">-</td>
+<td align = "center">-</td>
+<td align = "center">24</td>
+</tr>
+</table>
+</div><!-- content -->
+</div><!-- main_wrapper -->
+</body>
+</html>

src/src/fifo_top/temp/FIFO/FifoRxRF_syn_rsc.xml

@@ -0,0 +1,2 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<Module name="FifoRxRF" Register="98" Alu="21" Lut="110" Ssram="24" T_Register="98(98)" T_Alu="21(21)" T_Lut="110(110)" T_Ssram="24(24)"/>

src/src/fifo_top/temp/FIFO/FifoRxRF_tmp.v

@@ -0,0 +1,27 @@
+//Copyright (C)2014-2024 Gowin Semiconductor Corporation.
+//All rights reserved.
+//File Title: Template file for instantiation
+//Tool Version: V1.9.9.01 (64-bit)
+//Part Number: GW1N-LV9PG256C6/I5
+//Device: GW1N-9
+//Device Version: C
+//Created Time: Thu Mar 21 09:39:05 2024
+
+//Change the instance name and port connections to the signal names
+//--------Copy here to design--------
+
+	FifoRxRF your_instance_name(
+		.Data(Data_i), //input [23:0] Data
+		.Reset(Reset_i), //input Reset
+		.WrClk(WrClk_i), //input WrClk
+		.RdClk(RdClk_i), //input RdClk
+		.WrEn(WrEn_i), //input WrEn
+		.RdEn(RdEn_i), //input RdEn
+		.Wnum(Wnum_o), //output [6:0] Wnum
+		.Rnum(Rnum_o), //output [6:0] Rnum
+		.Q(Q_o), //output [23:0] Q
+		.Empty(Empty_o), //output Empty
+		.Full(Full_o) //output Full
+	);
+
+//--------Copy end-------------------

src/src/fifo_top/temp/FIFO/fifo_define.v

@@ -0,0 +1,8 @@
+`define module_name FifoRxRF
+`define getname(oriName,tmodule_name) \~oriName.tmodule_name 
+`define DSR_BASED
+`define FWFT
+`define Count_W
+`define Count_R
+`define En_Reset
+`define Reset_Synchronization

src/src/fifo_top/temp/FIFO/fifo_parameter.v

@@ -0,0 +1,6 @@
+parameter WDEPTH = 64;
+parameter WDSIZE = 24;
+parameter RDEPTH = 64;
+parameter RDSIZE = 24;
+parameter ASIZE = 6;
+parameter RASIZE = 6;

src/src/fifo_top/temp/FIFO/project.ini

@@ -0,0 +1 @@
+RESOURCE_CHECK=false

src/src/gClkGen/gClkGen.ipc

@@ -0,0 +1,24 @@
+[General]
+ipc_version=4
+file=gClkGen
+module=gClkGen
+target_device=gw2a55c-005
+type=clock_rpll
+version=1.0
+
+[Config]
+CKLOUTD3=false
+CLKFB_SOURCE=0
+CLKIN_FREQ=50
+CLKOUTD=false
+CLKOUTP=false
+CLKOUT_BYPASS=false
+CLKOUT_DIVIDE_DYN=true
+CLKOUT_FREQ=100
+CLKOUT_TOLERANCE=0
+DYNAMIC=true
+LANG=0
+LOCK_EN=true
+MODE_GENERAL=true
+PLL_PWD=false
+RESET_PLL=false

src/src/gClkGen/gClkGen.mod

@@ -0,0 +1,33 @@
+-series GW2A
+-device GW2A-55
+-device_version C
+-package PBGA484
+-part_number GW2A-LV55PG484C8/I7
+
+
+-mod_name gClkGen
+-file_name gClkGen
+-path C:/Users/AnatoliyChigirinskiy/Documents/RF_FPGA/src/gClkGen/
+-type PLL
+-rPll true
+-file_type vlg
+-dev_type GW2A-55C
+-dyn_idiv_sel false
+-idiv_sel 1
+-dyn_fbdiv_sel false
+-fbdiv_sel 2
+-dyn_odiv_sel false
+-odiv_sel 8
+-dyn_da_en true
+-rst_sig false
+-rst_sig_p false
+-fclkin 50
+-clkfb_sel 0
+-en_lock true
+-clkout_bypass false
+-clkout_ft_dir 1
+-en_clkoutp false
+-clkoutp_bypass false
+-en_clkoutd false
+-clkoutd_bypass false
+-en_clkoutd3 false

src/src/gClkGen/gClkGen.v

@@ -0,0 +1,64 @@
+//Copyright (C)2014-2023 Gowin Semiconductor Corporation.
+//All rights reserved.
+//File Title: IP file
+//GOWIN Version: V1.9.9 Beta
+//Part Number: GW2A-LV55PG484C8/I7
+//Device: GW2A-55
+//Device Version: C
+//Created Time: Mon Feb 12 15:09:09 2024
+
+module gClkGen (clkout, lock, clkin);
+
+output clkout;
+output lock;
+input clkin;
+
+wire clkoutp_o;
+wire clkoutd_o;
+wire clkoutd3_o;
+wire gw_gnd;
+
+assign gw_gnd = 1'b0;
+
+rPLL rpll_inst (
+    .CLKOUT(clkout),
+    .LOCK(lock),
+    .CLKOUTP(clkoutp_o),
+    .CLKOUTD(clkoutd_o),
+    .CLKOUTD3(clkoutd3_o),
+    .RESET(gw_gnd),
+    .RESET_P(gw_gnd),
+    .CLKIN(clkin),
+    .CLKFB(gw_gnd),
+    .FBDSEL({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd}),
+    .IDSEL({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd}),
+    .ODSEL({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd}),
+    .PSDA({gw_gnd,gw_gnd,gw_gnd,gw_gnd}),
+    .DUTYDA({gw_gnd,gw_gnd,gw_gnd,gw_gnd}),
+    .FDLY({gw_gnd,gw_gnd,gw_gnd,gw_gnd})
+);
+
+defparam rpll_inst.FCLKIN = "50";
+defparam rpll_inst.DYN_IDIV_SEL = "false";
+defparam rpll_inst.IDIV_SEL = 0;
+defparam rpll_inst.DYN_FBDIV_SEL = "false";
+defparam rpll_inst.FBDIV_SEL = 1;
+defparam rpll_inst.DYN_ODIV_SEL = "false";
+defparam rpll_inst.ODIV_SEL = 8;
+defparam rpll_inst.PSDA_SEL = "0000";
+defparam rpll_inst.DYN_DA_EN = "true";
+defparam rpll_inst.DUTYDA_SEL = "1000";
+defparam rpll_inst.CLKOUT_FT_DIR = 1'b1;
+defparam rpll_inst.CLKOUTP_FT_DIR = 1'b1;
+defparam rpll_inst.CLKOUT_DLY_STEP = 0;
+defparam rpll_inst.CLKOUTP_DLY_STEP = 0;
+defparam rpll_inst.CLKFB_SEL = "internal";
+defparam rpll_inst.CLKOUT_BYPASS = "false";
+defparam rpll_inst.CLKOUTP_BYPASS = "false";
+defparam rpll_inst.CLKOUTD_BYPASS = "false";
+defparam rpll_inst.DYN_SDIV_SEL = 2;
+defparam rpll_inst.CLKOUTD_SRC = "CLKOUT";
+defparam rpll_inst.CLKOUTD3_SRC = "CLKOUT";
+defparam rpll_inst.DEVICE = "GW2A-55C";
+
+endmodule //gClkGen

src/src/gClkGen/gClkGen_tmp.v

@@ -0,0 +1,19 @@
+//Copyright (C)2014-2023 Gowin Semiconductor Corporation.
+//All rights reserved.
+//File Title: Template file for instantiation
+//GOWIN Version: V1.9.9 Beta
+//Part Number: GW2A-LV55PG484C8/I7
+//Device: GW2A-55
+//Device Version: C
+//Created Time: Mon Feb 12 15:09:09 2024
+
+//Change the instance name and port connections to the signal names
+//--------Copy here to design--------
+
+    gClkGen your_instance_name(
+        .clkout(clkout_o), //output clkout
+        .lock(lock_o), //output lock
+        .clkin(clkin_i) //input clkin
+    );
+
+//--------Copy end-------------------

src/src/gowin_rpll/ClkGen.ipc

@@ -0,0 +1,28 @@
+[General]
+ipc_version=4
+file=ClkGen
+module=ClkGen
+target_device=gw2a55c-005
+type=clock_rpll
+version=1.0
+
+[Config]
+CKLOUTD3=false
+CLKFB_SOURCE=0
+CLKIN_FREQ=50
+CLKOUTD=true
+CLKOUTP=false
+CLKOUT_BYPASS=false
+CLKOUT_DIVIDE_DYN=true
+CLKOUT_FREQ=360
+CLKOUT_TOLERANCE=0
+DYNAMIC=true
+LANG=0
+LOCK_EN=false
+MODE_GENERAL=true
+PLL_PWD=false
+RESET_PLL=false
+CLKOUTD_BYPASS=false
+CLKOUTD_FREQ=20
+CLKOUTD_SOURCE_CLKOUT=true
+CLKOUTD_TOLERANCE=0

src/src/gowin_rpll/ClkGen.mod

@@ -0,0 +1,35 @@
+-series GW2A
+-device GW2A-55
+-device_version C
+-package PBGA484
+-part_number GW2A-LV55PG484C8/I7
+
+
+-mod_name ClkGen
+-file_name ClkGen
+-path C:/Users/AnatoliyChigirinskiy/Documents/RF_FPGA/src/gowin_rpll/
+-type PLL
+-rPll true
+-file_type vlg
+-dev_type GW2A-55C
+-dyn_idiv_sel false
+-idiv_sel 5
+-dyn_fbdiv_sel false
+-fbdiv_sel 36
+-dyn_odiv_sel false
+-odiv_sel 2
+-dyn_sdiv_sel 18
+-dyn_da_en true
+-rst_sig false
+-rst_sig_p false
+-fclkin 50
+-clkfb_sel 0
+-en_lock false
+-clkout_bypass false
+-clkout_ft_dir 1
+-en_clkoutp false
+-clkoutp_bypass false
+-en_clkoutd true
+-clkoutd_bypass false
+-clkoutd_src CLKOUT
+-en_clkoutd3 false

src/src/gowin_rpll/ClkGen_tmp.v

@@ -0,0 +1,19 @@
+//Copyright (C)2014-2024 Gowin Semiconductor Corporation.
+//All rights reserved.
+//File Title: Template file for instantiation
+//Tool Version: V1.9.9.01 (64-bit)
+//Part Number: GW2A-LV55PG484C8/I7
+//Device: GW2A-55
+//Device Version: C
+//Created Time: Tue Feb 27 10:16:13 2024
+
+//Change the instance name and port connections to the signal names
+//--------Copy here to design--------
+
+    ClkGen your_instance_name(
+        .clkout(clkout_o), //output clkout
+        .clkoutd(clkoutd_o), //output clkoutd
+        .clkin(clkin_i) //input clkin
+    );
+
+//--------Copy end-------------------

src/src/gowin_rpll/gClkGen.ipc

@@ -0,0 +1,28 @@
+[General]
+ipc_version=4
+file=gClkGen
+module=gClkGen
+target_device=gw1n9c-046
+type=clock_rpll
+version=1.0
+
+[Config]
+CKLOUTD3=false
+CLKFB_SOURCE=0
+CLKIN_FREQ=24
+CLKOUTD=true
+CLKOUTD_BYPASS=false
+CLKOUTD_FREQ=5
+CLKOUTD_SOURCE_CLKOUT=true
+CLKOUTD_TOLERANCE=0
+CLKOUTP=false
+CLKOUT_BYPASS=false
+CLKOUT_DIVIDE_DYN=true
+CLKOUT_FREQ=100
+CLKOUT_TOLERANCE=0
+DYNAMIC=true
+LANG=0
+LOCK_EN=true
+MODE_GENERAL=true
+PLL_PWD=false
+RESET_PLL=false

src/src/gowin_rpll/gClkGen.mod

@@ -0,0 +1,35 @@
+-series GW1N
+-device GW1N-9
+-device_version C
+-package PBGA256
+-part_number GW1N-LV9PG256C6/I5
+
+
+-mod_name gClkGen
+-file_name gClkGen
+-path C:/RF_FPGA/src/src/gowin_rpll/
+-type PLL
+-rPll true
+-file_type vlg
+-dev_type GW1N-9C
+-dyn_idiv_sel false
+-idiv_sel 6
+-dyn_fbdiv_sel false
+-fbdiv_sel 25
+-dyn_odiv_sel false
+-odiv_sel 4
+-dyn_sdiv_sel 20
+-dyn_da_en true
+-rst_sig false
+-rst_sig_p false
+-fclkin 24
+-clkfb_sel 0
+-en_lock true
+-clkout_bypass false
+-clkout_ft_dir 1
+-en_clkoutp false
+-clkoutp_bypass false
+-en_clkoutd true
+-clkoutd_bypass false
+-clkoutd_src CLKOUT
+-en_clkoutd3 false

src/src/gowin_rpll/gClkGen.v

@@ -0,0 +1,64 @@
+//Copyright (C)2014-2024 Gowin Semiconductor Corporation.
+//All rights reserved.
+//File Title: IP file
+//Tool Version: V1.9.9.01 (64-bit)
+//Part Number: GW1N-LV9PG256C6/I5
+//Device: GW1N-9
+//Device Version: C
+//Created Time: Wed Mar  6 11:33:52 2024
+
+module gClkGen (clkout, lock, clkoutd, clkin);
+
+output clkout;
+output lock;
+output clkoutd;
+input clkin;
+
+wire clkoutp_o;
+wire clkoutd3_o;
+wire gw_gnd;
+
+assign gw_gnd = 1'b0;
+
+rPLL rpll_inst (
+    .CLKOUT(clkout),
+    .LOCK(lock),
+    .CLKOUTP(clkoutp_o),
+    .CLKOUTD(clkoutd),
+    .CLKOUTD3(clkoutd3_o),
+    .RESET(gw_gnd),
+    .RESET_P(gw_gnd),
+    .CLKIN(clkin),
+    .CLKFB(gw_gnd),
+    .FBDSEL({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd}),
+    .IDSEL({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd}),
+    .ODSEL({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd}),
+    .PSDA({gw_gnd,gw_gnd,gw_gnd,gw_gnd}),
+    .DUTYDA({gw_gnd,gw_gnd,gw_gnd,gw_gnd}),
+    .FDLY({gw_gnd,gw_gnd,gw_gnd,gw_gnd})
+);
+
+defparam rpll_inst.FCLKIN = "24";
+defparam rpll_inst.DYN_IDIV_SEL = "false";
+defparam rpll_inst.IDIV_SEL = 5;
+defparam rpll_inst.DYN_FBDIV_SEL = "false";
+defparam rpll_inst.FBDIV_SEL = 24;
+defparam rpll_inst.DYN_ODIV_SEL = "false";
+defparam rpll_inst.ODIV_SEL = 4;
+defparam rpll_inst.PSDA_SEL = "0000";
+defparam rpll_inst.DYN_DA_EN = "true";
+defparam rpll_inst.DUTYDA_SEL = "1000";
+defparam rpll_inst.CLKOUT_FT_DIR = 1'b1;
+defparam rpll_inst.CLKOUTP_FT_DIR = 1'b1;
+defparam rpll_inst.CLKOUT_DLY_STEP = 0;
+defparam rpll_inst.CLKOUTP_DLY_STEP = 0;
+defparam rpll_inst.CLKFB_SEL = "internal";
+defparam rpll_inst.CLKOUT_BYPASS = "false";
+defparam rpll_inst.CLKOUTP_BYPASS = "false";
+defparam rpll_inst.CLKOUTD_BYPASS = "false";
+defparam rpll_inst.DYN_SDIV_SEL = 20;
+defparam rpll_inst.CLKOUTD_SRC = "CLKOUT";
+defparam rpll_inst.CLKOUTD3_SRC = "CLKOUT";
+defparam rpll_inst.DEVICE = "GW1N-9C";
+
+endmodule //gClkGen

src/src/gowin_rpll/gClkGen_tmp.v

@@ -0,0 +1,20 @@
+//Copyright (C)2014-2024 Gowin Semiconductor Corporation.
+//All rights reserved.
+//File Title: Template file for instantiation
+//Tool Version: V1.9.9.01 (64-bit)
+//Part Number: GW1N-LV9PG256C6/I5
+//Device: GW1N-9
+//Device Version: C
+//Created Time: Wed Mar  6 11:33:52 2024
+
+//Change the instance name and port connections to the signal names
+//--------Copy here to design--------
+
+    gClkGen your_instance_name(
+        .clkout(clkout_o), //output clkout
+        .lock(lock_o), //output lock
+        .clkoutd(clkoutd_o), //output clkoutd
+        .clkin(clkin_i) //input clkin
+    );
+
+//--------Copy end-------------------

src/src/gowin_rpll/gowin_rpll/ClkGen.ipc

@@ -0,0 +1,28 @@
+[General]
+ipc_version=4
+file=ClkGen
+module=ClkGen
+target_device=gw1n9c-046
+type=clock_rpll
+version=1.0
+
+[Config]
+CKLOUTD3=false
+CLKFB_SOURCE=0
+CLKIN_FREQ=24
+CLKOUTD=true
+CLKOUTD_BYPASS=false
+CLKOUTD_FREQ=20
+CLKOUTD_SOURCE_CLKOUT=true
+CLKOUTD_TOLERANCE=0
+CLKOUTP=false
+CLKOUT_BYPASS=false
+CLKOUT_DIVIDE_DYN=true
+CLKOUT_FREQ=360
+CLKOUT_TOLERANCE=0
+DYNAMIC=true
+LANG=0
+LOCK_EN=false
+MODE_GENERAL=true
+PLL_PWD=false
+RESET_PLL=false

src/src/gowin_rpll/gowin_rpll/ClkGen.mod

@@ -0,0 +1,35 @@
+-series GW1N
+-device GW1N-9
+-device_version C
+-package PBGA256
+-part_number GW1N-LV9PG256C6/I5
+
+
+-mod_name ClkGen
+-file_name ClkGen
+-path C:/RF_FPGA/src/src/gowin_rpll/gowin_rpll/
+-type PLL
+-rPll true
+-file_type vlg
+-dev_type GW1N-9C
+-dyn_idiv_sel false
+-idiv_sel 1
+-dyn_fbdiv_sel false
+-fbdiv_sel 15
+-dyn_odiv_sel false
+-odiv_sel 2
+-dyn_sdiv_sel 18
+-dyn_da_en true
+-rst_sig false
+-rst_sig_p false
+-fclkin 24
+-clkfb_sel 0
+-en_lock false
+-clkout_bypass false
+-clkout_ft_dir 1
+-en_clkoutp false
+-clkoutp_bypass false
+-en_clkoutd true
+-clkoutd_bypass false
+-clkoutd_src CLKOUT
+-en_clkoutd3 false

src/src/gowin_rpll/gowin_rpll/ClkGen.v

@@ -0,0 +1,64 @@
+//Copyright (C)2014-2024 Gowin Semiconductor Corporation.
+//All rights reserved.
+//File Title: IP file
+//Tool Version: V1.9.9.01 (64-bit)
+//Part Number: GW1N-LV9PG256C6/I5
+//Device: GW1N-9
+//Device Version: C
+//Created Time: Tue Mar  5 17:30:46 2024
+
+module ClkGen (clkout, clkoutd, clkin);
+
+output clkout;
+output clkoutd;
+input clkin;
+
+wire lock_o;
+wire clkoutp_o;
+wire clkoutd3_o;
+wire gw_gnd;
+
+assign gw_gnd = 1'b0;
+
+rPLL rpll_inst (
+    .CLKOUT(clkout),
+    .LOCK(lock_o),
+    .CLKOUTP(clkoutp_o),
+    .CLKOUTD(clkoutd),
+    .CLKOUTD3(clkoutd3_o),
+    .RESET(gw_gnd),
+    .RESET_P(gw_gnd),
+    .CLKIN(clkin),
+    .CLKFB(gw_gnd),
+    .FBDSEL({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd}),
+    .IDSEL({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd}),
+    .ODSEL({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd}),
+    .PSDA({gw_gnd,gw_gnd,gw_gnd,gw_gnd}),
+    .DUTYDA({gw_gnd,gw_gnd,gw_gnd,gw_gnd}),
+    .FDLY({gw_gnd,gw_gnd,gw_gnd,gw_gnd})
+);
+
+defparam rpll_inst.FCLKIN = "24";
+defparam rpll_inst.DYN_IDIV_SEL = "false";
+defparam rpll_inst.IDIV_SEL = 0;
+defparam rpll_inst.DYN_FBDIV_SEL = "false";
+defparam rpll_inst.FBDIV_SEL = 14;
+defparam rpll_inst.DYN_ODIV_SEL = "false";
+defparam rpll_inst.ODIV_SEL = 2;
+defparam rpll_inst.PSDA_SEL = "0000";
+defparam rpll_inst.DYN_DA_EN = "true";
+defparam rpll_inst.DUTYDA_SEL = "1000";
+defparam rpll_inst.CLKOUT_FT_DIR = 1'b1;
+defparam rpll_inst.CLKOUTP_FT_DIR = 1'b1;
+defparam rpll_inst.CLKOUT_DLY_STEP = 0;
+defparam rpll_inst.CLKOUTP_DLY_STEP = 0;
+defparam rpll_inst.CLKFB_SEL = "internal";
+defparam rpll_inst.CLKOUT_BYPASS = "false";
+defparam rpll_inst.CLKOUTP_BYPASS = "false";
+defparam rpll_inst.CLKOUTD_BYPASS = "false";
+defparam rpll_inst.DYN_SDIV_SEL = 18;
+defparam rpll_inst.CLKOUTD_SRC = "CLKOUT";
+defparam rpll_inst.CLKOUTD3_SRC = "CLKOUT";
+defparam rpll_inst.DEVICE = "GW1N-9C";
+
+endmodule //ClkGen

src/src/gowin_rpll/gowin_rpll/ClkGen_tmp.v

@@ -0,0 +1,19 @@
+//Copyright (C)2014-2024 Gowin Semiconductor Corporation.
+//All rights reserved.
+//File Title: Template file for instantiation
+//Tool Version: V1.9.9.01 (64-bit)
+//Part Number: GW1N-LV9PG256C6/I5
+//Device: GW1N-9
+//Device Version: C
+//Created Time: Tue Mar  5 17:30:46 2024
+
+//Change the instance name and port connections to the signal names
+//--------Copy here to design--------
+
+    ClkGen your_instance_name(
+        .clkout(clkout_o), //output clkout
+        .clkoutd(clkoutd_o), //output clkoutd
+        .clkin(clkin_i) //input clkin
+    );
+
+//--------Copy end-------------------

src/src/initRst/InitRst.v

@@ -0,0 +1,104 @@
+module InitRst (
+    clk_i,
+    signal_o
+);
+
+//================================================================================
+//
+//  FUNCTIONS
+//
+//================================================================================
+
+    function integer bit_num;
+        input integer value;
+        begin
+            bit_num = 0;
+            while (value > 0) begin
+                value   = value >> 1;
+                bit_num = bit_num + 1;
+            end
+        end
+    endfunction
+
+//================================================================================
+//
+//  PARAMETER/LOCALPARAM
+//
+//================================================================================
+
+    parameter   DELAY_VALUE     = 25;
+    localparam  DELAY_CNT_W     = bit_num(DELAY_VALUE);
+
+//================================================================================
+//
+//  PORTS
+//
+//================================================================================
+
+    input           clk_i;
+    output  reg     signal_o;
+
+//================================================================================
+//
+//  STATE MACHINE STATES
+//
+//================================================================================
+
+    localparam      SM_RST_S    = 1'b0;
+    localparam      SM_DONE_S   = 1'b1;
+
+//================================================================================
+//
+//  REG/WIRE
+//
+//================================================================================
+
+    reg                         curr_state  = SM_RST_S;
+    reg     [DELAY_CNT_W-1:0]   delay_cnt   = {DELAY_CNT_W{1'b0}};
+    reg                         delay_flag  = 1'b0;
+
+    reg                         next_state;
+    reg     [DELAY_CNT_W-1:0]   delay_cnt_next	=	{DELAY_CNT_W{1'b0}};
+    reg                         signal_next;
+
+//================================================================================
+//
+//  CODING
+//
+//================================================================================
+
+initial begin
+    curr_state  = SM_RST_S;
+    delay_cnt   = {DELAY_CNT_W{1'b0}};
+    signal_o    = 1'b1;
+    delay_flag  = 1'b0;
+end
+
+always @(posedge clk_i) begin
+    curr_state  <= next_state;
+    delay_cnt   <= delay_cnt_next;
+    signal_o    <= signal_next;
+    delay_flag  <= delay_cnt > (DELAY_VALUE - 1);
+end
+
+always @(*) begin
+    next_state      = SM_RST_S;
+    delay_cnt_next  = delay_cnt;
+    signal_next     = 1'b1;
+    case(curr_state)
+        SM_RST_S    : begin
+            if (delay_flag) begin
+                next_state      = SM_DONE_S;
+            end else begin
+                next_state      = SM_RST_S;
+                delay_cnt_next  = delay_cnt + {{(DELAY_CNT_W-1){1'b0}}, 1'b1};
+            end
+        end
+        SM_DONE_S   : begin
+            signal_next = 1'b0;
+            next_state  = SM_DONE_S;
+        end
+    endcase
+end
+
+endmodule