Изменение скрипта

script/recreate.tcl

@@ -20,8 +20,8 @@ add_file -type verilog "$::DSN_ROOT/SB_TMSG_FPGA/src/src/fifo_top/MAX2870FIFO/fi
 add_file -type verilog "$::DSN_ROOT/SB_TMSG_FPGA/src/src/gowin_rpll/gClkGen.v"
 add_file -type verilog "$::DSN_ROOT/SB_TMSG_FPGA/src/src/gowin_rpll/gowin_rpll/ClkGen.v"
 add_file -type verilog "$::DSN_ROOT/SB_TMSG_FPGA/src/src/initRst/InitRst.v"
-add_file -type cst "$::DSN_ROOT/SB_TMSG_FPGA/src/constr/SB_TMSG_FPGA.cst"
-add_file -type sdc "$::DSN_ROOT/SB_TMSG_FPGA/src/constr/SB_TMSG_FPGA.sdc"
+add_file -type cst "$::DSN_ROOT/SB_TMSG_FPGA/src/constr/RF_FPGA.cst"
+add_file -type sdc "$::DSN_ROOT/SB_TMSG_FPGA/src/constr/RF_FPGA.sdc"