Добавлена задержка для trCnt на 1 такт. Изменён блок для работы с trCnt. Расставлены скобки в выражениях. Модуль FifoCtrl выключен, когда выбран режим 1 SPI.

src/src/Sim/tb_RF_FPGA.v

@@ -54,34 +54,53 @@ module tb_SPIm;
 
     reg modeSel; 
 
-    assign Val_o = (((modeSel)? trCnt : trCntSync) < 2 ) ? valQ:(modeSel) ? valQ:valR;
-    assign Sck_o = (((modeSel)? trCnt : trCntSync)< 2 ) ? SckQ:(modeSel) ? SckQ:SckR;
-    assign Ss_o = (((modeSel)? trCnt : trCntSync)<2) ? SsQ:(modeSel) ? SsQ:SsR;
-    assign Mosi0_o = (((modeSel)? trCnt : trCntSync)< 2 ) ? mosi0Q:(modeSel) ? mosi0Q:mosi0R;
+    // assign Val_o = (((modeSel)? trCnt : trCntSync) < 2 ) ? valQ:(modeSel) ? valQ:valR;
+    // assign Sck_o = (((modeSel)? trCnt : trCntSync)< 2 ) ? SckQ:(modeSel) ? SckQ:SckR;
+    // assign Ss_o = (((modeSel)? trCnt : trCntSync)<2) ? SsQ:(modeSel) ? SsQ:SsR;
+    // assign Mosi0_o = (((modeSel)? trCnt : trCntSync)< 2 ) ? mosi0Q:(modeSel) ? mosi0Q:mosi0R;
+    // assign Mosi1_io = (modeSel) ? Mosi1_o:1'bz;
+
+    assign Val_o = (modeSel) ? valQ:valR;
+    assign Sck_o = (modeSel) ? SckQ:SckR;
+    assign Ss_o = (modeSel) ? SsQ:SsR;
+    assign Mosi0_o = (modeSel) ? mosi0Q:mosi0R;
     assign Mosi1_io = (modeSel) ? Mosi1_o:1'bz;
 
 
-
-    always @(posedge Clk50) begin 
-        if (Rst_i) begin 
-            trCnt <= 5'd0;
-        end
-        else begin 
-            if (trCnt < 2  && trCntSync < 2 && !modeSel) begin
-                if (valQ) begin 
-                    trCnt <= trCnt + 1;
-                end
-            end
-            else if (trCnt < 7 && modeSel) begin 
-                if (valQ) begin 
-                    trCnt <= trCnt + 1;
-                end
-            end
-            else if (trCntSync >= 2 && !modeSel) begin 
-                trCnt <= 5'd0;
-            end
+    assign emptyFlagTx = (!locked) ? 1'b1 : 1'b0;
+
+    // always @(posedge Clk100) begin 
+    //     if (Rst_i) begin 
+    //         trCnt <= 5'd0;
+    //     end
+    //     else begin 
+    //         if (trCnt < 2  && trCntSync < 2 && !modeSel) begin
+    //             if (valQ) begin 
+    //                 trCnt <= trCnt + 1;
+    //             end
+    //         end
+    //         else if (trCnt < 7 && modeSel) begin 
+    //             if (valQ) begin 
+    //                 trCnt <= trCnt + 1;
+    //             end
+    //         end
+    //         else if (trCntSync >= 2 && !modeSel) begin 
+    //             trCnt <= 5'd0;
+    //         end
+    //     end
+    // end
+
+
+always @(posedge Clk20) begin 
+    if (Rst_i) begin 
+        trCnt <= 5'd0;
+    end
+    else begin 
+        if (valR) begin 
+            trCnt <= trCnt + 1;
         end
     end
+end
 
 
 
@@ -123,7 +142,7 @@ module tb_SPIm;
     SPIm_tb SPIm_inst (
         .Clk_i(Clk20), 
         .Rst_i(Rst_i), 
-        .Start_i(start), 
+        .Start_i(Start_i), 
         .ClockPhase_i(CPHA_i), 
         .SpiData_i(SPIdata),
         .SelSt_i(SELST_i),
@@ -146,6 +165,7 @@ module tb_SPIm;
         .Rst_i(Rst_i),
         .Start_i(Start_i),
         .ClockPhase_i(CPHA_i),
+        .EmptyFlag_i(emptyFlagTx),
         .SpiData_i(SPIdata),
         .SpiDataVal_i(SpiDataVal_i),
         .SelSt_i(SELST_i),
@@ -172,6 +192,7 @@ module tb_SPIm;
     RFTop RFTop_inst (
         .Clk_i(Clk24),
         .Sck_i(Sck_o),
+        .Rst_i(Rst_i),
         .Ss_i(Ss_o),
         .Mosi0_i(Mosi0_o),
         .Mosi1_io(Mosi1_o),
@@ -220,69 +241,99 @@ module tb_SPIm;
       
     end
 
-    always @(*) begin
-        if (locked && !rstInit && modeSel)  begin
-            case (trCnt) 
-            0: begin 
-                SPIdata = {8'haa,8'haa,7'haa,1'b0};
-            end
-            1:begin 
-                SPIdata = {1'h0, 7'h2a, 16'd10};
-            end
-            2:begin 
-                SPIdata = {1'h0, 7'h2a, 16'd20};
-            end
-            3:begin 
-                SPIdata = {1'h0, 7'h2a, 16'd30};
-            end
-            4:begin 
-                SPIdata = {1'h0, 7'h2a, 16'd40};
-            end
-            5:begin 
-                SPIdata = {1'h0, 7'h2a, 16'd50};
-            end
-            6:begin 
-                SPIdata = {1'h0, 7'h2a, 16'd60};
-            end
-            7:begin 
-                SPIdata = {1'h0, 7'h2a, 16'd70};
-            end
-        endcase
-        end
-        else if (locked && !rstInit && !modeSel) begin 
-            case (trCnt) 
+    always @(*) begin 
+        if (locked && !rstInit && !modeSel) begin 
+            case(trCnt) 
             0: begin 
-                SPIdata = 24'h555554;
+                SPIdata = {1'h0, 5'h6, 17'h4, 1'h0};
             end
-            1:begin 
-                SPIdata = {1'h0, 7'h2a, 16'd10};
+            1 : begin 
+                SPIdata = 24'h04000;
             end
-        endcase
-        case (trCntSync) 
-           2 : begin 
-            SPIdata = {1'h0, 7'h2a, 16'd20};
+            2: begin 
+                SPIdata = 24'h1c003;
             end
             3 : begin 
-                SPIdata = {1'h0, 7'h2a, 16'd30};
+                SPIdata = 24'h040010;
             end
             4 : begin 
-                SPIdata = {1'h0, 7'h2a, 16'd40};
-            end
-            5 : begin 
-                SPIdata = {1'h0, 7'h2a, 16'd50};
-            end
-            6 : begin 
-                SPIdata = {1'h0, 7'h2a, 16'd60};
+                SPIdata = 24'h1800d;
             end
-            7 : begin 
-                SPIdata = {1'h0, 7'h2a, 16'd70};
+            default : begin 
+                SPIdata = 24'h0;
             end
-        endcase
-        end
-        else begin 
-            SPIdata = 24'h0;
+            endcase
         end
     end
 
 
+
+
+
+    // always @(*) begin
+    //     if (locked && !rstInit && modeSel)  begin
+    //         case (trCnt) 
+    //         0: begin 
+    //             // SPIdata = {8'haa,8'haa,7'haa,1'b0};
+    //             SPIdata = 24'h0;
+    //         end
+    //         1:begin 
+    //             SPIdata = {1'h0, 7'h2a, 16'd10};
+    //         end
+    //         2:begin 
+    //             SPIdata = {1'h1, 7'h2a, 16'd20};
+    //         end
+    //         3:begin 
+    //             SPIdata = {1'h0, 7'h2a, 16'd30};
+    //         end
+    //         4:begin 
+    //             SPIdata = {1'h0, 7'h2a, 16'd40};
+    //         end
+    //         5:begin 
+    //             SPIdata = {1'h0, 7'h2a, 16'd50};
+    //         end
+    //         6:begin 
+    //             SPIdata = {1'h0, 7'h2a, 16'd60};
+    //         end
+    //         7:begin 
+    //             SPIdata = {1'h0, 7'h2a, 16'd70};
+    //         end
+    //     endcase
+    //     end
+    //     else if (locked && !rstInit && !modeSel) begin 
+    //         case (trCnt) 
+    //         0: begin 
+    //             SPIdata = 24'h555554;
+    //         end
+    //         1:begin 
+    //             SPIdata = {1'h0, 7'h2a, 16'd10};
+    //         end
+    //     endcase
+    //     case (trCntSync) 
+    //        2 : begin 
+    //         SPIdata = {1'h0, 7'h2a, 16'd20};
+    //         end
+    //         3 : begin 
+    //             SPIdata = {1'h0, 7'h2a, 16'd30};
+    //         end
+    //         4 : begin 
+    //             SPIdata = {1'h0, 7'h2a, 16'd40};
+    //         end
+    //         5 : begin 
+    //             SPIdata = {1'h0, 7'h2a, 16'd50};
+    //         end
+    //         6 : begin 
+    //             SPIdata = {1'h0, 7'h2a, 16'd60};
+    //         end
+    //         7 : begin 
+    //             SPIdata = {1'h0, 7'h2a, 16'd70};
+    //         end
+    //     endcase
+    //     end
+    //     else begin 
+    //         SPIdata = 24'h0;
+    //     end
+    // end
+
+
 endmodule

src/src/Top/RFTop.v

@@ -34,6 +34,8 @@ output Clk50_o,
 output [FifoNum-1:0] Ss_o,
 output [FifoNum-1:0] Sck_o,
 output [FifoNum-1:0] Mosi0_o,
+// output Locked_o,
+// output RstInit_o,
 
 output [21:0] GPIO_o
 
@@ -132,7 +134,7 @@ wire [15:0] tempI2CData;
 
 
 
-
+reg [1:0] numOfConfigCmds;
 //sums
 
 wire [6:0] sumForLmx = numOfConfigCmds+packetNum1;
@@ -154,6 +156,9 @@ reg tempI2CDataReady;
 reg [15:0] misoRegI2C;
 reg [15:0] tempI2CDataReg;
 reg [Width-1:0] dataToRxFifoReg;
+reg             valToRxFifoReg;
+reg [16:0] trCntReg;
+reg [16:0] trCntRR;
 
 //================================================================================
 
@@ -167,6 +172,7 @@ reg [Width-1:0] configReg2;
 
 reg [15:0] trCnt;
 reg [15:0] trCnt1Spi;
+reg [16:0] trCnt1SpiReg;
 reg [2:0] trCntDDS;
 reg [2:0] trCntMAX2870;
 
@@ -174,8 +180,9 @@ reg [2:0] trCntMAX2870;
 reg misoReg;
 reg ssReg;
 reg ssRR;
+reg ssRRR;
+
 
-reg [1:0] numOfConfigCmds;
 
 reg [23:0] GPIOReg;
 
@@ -217,8 +224,8 @@ assign packetNum8 = configReg1[8:7];//GPIO
 
 assign modeSel = configReg1[23];
 assign terminateBit = configReg1[0];
-assign deviceID = (!modeSel)?configReg1[22:18] : 5'b0;
-assign wordNum = (!modeSel)?configReg1[17:1] : 17'b0;
+assign deviceID = (!modeSel) ? configReg1[22:18] : 5'b0;
+assign wordNum = (!modeSel) ? configReg1[17:1] : 17'b0;
 
 // assign dataToRxFifo = (RorQSPIFlag) ? dataToRxFifoQ : dataToRxFifoR;
 
@@ -229,35 +236,36 @@ assign dataToRxFifo = dataToRxFifoReg;
 
  
 // assign valToRxFifo = (RorQSPIFlag) ? valToRxFifoQ : valToRxFifoR;
-assign valToRxFifo = (((currState == IDLE) ? (RorQSPIFlag) ? valToRxFifoQ : valToRxFifoR : (modeSel) ? valToRxFifoQ : valToRxFifoR));
+// assign valToRxFifo = (((currState == IDLE) ? (RorQSPIFlag) ? valToRxFifoQ : valToRxFifoR : (modeSel) ? valToRxFifoQ : valToRxFifoR));
+assign valToRxFifo = valToRxFifoReg;
 assign rstSpi = (!IDLE) ? ((modeSel) ? 1'b0 : 1'b1) : 1'b0;
 
-assign Ss_o[0] = (modeSel) ? ss[0] : (currState == LMX2594)? Ss_i : 1'b1;
-assign Ss_o[1] = (modeSel) ? ss[1] : (currState == DDS)? Ss_i : 1'b1;
-assign Ss_o[2] = (modeSel) ? ss[2] : (currState == POT)? Ss_i : 1'b1;
-assign Ss_o[3] = (modeSel) ? ss[3] : (currState == DAC)? Ss_i : 1'b1;
-assign Ss_o[4] = (modeSel) ? ss[4] : (currState == ATTENUATOR)? Ss_i : 1'b1;
-assign Ss_o[5] = (modeSel) ? ss[5] : (currState == SHIFTREG)? Ss_i : 1'b1;
-assign Ss_o[6] = (modeSel) ? ss[6] : (currState == MAX2870)? Ss_i : 1'b1;
-
-assign Sck_o[0] = (modeSel) ? sck[0] : (currState == LMX2594)? Sck_i : 1'b0;
-assign Sck_o[1] = (modeSel) ? sck[1] : (currState == DDS)? Sck_i : 1'b0;
-assign Sck_o[2] = (modeSel) ? sck[2] : (currState == POT)? Sck_i : 1'b0;
-assign Sck_o[3] = (modeSel) ? sck[3] : (currState == DAC)? Sck_i : 1'b0;
-assign Sck_o[4] = (modeSel) ? sck[4] : (currState == ATTENUATOR)? Sck_i : 1'b0;
-assign Sck_o[5] = (modeSel) ? sck[5] : (currState == SHIFTREG)? Sck_i : 1'b0;
-assign Sck_o[6] = (modeSel) ? sck[6] : (currState == MAX2870)? Sck_i : 1'b0;
-
-
-assign Mosi0_o[0] = (modeSel) ? mosi0[0] : (currState == LMX2594 && currState != IDLE )?Mosi0_i : 1'b0;
-assign Mosi0_o[1] = (modeSel) ? mosi0[1] : (currState == DDS && currState != IDLE )?Mosi0_i : 1'b0;
-assign Mosi0_o[2] = (modeSel) ? mosi0[2] : (currState == POT && currState != IDLE  )?Mosi0_i : 1'b0;
-assign Mosi0_o[3] = (modeSel) ? mosi0[3] : (currState == DAC && currState != IDLE )?Mosi0_i : 1'b0;
-assign Mosi0_o[4] = (modeSel) ? mosi0[4] : (currState == ATTENUATOR && currState != IDLE )?Mosi0_i : 1'b0;
-assign Mosi0_o[5] = (modeSel) ? mosi0[5] : (currState == SHIFTREG && currState != IDLE )?Mosi0_i : 1'b0;
-assign Mosi0_o[6] = (modeSel) ? mosi0[6] : (currState == MAX2870 && currState != IDLE )?Mosi0_i : 1'b0;
-
-assign Mosi1_io = (!modeSel && currState != IDLE) ? misoReg : 1'bz;
+assign Ss_o[0] = (modeSel) ? ss[0] : ((currState == LMX2594) ? Ss_i : 1'b1);
+assign Ss_o[1] = (modeSel) ? ss[1] : ((currState == DDS) ? Ss_i : 1'b1);
+assign Ss_o[2] = (modeSel) ? ss[2] : ((currState == POT) ? Ss_i : 1'b1);
+assign Ss_o[3] = (modeSel) ? ss[3] : ((currState == DAC) ? Ss_i : 1'b1);
+assign Ss_o[4] = (modeSel) ? ss[4] : ((currState == ATTENUATOR) ? Ss_i : 1'b1);
+assign Ss_o[5] = (modeSel) ? ss[5] : ((currState == SHIFTREG) ? Ss_i : 1'b1);
+assign Ss_o[6] = (modeSel) ? ss[6] : ((currState == MAX2870) ? Ss_i : 1'b1);
+
+assign Sck_o[0] = (modeSel) ? sck[0] : ((currState == LMX2594) ? Sck_i : 1'b0);
+assign Sck_o[1] = (modeSel) ? sck[1] : ((currState == DDS) ? Sck_i : 1'b0);
+assign Sck_o[2] = (modeSel) ? sck[2] : ((currState == POT) ? Sck_i : 1'b0);
+assign Sck_o[3] = (modeSel) ? sck[3] : ((currState == DAC) ? Sck_i : 1'b0);
+assign Sck_o[4] = (modeSel) ? sck[4] : ((currState == ATTENUATOR) ? Sck_i : 1'b0);
+assign Sck_o[5] = (modeSel) ? sck[5] : ((currState == SHIFTREG) ? Sck_i : 1'b0);
+assign Sck_o[6] = (modeSel) ? sck[6] : ((currState == MAX2870) ? Sck_i : 1'b0);
+
+
+assign Mosi0_o[0] = (modeSel) ? mosi0[0] : (((currState == LMX2594) && (currState != IDLE)) ? Mosi0_i : 1'b0);
+assign Mosi0_o[1] = (modeSel) ? mosi0[1] : (((currState == DDS) && (currState != IDLE)) ? Mosi0_i : 1'b0);
+assign Mosi0_o[2] = (modeSel) ? mosi0[2] : (((currState == POT) && (currState != IDLE)) ? Mosi0_i : 1'b0);
+assign Mosi0_o[3] = (modeSel) ? mosi0[3] : (((currState == DAC) && (currState != IDLE)) ? Mosi0_i : 1'b0);
+assign Mosi0_o[4] = (modeSel) ? mosi0[4] : (((currState == ATTENUATOR) && (currState != IDLE)) ? Mosi0_i : 1'b0);
+assign Mosi0_o[5] = (modeSel) ? mosi0[5] : (((currState == SHIFTREG) && (currState != IDLE)) ? Mosi0_i : 1'b0);
+assign Mosi0_o[6] = (modeSel) ? mosi0[6] : (((currState == MAX2870) && (currState != IDLE)) ? Mosi0_i : 1'b0);
+
+assign Mosi1_io = (!modeSel && (currState != IDLE)) ? misoReg : 1'bz;
 
 assign RstInit_o = rstInit;
 
@@ -272,41 +280,67 @@ assign GPIO_o = GPIOReg[21:0];
 
 
 
-always @(*) begin 
+always @(posedge clk100) begin 
     if (currState == IDLE) begin 
         if (RorQSPIFlag) begin 
-            dataToRxFifoReg = dataToRxFifoQ;
+            dataToRxFifoReg <= dataToRxFifoQ;
         end
         else begin 
-            dataToRxFifoReg = dataToRxFifoR;
+            dataToRxFifoReg <= dataToRxFifoR;
         end
     end
     else begin 
         if (modeSel) begin 
-            dataToRxFifoReg = dataToRxFifoQ;
+            dataToRxFifoReg <= dataToRxFifoQ;
         end
         else begin 
-            dataToRxFifoReg = dataToRxFifoR;
+            dataToRxFifoReg <= dataToRxFifoR;
         end
     end
 end
 
 
+always @(posedge clk100) begin 
+    if (currState == IDLE) begin 
+        if (RorQSPIFlag) begin
+            valToRxFifoReg <= valToRxFifoQ;
+        end
+        else begin 
+            valToRxFifoReg <= valToRxFifoR;
+        end
+    end
+    else begin
+        if (modeSel) begin 
+            valToRxFifoReg <= valToRxFifoQ;
+        end
+        else begin 
+            valToRxFifoReg <= valToRxFifoR;
+        end
+    end
+end
+
 
 
 
 always @(posedge clk100) begin 
     ssReg <= Ss_i;
     ssRR <= ssReg;
+    ssRRR <= ssRR;
+end
+
+
+always @(posedge clk100) begin
+    trCnt1SpiReg <= trCnt1Spi;
 end
 
 
+
 always @(posedge clk100) begin 
-    if (Rst_i || rstInit) begin 
+    if (Rst_i || rstInit ) begin 
         trCnt1Spi <= 0; 
     end
     else begin 
-        if (ssReg && !ssRR && !modeSel && currState != IDLE) begin 
+        if (ssRR && !ssRRR && !modeSel && currState != IDLE) begin 
             trCnt1Spi <= trCnt1Spi + 1;
         end
         else if (trCnt1Spi == wordNum || currState == IDLE) begin 
@@ -411,7 +445,7 @@ temp_i2c_master_ver2 I2Cm_inst (
 
 
 always @(*) begin
-    if (Rst_i || rstInit) begin 
+    if (Rst_i ) begin 
         numOfConfigCmds = 2'd1;
     end
     else begin 
@@ -438,7 +472,6 @@ end
 
 
 
-
 always @(*) begin 
     case (currState) 
         IDLE : begin 
@@ -497,7 +530,7 @@ always @(posedge clk100) begin
         configReg1 <= 24'h0;
     end
     else begin 
-        if (currState == IDLE && valToRxFifo) begin 
+        if ((currState == IDLE) && (valToRxFifo)) begin 
             configReg1 <=dataToRxFifo;
         end
         else begin 
@@ -534,22 +567,56 @@ always @(posedge clk100) begin
 end
 
 
+always @(posedge clk100) begin 
+    trCntReg <= trCnt;
+    trCntRR <= trCntReg;
+end
+
+
+
+// always @(posedge clk100) begin 
+//     if (Rst_i || rstInit ) begin 
+//         trCnt <= 0;
+//     end
+//     else begin 
+//         else if (modeSel) begin
+//             if (trCnt == packetNum1 + packetNum2 + packetNum3 + packetNum4 + packetNum5 + packetNum6 + packetNum7 + packetNum8 + numOfConfigCmds && trCnt != 0 ) begin 
+//                 trCnt <= 0;
+//             end
+//         end
+//         else if (!modeSel) begin 
+//             if (currState != IDLE) begin 
+//                 trCnt <= 0;
+//             end
+//             else begin 
+//                 if (trCnt >= 2) begin 
+//                     trCnt <= 0;
+//                 end
+//             end
+//         end
+//     end
+// end
 
 always @(posedge clk100) begin 
     if (Rst_i || rstInit) begin 
         trCnt <= 0;
     end
     else begin 
-        if (valToRxFifo) begin 
-            trCnt <= trCnt + 1;
-        end
-        if (modeSel) begin
-            if (trCnt == packetNum1 + packetNum2 + packetNum3 + packetNum4 + packetNum5 + packetNum6 + packetNum7 + packetNum8 + numOfConfigCmds && trCnt != 0 ) begin 
+        if (modeSel) begin 
+            if (valToRxFifo) begin 
+                trCnt <= trCnt + 1;
+            end
+            else if (trCnt == packetNum1 + packetNum2 + packetNum3 + packetNum4 + packetNum5 + packetNum6 + packetNum7 + packetNum8 + numOfConfigCmds) begin 
                 trCnt <= 0;
             end
         end
-        if (!modeSel) begin 
-            if (currState != IDLE) begin 
+        else begin 
+            if (currState == IDLE) begin 
+                if (valToRxFifo) begin 
+                    trCnt <= trCnt + 1;
+                end
+            end
+            else begin 
                 trCnt <= 0;
             end
         end
@@ -558,9 +625,8 @@ end
 
 
 
-
 always @(posedge clk100) begin 
-    if (Rst_i || rstInit) begin 
+    if (Rst_i) begin 
         trCntMAX2870 <= 0;
     end
     else begin 
@@ -608,7 +674,7 @@ ClkGenGowin CustomDiv (
 
 QuadSPIs QuadSPIs_inst (
     .Clk_i(clk100),
-    .Rst_i(rstInit || Rst_i),
+    .Rst_i(Rst_i),
     .Sck_i(Sck_i),
     .Ss_i(Ss_i),
     .Mosi0_i(Mosi0_i),
@@ -625,7 +691,7 @@ QuadSPIs QuadSPIs_inst (
 
 SPIs SPIs_inst (
     .Clk_i(clk100),
-    .Rst_i(rstInit || Rst_i),
+    .Rst_i(Rst_i),
     .Sck_i(Sck_i),
     .Ss_i(Ss_i),
     .Mosi0_i(Mosi0_i),
@@ -787,7 +853,7 @@ FifoCtrl #(
 ) FifoCtrl_inst (
     .WrClk_i(clk100),
     .RdClk_i(rdClk),
-    .Rst_i(Rst_i ),
+    .Rst_i(!modeSel),
     .ValToRxFifo_i(valToRxFifo),
     .DataToRxFifo_i(dataToRxFifo),
     .ValToReadFromRxFifo1_i(valToReadFromRxFifo[0]),
@@ -852,7 +918,7 @@ InitRst RstForSynth_inst (
 
 
 always @(posedge clk100) begin 
-    if (Rst_i || rstInit ) begin 
+    if (Rst_i || rstInit) begin 
         currState <= IDLE;
     end else begin 
         currState <= nextState;
@@ -911,7 +977,7 @@ always @(*) begin
                 end  
             end
             else begin 
-                if (trCnt == 16'h1) begin 
+                if ( trCntReg== 16'h1) begin 
                     nextState = deviceID + 1;
                 end
                 else begin 
@@ -956,9 +1022,11 @@ always @(*) begin
                 if (trCnt1Spi == wordNum ) begin 
                     nextState = IDLE;
                 end
-                else if (trCnt1Spi < wordNum ) begin 
-                    nextState = LMX2594;
-                end
+                 else begin 
+                        if  (trCnt1Spi < wordNum) begin 
+                            nextState = LMX2594;
+                        end
+                 end
             end
         end
         DDS: begin
@@ -989,17 +1057,14 @@ always @(*) begin
                 end
             end
             else begin 
-                if (wordNum != 0) begin 
-                    if (trCnt1Spi == wordNum) begin 
-                        nextState = IDLE;
-                    end
-                    else if (trCnt1Spi < wordNum) begin 
-                        nextState = DDS;
-                    end
-                end
-                else begin 
+                   if (trCnt1Spi == wordNum ) begin 
                     nextState = IDLE;
                 end
+                 else begin 
+                        if (trCnt1Spi < wordNum) begin 
+                            nextState = DDS;
+                        end
+                 end
             end
         end
         POT: begin
@@ -1030,12 +1095,14 @@ always @(*) begin
                 end
             end
             else begin 
-                if (trCnt1Spi == wordNum) begin 
+                if (trCnt1Spi == wordNum ) begin 
                     nextState = IDLE;
                 end
-                else if (trCnt1Spi < wordNum) begin 
-                    nextState = POT;
-                end
+                 else begin 
+                        if (trCnt1Spi < wordNum) begin 
+                            nextState = POT;
+                        end
+                 end
             end
         end
         DAC: begin
@@ -1062,13 +1129,15 @@ always @(*) begin
                     nextState = DAC;
                 end
             end
-            else begin 
-                if (trCnt1Spi == wordNum) begin 
+            else begin
+                if (trCnt1Spi == wordNum ) begin 
                     nextState = IDLE;
                 end
-                else if (trCnt1Spi < wordNum) begin 
-                    nextState = DAC;
-                end
+                 else begin 
+                        if (trCnt1Spi < wordNum) begin 
+                            nextState = DAC;
+                        end
+                 end
             end
         end
         ATTENUATOR: begin
@@ -1090,12 +1159,14 @@ always @(*) begin
                 end
             end
             else begin 
-                if (trCnt1Spi == wordNum) begin 
+               if (trCnt1Spi == wordNum ) begin 
                     nextState = IDLE;
                 end
-                else if (trCnt1Spi < wordNum) begin 
-                    nextState = ATTENUATOR;
-                end
+                 else begin 
+                        if (trCnt1Spi < wordNum) begin 
+                            nextState = ATTENUATOR;
+                        end
+                 end
             end
         end
         SHIFTREG : begin 
@@ -1113,15 +1184,17 @@ always @(*) begin
                     nextState = SHIFTREG;
                 end
             end
-            else begin 
-                if (trCnt1Spi == wordNum) begin 
+            else begin
+                if (trCnt1Spi == wordNum ) begin 
                     nextState = IDLE;
                 end
-                else if (trCnt1Spi < wordNum) begin 
-                    nextState = SHIFTREG;
-                end
+                 else begin 
+                        if (trCnt1Spi < wordNum) begin 
+                            nextState = SHIFTREG;
+                        end
+                 end
             end
-        end
+        end  
         MAX2870 : begin 
             if (modeSel) begin 
                 if ((trCnt == (sumForMAX)) && (packetNum8 != 0))  begin 
@@ -1134,13 +1207,15 @@ always @(*) begin
                     nextState = MAX2870;
                 end
             end
-            else begin 
-                if (trCnt1Spi == wordNum) begin 
+            else begin
+                if (trCnt1Spi == wordNum ) begin 
                     nextState = IDLE;
                 end
-                else if (trCnt1Spi < wordNum) begin 
-                    nextState = MAX2870;
-                end
+                 else begin 
+                        if (trCnt1Spi < wordNum) begin 
+                            nextState = MAX2870;
+                        end
+                 end
             end
         end
         GPIO : begin 
@@ -1152,13 +1227,15 @@ always @(*) begin
                     nextState = GPIO;
                 end
             end
-            else begin 
-                if (trCnt1Spi == wordNum  ) begin 
+            else begin
+                if (trCnt1Spi == wordNum ) begin 
                     nextState = IDLE;
                 end
-                else if (trCnt1Spi < wordNum) begin 
-                    nextState = GPIO;
-                end
+                 else begin 
+                        if (trCnt1Spi < wordNum) begin 
+                            nextState = GPIO;
+                        end
+                 end
             end
         end
         TEMPSENS : begin 
@@ -1166,15 +1243,14 @@ always @(*) begin
                 nextState = IDLE;
             end
             else begin 
-                if (trCnt1Spi == wordNum) begin 
-                    nextState = IDLE;
-                end
-                else if (trCnt1Spi < wordNum) begin 
-                    nextState = TEMPSENS;
-                end
-                else begin 
+                if (trCnt1Spi == wordNum ) begin 
                     nextState = IDLE;
                 end
+                 else begin 
+                        if ( trCnt1Spi < wordNum) begin 
+                            nextState = TEMPSENS;
+                        end
+                 end
             end
         end
         default: begin 

src/src/fifo_top/FifoCtrl.v

@@ -2,7 +2,8 @@ module FifoCtrl#(
     parameter FifoNum = 8
 )(
 input WrClk_i,
-input [FifoNum-1:0] Rst_i,
+// input [FifoNum-1:0] RstSync_i,
+input Rst_i,
 input[FifoNum-1:0]  RdClk_i,
 input [4:0] CurrState_i,
 input [2:0] DDSFifoCnt_i,
@@ -152,219 +153,293 @@ end
 
 
 
-always @(posedge WrClk_i) begin 
-    case (CurrState_i) 
-    0 : begin 
-        rxFifoWrEn <= 1'b0;
-    end
-    1: begin 
-        if (!fullFlag[0] && ValToRxFifo_i) begin 
-                rxFifoWrEn[0] <= 1'b1;
-            end
-            else begin 
-                rxFifoWrEn[0] <= 1'b0;
-            end
-    end
-    2: begin 
-        if (!fullFlag[1] && ValToRxFifo_i && DDSFifoCnt_i == 3'h2 ) begin 
-                rxFifoWrEn[1] <= 1'b1;
-            end
-            else begin 
-                rxFifoWrEn[1] <= 1'b0;
-            end
+always @(posedge WrClk_i) begin
+    if (Rst_i) begin
+        rxFifoWrEn = 0;
     end
-    3: begin 
-        if (!fullFlag[2] && ValToRxFifo_i) begin 
-                rxFifoWrEn[2] <= 1'b1;
-            end
-            else begin 
-                rxFifoWrEn[2] <= 1'b0;
-            end
-    end
-    4: begin 
-        if (!fullFlag[3] && ValToRxFifo_i) begin 
-                rxFifoWrEn[3] <= 1'b1;
-            end
-            else begin 
-                rxFifoWrEn[3] <= 1'b0;
-            end
-    end
-    5: begin 
-        if (!fullFlag[4] && ValToRxFifo_i) begin 
-                rxFifoWrEn[4] <= 1'b1;
-            end
-            else begin 
-                rxFifoWrEn[4] <= 1'b0;
-            end
-    end
-    6: begin 
-        if (!fullFlag[5] && ValToRxFifo_i) begin 
-                rxFifoWrEn[5] <= 1'b1;
-            end
-            else begin 
-                rxFifoWrEn[5] <= 1'b0;
-            end
-    end
-    7: begin 
-        if (!fullFlag[6] && ValToRxFifo_i && MAX2870FifoCnt_i == 3'h1) begin 
-                rxFifoWrEn[6] <= 1'b1;
-            end
-            else begin 
-                rxFifoWrEn[6] <= 1'b0;
-            end
-    end
-    default: begin 
-        rxFifoWrEn <= 1'b0;
+    else begin  
+        case (CurrState_i) 
+        0 : begin 
+            rxFifoWrEn <= 1'b0;
+        end
+        1: begin 
+            if (!fullFlag[0] && ValToRxFifo_i) begin 
+                    rxFifoWrEn[0] <= 1'b1;
+                end
+                else begin 
+                    rxFifoWrEn[0] <= 1'b0;
+                end
+        end
+        2: begin 
+            if (!fullFlag[1] && ValToRxFifo_i && DDSFifoCnt_i == 3'h2 ) begin 
+                    rxFifoWrEn[1] <= 1'b1;
+                end
+                else begin 
+                    rxFifoWrEn[1] <= 1'b0;
+                end
+        end
+        3: begin 
+            if (!fullFlag[2] && ValToRxFifo_i) begin 
+                    rxFifoWrEn[2] <= 1'b1;
+                end
+                else begin 
+                    rxFifoWrEn[2] <= 1'b0;
+                end
+        end
+        4: begin 
+            if (!fullFlag[3] && ValToRxFifo_i) begin 
+                    rxFifoWrEn[3] <= 1'b1;
+                end
+                else begin 
+                    rxFifoWrEn[3] <= 1'b0;
+                end
+        end
+        5: begin 
+            if (!fullFlag[4] && ValToRxFifo_i) begin 
+                    rxFifoWrEn[4] <= 1'b1;
+                end
+                else begin 
+                    rxFifoWrEn[4] <= 1'b0;
+                end
+        end
+        6: begin 
+            if (!fullFlag[5] && ValToRxFifo_i) begin 
+                    rxFifoWrEn[5] <= 1'b1;
+                end
+                else begin 
+                    rxFifoWrEn[5] <= 1'b0;
+                end
+        end
+        7: begin 
+            if (!fullFlag[6] && ValToRxFifo_i && MAX2870FifoCnt_i == 3'h1) begin 
+                    rxFifoWrEn[6] <= 1'b1;
+                end
+                else begin 
+                    rxFifoWrEn[6] <= 1'b0;
+                end
+        end
+        default: begin 
+            rxFifoWrEn <= 1'b0;
+        end
+        endcase
     end
-    endcase
 end
 
 always @(posedge RdClk_i[0]) begin
-    if (!emptyFlag[0] && ValToReadFromRxFifo1_i && rdEnCnt1 < 1 ) begin 
-        rxFifoReadEn[0] <= 1'b1;
-    end
-    else if (rdEnCnt1 >= 1 ) begin 
-        rxFifoReadEn[0] <= 1'b0;
+    if (Rst_i) begin
+        rxFifoReadEn[0] <= 0;
     end
     else begin 
-        rxFifoReadEn[0] <= 1'b0;
+        if (!emptyFlag[0] && ValToReadFromRxFifo1_i && rdEnCnt1 < 1 ) begin 
+            rxFifoReadEn[0] <= 1'b1;
+        end
+        else if (rdEnCnt1 >= 1 ) begin 
+            rxFifoReadEn[0] <= 1'b0;
+        end
+        else begin 
+            rxFifoReadEn[0] <= 1'b0;
+        end
     end
 end
 
-always @(posedge RdClk_i[1]) begin 
-    if (!emptyFlag[1] && ValToReadFromRxFifo2_i && rdEnCnt2 < 1 ) begin 
-        rxFifoReadEn[1] <= 1'b1;
-    end
-    else if (rdEnCnt2 >= 1 ) begin 
-        rxFifoReadEn[1] <= 1'b0;
+always @(posedge RdClk_i[1]) begin
+    if (Rst_i) begin
+        rxFifoReadEn[1] <= 0;
     end
-    else begin 
-        rxFifoReadEn[1] <= 1'b0;
+    else begin  
+        if (!emptyFlag[1] && ValToReadFromRxFifo2_i && rdEnCnt2 < 1 ) begin 
+            rxFifoReadEn[1] <= 1'b1;
+        end
+        else if (rdEnCnt2 >= 1 ) begin 
+            rxFifoReadEn[1] <= 1'b0;
+        end
+        else begin 
+            rxFifoReadEn[1] <= 1'b0;
+        end
     end
 end
 
-always @(posedge RdClk_i[2]) begin 
-    if (!emptyFlag[2] && ValToReadFromRxFifo3_i && rdEnCnt3 < 1 ) begin 
-        rxFifoReadEn[2] <= 1'b1;
-    end
-    else if (rdEnCnt3 >= 1 ) begin 
-        rxFifoReadEn[2] <= 1'b0;
-    end
-    else begin 
-        rxFifoReadEn[2] <= 1'b0;
-    end
+always @(posedge RdClk_i[2]) begin
+    if (Rst_i) begin 
+        rxFifoReadEn[2] <= 0;
+    end 
+        if (!emptyFlag[2] && ValToReadFromRxFifo3_i && rdEnCnt3 < 1 ) begin 
+            rxFifoReadEn[2] <= 1'b1;
+        end
+        else if (rdEnCnt3 >= 1 ) begin 
+            rxFifoReadEn[2] <= 1'b0;
+        end
+        else begin 
+            rxFifoReadEn[2] <= 1'b0;
+        end
 end
 
-always @(posedge RdClk_i[3]) begin 
-    if (!emptyFlag[3] && ValToReadFromRxFifo4_i && rdEnCnt4 < 1 ) begin 
-        rxFifoReadEn[3] <= 1'b1;
-    end
-    else if (rdEnCnt4 >= 1 ) begin 
+always @(posedge RdClk_i[3]) begin
+    if (Rst_i) begin 
         rxFifoReadEn[3] <= 1'b0;
     end
     else begin 
-        rxFifoReadEn[3] <= 1'b0;
+        if (!emptyFlag[3] && ValToReadFromRxFifo4_i && rdEnCnt4 < 1 ) begin 
+            rxFifoReadEn[3] <= 1'b1;
+        end
+        else if (rdEnCnt4 >= 1 ) begin 
+            rxFifoReadEn[3] <= 1'b0;
+        end
+        else begin 
+            rxFifoReadEn[3] <= 1'b0;
+        end
     end
 end
 
-always @(posedge RdClk_i[4]) begin 
-    if (!emptyFlag[4] && ValToReadFromRxFifo5_i && rdEnCnt5 < 1 ) begin 
-        rxFifoReadEn[4] <= 1'b1;
-    end
-    else if (rdEnCnt5 >= 1 ) begin 
+always @(posedge RdClk_i[4]) begin
+    if (Rst_i) begin 
         rxFifoReadEn[4] <= 1'b0;
     end
     else begin 
-        rxFifoReadEn[4] <= 1'b0;
+        if (!emptyFlag[4] && ValToReadFromRxFifo5_i && rdEnCnt5 < 1 ) begin 
+            rxFifoReadEn[4] <= 1'b1;
+        end
+        else if (rdEnCnt5 >= 1 ) begin 
+            rxFifoReadEn[4] <= 1'b0;
+        end
+        else begin 
+            rxFifoReadEn[4] <= 1'b0;
+        end
     end
 end
 
-always @(posedge RdClk_i[5]) begin 
-    if (!emptyFlag[5] && ValToReadFromRxFifo6_i && rdEnCnt6 < 1 ) begin 
-        rxFifoReadEn[5] <= 1'b1;
-    end
-    else if (rdEnCnt6 >= 1 ) begin 
+always @(posedge RdClk_i[5]) begin
+      if (Rst_i) begin 
         rxFifoReadEn[5] <= 1'b0;
     end
-    else begin 
-        rxFifoReadEn[5] <= 1'b0;
+    else begin  
+        if (!emptyFlag[5] && ValToReadFromRxFifo6_i && rdEnCnt6 < 1 ) begin 
+            rxFifoReadEn[5] <= 1'b1;
+        end
+        else if (rdEnCnt6 >= 1 ) begin 
+            rxFifoReadEn[5] <= 1'b0;
+        end
+        else begin 
+            rxFifoReadEn[5] <= 1'b0;
+        end 
     end
 end
 
-always @(posedge RdClk_i[6]) begin 
-    if (!emptyFlag[6] && ValToReadFromRxFifo7_i && rdEnCnt7 < 1 ) begin 
-        rxFifoReadEn[6] <= 1'b1;
-    end
-    else if (rdEnCnt7 >= 1 ) begin 
+always @(posedge RdClk_i[6]) begin
+      if (Rst_i) begin 
         rxFifoReadEn[6] <= 1'b0;
     end
-    else begin 
-        rxFifoReadEn[6] <= 1'b0;
+        else begin  
+        if (!emptyFlag[6] && ValToReadFromRxFifo7_i && rdEnCnt7 < 1 ) begin 
+            rxFifoReadEn[6] <= 1'b1;
+        end
+        else if (rdEnCnt7 >= 1 ) begin 
+            rxFifoReadEn[6] <= 1'b0;
+        end
+        else begin 
+            rxFifoReadEn[6] <= 1'b0;
+        end
     end
 end
 
 
-always @(posedge RdClk_i[0]) begin 
-    if (rxFifoReadEn[0]) begin 
-        rdEnCnt1 <= rdEnCnt1 + 1'b1;
+
+always @(posedge RdClk_i[0]) begin
+    if (Rst_i) begin
+        rdEnCnt1 <= 0;
     end
-    else begin 
-        rdEnCnt1 <= 1'b0;
+    else begin  
+        if (rxFifoReadEn[0]) begin 
+            rdEnCnt1 <= rdEnCnt1 + 1'b1;
+        end
+        else begin 
+            rdEnCnt1 <= 1'b0;
+        end
     end
 end
 
 
-always @(posedge RdClk_i[1]) begin 
-    if (rxFifoReadEn[1]) begin 
-        rdEnCnt2 <= rdEnCnt2 + 1'b1;
+always @(posedge RdClk_i[1]) begin
+    if (Rst_i) begin
+        rdEnCnt2 <= 0;
     end
-    else begin 
-        rdEnCnt2 <= 1'b0;
+    else begin  
+        if (rxFifoReadEn[1]) begin 
+            rdEnCnt2 <= rdEnCnt2 + 1'b1;
+        end
+        else begin 
+            rdEnCnt2 <= 1'b0;
+        end
     end
 end
 
-always @(posedge RdClk_i[2]) begin 
-    if (rxFifoReadEn[2]) begin 
-        rdEnCnt3 <= rdEnCnt3 + 1'b1;
+always @(posedge RdClk_i[2]) begin
+    if (Rst_i) begin
+        rdEnCnt3 <= 0;
     end
-    else begin 
-        rdEnCnt3 <= 1'b0;
+    else begin   
+        if (rxFifoReadEn[2]) begin 
+            rdEnCnt3 <= rdEnCnt3 + 1'b1;
+        end
+        else begin 
+            rdEnCnt3 <= 1'b0;
+        end
     end
 end
 
-always @(posedge RdClk_i[3]) begin 
-    if (rxFifoReadEn[3]) begin 
-        rdEnCnt4 <= rdEnCnt4 + 1'b1;
+always @(posedge RdClk_i[3]) begin
+    if (Rst_i) begin
+        rdEnCnt4 <= 0;
     end
     else begin 
-        rdEnCnt4 <= 1'b0;
+        if (rxFifoReadEn[3]) begin 
+            rdEnCnt4 <= rdEnCnt4 + 1'b1;
+        end
+        else begin 
+            rdEnCnt4 <= 1'b0;
+        end
     end
 end
 
-always @(posedge RdClk_i[4]) begin 
-    if (rxFifoReadEn[4]) begin 
-        rdEnCnt5 <= rdEnCnt5 + 1'b1;
+always @(posedge RdClk_i[4]) begin
+    if (Rst_i) begin
+        rdEnCnt5 <= 0;
     end
-    else begin 
-        rdEnCnt5 <= 1'b0;
+    else begin  
+        if (rxFifoReadEn[4]) begin 
+            rdEnCnt5 <= rdEnCnt5 + 1'b1;
+        end
+        else begin 
+            rdEnCnt5 <= 1'b0;
+        end
     end
 end
 
-always @(posedge RdClk_i[5]) begin 
-    if (rxFifoReadEn[5]) begin 
-        rdEnCnt6 <= rdEnCnt6 + 1'b1;
+always @(posedge RdClk_i[5]) begin
+    if (Rst_i) begin
+        rdEnCnt6 <= 0;
     end
-    else begin 
-        rdEnCnt6 <= 1'b0;
+    else begin  
+        if (rxFifoReadEn[5]) begin 
+            rdEnCnt6 <= rdEnCnt6 + 1'b1;
+        end
+        else begin 
+            rdEnCnt6 <= 1'b0;
+        end
     end
 end
 
-always @(posedge RdClk_i[6]) begin 
-    if (rxFifoReadEn[6]) begin 
-        rdEnCnt7 <= rdEnCnt7 + 1'b1;
+always @(posedge RdClk_i[6]) begin
+    if (Rst_i) begin
+        rdEnCnt7 <= 0;
     end
-    else begin 
-        rdEnCnt7 <= 1'b0;
+    else begin  
+        if (rxFifoReadEn[6]) begin 
+            rdEnCnt7 <= rdEnCnt7 + 1'b1;
+        end
+        else begin 
+            rdEnCnt7 <= 1'b0;
+        end
     end
 end
 
@@ -375,7 +450,7 @@ generate for (i = 0; i < FifoNum; i = i + 1 ) begin : fifoGen
     if (i != 1  && i != 6 && i != 7) begin
         FifoRxRF RxFifoRF (
             .Data(dataToRxFifo[i]),
-            .Reset(Rst_i[i]),
+            .Reset(Rst_i),
             .WrClk(WrClk_i),
             .RdClk(RdClk_i[i]),
             .WrEn(rxFifoWrEn[i]),
@@ -391,7 +466,7 @@ endgenerate
 
 FifoDDS DDSFifo (
     .Data(dataToRxFifo2),
-    .Reset(Rst_i[1]),
+    .Reset(Rst_i),
     .WrClk(WrClk_i),
     .RdClk(RdClk_i[1]),
     .WrEn(rxFifoWrEn[1]),
@@ -407,7 +482,7 @@ FifoDDS DDSFifo (
 
 FifoMax2870 Max2870Fifo (
     .Data(dataToFifoMax2870),
-    .Reset(Rst_i[6]),
+    .Reset(Rst_i),
     .WrClk(WrClk_i),
     .RdClk(RdClk_i[6]),
     .WrEn(rxFifoWrEn[6]),