Создан новый тестбенч - SB_TMSG_tb

src/constr/RF_FPGA.cst

@@ -4,7 +4,7 @@
 //Tool Version: V1.9.9.01 (64-bit)
 //Part Number: GW1N-LV9PG256C6/I5
 //Device: GW1N-9
-//Created Time: Tue 04 09 09:51:32 2024
+//Created Time: Fri 04 12 11:25:42 2024
 
 IO_LOC "GPIO_o[21]" E1;
 IO_PORT "GPIO_o[21]" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;
@@ -50,6 +50,8 @@ IO_LOC "GPIO_o[1]" H16;
 IO_PORT "GPIO_o[1]" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;
 IO_LOC "GPIO_o[0]" G16;
 IO_PORT "GPIO_o[0]" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;
+IO_PORT "RstInit_o" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;
+IO_PORT "Locked_o" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;
 IO_PORT "Mosi0_o[7]" IO_TYPE=LVCMOS33;
 IO_LOC "Mosi0_o[6]" C1;
 IO_PORT "Mosi0_o[6]" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;

src/src/Sim/SB_TMSG_tb.sv

@@ -0,0 +1,358 @@
+`timescale 1ns/1ps
+
+module SB_TMSG_tb;
+   parameter CLK_PERIOD = 8.13; // Clock period in ns
+
+    // Inputs
+    logic Clk_i;
+    logic Clk100;
+    logic Clk20;
+    logic Clk80;
+    logic Clk50;
+    logic Clk24;
+    logic Clk10; 
+    logic Rst_i;
+    logic Start_i;
+    logic CPHA_i;
+    logic [31:0] SPIdata;
+	logic SpiDataVal_i;
+    logic SELST_i;
+    logic [1:0] WidthSel_i;
+    logic LAG_i;
+    logic LEAD_i;
+    logic EndianSel_i;
+    logic [5:0] Stop_i;
+    logic PulsePol_i;
+
+    // Outputs
+    wire Mosi0_o;
+    wire Mosi1_o;
+    wire Mosi1_io;
+    wire Mosi2_o;
+    wire Mosi3_o;
+    wire Sck_o;
+    wire Ss_o;
+    wire Val_o;
+
+    wire valR;
+    wire valQ;
+    wire SckR;
+    wire SckQ;
+    wire SsR;
+    wire SsQ;
+    wire mosi0R;
+    wire mosi0Q;
+
+    wire locked;
+    wire rstInit;
+
+    logic [16:0] trCnt;
+    logic [4:0] trCntSync;
+
+
+    logic modeSel; 
+    logic [23:0] randData;
+    logic [31:0] randData32;
+    logic [5:0] QSPITotalWordNum;
+    logic Stop;
+    logic [31:0] stopCnt;
+    logic rstForFPGA;
+
+//***********************************************
+//	            Lines From RF Top
+//***********************************************
+
+    logic [7:0] sckFromRFTop;
+    logic [7:0] mosiFromRFTop;
+    logic [7:0] ssFromRFTop;
+
+
+    logic [23:0] dataFromSPItb;
+    logic        valFromSPItb; 
+
+//***********************************************
+//	            CLASSES
+//***********************************************
+
+class Packet;
+    rand bit [23:0] data;
+    rand bit [31:0] data32;
+endclass
+
+Packet pkt;
+
+//***********************************************
+//	      HEADERS FOR DEVICES
+//***********************************************
+localparam [4:0]  DeviceIdLmx2594 = 5'h0;
+localparam [4:0]  DeviceIdDDS = 5'h1;
+localparam [4:0]  DeviceIdPot = 5'h2;
+localparam [4:0]  DeviceIdDac = 5'h3;
+localparam [4:0]  DeviceIdAtt = 5'h4;
+localparam [4:0]  DeviceIdShReg = 5'h5;
+localparam [4:0]  DeviceIdMax2870 = 5'h6;
+localparam [4:0]  DeviceIdGPIO = 5'h7;
+
+localparam [16:0] Lmx2594InitWordNum = 17'd113;
+localparam [16:0] DDSInitWordNum = 17'd37;
+localparam [16:0] MaxInitWordNum = 17'd6;
+
+localparam [23:0] InitLMX2594Header = {1'h0, DeviceIdLmx2594, Lmx2594InitWordNum, 1'h1};
+localparam [23:0] InitDDSHeader = {1'h0, DeviceIdDDS, DDSInitWordNum, 1'h1};
+localparam [23:0] InitMAX2870Header = {1'h0, DeviceIdMax2870, MaxInitWordNum, 1'h1};
+localparam [3:0]  LMXWordNum = 4'd14;
+localparam [1:0]  DDSWordNum = 2'd3;
+localparam        POTWordNum = 1'd1;
+localparam        DACWordNum = 1'd1;
+localparam        ATTWordNum = 1'd1;
+localparam [1:0]  ShRegWordNum = 1'd1;
+localparam [2:0]  MaxWordNum =   3'd2;
+localparam [1:0]  GPIOWordNum =  2'd1;
+
+localparam [23:0] AllDevQSPIHeader = {1'h1, LMXWordNum, DDSWordNum, POTWordNum, DACWordNum,ATTWordNum, ShRegWordNum,MaxWordNum, GPIOWordNum, 7'h1};
+
+//***********************************************
+//	           ASSIGNS
+//***********************************************
+
+assign Val_o = (modeSel) ? valQ : valR;
+assign Sck_o = (modeSel) ? SckQ : SckR;
+assign Ss_o = (modeSel) ? SsQ : SsR;
+assign Mosi0_o = (modeSel) ? mosi0Q : mosi0R;
+
+assign emptyFlagTx = (trCnt > 183) ? 1'b1 : 1'b0;
+assign QSPITotalWordNum = LMXWordNum + DDSWordNum + POTWordNum + DACWordNum + ATTWordNum + ShRegWordNum + MaxWordNum + GPIOWordNum; 
+
+
+//***********************************************
+//	           CLOCK GENERATION
+//***********************************************
+always #(CLK_PERIOD/2) Clk_i = ~Clk_i;
+always #(10/2) Clk100 = ~Clk100;
+always #(20/2) Clk50 = ~Clk50;
+always #(12.5/2) Clk80 = ~Clk80;
+always #(41.67/2) Clk24 = ~Clk24;
+always #(50/2) Clk20 = ~Clk20;
+always #(50)   Clk10 = ~Clk10; 
+
+//***********************************************
+//	           INITIALIZATION
+//***********************************************
+
+initial begin
+      // Initialize Inputs
+      Clk_i = 1;
+      Clk100= 1;
+      Clk20 = 1;
+      Clk50 = 1;
+      Clk80 = 1;
+      Clk24 = 1;
+      rstForFPGA = 0;
+      Clk10 = 1;
+      pkt = new();
+      Rst_i = 1;
+      Start_i = 0;
+      CPHA_i = 0;		SpiDataVal_i = 0;
+      SELST_i = 1;//0:High, 1:Low
+    //   WidthSel_i = 2; // 3-32bit, 2-24bit, 1-16bit, 0-8bit
+      LAG_i = 0;
+      LEAD_i = 0;
+      EndianSel_i = 0; // 0:MSB first, 1:lsb first
+      PulsePol_i = 0;
+      // Reset the system
+      #(CLK_PERIOD*10) Rst_i = 0;
+      #(300000-60) rstForFPGA = 1;
+      #(CLK_PERIOD*4) rstForFPGA = 0;
+      #(20) Start_i = 1; // Start SPI transaction
+    
+  end
+//***********************************************
+
+always_ff @(posedge Clk10) begin
+    if (Rst_i) begin 
+        trCnt <= 0;
+    end
+    else begin 
+        if (Val_o) begin 
+            trCnt <= trCnt + 1;
+        end
+    end
+end
+
+genvar i;
+always_comb begin 
+    if (Rst_i) begin 
+        WidthSel_i = 2'd0;
+    end
+    else begin 
+        if (trCnt > 152 && trCnt < 159) begin 
+            WidthSel_i = 2'd3;
+        end
+        else begin 
+            WidthSel_i = 2'd2;
+        end
+    end
+end
+
+always_comb begin 
+    if (Rst_i) begin 
+        modeSel = 0;
+    end
+    else begin 
+        if (trCnt == 159) begin 
+            modeSel = 1;
+        end
+    end
+end
+
+always_comb begin 
+    if (Rst_i) begin 
+        Stop_i = 6'd0;
+    end
+    else begin 
+        if (trCnt == 158) begin 
+            Stop_i = 6'h0;
+        end
+        else begin
+            Stop_i = 6'd0;
+        end
+    end
+end
+
+always_ff @(posedge Clk10) begin 
+    if (Rst_i) begin 
+        randData<=0;
+        randData32 <= 0;
+    end
+    else begin 
+        randData <= pkt.randomize(data);
+        randData32 <= pkt.randomize(data32);
+    end
+end
+
+always_comb begin 
+    if (Rst_i) begin 
+        SPIdata = 0;
+    end
+    else begin 
+        // if (!rstInit && locked) begin
+            if (trCnt == 0) begin 
+                SPIdata = InitLMX2594Header;
+            end
+            // else if (trCnt > 0 && trCnt < 114) begin 
+            //     SPIdata = pkt.data;
+            // end
+            else if (trCnt == 114) begin 
+                SPIdata = InitDDSHeader;
+            end
+            else if (trCnt == 152) begin 
+                SPIdata = InitMAX2870Header;
+            end
+            else if (trCnt > 152 && trCnt < 159) begin 
+                // if (trCnt % 2 == 0) begin 
+                //     SPIdata = 32'haaaaaaaa;
+                // end
+                // else begin 
+                //     SPIdata = 32'h55555555;
+                // end
+                SPIdata = pkt.data32;
+            end
+            else if (trCnt == 159) begin 
+                SPIdata = AllDevQSPIHeader;
+            end
+            else begin
+                // if (trCnt % 2 == 0) begin 
+                //     SPIdata = 24'haaaaaa;
+                // end
+                // else begin 
+                //     SPIdata = 24'h555555;
+                // end
+                SPIdata = pkt.data;
+            end
+        end
+    end
+// end
+
+
+
+SPIs SPIs_inst (
+    .Clk_i(Clk100),
+    .Rst_i(Rst_i),
+    .Sck_i(sckFromRFTop[0]),
+    .Ss_i(ssFromRFTop[0]),
+    .Mosi0_i(mosiFromRFTop[0]),
+    .DataToRxFifo_o(dataFromSPItb),
+    .Val_o(valFromSPItb)
+);
+
+
+
+//***********************************************
+//	           DUT INSTANTIATION
+//***********************************************
+
+   SPIm SPIm_inst (
+        .Clk_i(Clk10), 
+        .Rst_i(Rst_i || modeSel), 
+        .Start_i(Start_i), 
+        .ClockPhase_i(CPHA_i),
+        .EmptyFlag_i(emptyFlagTx), 
+        .SpiData_i(SPIdata),
+        .SelSt_i(SELST_i),
+        .WidthSel_i(WidthSel_i),
+        .Lag_i(LAG_i),
+        .Lead_i(LEAD_i),
+        .EndianSel_i(EndianSel_i),
+        .Stop_i(Stop_i),
+        .PulsePol_i(PulsePol_i),
+        .Mosi0_o(mosi0R),
+        .Sck_o(SckR),
+        .Ss_o(SsR),
+        .Val_o(valR)
+    );
+
+
+    QuadSPIm QuadSPIm_inst (
+        .Clk_i(Clk10),
+        .Rst_i(Rst_i || !modeSel),
+        .Start_i(Start_i),
+        .ClockPhase_i(CPHA_i),
+        .EmptyFlag_i(emptyFlagTx),
+        .SpiData_i(SPIdata),
+        .SpiDataVal_i(SpiDataVal_i),
+        .SelSt_i(SELST_i),
+        .WidthSel_i(WidthSel_i),
+        .Lag_i(LAG_i),
+        .Lead_i(LEAD_i),
+        .EndianSel_i(EndianSel_i),
+        .Stop_i(Stop_i),
+        .PulsePol_i(PulsePol_i),
+        .Mosi0_i(mosi0Q),
+        .Mosi1_i(Mosi1_o),
+        .Mosi2_i(Mosi2_o),
+        .Mosi3_i(Mosi3_o),
+        .Sck_o(SckQ),
+        .Ss_o(SsQ),
+        .Val_o(valQ)
+    );
+
+
+    RFTop RFTop_inst (
+        .Clk_i(Clk24),
+        .Sck_i(Sck_o),
+        .Rst_i(rstForFPGA),
+        .Ss_i(Ss_o),
+        .Mosi0_i(Mosi0_o),
+        .Mosi1_io(Mosi1_o),
+        .Mosi2_i(Mosi2_o),
+        .Mosi3_i(Mosi3_o),
+        .Sck_o(sckFromRFTop),
+        .Mosi0_o(mosiFromRFTop),
+        .Ss_o(ssFromRFTop)
+
+    );
+
+
+
+
+    endmodule

src/src/Sim/SPIm_tb.v

@@ -1,7 +1,8 @@
-module SPIm_tb (
+module SPIm (
     input Clk_i,
     input Rst_i,
     input Start_i,
+    input EmptyFlag_i,
     input ClockPhase_i,
     input [31:0] SpiData_i,
     input SelSt_i,
@@ -29,6 +30,7 @@ module SPIm_tb (
     reg [31:0] trCnt;
     reg valReg;
     reg valToRxFifo1;
+    reg lineBusy;
     reg [5:0] ssCnt;
     reg Ss;
     reg [31:0]spiDataR;
@@ -64,7 +66,26 @@ module SPIm_tb (
         end
     end
     
-
+    
+    always @(*) begin 
+        if (SelSt_i) begin 
+            if (!Ss_o) begin 
+                lineBusy = 1'b1;
+            end
+            else begin 
+                lineBusy = 1'b0;
+            end
+        end
+        else begin 
+            if (Ss_o) begin 
+                lineBusy = 1'b1;
+            end
+            else begin 
+                lineBusy = 1'b0;
+            end
+        end
+    end
+    
     
     
     always @(posedge Clk_i) begin
@@ -79,7 +100,7 @@ module SPIm_tb (
             oldDataFlag = 1'b0;
         end
         else begin 
-            if (spiDataR == SpiData_i) begin 
+            if (spiDataR == SpiData_i && (SpiData_i != 0) || EmptyFlag_i) begin 
                 oldDataFlag = 1'b1;
             end
             else begin 
@@ -199,7 +220,7 @@ module SPIm_tb (
                         end
                     end
                     else begin 
-                        if (!Ss && (ssCnt <ssNum + Lag_i + Lead_i && ssCnt > Lag_i)) begin 
+                        if (!Ss && (ssCnt <ssNum + Lag_i + Lag_i && ssCnt > Lag_i)) begin 
                             Sck_o = ~(Clk_i);
                         end
                         else begin 
@@ -277,7 +298,7 @@ module SPIm_tb (
                         end
                     end
                     else begin 
-                        if (ssPol && (ssCnt <ssNum + Lag_i + Lead_i && ssCnt > Lag_i)) begin 
+                        if (ssPol && (ssCnt <ssNum + Lag_i + Lag_i && ssCnt > Lag_i)) begin 
                             Sck_o = ~(Clk_i);
                         end
                         else begin 
@@ -398,7 +419,7 @@ module SPIm_tb (
             startFlag = 1'b0;
         end
         else begin 
-            if (Start_i&& !stopFlag && SpiData_i != 0 && !oldDataFlag ) begin 
+            if (Start_i && !stopFlag && !EmptyFlag_i) begin 
                 startFlag = 1'b1;
             end
             else begin 
@@ -407,7 +428,7 @@ module SPIm_tb (
         end
     end
     
-    always @(posedge Clk_i) begin
+    always @(*) begin
         if (SelSt_i) begin 
             if (Ss_o && !ssR) begin 
                 valReg = 1'b1;

src/src/Sim/tb_RF_FPGA.v

@@ -48,18 +48,25 @@ module tb_SPIm;
     wire locked;
     wire rstInit;
 
-    reg [4:0] trCnt;
+    reg [16:0] trCnt;
     reg [4:0] trCntSync;
 
     reg start; 
 
     reg modeSel; 
 
-    // assign Val_o = (((modeSel)? trCnt : trCntSync) < 2 ) ? valQ:(modeSel) ? valQ:valR;
-    // assign Sck_o = (((modeSel)? trCnt : trCntSync)< 2 ) ? SckQ:(modeSel) ? SckQ:SckR;
-    // assign Ss_o = (((modeSel)? trCnt : trCntSync)<2) ? SsQ:(modeSel) ? SsQ:SsR;
-    // assign Mosi0_o = (((modeSel)? trCnt : trCntSync)< 2 ) ? mosi0Q:(modeSel) ? mosi0Q:mosi0R;
-    // assign Mosi1_io = (modeSel) ? Mosi1_o:1'bz;
+
+//***********************************************
+//	HEADERS FOR DEVICES
+//***********************************************
+
+localparam InitLMX2594Header = {1'h0, 5'h0, 17'd113, 1'h1};
+localparam InitDDSHeader = {1'h0, 5'h1, 17'd37, 1'h1};
+localparam InitMAX2870Header = {1'h0, 5'h6, 17'd6, 1'h1};
+
+
+
+
 
     assign Val_o = (modeSel) ? valQ:valR;
     assign Sck_o = (modeSel) ? SckQ:SckR;
@@ -68,28 +75,8 @@ module tb_SPIm;
     assign Mosi1_io = (modeSel) ? Mosi1_o:1'bz;
 
 
-    assign emptyFlagTx = (!locked || trCnt > 5 ) ? 1'b1 : 1'b0;
+    assign emptyFlagTx = (!locked || trCnt > 152 ) ? 1'b1 : 1'b0;
 
-    // always @(posedge Clk100) begin 
-    //     if (Rst_i) begin 
-    //         trCnt <= 5'd0;
-    //     end
-    //     else begin 
-    //         if (trCnt < 2  && trCntSync < 2 && !modeSel) begin
-    //             if (valQ) begin 
-    //                 trCnt <= trCnt + 1;
-    //             end
-    //         end
-    //         else if (trCnt < 7 && modeSel) begin 
-    //             if (valQ) begin 
-    //                 trCnt <= trCnt + 1;
-    //             end
-    //         end
-    //         else if (trCntSync >= 2 && !modeSel) begin 
-    //             trCnt <= 5'd0;
-    //         end
-    //     end
-    // end
 
 
 always @(posedge Clk10) begin 
@@ -103,37 +90,47 @@ always @(posedge Clk10) begin
     end
 end
 
+genvar i;
 
 
- always @(posedge Clk20) begin 
-    if (Rst_i) begin 
-        trCntSync <= 5'd0;
+always @(*) begin 
+    if (Rst_i) begin
+        SPIdata = 24'h0;
     end
     else begin
-        if (trCnt >= 2) begin 
-            trCntSync <= trCnt;
-        end
-        else if (Val_o && trCntSync < 7 ) begin 
-            trCntSync <= trCntSync+1;
-        end
-    end
- end
-
-
-
-
-
-
-    always @(posedge Clk20) begin 
-        if (Rst_i) begin
-            start <= 1'b0;
-        end
-        else begin 
-            if (trCnt >= 2 ) begin 
-                start <= 1'b1;
+        if (rstInit && !modeSel) begin 
+            case (trCnt)
+            0: begin 
+                SPIdata = InitLMX2594Header;
+            end
+            for (i = 1; i < 6; i = i + 1) begin 
+                i: begin 
+                    SPIdata = rand();
+                end
+            end
+            114: begin 
+                SPIdata = InitDDSHeader;
+            end
+            for (i = 115; i < 115+37; i = i + 1) begin 
+                i: begin 
+                    SPIdata = rand();
+                end
+            end
+            152: begin 
+                SPIdata = InitMAX2870Header;
+            end
+            for (i = 153; i < 153+6; i = i + 1) begin 
+                i: begin 
+                    SPIdata = rand();
+                end
+            end
+            default: begin 
+                SPIdata = 24'h0;
             end
+            endcase
         end
     end
+end
 
 
 
@@ -244,103 +241,38 @@ end
       
     end
 
-    always @(*) begin 
-        if (locked && !rstInit && !modeSel) begin 
-            case(trCnt) 
-            0: begin 
-                SPIdata = {1'h0, 5'h6, 17'h5, 1'h1};
-            end
-            // 0: begin 
-            //     SPIdata = {1'h1,4'h0, 2'h3,1'h1,1'h1,1'h0,2'h0,3'h0,2'h0, 7'h1};
-            // end
-            1 : begin 
-                SPIdata = 24'h04000;
-            end
-            2: begin 
-                SPIdata = 24'h1c003;
-            end
-            3 : begin 
-                SPIdata = 24'h040010;
-            end
-            4 : begin 
-                SPIdata = 24'h1800d;
-            end
-            5 : begin
-                SPIdata = 24'hc63f00;
-            end
-            default : begin 
-                SPIdata = 24'h0;
-            end
-            endcase
-        end
-    end
-
 
 
 
 
-    // always @(*) begin
-    //     if (locked && !rstInit && modeSel)  begin
-    //         case (trCnt) 
+    // always @(*) begin 
+    //     if (locked && !rstInit && !modeSel) begin 
+    //         case(trCnt) 
     //         0: begin 
-    //             // SPIdata = {8'haa,8'haa,7'haa,1'b0};
-    //             SPIdata = 24'h0;
-    //         end
-    //         1:begin 
-    //             SPIdata = {1'h0, 7'h2a, 16'd10};
-    //         end
-    //         2:begin 
-    //             SPIdata = {1'h1, 7'h2a, 16'd20};
+    //             SPIdata = {1'h0, 5'h6, 17'h5, 1'h1};
     //         end
-    //         3:begin 
-    //             SPIdata = {1'h0, 7'h2a, 16'd30};
+    //         // 0: begin 
+    //         //     SPIdata = {1'h1,4'h0, 2'h3,1'h1,1'h1,1'h0,2'h0,3'h0,2'h0, 7'h1};
+    //         // end
+    //         1 : begin 
+    //             SPIdata = 24'h04000;
     //         end
-    //         4:begin 
-    //             SPIdata = {1'h0, 7'h2a, 16'd40};
-    //         end
-    //         5:begin 
-    //             SPIdata = {1'h0, 7'h2a, 16'd50};
-    //         end
-    //         6:begin 
-    //             SPIdata = {1'h0, 7'h2a, 16'd60};
-    //         end
-    //         7:begin 
-    //             SPIdata = {1'h0, 7'h2a, 16'd70};
-    //         end
-    //     endcase
-    //     end
-    //     else if (locked && !rstInit && !modeSel) begin 
-    //         case (trCnt) 
-    //         0: begin 
-    //             SPIdata = 24'h555554;
-    //         end
-    //         1:begin 
-    //             SPIdata = {1'h0, 7'h2a, 16'd10};
-    //         end
-    //     endcase
-    //     case (trCntSync) 
-    //        2 : begin 
-    //         SPIdata = {1'h0, 7'h2a, 16'd20};
+    //         2: begin 
+    //             SPIdata = 24'h1c003;
     //         end
     //         3 : begin 
-    //             SPIdata = {1'h0, 7'h2a, 16'd30};
+    //             SPIdata = 24'h040010;
     //         end
     //         4 : begin 
-    //             SPIdata = {1'h0, 7'h2a, 16'd40};
+    //             SPIdata = 24'h1800d;
     //         end
-    //         5 : begin 
-    //             SPIdata = {1'h0, 7'h2a, 16'd50};
+    //         5 : begin
+    //             SPIdata = 24'hc63f00;
     //         end
-    //         6 : begin 
-    //             SPIdata = {1'h0, 7'h2a, 16'd60};
-    //         end
-    //         7 : begin 
-    //             SPIdata = {1'h0, 7'h2a, 16'd70};
+    //         default : begin 
+    //             SPIdata = 24'h0;
     //         end
-    //     endcase
-    //     end
-    //     else begin 
-    //         SPIdata = 24'h0;
+    //         endcase
     //     end
     // end
 

src/src/Top/RFTop.v

@@ -138,14 +138,14 @@ wire [15:0] tempI2CData;
 reg [1:0] numOfConfigCmds;
 //sums
 
-wire [6:0] sumForLmx = packetNum1;
-wire [6:0] sumForDDS = packetNum2 ;
-wire [6:0] sumForPot = packetNum3;
-wire [6:0] sumForDAC = packetNum4;
-wire [6:0] sumForATT = packetNum5;
-wire [6:0] sumForShiftReg = packetNum6;
-wire [6:0] sumForMAX = packetNum7;
-wire [6:0] sumForGPIO = packetNum8;
+wire [3:0] sumForLmx = packetNum1;
+wire [1:0] sumForDDS = packetNum2 ;
+wire  sumForPot = packetNum3;
+wire  sumForDAC = packetNum4;
+wire  sumForATT = packetNum5;
+wire [1:0] sumForShiftReg = packetNum6;
+wire [2:0] sumForMAX = packetNum7;
+wire [1:0] sumForGPIO = packetNum8;
 
 
 
@@ -292,6 +292,7 @@ assign GPIO_o = GPIOReg[21:0];
 
 
 
+
 always @(posedge clk100) begin 
     if (currState == IDLE) begin 
         if (RorQSPIFlag) begin 
@@ -944,10 +945,11 @@ SPImDDS #(
 
 FifoCtrl #(
     .FifoNum(FifoNum)
-) FifoCtrl_inst (
+)(* DONT_TOUCH = "yes" *)  FifoCtrl_inst (
     .WrClk_i(clk100),
     .RdClk_i(rdClk),
-    .Rst_i(!modeSel),
+    .Rst_i(rstInit),
+    .ModeSel_i(modeSel),
     .ValToRxFifo_i(valToRxFifo),
     .DataToRxFifo_i(dataToRxFifo),
     .ValToReadFromRxFifo1_i(valToReadFromRxFifo[0]),
@@ -1028,6 +1030,11 @@ InitRst RstForSynth_inst (
 
 
 
+always @(posedge clk100) begin 
+    currStateR <= currState;
+end
+
+
 
 
 
@@ -1082,30 +1089,30 @@ always @(posedge clk100 ) begin
         end
         LMX2594: begin
             if (modeSel) begin 
-                if ((cntLMX == sumForLmx) && (packetNum2 != 0)) begin 
+                if (cntLMX == sumForLmx) begin 
                     currState <= DDS;
                 end
-                else if ((cntLMX == sumForLmx) && (packetNum1 == 0)  && (packetNum2 == 0) && (packetNum3 != 0)) begin 
-                    currState <= POT;
-                end
-                else if ((cntLMX == sumForLmx) && (packetNum2 == 0) && (packetNum3 == 0) && (packetNum4 != 0)) begin 
-                    currState <= DAC;
-                end
-                else if ((cntLMX == sumForLmx) && (packetNum2 == 0) && (packetNum3 == 0) && (packetNum4 == 0) && (packetNum5 != 0)) begin 
-                    currState <= ATTENUATOR;
-                end
-                else if ((cntLMX == sumForLmx) && (packetNum2 == 0) && (packetNum3 == 0) && (packetNum4 == 0)  && (packetNum5 == 0) && (packetNum6 != 0)) begin 
-                    currState <= SHIFTREG; 
-                end
-                else if ((cntLMX == sumForLmx) && (packetNum2 == 0) && (packetNum3 == 0) && (packetNum4 == 0)  && (packetNum5 == 0) && (packetNum6 == 0) && (packetNum7 != 0)) begin 
-                    currState <= MAX2870; 
-                end
-                else if ((cntLMX == sumForLmx) && (packetNum2 == 0) && (packetNum3 == 0) && (packetNum4 == 0)  && (packetNum5 == 0) && (packetNum6 == 0) && (packetNum7 == 0) && (packetNum8 != 0)) begin 
-                    currState <= GPIO; 
-                end
-                else if ((cntLMX == sumForLmx) && (packetNum2 == 0) && (packetNum3 == 0) && (packetNum4 == 0)  && (packetNum5 == 0) && (packetNum6 == 0) && (packetNum7 == 0) && (packetNum8 == 0)) begin 
-                    currState <= IDLE; 
-                end
+                // else if ((cntLMX == sumForLmx) && (packetNum1 == 0)  && (packetNum2 == 0) && (packetNum3 != 0)) begin 
+                //     currState <= POT;
+                // end
+                // else if ((cntLMX == sumForLmx) && (packetNum2 == 0) && (packetNum3 == 0) && (packetNum4 != 0)) begin 
+                //     currState <= DAC;
+                // end
+                // else if ((cntLMX == sumForLmx) && (packetNum2 == 0) && (packetNum3 == 0) && (packetNum4 == 0) && (packetNum5 != 0)) begin 
+                //     currState <= ATTENUATOR;
+                // end
+                // else if ((cntLMX == sumForLmx) && (packetNum2 == 0) && (packetNum3 == 0) && (packetNum4 == 0)  && (packetNum5 == 0) && (packetNum6 != 0)) begin 
+                //     currState <= SHIFTREG; 
+                // end
+                // else if ((cntLMX == sumForLmx) && (packetNum2 == 0) && (packetNum3 == 0) && (packetNum4 == 0)  && (packetNum5 == 0) && (packetNum6 == 0) && (packetNum7 != 0)) begin 
+                //     currState <= MAX2870; 
+                // end
+                // else if ((cntLMX == sumForLmx) && (packetNum2 == 0) && (packetNum3 == 0) && (packetNum4 == 0)  && (packetNum5 == 0) && (packetNum6 == 0) && (packetNum7 == 0) && (packetNum8 != 0)) begin 
+                //     currState <= GPIO; 
+                // end
+                // else if ((cntLMX == sumForLmx) && (packetNum2 == 0) && (packetNum3 == 0) && (packetNum4 == 0)  && (packetNum5 == 0) && (packetNum6 == 0) && (packetNum7 == 0) && (packetNum8 == 0)) begin 
+                //     currState <= IDLE; 
+                // end
                 else if (cntLMX != sumForLmx) begin 
                     currState <= LMX2594;
                 end
@@ -1123,27 +1130,27 @@ always @(posedge clk100 ) begin
         end
         DDS: begin
             if (modeSel) begin 
-                if ((cntDDS == sumForDDS) && (packetNum3 != 0)) begin 
+                if ((cntDDS == sumForDDS)) begin 
                     currState <= POT;
                 end
-                else if ((cntDDS == sumForDDS) && (packetNum3 == 0) && (packetNum4 != 0)) begin 
-                    currState <= DAC;
-                end
-                else if ((cntDDS == sumForDDS) && (packetNum3 == 0) && (packetNum4 == 0) && (packetNum5 != 0) ) begin 
-                    currState <= ATTENUATOR;
-                end
-                else if ((cntDDS == sumForDDS) && (packetNum3 == 0) && (packetNum4 == 0) && (packetNum5 == 0) && (packetNum6 != 0)) begin 
-                    currState <= SHIFTREG;
-                end
-                else if ((cntDDS == sumForDDS) && (packetNum3 == 0) && (packetNum4 == 0) && (packetNum5 == 0) && (packetNum6 == 0 ) && (packetNum7 != 0)) begin 
-                    currState <= MAX2870;
-                end
-                else if ((cntDDS == sumForDDS) && (packetNum3 == 0) && (packetNum4 == 0 ) && (packetNum5 == 0) && (packetNum6 == 0) && (packetNum7 == 0) && (packetNum8 != 0)) begin 
-                    currState <= GPIO;
-                end
-                else if ((cntDDS == sumForDDS ) && (packetNum3 == 0) && (packetNum4 == 0) && (packetNum5 == 0) && (packetNum6 == 0) && (packetNum7 == 0) && (packetNum8 == 0)) begin 
-                    currState <= IDLE;
-                end
+                // else if ((cntDDS == sumForDDS) && (packetNum3 == 0) && (packetNum4 != 0)) begin 
+                //     currState <= DAC;
+                // end
+                // else if ((cntDDS == sumForDDS) && (packetNum3 == 0) && (packetNum4 == 0) && (packetNum5 != 0) ) begin 
+                //     currState <= ATTENUATOR;
+                // end
+                // else if ((cntDDS == sumForDDS) && (packetNum3 == 0) && (packetNum4 == 0) && (packetNum5 == 0) && (packetNum6 != 0)) begin 
+                //     currState <= SHIFTREG;
+                // end
+                // else if ((cntDDS == sumForDDS) && (packetNum3 == 0) && (packetNum4 == 0) && (packetNum5 == 0) && (packetNum6 == 0 ) && (packetNum7 != 0)) begin 
+                //     currState <= MAX2870;
+                // end
+                // else if ((cntDDS == sumForDDS) && (packetNum3 == 0) && (packetNum4 == 0 ) && (packetNum5 == 0) && (packetNum6 == 0) && (packetNum7 == 0) && (packetNum8 != 0)) begin 
+                //     currState <= GPIO;
+                // end
+                // else if ((cntDDS == sumForDDS ) && (packetNum3 == 0) && (packetNum4 == 0) && (packetNum5 == 0) && (packetNum6 == 0) && (packetNum7 == 0) && (packetNum8 == 0)) begin 
+                //     currState <= IDLE;
+                // end
                 else if (cntDDS != sumForDDS) begin 
                     currState <= DDS;
                 end
@@ -1161,24 +1168,24 @@ always @(posedge clk100 ) begin
         end
         POT: begin
             if (modeSel) begin 
-                if ((cntPot == sumForPot) && (packetNum4 != 0)) begin 
+                if (cntPot == sumForPot) begin 
                     currState <= DAC;
                 end
-                else if ((cntPot == sumForPot) && (packetNum4 == 0) && (packetNum5 != 0)) begin 
-                    currState <= ATTENUATOR;
-                end
-                else if ((cntPot == sumForPot) && (packetNum4 == 0) && (packetNum5 == 0) && (packetNum6 != 0)) begin 
-                    currState <= SHIFTREG;
-                end
-                else if ((cntPot == sumForPot) && (packetNum4 == 0) && (packetNum5 == 0) && (packetNum6 == 0) && (packetNum7 != 0)) begin 
-                    currState <= MAX2870;
-                end
-                else if ((cntPot == sumForPot) && (packetNum4 == 0) && (packetNum5 == 0) && (packetNum6 == 0) && (packetNum7 == 0) && (packetNum8 != 0)) begin 
-                    currState <= GPIO;
-                end
-                else if ((cntPot == sumForPot) && (packetNum4 == 0) && (packetNum5 == 0) && (packetNum6 == 0) && (packetNum7 == 0) && (packetNum8 == 0)) begin 
-                    currState <= IDLE;
-                end
+                // else if ((cntPot == sumForPot) && (packetNum4 == 0) && (packetNum5 != 0)) begin 
+                //     currState <= ATTENUATOR;
+                // end
+                // else if ((cntPot == sumForPot) && (packetNum4 == 0) && (packetNum5 == 0) && (packetNum6 != 0)) begin 
+                //     currState <= SHIFTREG;
+                // end
+                // else if ((cntPot == sumForPot) && (packetNum4 == 0) && (packetNum5 == 0) && (packetNum6 == 0) && (packetNum7 != 0)) begin 
+                //     currState <= MAX2870;
+                // end
+                // else if ((cntPot == sumForPot) && (packetNum4 == 0) && (packetNum5 == 0) && (packetNum6 == 0) && (packetNum7 == 0) && (packetNum8 != 0)) begin 
+                //     currState <= GPIO;
+                // end
+                // else if ((cntPot == sumForPot) && (packetNum4 == 0) && (packetNum5 == 0) && (packetNum6 == 0) && (packetNum7 == 0) && (packetNum8 == 0)) begin 
+                //     currState <= IDLE;
+                // end
                 else if (cntPot != sumForPot) begin 
                     currState <= POT;
                 end
@@ -1196,21 +1203,21 @@ always @(posedge clk100 ) begin
         end
         DAC: begin
             if (modeSel) begin 
-                if ((cntDAC == sumForDAC) && (packetNum5 != 0) ) begin 
+                if (cntDAC == sumForDAC) begin 
                     currState <= ATTENUATOR;
                 end
-                else if ((cntDAC == sumForDAC) && (packetNum5 == 0) && (packetNum6 != 0)) begin 
-                    currState <= SHIFTREG;
-                end
-                else if ((cntDAC == sumForDAC) && (packetNum5 == 0) && (packetNum6 == 0) && (packetNum7 != 0)) begin 
-                    currState <= MAX2870;
-                end
-                else if ((cntDAC == sumForDAC) && (packetNum5 == 0) && (packetNum6 == 0) && (packetNum7 == 0) && (packetNum8 != 0)) begin 
-                    currState <= GPIO;
-                end
-                else if ((cntDAC == sumForDAC) && (packetNum5 == 0) && (packetNum6 == 0) && (packetNum7 == 0) && (packetNum8 == 0)) begin 
-                    currState <= IDLE;
-                end
+                // else if ((cntDAC == sumForDAC) && (packetNum5 == 0) && (packetNum6 != 0)) begin 
+                //     currState <= SHIFTREG;
+                // end
+                // else if ((cntDAC == sumForDAC) && (packetNum5 == 0) && (packetNum6 == 0) && (packetNum7 != 0)) begin 
+                //     currState <= MAX2870;
+                // end
+                // else if ((cntDAC == sumForDAC) && (packetNum5 == 0) && (packetNum6 == 0) && (packetNum7 == 0) && (packetNum8 != 0)) begin 
+                //     currState <= GPIO;
+                // end
+                // else if ((cntDAC == sumForDAC) && (packetNum5 == 0) && (packetNum6 == 0) && (packetNum7 == 0) && (packetNum8 == 0)) begin 
+                //     currState <= IDLE;
+                // end
                 else if (cntDAC != sumForDAC) begin 
                     currState <= DAC;
                 end
@@ -1228,18 +1235,18 @@ always @(posedge clk100 ) begin
         end
         ATTENUATOR: begin
             if (modeSel) begin 
-                if ((cntATT == sumForATT) && (packetNum6 != 0) ) begin 
+                if (cntATT == sumForATT) begin 
                     currState <= SHIFTREG;
                 end
-                else if ((cntATT == sumForATT) && (packetNum6 == 0) && (packetNum7 != 0)) begin 
-                    currState <= MAX2870;
-                end
-                else if ((cntATT == sumForATT) && (packetNum6 == 0) && (packetNum7 == 0) && (packetNum8 != 0)) begin 
-                    currState <= GPIO;
-                end
-                else if ((cntATT == sumForATT) && (packetNum6 == 0) && (packetNum7 == 0) && (packetNum8 == 0)) begin 
-                    currState <= IDLE;
-                end
+                // else if ((cntATT == sumForATT) && (packetNum6 == 0) && (packetNum7 != 0)) begin 
+                //     currState <= MAX2870;
+                // end
+                // else if ((cntATT == sumForATT) && (packetNum6 == 0) && (packetNum7 == 0) && (packetNum8 != 0)) begin 
+                //     currState <= GPIO;
+                // end
+                // else if ((cntATT == sumForATT) && (packetNum6 == 0) && (packetNum7 == 0) && (packetNum8 == 0)) begin 
+                //     currState <= IDLE;
+                // end
                 else if (cntATT != sumForATT) begin 
                     currState <= ATTENUATOR;
                 end
@@ -1257,15 +1264,15 @@ always @(posedge clk100 ) begin
         end
         SHIFTREG : begin 
             if (modeSel) begin 
-                if ((cntShiftReg == sumForShiftReg) && (packetNum7 != 0) ) begin 
+                if (cntShiftReg == sumForShiftReg) begin 
                     currState <= MAX2870;
                 end
-                else if ((cntShiftReg == sumForShiftReg) && (packetNum7 == 0) && (packetNum8 != 0)) begin 
-                    currState <= GPIO;
-                end
-                else if ((cntShiftReg == sumForShiftReg) && (packetNum7 == 0) && (packetNum8 == 0)) begin 
-                    currState <= IDLE;
-                end
+                // else if ((cntShiftReg == sumForShiftReg) && (packetNum7 == 0) && (packetNum8 != 0)) begin 
+                //     currState <= GPIO;
+                // end
+                // else if ((cntShiftReg == sumForShiftReg) && (packetNum7 == 0) && (packetNum8 == 0)) begin 
+                //     currState <= IDLE;
+                // end
                 else if (cntShiftReg != sumForShiftReg) begin 
                     currState <= SHIFTREG;
                 end
@@ -1283,12 +1290,12 @@ always @(posedge clk100 ) begin
         end  
         MAX2870 : begin 
             if (modeSel) begin 
-                if ((cntMAX == sumForMAX) && (packetNum8 != 0))  begin 
+                if (cntMAX == sumForMAX)  begin 
                     currState <= GPIO;
                 end
-                else if ((cntMAX == sumForMAX) && (packetNum8 == 0)) begin 
-                    currState <= IDLE;
-                end
+                // else if ((cntMAX == sumForMAX) && (packetNum8 == 0)) begin 
+                //     currState <= IDLE;
+                // end
                 else if (cntMAX != sumForMAX) begin 
                     currState <= MAX2870;
                 end

src/src/fifo_top/FifoCtrl.v

@@ -8,6 +8,7 @@ input[FifoNum-1:0]  RdClk_i,
 input [4:0] CurrState_i,
 input [2:0] DDSFifoCnt_i,
 input [2:0] MAX2870FifoCnt_i,
+input ModeSel_i,
 input ValToReadFromRxFifo1_i,
 input ValToReadFromRxFifo2_i,
 input ValToReadFromRxFifo3_i,
@@ -220,7 +221,7 @@ always @(posedge WrClk_i) begin
             rxFifoWrEn <= 1'b0;
         end
         1: begin 
-            if (!fullFlag[0] && ValToRxFifo_i) begin 
+            if (!fullFlag[0] && ValToRxFifo_i && ModeSel_i) begin 
                     rxFifoWrEn[0] <= 1'b1;
                 end
                 else begin 
@@ -228,7 +229,7 @@ always @(posedge WrClk_i) begin
                 end
         end
         2: begin 
-            if (!fullFlag[1] && ValToRxFifo_i && DDSFifoCnt_i == 3'h2 ) begin 
+            if (!fullFlag[1] && ValToRxFifo_i && DDSFifoCnt_i == 3'h2 && ModeSel_i) begin 
                     rxFifoWrEn[1] <= 1'b1;
                 end
                 else begin 
@@ -236,7 +237,7 @@ always @(posedge WrClk_i) begin
                 end
         end
         3: begin 
-            if (!fullFlag[2] && ValToRxFifo_i) begin 
+            if (!fullFlag[2] && ValToRxFifo_i && ModeSel_i ) begin 
                     rxFifoWrEn[2] <= 1'b1;
                 end
                 else begin 
@@ -244,7 +245,7 @@ always @(posedge WrClk_i) begin
                 end
         end
         4: begin 
-            if (!fullFlag[3] && ValToRxFifo_i) begin 
+            if (!fullFlag[3] && ValToRxFifo_i && ModeSel_i) begin 
                     rxFifoWrEn[3] <= 1'b1;
                 end
                 else begin 
@@ -252,7 +253,7 @@ always @(posedge WrClk_i) begin
                 end
         end
         5: begin 
-            if (!fullFlag[4] && ValToRxFifo_i) begin 
+            if (!fullFlag[4] && ValToRxFifo_i && ModeSel_i ) begin 
                     rxFifoWrEn[4] <= 1'b1;
                 end
                 else begin 
@@ -260,7 +261,7 @@ always @(posedge WrClk_i) begin
                 end
         end
         6: begin 
-            if (!fullFlag[5] && ValToRxFifo_i) begin 
+            if (!fullFlag[5] && ValToRxFifo_i && ModeSel_i) begin 
                     rxFifoWrEn[5] <= 1'b1;
                 end
                 else begin 
@@ -268,7 +269,7 @@ always @(posedge WrClk_i) begin
                 end
         end
         7: begin 
-            if (!fullFlag[6] && ValToRxFifo_i && MAX2870FifoCnt_i == 3'h1) begin 
+            if (!fullFlag[6] && ValToRxFifo_i && MAX2870FifoCnt_i == 3'h1 && ModeSel_i) begin 
                     rxFifoWrEn[6] <= 1'b1;
                 end
                 else begin 

src/src/gowin_rpll/gClkGen.ipc

@@ -20,7 +20,7 @@ CLKOUT_BYPASS=false
 CLKOUT_DIVIDE_DYN=true
 CLKOUT_FREQ=100
 CLKOUT_TOLERANCE=0
-DYNAMIC=true
+DYNAMIC=false
 LANG=0
 LOCK_EN=true
 MODE_GENERAL=true

src/src/gowin_rpll/gClkGen.mod

@@ -19,14 +19,13 @@
 -dyn_odiv_sel false
 -odiv_sel 4
 -dyn_sdiv_sel 20
--dyn_da_en true
+-dyn_da_en false
 -rst_sig false
 -rst_sig_p false
 -fclkin 24
 -clkfb_sel 0
 -en_lock true
 -clkout_bypass false
--clkout_ft_dir 1
 -en_clkoutp false
 -clkoutp_bypass false
 -en_clkoutd true

src/src/gowin_rpll/gClkGen.v

@@ -5,7 +5,7 @@
 //Part Number: GW1N-LV9PG256C6/I5
 //Device: GW1N-9
 //Device Version: C
-//Created Time: Wed Mar  6 11:33:52 2024
+//Created Time: Mon Apr 15 11:33:00 2024
 
 module gClkGen (clkout, lock, clkoutd, clkin);
 
@@ -46,7 +46,7 @@ defparam rpll_inst.FBDIV_SEL = 24;
 defparam rpll_inst.DYN_ODIV_SEL = "false";
 defparam rpll_inst.ODIV_SEL = 4;
 defparam rpll_inst.PSDA_SEL = "0000";
-defparam rpll_inst.DYN_DA_EN = "true";
+defparam rpll_inst.DYN_DA_EN = "false";
 defparam rpll_inst.DUTYDA_SEL = "1000";
 defparam rpll_inst.CLKOUT_FT_DIR = 1'b1;
 defparam rpll_inst.CLKOUTP_FT_DIR = 1'b1;

src/src/gowin_rpll/gClkGen_tmp.v

@@ -5,7 +5,7 @@
 //Part Number: GW1N-LV9PG256C6/I5
 //Device: GW1N-9
 //Device Version: C
-//Created Time: Wed Mar  6 11:33:52 2024
+//Created Time: Mon Apr 15 11:33:00 2024
 
 //Change the instance name and port connections to the signal names
 //--------Copy here to design--------