Перевели автомат в синхронный режим. Переключение состояний корректное(в железе). Некорретная работа Fifo или SPIm для устройств LMX2594,DDS.

src/src/Sim/tb_RF_FPGA.v

@@ -11,7 +11,8 @@ module tb_SPIm;
     reg Clk20;
     reg Clk80;
     reg Clk50;
-    reg Clk24; 
+    reg Clk24;
+    reg Clk10; 
     reg Rst_i;
     reg Start_i;
     reg CPHA_i;
@@ -91,12 +92,12 @@ module tb_SPIm;
     // end
 
 
-always @(posedge Clk20) begin 
+always @(posedge Clk10) begin 
     if (Rst_i) begin 
         trCnt <= 5'd0;
     end
     else begin 
-        if (valR) begin 
+        if (Val_o) begin 
             trCnt <= trCnt + 1;
         end
     end
@@ -140,7 +141,7 @@ end
 
 
     SPIm_tb SPIm_inst (
-        .Clk_i(Clk20), 
+        .Clk_i(Clk10), 
         .Rst_i(Rst_i), 
         .Start_i(Start_i), 
         .ClockPhase_i(CPHA_i), 
@@ -161,7 +162,7 @@ end
 
 
     QuadSPIm QuadSPIm_inst (
-        .Clk_i(Clk20),
+        .Clk_i(Clk10),
         .Rst_i(Rst_i),
         .Start_i(Start_i),
         .ClockPhase_i(CPHA_i),
@@ -212,6 +213,7 @@ end
     always #(12.5/2) Clk80 = ~Clk80;
     always #(41.67/2) Clk24 = ~Clk24;
     always #(50/2) Clk20 = ~Clk20;
+    always #(50)   Clk10 = ~Clk10; 
 
     // Initial setup and test sequence
     initial begin
@@ -222,11 +224,12 @@ end
         Clk50 = 1;
         Clk80 = 1;
         Clk24 = 1;
+        Clk10 = 1;
         Rst_i = 1;
         Start_i = 0;
         CPHA_i = 0;
 		SpiDataVal_i = 0;
-        modeSel = 1;
+        modeSel = 0;
         SELST_i = 1;//0:High, 1:Low
         WidthSel_i = 2; // 3-32bit, 2-24bit, 1-16bit, 0-8bit
         LAG_i = 0;
@@ -242,14 +245,14 @@ end
     end
 
     always @(*) begin 
-        if (locked && !rstInit && modeSel) begin 
+        if (locked && !rstInit && !modeSel) begin 
             case(trCnt) 
-            // 0: begin 
-            //     SPIdata = {1'h1, 5'h6, 17'h4, 1'h0};
-            // end
             0: begin 
-                SPIdata = {1'h1,4'h0, 2'h3,1'h1,1'h1,1'h0,2'h0,3'h0,2'h0, 7'h1};
+                SPIdata = {1'h0, 5'h6, 17'h5, 1'h1};
             end
+            // 0: begin 
+            //     SPIdata = {1'h1,4'h0, 2'h3,1'h1,1'h1,1'h0,2'h0,3'h0,2'h0, 7'h1};
+            // end
             1 : begin 
                 SPIdata = 24'h04000;
             end

src/src/Top/RFTop.v

@@ -138,14 +138,14 @@ wire [15:0] tempI2CData;
 reg [1:0] numOfConfigCmds;
 //sums
 
-wire [6:0] sumForLmx = numOfConfigCmds+packetNum1;
-wire [6:0] sumForDDS = numOfConfigCmds + packetNum1 + packetNum2 ;
-wire [6:0] sumForPot = numOfConfigCmds + packetNum1 + packetNum2 + packetNum3;
-wire [6:0] sumForDAC = numOfConfigCmds + packetNum1 + packetNum2 + packetNum3 + packetNum4;
-wire [6:0] sumForATT = numOfConfigCmds + packetNum1 + packetNum2 + packetNum3 + packetNum4 + packetNum5;
-wire [6:0] sumForShiftReg = numOfConfigCmds + packetNum1 + packetNum2 + packetNum3 + packetNum4 + packetNum5 + packetNum6;
-wire [6:0] sumForMAX = numOfConfigCmds + packetNum1 + packetNum2 + packetNum3 + packetNum4 + packetNum5 + packetNum6 + packetNum7;
-wire [6:0] sumForGPIO = numOfConfigCmds + packetNum1 + packetNum2 + packetNum3 + packetNum4 + packetNum5 + packetNum6 + packetNum7 + packetNum8;
+wire [6:0] sumForLmx = packetNum1;
+wire [6:0] sumForDDS = packetNum2 ;
+wire [6:0] sumForPot = packetNum3;
+wire [6:0] sumForDAC = packetNum4;
+wire [6:0] sumForATT = packetNum5;
+wire [6:0] sumForShiftReg = packetNum6;
+wire [6:0] sumForMAX = packetNum7;
+wire [6:0] sumForGPIO = packetNum8;
 
 
 
@@ -159,6 +159,14 @@ reg [15:0] tempI2CDataReg;
 reg [Width-1:0] dataToRxFifoReg;
 reg             valToRxFifoReg;
 reg [16:0] trCntReg;
+reg [3:0]  cntLMX;
+reg [1:0]  cntDDS;
+reg   cntPot;
+reg   cntDAC;
+reg   cntATT;
+reg [1:0]  cntShiftReg;
+reg [2:0]  cntMAX;
+reg [1:0]  cntGPIO;
 reg [16:0] trCntRR;
 
 //================================================================================
@@ -166,6 +174,7 @@ reg [16:0] trCntRR;
 
 
 reg [4:0] currState;
+reg [4:0] currStateR;
 reg [4:0] nextState;
 
 reg [Width-1:0] configReg1;
@@ -281,6 +290,8 @@ assign GPIO_o = GPIOReg[21:0];
 
 
 
+
+
 always @(posedge clk100) begin 
     if (currState == IDLE) begin 
         if (RorQSPIFlag) begin 
@@ -498,34 +509,6 @@ end
 
 
 
-// always @(posedge clk100) begin 
-//     if (Rst_i || rstInit) begin 
-//         configReg1 <= 24'h0;
-//         configReg2 <= 24'h0;
-//     end
-//     else begin 
-//         if (currState == IDLE && valToRxFifo) begin 
-//             configReg1 <=dataToRxFifo;
-//         end
-//         else if (currState == IDLE && terminateBit == 0 && (trCnt == numOfConfigCmds)) begin 
-//             configReg2 <=dataToRxFifo;
-//         end
-//         if (terminateBit == 1 ) begin 
-//             configReg2 <= 24'h0;
-//         end
-//         if (modeSel) begin 
-//             if (trCnt == packetNum1 + packetNum2 + packetNum3 + packetNum4 + packetNum5 + packetNum6 + packetNum7 + packetNum8 + numOfConfigCmds && trCnt != 0 && currState != IDLE) begin 
-//                 configReg1 <= 24'h0;
-//             end
-//         end
-//         if (!modeSel) begin 
-//             if (trCnt1Spi == wordNum && wordNum != 0) begin 
-//                 configReg1 <= 24'h0;
-//             end
-//         end  
-//     end
-// end
-
 always @(posedge clk100) begin 
     if (Rst_i || rstInit) begin 
         configReg1 <= 24'h0;
@@ -535,11 +518,11 @@ always @(posedge clk100) begin
             configReg1 <=dataToRxFifo;
         end
         else begin 
-            if (modeSel) begin 
-                if ((trCnt == sumForGPIO) && (trCnt != 0)) begin 
-                    configReg1 <= 24'h0;
-                end
-            end
+            // if (modeSel) begin 
+            //     if ((currState == IDLE) && (trCnt == 0)) begin 
+            //         configReg1 <= 24'h0;
+            //     end
+            // end
             if (!modeSel) begin 
                 if ((trCnt1Spi == wordNum) && (wordNum != 0)) begin 
                     configReg1 <= 24'h0;
@@ -574,40 +557,18 @@ always @(posedge clk100) begin
 end
 
 
-
-// always @(posedge clk100) begin 
-//     if (Rst_i || rstInit ) begin 
-//         trCnt <= 0;
-//     end
-//     else begin 
-//         else if (modeSel) begin
-//             if (trCnt == packetNum1 + packetNum2 + packetNum3 + packetNum4 + packetNum5 + packetNum6 + packetNum7 + packetNum8 + numOfConfigCmds && trCnt != 0 ) begin 
-//                 trCnt <= 0;
-//             end
-//         end
-//         else if (!modeSel) begin 
-//             if (currState != IDLE) begin 
-//                 trCnt <= 0;
-//             end
-//             else begin 
-//                 if (trCnt >= 2) begin 
-//                     trCnt <= 0;
-//                 end
-//             end
-//         end
-//     end
-// end
-
 always @(posedge clk100) begin 
     if (Rst_i || rstInit) begin 
         trCnt <= 0;
     end
     else begin 
-        if (modeSel) begin 
-            if (valToRxFifo) begin 
-                trCnt <= trCnt + 1;
+        if (modeSel) begin
+            if (currState == IDLE) begin  
+                if (valToRxFifo) begin 
+                    trCnt <= trCnt + 1;
+                end
             end
-            else if (trCnt == packetNum1 + packetNum2 + packetNum3 + packetNum4 + packetNum5 + packetNum6 + packetNum7 + packetNum8 + numOfConfigCmds) begin 
+            else begin 
                 trCnt <= 0;
             end
         end
@@ -625,6 +586,135 @@ always @(posedge clk100) begin
 end
 
 
+always @(posedge clk100) begin 
+    if (Rst_i || rstInit) begin 
+        cntLMX <= 0;
+    end
+    else begin 
+        if (currState == LMX2594) begin 
+            if (valToRxFifo) begin 
+                cntLMX <= cntLMX + 1;
+            end
+        end
+        else begin 
+            cntLMX <= 0;
+        end
+    end
+end
+
+always @(posedge clk100) begin 
+    if (Rst_i || rstInit) begin 
+        cntDDS <= 0;
+    end
+    else begin 
+        if (currState == DDS) begin 
+            if (valToRxFifo) begin 
+                cntDDS <= cntDDS + 1;
+            end
+        end
+        else begin 
+            cntDDS <= 0;
+        end
+    end
+end
+
+always @(posedge clk100) begin 
+    if (Rst_i || rstInit) begin 
+        cntPot <= 0;
+    end
+    else begin 
+        if (currState == POT) begin 
+            if (valToRxFifo) begin 
+                cntPot <= cntPot + 1;
+            end
+        end
+        else begin 
+            cntPot <= 0;
+        end
+    end
+end
+
+always @(posedge clk100) begin 
+    if (Rst_i || rstInit) begin 
+        cntDAC <= 0;
+    end
+    else begin 
+        if (currState == DAC) begin 
+            if (valToRxFifo) begin 
+                cntDAC <= cntDAC + 1;
+            end
+        end
+        else begin 
+            cntDAC <= 0;
+        end
+    end
+end
+
+always @(posedge clk100) begin 
+    if (Rst_i || rstInit) begin 
+        cntATT <= 0;
+    end
+    else begin 
+        if (currState == ATTENUATOR) begin 
+            if (valToRxFifo) begin 
+                cntATT <= cntATT + 1;
+            end
+        end
+        else begin 
+            cntATT <= 0;
+        end
+    end
+end
+
+always @(posedge clk100) begin 
+    if (Rst_i || rstInit) begin 
+        cntShiftReg <= 0;
+    end
+    else begin 
+        if (currState == SHIFTREG) begin 
+            if (valToRxFifo) begin 
+                cntShiftReg <= cntShiftReg + 1;
+            end
+        end
+        else begin 
+            cntShiftReg <= 0;
+        end
+    end
+end
+
+always @(posedge clk100) begin 
+    if (Rst_i || rstInit) begin 
+        cntMAX <= 0;
+    end
+    else begin 
+        if (currState == MAX2870) begin 
+            if (valToRxFifo) begin 
+                cntMAX <= cntMAX + 1;
+            end
+        end
+        else begin 
+            cntMAX <= 0;
+        end
+    end
+end
+
+always @(posedge clk100) begin 
+    if (Rst_i || rstInit) begin 
+        cntGPIO <= 0;
+    end
+    else begin 
+        if (currState == GPIO) begin 
+            if (valToRxFifo) begin 
+                cntGPIO <= cntGPIO + 1;
+            end
+        end
+        else begin 
+            cntGPIO <= 0;
+        end
+    end
+end
+
+
 
 always @(posedge clk100) begin 
     if (Rst_i) begin 
@@ -922,14 +1012,17 @@ InitRst RstForSynth_inst (
 
 
 
-always @(posedge clk100) begin 
-    if (Rst_i || rstInit) begin 
-        currState <= IDLE;
-    end else begin 
-        currState <= nextState;
-    end
-end
+// always @(posedge clk100) begin 
+//     if (Rst_i || rstInit) begin 
+//         currState <= IDLE;
+//     end else begin 
+//         currState <= nextState;
+//     end
+// end
 
+// always @(posedge clk100) begin 
+//     currStateR <= currState;
+// end
 
 
 
@@ -939,315 +1032,315 @@ end
 
 
 
-always @(*) begin 
+always @(posedge clk100 ) begin 
     if (Rst_i || rstInit) begin
-        nextState = IDLE;
+        currState <= IDLE;
     end
     else begin
         case(currState)
         IDLE: begin 
             if (modeSel) begin 
-                if ((trCntReg == numOfConfigCmds) && (packetNum1 != 0) ) begin
-                    nextState = LMX2594;
+                if ((trCntReg == 17'h1) && (packetNum1 != 0) ) begin
+                    currState <= LMX2594;
                 end
-                else if ((trCntReg == numOfConfigCmds) && (packetNum1 == 0) && (packetNum2 != 0) ) begin 
-                    nextState = DDS;
+                else if ((trCntReg == 17'h1) && (packetNum1 == 0) && (packetNum2 != 0) ) begin 
+                    currState <= DDS;
                 end
-                else if ((trCntReg == numOfConfigCmds) && (packetNum1 == 0) && (packetNum2 == 0) && (packetNum3 != 0)) begin 
-                    nextState = POT; 
+                else if ((trCntReg == 17'h1) && (packetNum1 == 0) && (packetNum2 == 0) && (packetNum3 != 0)) begin 
+                    currState <= POT; 
                 end
-                else if ((trCntReg == numOfConfigCmds) && (packetNum1 == 0) && (packetNum2 == 0) && (packetNum3 == 0) && (packetNum4 != 0)) begin 
-                    nextState = DAC;
+                else if ((trCntReg == 17'h1) && (packetNum1 == 0) && (packetNum2 == 0) && (packetNum3 == 0) && (packetNum4 != 0)) begin 
+                    currState <= DAC;
                 end
-                else if ((trCntReg == numOfConfigCmds) && (packetNum1 == 0) && (packetNum2 == 0) && (packetNum3 == 0) && (packetNum4 == 0) && (packetNum5 != 0) ) begin 
-                    nextState = ATTENUATOR;
+                else if ((trCntReg == 17'h1) && (packetNum1 == 0) && (packetNum2 == 0) && (packetNum3 == 0) && (packetNum4 == 0) && (packetNum5 != 0) ) begin 
+                    currState <= ATTENUATOR;
                 end
-                else if ((trCntReg == numOfConfigCmds)  && (packetNum1 == 0) && (packetNum2 == 0) && (packetNum3 == 0) && (packetNum4 == 0) && (packetNum5 == 0) && (packetNum6 != 0)) begin 
-                    nextState = SHIFTREG;
+                else if ((trCntReg == 17'h1)  && (packetNum1 == 0) && (packetNum2 == 0) && (packetNum3 == 0) && (packetNum4 == 0) && (packetNum5 == 0) && (packetNum6 != 0)) begin 
+                    currState <= SHIFTREG;
                 end
-                else if ((trCntReg == numOfConfigCmds) && (packetNum1 == 0) && (packetNum2 == 0) && (packetNum3 == 0) && (packetNum4 == 0) && (packetNum5 == 0) && (packetNum6 == 0) && (packetNum7 != 0)) begin 
-                    nextState = MAX2870;
+                else if ((trCntReg == 17'h1) && (packetNum1 == 0) && (packetNum2 == 0) && (packetNum3 == 0) && (packetNum4 == 0) && (packetNum5 == 0) && (packetNum6 == 0) && (packetNum7 != 0)) begin 
+                    currState <= MAX2870;
                 end
-                else if ((trCntReg == numOfConfigCmds) && (packetNum1 == 0) && (packetNum2 == 0) && (packetNum3 == 0) && (packetNum4 == 0) && (packetNum5 == 0) && (packetNum6 == 0) && (packetNum7 == 0) && (packetNum8 != 0)) begin 
-                    nextState = GPIO;
+                else if ((trCntReg == 17'h1) && (packetNum1 == 0) && (packetNum2 == 0) && (packetNum3 == 0) && (packetNum4 == 0) && (packetNum5 == 0) && (packetNum6 == 0) && (packetNum7 == 0) && (packetNum8 != 0)) begin 
+                    currState <= GPIO;
                 end
                 else if ((trCntReg == 17'h1) && (packetNum1 == 0) && (packetNum2 == 0) && (packetNum3 == 0) && (packetNum4 == 0) && (packetNum5 == 0) && (packetNum6 == 0) && (packetNum7 == 0 ) && (packetNum8 == 0)) begin 
-                    nextState = IDLE;
+                    currState <= IDLE;
                 end
                 else begin 
-                    nextState = IDLE;
+                    currState <= IDLE;
                 end  
             end
             else begin 
                 if ( trCntReg== 16'h1) begin 
-                    nextState = deviceID + 1;
+                    currState <= deviceID + 1;
                 end
                 else begin 
-                    nextState = IDLE;
+                    currState <= IDLE;
                 end
             end 
         end
         LMX2594: begin
             if (modeSel) begin 
-                if ((trCntReg == sumForLmx) && (packetNum2 != 0)) begin 
-                    nextState = DDS;
+                if ((cntLMX == sumForLmx) && (packetNum2 != 0)) begin 
+                    currState <= DDS;
                 end
-                else if ((trCntReg == sumForLmx) && (packetNum1 == 0)  && (packetNum2 == 0) && (packetNum3 != 0)) begin 
-                    nextState = POT;
+                else if ((cntLMX == sumForLmx) && (packetNum1 == 0)  && (packetNum2 == 0) && (packetNum3 != 0)) begin 
+                    currState <= POT;
                 end
-                else if ((trCntReg == sumForLmx) && (packetNum2 == 0) && (packetNum3 == 0) && (packetNum4 != 0)) begin 
-                    nextState = DAC;
+                else if ((cntLMX == sumForLmx) && (packetNum2 == 0) && (packetNum3 == 0) && (packetNum4 != 0)) begin 
+                    currState <= DAC;
                 end
-                else if ((trCntReg == sumForLmx) && (packetNum2 == 0) && (packetNum3 == 0) && (packetNum4 == 0) && (packetNum5 != 0)) begin 
-                    nextState = ATTENUATOR;
+                else if ((cntLMX == sumForLmx) && (packetNum2 == 0) && (packetNum3 == 0) && (packetNum4 == 0) && (packetNum5 != 0)) begin 
+                    currState <= ATTENUATOR;
                 end
-                else if ((trCntReg == sumForLmx) && (packetNum2 == 0) && (packetNum3 == 0) && (packetNum4 == 0)  && (packetNum5 == 0) && (packetNum6 != 0)) begin 
-                    nextState = SHIFTREG; 
+                else if ((cntLMX == sumForLmx) && (packetNum2 == 0) && (packetNum3 == 0) && (packetNum4 == 0)  && (packetNum5 == 0) && (packetNum6 != 0)) begin 
+                    currState <= SHIFTREG; 
                 end
-                else if ((trCntReg == sumForLmx) && (packetNum2 == 0) && (packetNum3 == 0) && (packetNum4 == 0)  && (packetNum5 == 0) && (packetNum6 == 0) && (packetNum7 != 0)) begin 
-                    nextState = MAX2870; 
+                else if ((cntLMX == sumForLmx) && (packetNum2 == 0) && (packetNum3 == 0) && (packetNum4 == 0)  && (packetNum5 == 0) && (packetNum6 == 0) && (packetNum7 != 0)) begin 
+                    currState <= MAX2870; 
                 end
-                else if ((trCntReg == sumForLmx) && (packetNum2 == 0) && (packetNum3 == 0) && (packetNum4 == 0)  && (packetNum5 == 0) && (packetNum6 == 0) && (packetNum7 == 0) && (packetNum8 != 0)) begin 
-                    nextState = GPIO; 
+                else if ((cntLMX == sumForLmx) && (packetNum2 == 0) && (packetNum3 == 0) && (packetNum4 == 0)  && (packetNum5 == 0) && (packetNum6 == 0) && (packetNum7 == 0) && (packetNum8 != 0)) begin 
+                    currState <= GPIO; 
                 end
-                else if ((trCntReg == sumForLmx) && (packetNum2 == 0) && (packetNum3 == 0) && (packetNum4 == 0)  && (packetNum5 == 0) && (packetNum6 == 0) && (packetNum7 == 0) && (packetNum8 == 0)) begin 
-                    nextState = IDLE; 
+                else if ((cntLMX == sumForLmx) && (packetNum2 == 0) && (packetNum3 == 0) && (packetNum4 == 0)  && (packetNum5 == 0) && (packetNum6 == 0) && (packetNum7 == 0) && (packetNum8 == 0)) begin 
+                    currState <= IDLE; 
                 end
-                else if (trCntReg != sumForLmx) begin 
-                    nextState = LMX2594;
+                else if (cntLMX != sumForLmx) begin 
+                    currState <= LMX2594;
                 end
             end
             else begin 
                 if (trCnt1Spi == wordNum ) begin 
-                    nextState = IDLE;
+                    currState <= IDLE;
                 end
                  else begin 
                         if  (trCnt1Spi < wordNum) begin 
-                            nextState = LMX2594;
+                            currState <= LMX2594;
                         end
                  end
             end
         end
         DDS: begin
             if (modeSel) begin 
-                if ((trCntReg == sumForDDS) && (packetNum3 != 0)) begin 
-                    nextState = POT;
+                if ((cntDDS == sumForDDS) && (packetNum3 != 0)) begin 
+                    currState <= POT;
                 end
-                else if ((trCntReg == sumForDDS) && (packetNum3 == 0) && (packetNum4 != 0)) begin 
-                    nextState = DAC;
+                else if ((cntDDS == sumForDDS) && (packetNum3 == 0) && (packetNum4 != 0)) begin 
+                    currState <= DAC;
                 end
-                else if ((trCntReg == sumForDDS) && (packetNum3 == 0) && (packetNum4 == 0) && (packetNum5 != 0) ) begin 
-                    nextState = ATTENUATOR;
+                else if ((cntDDS == sumForDDS) && (packetNum3 == 0) && (packetNum4 == 0) && (packetNum5 != 0) ) begin 
+                    currState <= ATTENUATOR;
                 end
-                else if ((trCntReg == sumForDDS) && (packetNum3 == 0) && (packetNum4 == 0) && (packetNum5 == 0) && (packetNum6 != 0)) begin 
-                    nextState = SHIFTREG;
+                else if ((cntDDS == sumForDDS) && (packetNum3 == 0) && (packetNum4 == 0) && (packetNum5 == 0) && (packetNum6 != 0)) begin 
+                    currState <= SHIFTREG;
                 end
-                else if ((trCntReg == sumForDDS) && (packetNum3 == 0) && (packetNum4 == 0) && (packetNum5 == 0) && (packetNum6 == 0 ) && (packetNum7 != 0)) begin 
-                    nextState = MAX2870;
+                else if ((cntDDS == sumForDDS) && (packetNum3 == 0) && (packetNum4 == 0) && (packetNum5 == 0) && (packetNum6 == 0 ) && (packetNum7 != 0)) begin 
+                    currState <= MAX2870;
                 end
-                else if ((trCntReg == sumForDDS) && (packetNum3 == 0) && (packetNum4 == 0 ) && (packetNum5 == 0) && (packetNum6 == 0) && (packetNum7 == 0) && (packetNum8 != 0)) begin 
-                    nextState = GPIO;
+                else if ((cntDDS == sumForDDS) && (packetNum3 == 0) && (packetNum4 == 0 ) && (packetNum5 == 0) && (packetNum6 == 0) && (packetNum7 == 0) && (packetNum8 != 0)) begin 
+                    currState <= GPIO;
                 end
-                else if ((trCntReg == sumForDDS ) && (packetNum3 == 0) && (packetNum4 == 0) && (packetNum5 == 0) && (packetNum6 == 0) && (packetNum7 == 0) && (packetNum8 == 0)) begin 
-                    nextState = IDLE;
+                else if ((cntDDS == sumForDDS ) && (packetNum3 == 0) && (packetNum4 == 0) && (packetNum5 == 0) && (packetNum6 == 0) && (packetNum7 == 0) && (packetNum8 == 0)) begin 
+                    currState <= IDLE;
                 end
-                else if (trCntReg != sumForDDS) begin 
-                    nextState = DDS;
+                else if (cntDDS != sumForDDS) begin 
+                    currState <= DDS;
                 end
             end
             else begin 
                    if (trCnt1Spi == wordNum ) begin 
-                    nextState = IDLE;
+                    currState <= IDLE;
                 end
                  else begin 
                         if (trCnt1Spi < wordNum) begin 
-                            nextState = DDS;
+                            currState <= DDS;
                         end
                  end
             end
         end
         POT: begin
             if (modeSel) begin 
-                if ((trCntReg == sumForPot) && (packetNum4 != 0)) begin 
-                    nextState = DAC;
+                if ((cntPot == sumForPot) && (packetNum4 != 0)) begin 
+                    currState <= DAC;
                 end
-                else if ((trCntReg == sumForPot) && (packetNum4 == 0) && (packetNum5 != 0)) begin 
-                    nextState = ATTENUATOR;
+                else if ((cntPot == sumForPot) && (packetNum4 == 0) && (packetNum5 != 0)) begin 
+                    currState <= ATTENUATOR;
                 end
-                else if ((trCntReg == sumForPot) && (packetNum4 == 0) && (packetNum5 == 0) && (packetNum6 != 0)) begin 
-                    nextState = SHIFTREG;
+                else if ((cntPot == sumForPot) && (packetNum4 == 0) && (packetNum5 == 0) && (packetNum6 != 0)) begin 
+                    currState <= SHIFTREG;
                 end
-                else if ((trCntReg == sumForPot) && (packetNum4 == 0) && (packetNum5 == 0) && (packetNum6 == 0) && (packetNum7 != 0)) begin 
-                    nextState = MAX2870;
+                else if ((cntPot == sumForPot) && (packetNum4 == 0) && (packetNum5 == 0) && (packetNum6 == 0) && (packetNum7 != 0)) begin 
+                    currState <= MAX2870;
                 end
-                else if ((trCntReg == sumForPot) && (packetNum4 == 0) && (packetNum5 == 0) && (packetNum6 == 0) && (packetNum7 == 0) && (packetNum8 != 0)) begin 
-                    nextState = GPIO;
+                else if ((cntPot == sumForPot) && (packetNum4 == 0) && (packetNum5 == 0) && (packetNum6 == 0) && (packetNum7 == 0) && (packetNum8 != 0)) begin 
+                    currState <= GPIO;
                 end
-                else if ((trCntReg == sumForPot) && (packetNum4 == 0) && (packetNum5 == 0) && (packetNum6 == 0) && (packetNum7 == 0) && (packetNum8 == 0)) begin 
-                    nextState = IDLE;
+                else if ((cntPot == sumForPot) && (packetNum4 == 0) && (packetNum5 == 0) && (packetNum6 == 0) && (packetNum7 == 0) && (packetNum8 == 0)) begin 
+                    currState <= IDLE;
                 end
-                else if (trCntReg != sumForPot) begin 
-                    nextState = POT;
+                else if (cntPot != sumForPot) begin 
+                    currState <= POT;
                 end
             end
             else begin 
                 if (trCnt1Spi == wordNum ) begin 
-                    nextState = IDLE;
+                    currState <= IDLE;
                 end
                  else begin 
                         if (trCnt1Spi < wordNum) begin 
-                            nextState = POT;
+                            currState <= POT;
                         end
                  end
             end
         end
         DAC: begin
             if (modeSel) begin 
-                if ((trCntReg == sumForDAC) && (packetNum5 != 0) ) begin 
-                    nextState = ATTENUATOR;
+                if ((cntDAC == sumForDAC) && (packetNum5 != 0) ) begin 
+                    currState <= ATTENUATOR;
                 end
-                else if ((trCntReg == sumForDAC) && (packetNum5 == 0) && (packetNum6 != 0)) begin 
-                    nextState = SHIFTREG;
+                else if ((cntDAC == sumForDAC) && (packetNum5 == 0) && (packetNum6 != 0)) begin 
+                    currState <= SHIFTREG;
                 end
-                else if ((trCntReg == sumForDAC) && (packetNum5 == 0) && (packetNum6 == 0) && (packetNum7 != 0)) begin 
-                    nextState = MAX2870;
+                else if ((cntDAC == sumForDAC) && (packetNum5 == 0) && (packetNum6 == 0) && (packetNum7 != 0)) begin 
+                    currState <= MAX2870;
                 end
-                else if ((trCntReg == sumForDAC) && (packetNum5 == 0) && (packetNum6 == 0) && (packetNum7 == 0) && (packetNum8 != 0)) begin 
-                    nextState = GPIO;
+                else if ((cntDAC == sumForDAC) && (packetNum5 == 0) && (packetNum6 == 0) && (packetNum7 == 0) && (packetNum8 != 0)) begin 
+                    currState <= GPIO;
                 end
-                else if ((trCntReg == sumForDAC) && (packetNum5 == 0) && (packetNum6 == 0) && (packetNum7 == 0) && (packetNum8 == 0)) begin 
-                    nextState = IDLE;
+                else if ((cntDAC == sumForDAC) && (packetNum5 == 0) && (packetNum6 == 0) && (packetNum7 == 0) && (packetNum8 == 0)) begin 
+                    currState <= IDLE;
                 end
-                else if (trCntReg != sumForDAC) begin 
-                    nextState = DAC;
+                else if (cntDAC != sumForDAC) begin 
+                    currState <= DAC;
                 end
             end
             else begin
                 if (trCnt1Spi == wordNum ) begin 
-                    nextState = IDLE;
+                    currState <= IDLE;
                 end
                  else begin 
                         if (trCnt1Spi < wordNum) begin 
-                            nextState = DAC;
+                            currState <= DAC;
                         end
                  end
             end
         end
         ATTENUATOR: begin
             if (modeSel) begin 
-                if ((trCntReg == sumForATT) && (packetNum6 != 0) ) begin 
-                    nextState = SHIFTREG;
+                if ((cntATT == sumForATT) && (packetNum6 != 0) ) begin 
+                    currState <= SHIFTREG;
                 end
-                else if ((trCntReg == sumForATT) && (packetNum6 == 0) && (packetNum7 != 0)) begin 
-                    nextState = MAX2870;
+                else if ((cntATT == sumForATT) && (packetNum6 == 0) && (packetNum7 != 0)) begin 
+                    currState <= MAX2870;
                 end
-                else if ((trCntReg == sumForATT) && (packetNum6 == 0) && (packetNum7 == 0) && (packetNum8 != 0)) begin 
-                    nextState = GPIO;
+                else if ((cntATT == sumForATT) && (packetNum6 == 0) && (packetNum7 == 0) && (packetNum8 != 0)) begin 
+                    currState <= GPIO;
                 end
-                else if ((trCntReg == sumForATT) && (packetNum6 == 0) && (packetNum7 == 0) && (packetNum8 == 0)) begin 
-                    nextState = IDLE;
+                else if ((cntATT == sumForATT) && (packetNum6 == 0) && (packetNum7 == 0) && (packetNum8 == 0)) begin 
+                    currState <= IDLE;
                 end
-                else if (trCntReg != sumForATT) begin 
-                    nextState = ATTENUATOR;
+                else if (cntATT != sumForATT) begin 
+                    currState <= ATTENUATOR;
                 end
             end
             else begin 
                if (trCnt1Spi == wordNum ) begin 
-                    nextState = IDLE;
+                    currState = IDLE;
                 end
                  else begin 
                         if (trCnt1Spi < wordNum) begin 
-                            nextState = ATTENUATOR;
+                            currState <= ATTENUATOR;
                         end
                  end
             end
         end
         SHIFTREG : begin 
             if (modeSel) begin 
-                if ((trCntReg == sumForShiftReg) && (packetNum7 != 0) ) begin 
-                    nextState = MAX2870;
+                if ((cntShiftReg == sumForShiftReg) && (packetNum7 != 0) ) begin 
+                    currState <= MAX2870;
                 end
-                else if ((trCntReg == sumForShiftReg) && (packetNum7 == 0) && (packetNum8 != 0)) begin 
-                    nextState = GPIO;
+                else if ((cntShiftReg == sumForShiftReg) && (packetNum7 == 0) && (packetNum8 != 0)) begin 
+                    currState <= GPIO;
                 end
-                else if ((trCntReg == sumForShiftReg) && (packetNum7 == 0) && (packetNum8 == 0)) begin 
-                    nextState = IDLE;
+                else if ((cntShiftReg == sumForShiftReg) && (packetNum7 == 0) && (packetNum8 == 0)) begin 
+                    currState <= IDLE;
                 end
-                else if (trCntReg != sumForShiftReg) begin 
-                    nextState = SHIFTREG;
+                else if (cntShiftReg != sumForShiftReg) begin 
+                    currState <= SHIFTREG;
                 end
             end
             else begin
                 if (trCnt1Spi == wordNum ) begin 
-                    nextState = IDLE;
+                    currState <= IDLE;
                 end
                  else begin 
                         if (trCnt1Spi < wordNum) begin 
-                            nextState = SHIFTREG;
+                            currState <= SHIFTREG;
                         end
                  end
             end
         end  
         MAX2870 : begin 
             if (modeSel) begin 
-                if ((trCntReg == sumForMAX) && (packetNum8 != 0))  begin 
-                    nextState = GPIO;
+                if ((cntMAX == sumForMAX) && (packetNum8 != 0))  begin 
+                    currState <= GPIO;
                 end
-                else if ((trCntReg == sumForMAX) && (packetNum8 == 0)) begin 
-                    nextState = IDLE;
+                else if ((cntMAX == sumForMAX) && (packetNum8 == 0)) begin 
+                    currState <= IDLE;
                 end
-                else if (trCntReg != sumForMAX) begin 
-                    nextState = MAX2870;
+                else if (cntMAX != sumForMAX) begin 
+                    currState <= MAX2870;
                 end
             end
             else begin
                 if (trCnt1Spi == wordNum ) begin 
-                    nextState = IDLE;
+                    currState <= IDLE;
                 end
                  else begin 
                         if (trCnt1Spi < wordNum) begin 
-                            nextState = MAX2870;
+                            currState <= MAX2870;
                         end
                  end
             end
         end
         GPIO : begin 
             if (modeSel) begin 
-                if (trCntReg == sumForGPIO) begin 
-                    nextState = IDLE;
+                if (cntGPIO == sumForGPIO) begin 
+                    currState <= IDLE;
                 end
-                else if (trCntReg != sumForGPIO) begin 
-                    nextState = GPIO;
+                else if (cntGPIO != sumForGPIO) begin 
+                    currState <= GPIO;
                 end
             end
             else begin
                 if (trCnt1Spi == wordNum ) begin 
-                    nextState = IDLE;
+                    currState <= IDLE;
                 end
                  else begin 
                         if (trCnt1Spi < wordNum) begin 
-                            nextState = GPIO;
+                            currState <= GPIO;
                         end
                  end
             end
         end
         TEMPSENS : begin 
             if (modeSel) begin 
-                nextState = IDLE;
+                currState <= IDLE;
             end
             else begin 
                 if (trCnt1Spi == wordNum ) begin 
-                    nextState = IDLE;
+                    currState <= IDLE;
                 end
                  else begin 
                         if ( trCnt1Spi < wordNum) begin 
-                            nextState = TEMPSENS;
+                            currState <= TEMPSENS;
                         end
                  end
             end
         end
         default: begin 
-            nextState = IDLE;
+            currState <= IDLE;
         end
         endcase
     end

src/src/fifo_top/FifoCtrl.v

@@ -44,9 +44,13 @@ reg     [FifoNum-1:0] rxFifoWrEn;
 reg     [FifoNum-1:0] rxFifoReadEn;
 
 reg     [0:23] dataToRxFifoReg [FifoNum-1:0];
+reg     [23:0] dataToRxFifoRegRegR [FifoNum-1:0];
 reg     [23:0] dataToRxFifoReg21;
 reg     [23:0] dataToRxFifoReg22;
 reg     [23:0] dataToRxFifoReg23;
+reg     [23:0] dataToRxFifoReg21R;
+reg     [23:0] dataToRxFifoReg22R;
+reg     [23:0] dataToRxFifoReg23R;
 wire    [71:0] dataToRxFifo2;
 wire    [71:0] dataFromRxFifo2;
 wire    [6:0] wNumDDS;
@@ -73,11 +77,11 @@ wire [0:23] dataFromRxFifo [FifoNum-1:0];
 
 
 
-assign dataToRxFifo[0]= dataToRxFifoReg[0];
-assign dataToRxFifo[1]= dataToRxFifoReg[1];
-assign dataToRxFifo[2]= dataToRxFifoReg[2];
-assign dataToRxFifo[3]= dataToRxFifoReg[3];
-assign dataToRxFifo[4]= dataToRxFifoReg[4];
+assign dataToRxFifo[0]= dataToRxFifoRegRegR[0];
+assign dataToRxFifo[1]= dataToRxFifoRegRegR[1];
+assign dataToRxFifo[2]= dataToRxFifoRegRegR[2];
+assign dataToRxFifo[3]= dataToRxFifoRegRegR[3];
+assign dataToRxFifo[4]= dataToRxFifoRegRegR[4];
 assign DataFromRxFifo1_o = dataFromRxFifo[0];
 assign DataFromRxFifo2_o = dataFromRxFifo2[71:8];
 assign DataFromMAX2870Fifo_o = dataFromMAX2870Fifo[47-:32];
@@ -91,13 +95,54 @@ assign WrEnMAX2870Fifo_o = rxFifoWrEn[6];
 
 
 
-assign dataToRxFifo2 = {dataToRxFifoReg21, dataToRxFifoReg22, dataToRxFifoReg23};
+assign dataToRxFifo2 = {dataToRxFifoReg21R, dataToRxFifoReg22R, dataToRxFifoReg23R};
 assign dataToFifoMax2870 = dataToFifoMax2870Reg;
 
 assign EmptyFlag_o = emptyFlag;
 
 integer k; 
 
+always @(posedge WrClk_i) begin 
+    dataToRxFifoRegRegR[0] <= dataToRxFifoReg[0];
+end
+
+always @(posedge WrClk_i) begin 
+    dataToRxFifoRegRegR[1] <= dataToRxFifoReg[1];
+end
+
+always @(posedge WrClk_i) begin 
+    dataToRxFifoRegRegR[2] <= dataToRxFifoReg[2];
+end
+
+always @(posedge WrClk_i) begin 
+    dataToRxFifoRegRegR[3] <= dataToRxFifoReg[3];
+end
+
+always @(posedge WrClk_i) begin 
+    dataToRxFifoRegRegR[4] <= dataToRxFifoReg[4];
+end
+
+always @(posedge WrClk_i) begin 
+    dataToRxFifoRegRegR[5] <= dataToRxFifoReg[5];
+end
+
+always @(posedge WrClk_i) begin 
+    dataToRxFifoRegRegR[6] <= dataToRxFifoReg[6];
+end
+
+always @(posedge WrClk_i) begin 
+    dataToRxFifoRegRegR[7] <= dataToRxFifoReg[7];
+end
+
+
+
+
+always @(posedge WrClk_i) begin 
+    dataToRxFifoReg21R <= dataToRxFifoReg21;
+    dataToRxFifoReg22R <= dataToRxFifoReg22;
+    dataToRxFifoReg23R <= dataToRxFifoReg23;
+end
+
 always @(posedge WrClk_i) begin
     if (Rst_i) begin 
         for (k = 0; k < FifoNum; k = k + 1) begin