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@@ -3,7 +3,7 @@
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#
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# recreate_vna_pcie.tcl: Tcl script for re-creating project 'VNA_PCIE_PROJ'
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#
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-# Generated by Vivado on Tue Oct 08 17:41:06 +0700 2024
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+# Generated by Vivado on Wed Oct 09 10:32:15 +0700 2024
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# IP Build 5075265 on Wed May 22 21:45:21 MDT 2024
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#
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# This file contains the Vivado Tcl commands for re-creating the project to the state*
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@@ -23,9 +23,8 @@
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# 2. The following source(s) files that were local or imported into the original project.
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# (Please see the '$orig_proj_dir' and '$origin_dir' variable setting below at the start of the script)
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#
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-# "c:/Projects/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/sources_1/ip/pcie1234/pcie1234.xci"
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-# "c:/Projects/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/sources_1/ip/ClkPllSysTo125/ClkPllSysTo125.xci"
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-# "C:/Projects/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/synth_1/PciVnaEmulTop.dcp"
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+# "c:/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/sources_1/ip/pcie1234/pcie1234.xci"
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+# "c:/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/sources_1/ip/ClkPllSysTo125/ClkPllSysTo125.xci"
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#
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# 3. The following remote source files that were added to the original project:-
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#
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@@ -115,9 +114,8 @@
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proc checkRequiredFiles { origin_dir} {
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set status true
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set files [list \
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- "[file normalize "$origin_dir/Projects/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/sources_1/ip/pcie1234/pcie1234.xci"]"\
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- "[file normalize "$origin_dir/Projects/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/sources_1/ip/ClkPllSysTo125/ClkPllSysTo125.xci"]"\
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- "[file normalize "$origin_dir/Projects/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/synth_1/PciVnaEmulTop.dcp"]"\
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+ "[file normalize "$origin_dir/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/sources_1/ip/pcie1234/pcie1234.xci"]"\
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+ "[file normalize "$origin_dir/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/sources_1/ip/ClkPllSysTo125/ClkPllSysTo125.xci"]"\
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]
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foreach ifile $files {
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if { ![file isfile $ifile] } {
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@@ -281,7 +279,7 @@ if { $::argc > 0 } {
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}
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# Set the directory path for the original project from where this script was exported
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-set orig_proj_dir "[file normalize "$origin_dir/Projects/VNA_PCIE_PROJ"]"
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+set orig_proj_dir "[file normalize "$origin_dir/VNA_PCIE_PROJ"]"
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# Check for paths and files needed for project creation
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set validate_required 0
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@@ -407,6 +405,16 @@ set files [list \
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]
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add_files -norecurse -fileset $obj $files
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+# Import local files from the original project
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+set files [list \
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+ [file normalize "${origin_dir}/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/sources_1/ip/pcie1234/pcie1234.xci" ]\
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+ [file normalize "${origin_dir}/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/sources_1/ip/ClkPllSysTo125/ClkPllSysTo125.xci" ]\
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+]
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+set imported_files ""
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+foreach f $files {
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+ lappend imported_files [import_files -fileset sources_1 $f]
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+}
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+
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# Set 'sources_1' fileset file properties for remote files
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set file "$origin_dir/VNA_PCIE_REPO/src/src/PCIeImports/board_common.vh"
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set file [file normalize $file]
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@@ -434,26 +442,6 @@ set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
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set_property -name "file_type" -value "Verilog Header" -objects $file_obj
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-# Set 'sources_1' fileset file properties for local files
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-# None
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-
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-# Set 'sources_1' fileset properties
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-set obj [get_filesets sources_1]
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-set_property -name "dataflow_viewer_settings" -value "min_width=16" -objects $obj
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-set_property -name "top" -value "PciVnaEmulTop" -objects $obj
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-set_property -name "top_auto_set" -value "0" -objects $obj
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-
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-# Set 'sources_1' fileset object
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-set obj [get_filesets sources_1]
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-# Import local files from the original project
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-set files [list \
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- [file normalize "${origin_dir}/Projects/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/sources_1/ip/pcie1234/pcie1234.xci" ]\
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-]
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-set imported_files [import_files -fileset sources_1 $files]
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-
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-# Set 'sources_1' fileset file properties for remote files
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-# None
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-
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# Set 'sources_1' fileset file properties for local files
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set file "pcie1234/pcie1234.xci"
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set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
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@@ -463,19 +451,6 @@ if { ![get_property "is_locked" $file_obj] } {
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set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
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}
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-
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-# Set 'sources_1' fileset object
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-set obj [get_filesets sources_1]
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-# Import local files from the original project
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-set files [list \
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- [file normalize "${origin_dir}/Projects/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/sources_1/ip/ClkPllSysTo125/ClkPllSysTo125.xci" ]\
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-]
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-set imported_files [import_files -fileset sources_1 $files]
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-
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-# Set 'sources_1' fileset file properties for remote files
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-# None
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-
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-# Set 'sources_1' fileset file properties for local files
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set file "ClkPllSysTo125/ClkPllSysTo125.xci"
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set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
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set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
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@@ -485,6 +460,12 @@ if { ![get_property "is_locked" $file_obj] } {
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}
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+# Set 'sources_1' fileset properties
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+set obj [get_filesets sources_1]
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+set_property -name "dataflow_viewer_settings" -value "min_width=16" -objects $obj
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+set_property -name "top" -value "PciVnaEmulTop" -objects $obj
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+set_property -name "top_auto_set" -value "0" -objects $obj
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+
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# Create 'constrs_1' fileset (if not found)
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if {[string equal [get_filesets -quiet constrs_1] ""]} {
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create_fileset -constrset constrs_1
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@@ -521,23 +502,7 @@ set_property -name "top_lib" -value "xil_defaultlib" -objects $obj
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# Set 'utils_1' fileset object
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set obj [get_filesets utils_1]
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-# Import local files from the original project
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-set files [list \
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- [file normalize "${origin_dir}/Projects/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/synth_1/PciVnaEmulTop.dcp" ]\
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-]
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-set imported_files ""
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-foreach f $files {
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- lappend imported_files [import_files -fileset utils_1 $f]
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-}
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-
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-# Set 'utils_1' fileset file properties for remote files
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-# None
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-
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-# Set 'utils_1' fileset file properties for local files
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-set file "synth_1/PciVnaEmulTop.dcp"
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-set file_obj [get_files -of_objects [get_filesets utils_1] [list "*$file"]]
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-set_property -name "netlist_only" -value "0" -objects $file_obj
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-
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+# Empty (no sources present)
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# Set 'utils_1' fileset properties
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set obj [get_filesets utils_1]
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@@ -569,11 +534,8 @@ if { $obj != "" } {
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}
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set obj [get_runs synth_1]
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set_property -name "part" -value "xc7a100tfgg484-2" -objects $obj
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-set_property -name "incremental_checkpoint" -value "$proj_dir/${_xil_proj_name_}.srcs/utils_1/imports/synth_1/PciVnaEmulTop.dcp" -objects $obj
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set_property -name "auto_incremental_checkpoint" -value "1" -objects $obj
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set_property -name "strategy" -value "Vivado Synthesis Defaults" -objects $obj
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-set_property -name "steps.synth_design.args.flatten_hierarchy" -value "none" -objects $obj
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-set_property -name "steps.synth_design.args.gated_clock_conversion" -value "auto" -objects $obj
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# set the current synth run
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current_run -synthesis [get_runs synth_1]
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@@ -858,3 +820,129 @@ move_dashboard_gadget -name {drc_1} -row 2 -col 0
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move_dashboard_gadget -name {timing_1} -row 0 -col 1
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move_dashboard_gadget -name {utilization_2} -row 1 -col 1
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move_dashboard_gadget -name {methodology_1} -row 2 -col 1
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+
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+
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+##################################################################
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+# CHECK VIVADO VERSION
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+##################################################################
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+
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+set scripts_vivado_version 2024.1
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+set current_vivado_version [version -short]
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+
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+if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
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+ catch {common::send_msg_id "IPS_TCL-100" "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_ip_tcl to create an updated script."}
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+ return 1
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+}
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+
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+##################################################################
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+# START
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+##################################################################
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+
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+# To test this script, run the following commands from Vivado Tcl console:
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+# source recreateIp.tcl
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+# If there is no project opened, this script will create a
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+# project, but make sure you do not have an existing project
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+# in the current working folder.
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+
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+set list_projs [get_projects -quiet]
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+if { $list_projs eq "" } {
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+ create_project VNA_PCIE_PROJ VNA_PCIE_PROJ -part xc7a100tfgg484-2
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+ set_property target_language Verilog [current_project]
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+ set_property simulator_language Verilog [current_project]
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+}
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+
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+##################################################################
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+# CHECK IPs
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+##################################################################
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+
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+set bCheckIPs 1
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+set bCheckIPsPassed 1
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+if { $bCheckIPs == 1 } {
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+ set list_check_ips { xilinx.com:ip:clk_wiz:6.0 xilinx.com:ip:pcie_7x:3.3 }
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+ set list_ips_missing ""
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+ common::send_msg_id "IPS_TCL-1001" "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ."
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+
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+ foreach ip_vlnv $list_check_ips {
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+ set ip_obj [get_ipdefs -all $ip_vlnv]
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+ if { $ip_obj eq "" } {
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+ lappend list_ips_missing $ip_vlnv
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+ }
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+ }
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+
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+ if { $list_ips_missing ne "" } {
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+ catch {common::send_msg_id "IPS_TCL-105" "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." }
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+ set bCheckIPsPassed 0
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+ }
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+}
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+
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+if { $bCheckIPsPassed != 1 } {
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+ common::send_msg_id "IPS_TCL-102" "WARNING" "Will not continue with creation of design due to the error(s) above."
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+ return 1
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+}
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+
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+##################################################################
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+# CREATE IP ClkPllSysTo125
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+##################################################################
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+
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+set ClkPllSysTo125 [create_ip -name clk_wiz -vendor xilinx.com -library ip -version 6.0 -module_name ClkPllSysTo125]
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+
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+# User Parameters
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+set_property -dict [list \
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+ CONFIG.CLKOUT1_DRIVES {BUFG} \
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+ CONFIG.CLKOUT1_JITTER {203.457} \
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+ CONFIG.CLKOUT1_PHASE_ERROR {155.540} \
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+ CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {50.000} \
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+ CONFIG.CLKOUT2_DRIVES {BUFG} \
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+ CONFIG.CLKOUT3_DRIVES {BUFG} \
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+ CONFIG.CLKOUT4_DRIVES {BUFG} \
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+ CONFIG.CLKOUT5_DRIVES {BUFG} \
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+ CONFIG.CLKOUT6_DRIVES {BUFG} \
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+ CONFIG.CLKOUT7_DRIVES {BUFG} \
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+ CONFIG.MMCM_BANDWIDTH {OPTIMIZED} \
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+ CONFIG.MMCM_CLKFBOUT_MULT_F {17} \
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+ CONFIG.MMCM_CLKOUT0_DIVIDE_F {17} \
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+ CONFIG.MMCM_COMPENSATION {ZHOLD} \
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+ CONFIG.MMCM_DIVCLK_DIVIDE {2} \
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+ CONFIG.PRIMITIVE {PLL} \
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+ CONFIG.PRIM_SOURCE {Single_ended_clock_capable_pin} \
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+ CONFIG.SECONDARY_SOURCE {Single_ended_clock_capable_pin} \
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+ CONFIG.USE_LOCKED {false} \
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+ CONFIG.USE_PHASE_ALIGNMENT {false} \
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+ CONFIG.USE_RESET {false} \
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+] [get_ips ClkPllSysTo125]
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+
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+# Runtime Parameters
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+set_property -dict {
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+ GENERATE_SYNTH_CHECKPOINT {1}
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+} $ClkPllSysTo125
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+
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+##################################################################
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+
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+##################################################################
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+# CREATE IP pcie1234
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+##################################################################
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+
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+set pcie1234 [create_ip -name pcie_7x -vendor xilinx.com -library ip -version 3.3 -module_name pcie1234]
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+
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+# User Parameters
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+set_property -dict [list \
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+ CONFIG.Device_ID {7012} \
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+ CONFIG.Interface_Width {64_bit} \
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+ CONFIG.Link_Speed {2.5_GT/s} \
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+ CONFIG.Max_Payload_Size {512_bytes} \
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+ CONFIG.Maximum_Link_Width {X2} \
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+ CONFIG.PCIe_Blk_Locn {X0Y0} \
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+ CONFIG.Trans_Buf_Pipeline {None} \
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+ CONFIG.User_Clk_Freq {125} \
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+ CONFIG.en_ext_pipe_interface {false} \
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+ CONFIG.pipe_mode_sim {Enable_Pipe_Simulation} \
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+ CONFIG.pipe_sim {true} \
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+] [get_ips pcie1234]
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+
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+# Runtime Parameters
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+set_property -dict {
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+ GENERATE_SYNTH_CHECKPOINT {1}
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+} $pcie1234
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+
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+##################################################################
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+
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Anatoliy Chigirinskiy