Исправил скрипт

script/recreate.tcl

@@ -1,9 +1,9 @@
 #*****************************************************************************************
 # Vivado (TM) v2024.1 (64-bit)
 #
-# recreate.tcl: Tcl script for re-creating project 'VNA_PCIE_PROJ'
+# recreate_vna_pcie.tcl: Tcl script for re-creating project 'VNA_PCIE_PROJ'
 #
-# Generated by Vivado on Thu Oct 10 17:06:21 +0700 2024
+# Generated by Vivado on Wed Oct 09 11:04:50 +0700 2024
 # IP Build 5075265 on Wed May 22 21:45:21 MDT 2024
 #
 # This file contains the Vivado Tcl commands for re-creating the project to the state*
@@ -18,89 +18,12 @@
 # NOTE: In order to use this script for source control purposes, please make sure that the
 #       following files are added to the source control system:-
 #
-# 1. This project restoration tcl script (recreate.tcl) that was generated.
+# 1. This project restoration tcl script (recreate_vna_pcie.tcl) that was generated.
 #
 # 2. The following source(s) files that were local or imported into the original project.
 #    (Please see the '$orig_proj_dir' and '$origin_dir' variable setting below at the start of the script)
 #
-#    "C:/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PulseMeas/ActivePortSelector.v"
-#    "C:/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/InternalDsp/AdcCalibration.v"
-#    "C:/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/InternalDsp/ComplPrng.v"
-#    "C:/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/InternalDsp/CordicNco.v"
-#    "C:/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/InternalDsp/CordicRotation.v"
-#    "C:/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/DitherGen/DitherGenv2.v"
-#    "C:/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/InternalDsp/DspPipeline.v"
-#    "C:/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PCIeImports/EP_MEM.v"
-#    "C:/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/Math/FpCustomMultiplier.v"
-#    "C:/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/GainOverloadControl/GainControl.v"
-#    "C:/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/GainOverloadControl/GainControlWrapper.v"
-#    "C:/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/InitRst/InitRst.v"
-#    "C:/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/Top/IntermediateLogic.v"
-#    "C:/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/InternalDsp/InternalDsp.v"
-#    "C:/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/InternalDsp/MeasCtrlModule.v"
-#    "C:/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PulseMeas/MeasStartEventGen.v"
-#    "C:/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/Math/MultModule.v"
-#    "C:/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PulseMeas/Mux.v"
-#    "C:/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/Math/MyIntToFp.v"
-#    "C:/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/InternalDsp/NcoRstGen.v"
-#    "C:/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/GainOverloadControl/OverloadDetect.v"
-#    "C:/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PulseMeas/PGenRstGenerator.v"
-#    "C:/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PCIeImports/PIO.v"
-#    "C:/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PCIeImports/PIO_EP.v"
-#    "C:/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PCIeImports/PIO_EP_MEM_ACCESS.v"
-#    "C:/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PCIeImports/PIO_RX_ENGINE.v"
-#    "C:/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PCIeImports/PIO_TO_CTRL.v"
-#    "C:/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PCIeImports/PIO_TX_ENGINE.v"
-#    "C:/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PulseMeas/PulseGen.v"
-#    "C:/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/RegMap/RegMap.v"
-#    "C:/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/Top/S5443Top.v"
-#    "C:/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PulseMeas/SampleStrobeGenRstDemux.v"
-#    "C:/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/Math/SimpleMult.v"
-#    "C:/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PulseMeas/StartAfterGainSel.v"
-#    "C:/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/Math/SumAcc.v"
-#    "C:/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PulseMeas/TrigInt2Mux.v"
-#    "C:/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/InternalDsp/WinParameters.v"
-#    "C:/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/InternalDsp/Win_calc.v"
-#    "C:/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PCIeImports/pcie1234_pipe_clock.v"
-#    "C:/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PCIeImports/pcie1234_support.v"
-#    "C:/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PCIeImports/pcie_app_7x.v"
-#    "C:/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PCIeImports/xilinx_pcie_2_1_ep_7x.v"
-#    "C:/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/Top/PciVnaEmulTop.v"
-#    "C:/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/AdcDataRx/AdcSync.v"
-#    "C:/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/AdcDataRx/delay_controller_wrap.v"
-#    "C:/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/AdcDataRx/n_x_serdes_1_to_7_mmcm_idelay_sdr.v"
-#    "C:/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/AdcDataRx/serdes_1_to_7_mmcm_idelay_sdr.v"
-#    "C:/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/AdcDataRx/serdes_1_to_7_slave_idelay_sdr.v"
-#    "C:/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/AdcDataRx/top5x2_7to1_sdr_rx.v"
-#    "C:/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/AdcDataRx/AdcDataInterface.v"
-#    "C:/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/ClkGen/Clk200Gen.v"
-#    "C:/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/ExtDspInterface/DspInterface.v"
-#    "C:/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/ExtDspInterface/DspPpiOut.v"
-#    "C:/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/MeasDataFifo/FifoController.v"
-#    "C:/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/Top/IntermediateLogicTb.v"
-#    "C:/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/MeasDataFifo/MeasDataFifoWrapper.v"
-#    "C:/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PulseMeas/PulseGenNew.v"
-#    "C:/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/Sim/S5443TopPulseProfileTb.v"
-#    "C:/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/Sim/S5443TopSimpleMeasTb.v"
-#    "C:/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/ExtDspInterface/SlaveSpi.v"
-#    "C:/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PCIeImports/board_common.vh"
-#    "C:/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PCIeImports/pipe_interconnect.vh"
-#    "C:/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PCIeImports/board.v"
-#    "C:/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PCIeImports/pci_exp_usrapp_cfg.v"
-#    "C:/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PCIeImports/pci_exp_expect_tasks.vh"
-#    "C:/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PCIeImports/pci_exp_usrapp_com.v"
-#    "C:/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PCIeImports/pci_exp_usrapp_pl.v"
-#    "C:/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PCIeImports/pci_exp_usrapp_rx.v"
-#    "C:/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PCIeImports/tests.vh"
-#    "C:/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PCIeImports/sample_tests1.vh"
-#    "C:/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PCIeImports/pci_exp_usrapp_tx.v"
-#    "C:/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PCIeImports/pcie1234_gt_top_pipe_mode.v"
-#    "C:/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PCIeImports/pcie_2_1_rport_7x.v"
-#    "C:/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PCIeImports/pcie_axi_trn_bridge.v"
-#    "C:/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PCIeImports/sys_clk_gen.v"
-#    "C:/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PCIeImports/sys_clk_gen_ds.v"
-#    "C:/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PCIeImports/xil_sig2pipe.v"
-#    "C:/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PCIeImports/xilinx_pcie_2_1_rport_7x.v"
+#    "C:/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/synth_1/PciVnaEmulTop.dcp"
 #
 # 3. The following remote source files that were added to the original project:-
 #
@@ -188,93 +111,6 @@
 
 # Check file required for this script exists
 proc checkRequiredFiles { origin_dir} {
-  set status true
-  set files [list \
- "[file normalize "$origin_dir/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PulseMeas/ActivePortSelector.v"]"\
- "[file normalize "$origin_dir/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/InternalDsp/AdcCalibration.v"]"\
- "[file normalize "$origin_dir/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/InternalDsp/ComplPrng.v"]"\
- "[file normalize "$origin_dir/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/InternalDsp/CordicNco.v"]"\
- "[file normalize "$origin_dir/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/InternalDsp/CordicRotation.v"]"\
- "[file normalize "$origin_dir/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/DitherGen/DitherGenv2.v"]"\
- "[file normalize "$origin_dir/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/InternalDsp/DspPipeline.v"]"\
- "[file normalize "$origin_dir/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PCIeImports/EP_MEM.v"]"\
- "[file normalize "$origin_dir/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/Math/FpCustomMultiplier.v"]"\
- "[file normalize "$origin_dir/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/GainOverloadControl/GainControl.v"]"\
- "[file normalize "$origin_dir/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/GainOverloadControl/GainControlWrapper.v"]"\
- "[file normalize "$origin_dir/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/InitRst/InitRst.v"]"\
- "[file normalize "$origin_dir/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/Top/IntermediateLogic.v"]"\
- "[file normalize "$origin_dir/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/InternalDsp/InternalDsp.v"]"\
- "[file normalize "$origin_dir/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/InternalDsp/MeasCtrlModule.v"]"\
- "[file normalize "$origin_dir/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PulseMeas/MeasStartEventGen.v"]"\
- "[file normalize "$origin_dir/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/Math/MultModule.v"]"\
- "[file normalize "$origin_dir/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PulseMeas/Mux.v"]"\
- "[file normalize "$origin_dir/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/Math/MyIntToFp.v"]"\
- "[file normalize "$origin_dir/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/InternalDsp/NcoRstGen.v"]"\
- "[file normalize "$origin_dir/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/GainOverloadControl/OverloadDetect.v"]"\
- "[file normalize "$origin_dir/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PulseMeas/PGenRstGenerator.v"]"\
- "[file normalize "$origin_dir/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PCIeImports/PIO.v"]"\
- "[file normalize "$origin_dir/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PCIeImports/PIO_EP.v"]"\
- "[file normalize "$origin_dir/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PCIeImports/PIO_EP_MEM_ACCESS.v"]"\
- "[file normalize "$origin_dir/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PCIeImports/PIO_RX_ENGINE.v"]"\
- "[file normalize "$origin_dir/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PCIeImports/PIO_TO_CTRL.v"]"\
- "[file normalize "$origin_dir/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PCIeImports/PIO_TX_ENGINE.v"]"\
- "[file normalize "$origin_dir/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PulseMeas/PulseGen.v"]"\
- "[file normalize "$origin_dir/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/RegMap/RegMap.v"]"\
- "[file normalize "$origin_dir/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/Top/S5443Top.v"]"\
- "[file normalize "$origin_dir/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PulseMeas/SampleStrobeGenRstDemux.v"]"\
- "[file normalize "$origin_dir/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/Math/SimpleMult.v"]"\
- "[file normalize "$origin_dir/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PulseMeas/StartAfterGainSel.v"]"\
- "[file normalize "$origin_dir/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/Math/SumAcc.v"]"\
- "[file normalize "$origin_dir/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PulseMeas/TrigInt2Mux.v"]"\
- "[file normalize "$origin_dir/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/InternalDsp/WinParameters.v"]"\
- "[file normalize "$origin_dir/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/InternalDsp/Win_calc.v"]"\
- "[file normalize "$origin_dir/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PCIeImports/pcie1234_pipe_clock.v"]"\
- "[file normalize "$origin_dir/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PCIeImports/pcie1234_support.v"]"\
- "[file normalize "$origin_dir/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PCIeImports/pcie_app_7x.v"]"\
- "[file normalize "$origin_dir/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PCIeImports/xilinx_pcie_2_1_ep_7x.v"]"\
- "[file normalize "$origin_dir/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/Top/PciVnaEmulTop.v"]"\
- "[file normalize "$origin_dir/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/AdcDataRx/AdcSync.v"]"\
- "[file normalize "$origin_dir/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/AdcDataRx/delay_controller_wrap.v"]"\
- "[file normalize "$origin_dir/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/AdcDataRx/n_x_serdes_1_to_7_mmcm_idelay_sdr.v"]"\
- "[file normalize "$origin_dir/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/AdcDataRx/serdes_1_to_7_mmcm_idelay_sdr.v"]"\
- "[file normalize "$origin_dir/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/AdcDataRx/serdes_1_to_7_slave_idelay_sdr.v"]"\
- "[file normalize "$origin_dir/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/AdcDataRx/top5x2_7to1_sdr_rx.v"]"\
- "[file normalize "$origin_dir/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/AdcDataRx/AdcDataInterface.v"]"\
- "[file normalize "$origin_dir/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/ClkGen/Clk200Gen.v"]"\
- "[file normalize "$origin_dir/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/ExtDspInterface/DspInterface.v"]"\
- "[file normalize "$origin_dir/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/ExtDspInterface/DspPpiOut.v"]"\
- "[file normalize "$origin_dir/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/MeasDataFifo/FifoController.v"]"\
- "[file normalize "$origin_dir/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/Top/IntermediateLogicTb.v"]"\
- "[file normalize "$origin_dir/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/MeasDataFifo/MeasDataFifoWrapper.v"]"\
- "[file normalize "$origin_dir/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PulseMeas/PulseGenNew.v"]"\
- "[file normalize "$origin_dir/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/Sim/S5443TopPulseProfileTb.v"]"\
- "[file normalize "$origin_dir/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/Sim/S5443TopSimpleMeasTb.v"]"\
- "[file normalize "$origin_dir/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/ExtDspInterface/SlaveSpi.v"]"\
- "[file normalize "$origin_dir/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PCIeImports/board_common.vh"]"\
- "[file normalize "$origin_dir/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PCIeImports/pipe_interconnect.vh"]"\
- "[file normalize "$origin_dir/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PCIeImports/board.v"]"\
- "[file normalize "$origin_dir/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PCIeImports/pci_exp_usrapp_cfg.v"]"\
- "[file normalize "$origin_dir/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PCIeImports/pci_exp_expect_tasks.vh"]"\
- "[file normalize "$origin_dir/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PCIeImports/pci_exp_usrapp_com.v"]"\
- "[file normalize "$origin_dir/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PCIeImports/pci_exp_usrapp_pl.v"]"\
- "[file normalize "$origin_dir/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PCIeImports/pci_exp_usrapp_rx.v"]"\
- "[file normalize "$origin_dir/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PCIeImports/tests.vh"]"\
- "[file normalize "$origin_dir/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PCIeImports/sample_tests1.vh"]"\
- "[file normalize "$origin_dir/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PCIeImports/pci_exp_usrapp_tx.v"]"\
- "[file normalize "$origin_dir/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PCIeImports/pcie1234_gt_top_pipe_mode.v"]"\
- "[file normalize "$origin_dir/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PCIeImports/pcie_2_1_rport_7x.v"]"\
- "[file normalize "$origin_dir/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PCIeImports/pcie_axi_trn_bridge.v"]"\
- "[file normalize "$origin_dir/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PCIeImports/sys_clk_gen.v"]"\
- "[file normalize "$origin_dir/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PCIeImports/sys_clk_gen_ds.v"]"\
- "[file normalize "$origin_dir/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PCIeImports/xil_sig2pipe.v"]"\
- "[file normalize "$origin_dir/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PCIeImports/xilinx_pcie_2_1_rport_7x.v"]"\
-  ]
-  foreach ifile $files {
-    if { ![file isfile $ifile] } {
-      puts " Could not find local file $ifile "
-      set status false
-    }
-  }
 
   set files [list \
  "[file normalize "$origin_dir/VNA_PCIE_REPO/src/src/PulseMeas/ActivePortSelector.v"]"\
@@ -383,7 +219,7 @@ if { [info exists ::user_project_name] } {
 }
 
 variable script_file
-set script_file "recreate.tcl"
+set script_file "recreate_vna_pcie.tcl"
 
 # Help information for this script
 proc print_help {} {
@@ -465,15 +301,7 @@ set_property -name "part" -value "xc7a100tfgg484-2" -objects $obj
 set_property -name "revised_directory_structure" -value "1" -objects $obj
 set_property -name "sim.central_dir" -value "$proj_dir/${_xil_proj_name_}.ip_user_files" -objects $obj
 set_property -name "sim.ip.auto_export_scripts" -value "1" -objects $obj
-set_property -name "simulator_language" -value "Mixed" -objects $obj
 set_property -name "sim_compile_state" -value "1" -objects $obj
-set_property -name "webtalk.activehdl_export_sim" -value "1" -objects $obj
-set_property -name "webtalk.modelsim_export_sim" -value "1" -objects $obj
-set_property -name "webtalk.questa_export_sim" -value "1" -objects $obj
-set_property -name "webtalk.riviera_export_sim" -value "1" -objects $obj
-set_property -name "webtalk.vcs_export_sim" -value "1" -objects $obj
-set_property -name "webtalk.xcelium_export_sim" -value "1" -objects $obj
-set_property -name "webtalk.xsim_export_sim" -value "1" -objects $obj
 set_property -name "xpm_libraries" -value "XPM_CDC XPM_MEMORY" -objects $obj
 
 # Create 'sources_1' fileset (if not found)
@@ -591,6 +419,20 @@ set file [file normalize $file]
 set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
 set_property -name "file_type" -value "Verilog Header" -objects $file_obj
 
+
+# Set 'sources_1' fileset file properties for local files
+# None
+
+# Set 'sources_1' fileset properties
+set obj [get_filesets sources_1]
+set_property -name "dataflow_viewer_settings" -value "min_width=16" -objects $obj
+set_property -name "top" -value "PciVnaEmulTop" -objects $obj
+set_property -name "top_auto_set" -value "0" -objects $obj
+
+# Set 'sources_1' fileset object
+set obj [get_filesets sources_1]
+
+
 # Create 'constrs_1' fileset (if not found)
 if {[string equal [get_filesets -quiet constrs_1] ""]} {
   create_fileset -constrset constrs_1
@@ -609,9 +451,7 @@ set_property -name "file_type" -value "XDC" -objects $file_obj
 
 # Set 'constrs_1' fileset properties
 set obj [get_filesets constrs_1]
-set_property -name "target_constrs_file" -value "[file normalize "$origin_dir/VNA_PCIE_REPO/src/consrtrs/xilinx_pcie_7x_ep_x1g1.xdc"]" -objects $obj
 set_property -name "target_part" -value "xc7a100tfgg484-2" -objects $obj
-set_property -name "target_ucf" -value "[file normalize "$origin_dir/VNA_PCIE_REPO/src/consrtrs/xilinx_pcie_7x_ep_x1g1.xdc"]" -objects $obj
 
 # Create 'sim_1' fileset (if not found)
 if {[string equal [get_filesets -quiet sim_1] ""]} {
@@ -625,92 +465,12 @@ set obj [get_filesets sim_1]
 # Set 'sim_1' fileset properties
 set obj [get_filesets sim_1]
 set_property -name "top" -value "AdcDataInterface" -objects $obj
-set_property -name "top_auto_set" -value "0" -objects $obj
 set_property -name "top_lib" -value "xil_defaultlib" -objects $obj
 
 # Set 'utils_1' fileset object
 set obj [get_filesets utils_1]
 # Import local files from the original project
-set files [list \
- [file normalize "${origin_dir}/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PulseMeas/ActivePortSelector.v"]\
- [file normalize "${origin_dir}/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/InternalDsp/AdcCalibration.v"]\
- [file normalize "${origin_dir}/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/InternalDsp/ComplPrng.v"]\
- [file normalize "${origin_dir}/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/InternalDsp/CordicNco.v"]\
- [file normalize "${origin_dir}/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/InternalDsp/CordicRotation.v"]\
- [file normalize "${origin_dir}/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/DitherGen/DitherGenv2.v"]\
- [file normalize "${origin_dir}/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/InternalDsp/DspPipeline.v"]\
- [file normalize "${origin_dir}/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PCIeImports/EP_MEM.v"]\
- [file normalize "${origin_dir}/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/Math/FpCustomMultiplier.v"]\
- [file normalize "${origin_dir}/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/GainOverloadControl/GainControl.v"]\
- [file normalize "${origin_dir}/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/GainOverloadControl/GainControlWrapper.v"]\
- [file normalize "${origin_dir}/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/InitRst/InitRst.v"]\
- [file normalize "${origin_dir}/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/Top/IntermediateLogic.v"]\
- [file normalize "${origin_dir}/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/InternalDsp/InternalDsp.v"]\
- [file normalize "${origin_dir}/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/InternalDsp/MeasCtrlModule.v"]\
- [file normalize "${origin_dir}/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PulseMeas/MeasStartEventGen.v"]\
- [file normalize "${origin_dir}/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/Math/MultModule.v"]\
- [file normalize "${origin_dir}/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PulseMeas/Mux.v"]\
- [file normalize "${origin_dir}/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/Math/MyIntToFp.v"]\
- [file normalize "${origin_dir}/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/InternalDsp/NcoRstGen.v"]\
- [file normalize "${origin_dir}/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/GainOverloadControl/OverloadDetect.v"]\
- [file normalize "${origin_dir}/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PulseMeas/PGenRstGenerator.v"]\
- [file normalize "${origin_dir}/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PCIeImports/PIO.v"]\
- [file normalize "${origin_dir}/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PCIeImports/PIO_EP.v"]\
- [file normalize "${origin_dir}/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PCIeImports/PIO_EP_MEM_ACCESS.v"]\
- [file normalize "${origin_dir}/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PCIeImports/PIO_RX_ENGINE.v"]\
- [file normalize "${origin_dir}/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PCIeImports/PIO_TO_CTRL.v"]\
- [file normalize "${origin_dir}/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PCIeImports/PIO_TX_ENGINE.v"]\
- [file normalize "${origin_dir}/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PulseMeas/PulseGen.v"]\
- [file normalize "${origin_dir}/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/RegMap/RegMap.v"]\
- [file normalize "${origin_dir}/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/Top/S5443Top.v"]\
- [file normalize "${origin_dir}/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PulseMeas/SampleStrobeGenRstDemux.v"]\
- [file normalize "${origin_dir}/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/Math/SimpleMult.v"]\
- [file normalize "${origin_dir}/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PulseMeas/StartAfterGainSel.v"]\
- [file normalize "${origin_dir}/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/Math/SumAcc.v"]\
- [file normalize "${origin_dir}/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PulseMeas/TrigInt2Mux.v"]\
- [file normalize "${origin_dir}/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/InternalDsp/WinParameters.v"]\
- [file normalize "${origin_dir}/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/InternalDsp/Win_calc.v"]\
- [file normalize "${origin_dir}/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PCIeImports/pcie1234_pipe_clock.v"]\
- [file normalize "${origin_dir}/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PCIeImports/pcie1234_support.v"]\
- [file normalize "${origin_dir}/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PCIeImports/pcie_app_7x.v"]\
- [file normalize "${origin_dir}/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PCIeImports/xilinx_pcie_2_1_ep_7x.v"]\
- [file normalize "${origin_dir}/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/Top/PciVnaEmulTop.v"]\
- [file normalize "${origin_dir}/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/AdcDataRx/AdcSync.v"]\
- [file normalize "${origin_dir}/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/AdcDataRx/delay_controller_wrap.v"]\
- [file normalize "${origin_dir}/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/AdcDataRx/n_x_serdes_1_to_7_mmcm_idelay_sdr.v"]\
- [file normalize "${origin_dir}/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/AdcDataRx/serdes_1_to_7_mmcm_idelay_sdr.v"]\
- [file normalize "${origin_dir}/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/AdcDataRx/serdes_1_to_7_slave_idelay_sdr.v"]\
- [file normalize "${origin_dir}/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/AdcDataRx/top5x2_7to1_sdr_rx.v"]\
- [file normalize "${origin_dir}/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/AdcDataRx/AdcDataInterface.v"]\
- [file normalize "${origin_dir}/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/ClkGen/Clk200Gen.v"]\
- [file normalize "${origin_dir}/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/ExtDspInterface/DspInterface.v"]\
- [file normalize "${origin_dir}/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/ExtDspInterface/DspPpiOut.v"]\
- [file normalize "${origin_dir}/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/MeasDataFifo/FifoController.v"]\
- [file normalize "${origin_dir}/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/Top/IntermediateLogicTb.v"]\
- [file normalize "${origin_dir}/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/MeasDataFifo/MeasDataFifoWrapper.v"]\
- [file normalize "${origin_dir}/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PulseMeas/PulseGenNew.v"]\
- [file normalize "${origin_dir}/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/Sim/S5443TopPulseProfileTb.v"]\
- [file normalize "${origin_dir}/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/Sim/S5443TopSimpleMeasTb.v"]\
- [file normalize "${origin_dir}/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/ExtDspInterface/SlaveSpi.v"]\
- [file normalize "${origin_dir}/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PCIeImports/board_common.vh"]\
- [file normalize "${origin_dir}/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PCIeImports/pipe_interconnect.vh"]\
- [file normalize "${origin_dir}/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PCIeImports/board.v"]\
- [file normalize "${origin_dir}/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PCIeImports/pci_exp_usrapp_cfg.v"]\
- [file normalize "${origin_dir}/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PCIeImports/pci_exp_expect_tasks.vh"]\
- [file normalize "${origin_dir}/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PCIeImports/pci_exp_usrapp_com.v"]\
- [file normalize "${origin_dir}/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PCIeImports/pci_exp_usrapp_pl.v"]\
- [file normalize "${origin_dir}/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PCIeImports/pci_exp_usrapp_rx.v"]\
- [file normalize "${origin_dir}/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PCIeImports/tests.vh"]\
- [file normalize "${origin_dir}/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PCIeImports/sample_tests1.vh"]\
- [file normalize "${origin_dir}/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PCIeImports/pci_exp_usrapp_tx.v"]\
- [file normalize "${origin_dir}/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PCIeImports/pcie1234_gt_top_pipe_mode.v"]\
- [file normalize "${origin_dir}/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PCIeImports/pcie_2_1_rport_7x.v"]\
- [file normalize "${origin_dir}/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PCIeImports/pcie_axi_trn_bridge.v"]\
- [file normalize "${origin_dir}/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PCIeImports/sys_clk_gen.v"]\
- [file normalize "${origin_dir}/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PCIeImports/sys_clk_gen_ds.v"]\
- [file normalize "${origin_dir}/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PCIeImports/xil_sig2pipe.v"]\
- [file normalize "${origin_dir}/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PCIeImports/xilinx_pcie_2_1_rport_7x.v"]\
-]
+
 set imported_files ""
 foreach f $files {
   lappend imported_files [import_files -fileset utils_1 $f]
@@ -719,26 +479,7 @@ foreach f $files {
 # Set 'utils_1' fileset file properties for remote files
 # None
 
-# Set 'utils_1' fileset file properties for local files
-set file "PCIeImports/board_common.vh"
-set file_obj [get_files -of_objects [get_filesets utils_1] [list "*$file"]]
-set_property -name "file_type" -value "Verilog Header" -objects $file_obj
 
-set file "PCIeImports/pipe_interconnect.vh"
-set file_obj [get_files -of_objects [get_filesets utils_1] [list "*$file"]]
-set_property -name "file_type" -value "Verilog Header" -objects $file_obj
-
-set file "PCIeImports/pci_exp_expect_tasks.vh"
-set file_obj [get_files -of_objects [get_filesets utils_1] [list "*$file"]]
-set_property -name "file_type" -value "Verilog Header" -objects $file_obj
-
-set file "PCIeImports/tests.vh"
-set file_obj [get_files -of_objects [get_filesets utils_1] [list "*$file"]]
-set_property -name "file_type" -value "Verilog Header" -objects $file_obj
-
-set file "PCIeImports/sample_tests1.vh"
-set file_obj [get_files -of_objects [get_filesets utils_1] [list "*$file"]]
-set_property -name "file_type" -value "Verilog Header" -objects $file_obj
 
 
 # Set 'utils_1' fileset properties
@@ -1060,7 +801,6 @@ move_dashboard_gadget -name {timing_1} -row 0 -col 1
 move_dashboard_gadget -name {utilization_2} -row 1 -col 1
 move_dashboard_gadget -name {methodology_1} -row 2 -col 1
 
-
 ##################################################################
 # CHECK VIVADO VERSION
 ##################################################################