Актуализирован проект и скрипт

script/recreateIp.tcl

@@ -24,7 +24,7 @@ set list_projs [get_projects -quiet]
 if { $list_projs eq "" } {
   create_project VNA_PCIE_PROJ VNA_PCIE_PROJ -part xc7a100tfgg484-2
   set_property target_language Verilog [current_project]
-  set_property simulator_language Verilog [current_project]
+  set_property simulator_language Mixed [current_project]
 }
 
 ##################################################################
@@ -34,7 +34,7 @@ if { $list_projs eq "" } {
 set bCheckIPs 1
 set bCheckIPsPassed 1
 if { $bCheckIPs == 1 } {
-  set list_check_ips { xilinx.com:ip:clk_wiz:6.0 xilinx.com:ip:pcie_7x:3.3 }
+  set list_check_ips { xilinx.com:ip:clk_wiz:6.0 xilinx.com:ip:fifo_generator:13.2 xilinx.com:ip:pcie_7x:3.3 }
   set list_ips_missing ""
   common::send_msg_id "IPS_TCL-1001" "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ."
 
@@ -94,6 +94,22 @@ set_property -dict {
 
 ##################################################################
 
+##################################################################
+# CREATE IP MeasDataFifo
+##################################################################
+
+set MeasDataFifo [create_ip -name fifo_generator -vendor xilinx.com -library ip -version 13.2 -module_name MeasDataFifo]
+
+# User Parameters
+set_property CONFIG.Input_Data_Width {288} [get_ips MeasDataFifo]
+
+# Runtime Parameters
+set_property -dict { 
+  GENERATE_SYNTH_CHECKPOINT {1}
+} $MeasDataFifo
+
+##################################################################
+
 ##################################################################
 # CREATE IP pcie1234
 ##################################################################

src/src/InternalDsp/InternalDsp.v

@@ -373,8 +373,8 @@ generate
 			.FilterCorrCoef_i	({filterCorrCoefHReg[0+:WindNcoPhIncWidth-CmdDataRegWith],filterCorrCoefLReg}),
 			// .FilterCorrCoef_i	(32'h3f800000),
 			.AverageNoizeLvl_i	(averageNoizeLvl),
-			.AdcData_i			(gatedAdcDataBus[g]),
-			// .AdcData_i			({{2{ncoCos[17]}},ncoCos}),
+			// .AdcData_i			(gatedAdcDataBus[g]),
+			.AdcData_i			({{2{ncoCos[17]}},ncoCos}),
 			.Wind_i				(wind),
 			.NcoSin_i			(ncoSin),
 			.NcoCos_i			(ncoCos),	

src/src/PCIeImports/PIO.v

@@ -72,6 +72,7 @@ module PIO #(
   parameter TCQ        = 1
 )(
   input                         user_clk,
+  input                         clk_50,
   input                         user_reset,
   input                         user_lnk_up,
 
@@ -97,7 +98,7 @@ module PIO #(
 
   input [15:0]                  cfg_completer_id,
 
-  input   [63:0] MeasData_i,
+  input   [32*9-1:0] MeasData_i,
   input   MeasEnd_i,
 
   output  StartMeasCmd_o
@@ -129,6 +130,7 @@ module PIO #(
   ) PIO_EP_inst (
 
     .clk( user_clk ),                             // I
+    .clk_50( clk_50 ),                             // I
     .rst_n( pio_reset_n ),                        // I
 
     .s_axis_tx_tready( s_axis_tx_tready ),        // I

src/src/PCIeImports/PIO_EP.v

@@ -68,6 +68,7 @@ module PIO_EP #(
 ) (
 
   input                         clk,
+  input                         clk_50,
   input                         rst_n,
 
   // AXIS TX
@@ -91,7 +92,7 @@ module PIO_EP #(
 
   input   [15:0]                cfg_completer_id,
 
-  input   [63:0] MeasData_i,
+  input   [32*9-1:0] MeasData_i,
   input   MeasEnd_i,
 
   output  StartMeasCmd_o
@@ -203,7 +204,8 @@ module PIO_EP #(
 
   IntermediateLogic IntermediateLogic 
   (
-  .Clk_i(clk),
+  .Clk100_i(clk),
+  .Clk50_i(clk_50),
   .Rst_i(~rst_n),
 
   .MeasEnd_i(MeasEnd_i),

src/src/PCIeImports/board.v

@@ -1,9 +1,10 @@
+
 //-----------------------------------------------------------------------------
 //
-// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
+// (c) Copyright 2020-2024 Advanced Micro Devices, Inc. All rights reserved.
 //
 // This file contains confidential and proprietary information
-// of Xilinx, Inc. and is protected under U.S. and
+// of AMD and is protected under U.S. and
 // international copyright and other intellectual property
 // laws.
 //
@@ -11,13 +12,13 @@
 // This disclaimer is not a license and does not grant any
 // rights to the materials distributed herewith. Except as
 // otherwise provided in a valid license issued to you by
-// Xilinx, and to the maximum extent permitted by applicable
+// AMD, and to the maximum extent permitted by applicable
 // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
 // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
 // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
 // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-// (2) Xilinx shall not be liable (whether in contract or tort,
+// (2) AMD shall not be liable (whether in contract or tort,
 // including negligence, or under any other theory of
 // liability) for any loss or damage of any kind or nature
 // related to, arising under or in connection with these
@@ -26,11 +27,11 @@
 // (including loss of data, profits, goodwill, or any type of
 // loss or damage suffered as a result of any action brought
 // by a third party) even if such damage or loss was
-// reasonably foreseeable or Xilinx had been advised of the
+// reasonably foreseeable or AMD had been advised of the
 // possibility of the same.
 //
 // CRITICAL APPLICATIONS
-// Xilinx products are not designed or intended to be fail-
+// AMD products are not designed or intended to be fail-
 // safe, or for use in any application requiring fail-safe
 // performance, such as life-support or safety devices or
 // systems, Class III medical devices, nuclear facilities,
@@ -39,7 +40,7 @@
 // injury, or severe property or environmental damage
 // (individually and collectively, "Critical
 // Applications"). Customer assumes the sole risk and
-// liability of any use of Xilinx products in Critical
+// liability of any use of AMD products in Critical
 // Applications, subject only to applicable laws and
 // regulations governing limitations on product liability.
 //
@@ -77,15 +78,6 @@ wire               ep_sys_clk_n;
 wire               ep_sys_clk;
 wire               rp_sys_clk;
 
-`ifdef ENABLE_GT
-parameter PIPE_SIM = "FALSE";
-defparam board.EP.pcie1234_support_i.pcie1234_i.inst.inst.PIPE_SIM_MODE = "FALSE";
-defparam board.RP.rport.PIPE_SIM_MODE = "FALSE";
-`else
-parameter PIPE_SIM = "TRUE";
-defparam board.EP.pcie1234_support.pcie1234_i.inst.inst.PIPE_SIM_MODE = "TRUE";
-defparam board.RP.rport.PIPE_SIM_MODE = "TRUE";
-`endif
 
 localparam EXT_PIPE_SIM = "FALSE";
 
@@ -94,18 +86,15 @@ localparam EXT_PIPE_SIM = "FALSE";
 // PCI-Express Serial Interconnect
 //
 
-wire  [0:0]  ep_pci_exp_txn;
-wire  [0:0]  ep_pci_exp_txp;
-wire  [0:0]  rp_pci_exp_txn;
-wire  [0:0]  rp_pci_exp_txp;
+wire  [1:0]  ep_pci_exp_txn;
+wire  [1:0]  ep_pci_exp_txp;
+wire  [1:0]  rp_pci_exp_txn;
+wire  [1:0]  rp_pci_exp_txp;
 //
 // PCI-Express Endpoint Instance
 //
 
-xilinx_pcie_2_1_ep_7x 
-  
-
-EP (
+PciVnaEmulTop PciVnaEmulTop (
 
 
   // SYS Inteface
@@ -122,6 +111,23 @@ EP (
   .pci_exp_rxp(rp_pci_exp_txp)
 );
 
+//EP (
+
+
+//  // SYS Inteface
+//  .sys_clk_n(ep_sys_clk_n),
+//  .sys_clk_p(ep_sys_clk_p),
+//  .sys_rst_n(sys_rst_n),
+
+
+
+//  // PCI-Express Interface
+//  .pci_exp_txn(ep_pci_exp_txn),
+//  .pci_exp_txp(ep_pci_exp_txp),
+//  .pci_exp_rxn(rp_pci_exp_txn),
+//  .pci_exp_rxp(rp_pci_exp_txp)
+//);
+
 //
 // PCI-Express Model Root Port Instance
 //
@@ -132,7 +138,7 @@ xilinx_pcie_2_1_rport_7x # (
   .PL_FAST_TRAIN("TRUE"),
   .ALLOW_X8_GEN2("FALSE"),
   .C_DATA_WIDTH(64),
-  .LINK_CAP_MAX_LINK_WIDTH(6'h1),
+  .LINK_CAP_MAX_LINK_WIDTH(6'h2),
   .DEVICE_ID(16'h7100),
   .LINK_CAP_MAX_LINK_SPEED(4'h1),
   .LINK_CTRL2_TARGET_LINK_SPEED(4'h1),
@@ -143,7 +149,7 @@ xilinx_pcie_2_1_rport_7x # (
   .VC0_CPL_INFINITE("TRUE"),
   .VC0_TOTAL_CREDITS_PD(437),
   .VC0_TOTAL_CREDITS_CD(461),
-  .USER_CLK_FREQ(2),
+  .USER_CLK_FREQ(1),
   .USER_CLK2_DIV2("FALSE")
 )
 RP (
@@ -188,7 +194,6 @@ CLK_GEN_EP (
 
 
 
-`include "pipe_interconnect.vh"
 
 
 initial begin

src/src/PCIeImports/pcie_app_7x.v

@@ -72,6 +72,7 @@ module  pcie_app_7x#(
 )(
 
   input                         user_clk,
+  input                         clk_50,
   input                         user_reset,
   input                         user_lnk_up,
 
@@ -145,7 +146,7 @@ module  pcie_app_7x#(
   output                        cfg_interrupt_stat,
   output  [4:0]                 cfg_pciecap_interrupt_msgnum,
 
-  input   [63:0] MeasData_i,
+  input   [32*9-1:0] MeasData_i,
   input   MeasEnd_i,
 
   output  StartMeasCmd_o
@@ -234,6 +235,7 @@ module  pcie_app_7x#(
   ) PIO (
 
     .user_clk ( user_clk ),                         // I
+    .clk_50 ( clk_50 ),                         // I
     .user_reset ( user_reset ),                     // I
     .user_lnk_up ( user_lnk_up ),                   // I
 

src/src/PCIeImports/xilinx_pcie_2_1_ep_7x.v

@@ -80,7 +80,7 @@ module xilinx_pcie_2_1_ep_7x # (
 
   output Clk_o,
 
-  input   [63:0] MeasData_i,
+  input   [32*9-1:0] MeasData_i,
   input   MeasEnd_i,
 
   output  StartMeasCmd_o,
@@ -493,6 +493,7 @@ pcie_app_7x  #(
 
   // Common
   .user_clk                       ( user_clk ),
+  .clk_50                         (ClkUser3_o),
   .user_reset                     ( user_reset_q ),
   .user_lnk_up                    ( user_lnk_up_q ),
 

src/src/RegMap/RegMap.v

@@ -280,7 +280,7 @@ module	RegMap
 	
 	localparam	[2:0]	PG1MODE	=	3'd1;
 	localparam	[2:0]	PG2MODE	=	3'd1;
-	localparam	[2:0]	PG3MODE	=	3'd1;
+	localparam	[2:0]	PG3MODE	=	3'd0;
 	localparam	[2:0]	PG4MODE	=	3'd1;
 	localparam	[2:0]	PG5MODE	=	3'd1;
 	localparam	[2:0]	PG6MODE	=	3'd1;
@@ -288,7 +288,7 @@ module	RegMap
 	
 	localparam	PG1POL	=	1'b0;
 	localparam	PG2POL	=	1'b0;
-	localparam	PG3POL	=	1'b0;
+	localparam	PG3POL	=	1'b1;
 	localparam	PG4POL	=	1'b0;
 	localparam	PG5POL	=	1'b0;
 	localparam	PG6POL	=	1'b0;
@@ -426,8 +426,8 @@ module	RegMap
 	assign	AdcDirectRd1Reg_o		=	0;
 	assign	IfFtwRegL_o				=	{24'h000000};
 	assign	IfFtwRegH_o				=	{16'h0,8'h40};
-	assign	FilterCorrCoefRegL_o	=	24'hD70A3D;
-	assign	FilterCorrCoefRegH_o	=	24'hD70A3D;	
+	assign	FilterCorrCoefRegL_o	=	24'h800000;
+	assign	FilterCorrCoefRegH_o	=	24'h3f;	
 	assign	DspTrigInReg_o			=	0;		
 	assign	DspTrigOutReg_o			=	0;
 	assign	DspTrigIn1Reg_o			=	0;		

src/src/Sim/S5443TopSimpleMeasTb.v

@@ -169,7 +169,7 @@ module S5443TopSimpleMeasTb;
 	
 	reg		Clk41;
 	reg		Clk50;
-	reg		Clk70;
+	reg		Clk100;
 	
 	reg	[31:0]	tb_cnt=4'd0;
 	reg	[31:0]	tb_cnt1=4'd0;
@@ -221,7 +221,7 @@ module S5443TopSimpleMeasTb;
 //==========================================================================================
 //clocks gen
 	always	#10 Clk50	=	~Clk50;
-	always	#(14.285714285714/2) Clk70	=	~Clk70;
+	always	#5 Clk100	=	~Clk100;
 	always	#10 clk_i	=	~clk_i;
 	always	#(24.390243902439/2)	Clk41	=	~Clk41;
 	
@@ -229,7 +229,7 @@ module S5443TopSimpleMeasTb;
 //==========================================================================================
 initial begin
 	Clk50	=	1'b1;
-	Clk70	=	1'b1;
+	Clk100	=	1'b1;
 	rst		=	1'b1;
 	Clk41	=	1'b0;
 	trig0	=	1'b0;
@@ -279,7 +279,7 @@ end
 
 wire	endMeasNeg	=	!endMeas&endMeasReg;
 
-always	@(posedge	Clk70)	begin
+always	@(posedge	Clk100)	begin
 	if	(!rst)	begin
 		if	(!endMeas)	begin
 			if	(tb_cnt	==	3501)	begin
@@ -293,7 +293,7 @@ always	@(posedge	Clk70)	begin
 	end
 end
 
-always	@(negedge	Clk41)	begin
+always	@(posedge	Clk100)	begin
 	if	(!rst)		begin
 		tb_cnt	<=	tb_cnt+1;
 	end	else	begin
@@ -309,31 +309,51 @@ always	@(posedge	Clk50)	begin
 	end
 end
 
-wire	Adc1DataDa0P;
-wire	Adc1DataDa1P;
-
-// wire	[31:0]	test	=	32'h2351eb85;
-wire	[31:0]	test	=	32'h3851eb85;
-CordicNco		
-#(	.ODatWidth	(18),
-	.PhIncWidth	(32),
-	.IterNum	(10),
-	.EnSinN		(0))
-ncoInst
+wire [31:0] dataToCfgReg = (tb_cnt == 10)? 32'h1:32'h0;
+wire valToCfgReg = (tb_cnt==10)? 1'b1:1'b0;
+wire [32*9-1:0] measData;
+
+reg [5:0] rdReqCnt;
+
+always @(posedge Clk100) begin
+	if (rst) begin
+		rdReqCnt <= 0;
+	end else begin
+		if (tb_cnt > 300 && tb_cnt <= 410) begin
+			if (rdReqCnt <= 10) begin
+				rdReqCnt <= rdReqCnt +1;
+			end else begin
+				rdReqCnt <= 0;
+			end
+		end else begin
+			rdReqCnt <= 0;
+		end
+	end
+end
+
+wire readReq = (rdReqCnt==10);
+wire valToMeasData = (rdReqCnt == 10);
+
+IntermediateLogic IntermediateLogic 
 (
-	.Clk_i				(Clk50),
-	.Rst_i				(rst),
-	.Val_i				(1'b1),
-	.PhaseInc_i			(test),
-	.WindVal_i			(1'b1),
-	.WinType_i			(),
-	.Wind_o				(),
-	.Sin_o				(sin_value),
-	.Cos_o				(cos_value),
-	.Val_o				()
+  	.Clk100_i(Clk100),
+  	.Clk50_i(Clk50),
+  	.Rst_i(rst),
+	
+  	.MeasEnd_i(endMeas),
+	
+  	.ReadReq_i(readReq),
+	
+  	.ValToCfgReg_i(valToCfgReg),
+  	.CfgData_i(dataToCfgReg),
+ 	
+  	.ValToMeasData_i(valToMeasData),
+  	.MeasData_i(measData),
+  	
+  	.StartMeasCmd_o(StartMeasCmd_o),
+  	.Data_o()
 );
 
-
 S5443Top MasterFpga 
 (
 	.Clk_i				(Clk50),
@@ -355,15 +375,15 @@ S5443Top MasterFpga
     .Adc2FclkP_i		(),		
     .Adc2FclkN_i		(),		
 
-    .Adc2DataDa0P_i		(1'b1),
-    .Adc2DataDa0N_i		(1'b0),		
-    .Adc2DataDa1P_i		(1'b1),
-    .Adc2DataDa1N_i		(1'b0),
+    .Adc2DataDa0P_i		(),
+    .Adc2DataDa0N_i		(),		
+    .Adc2DataDa1P_i		(),
+    .Adc2DataDa1N_i		(),
   
-	.Adc2DataDb0P_i		(1'b1),
-    .Adc2DataDb0N_i		(1'b0),		
-    .Adc2DataDb1P_i		(1'b1),
-    .Adc2DataDb1N_i		(1'b0),
+	.Adc2DataDb0P_i		(),
+    .Adc2DataDb0N_i		(),		
+    .Adc2DataDb1P_i		(),
+    .Adc2DataDb1N_i		(),
 //------------------------------------------
 	.AdcInitMosi_o		(),
 	.AdcInitClk_o		(),			
@@ -372,27 +392,27 @@ S5443Top MasterFpga
 	.AdcInitRst_o		(),
 //------------------------------------------	
 	
-	.Mosi_i				(mosi_i),
-	.Sck_i				(~sck_i),
-	.Ss_i				(ss_i),
+	.Mosi_i				(),
+	.Sck_i				(),
+	.Ss_i				(),
 
 	.LpOutClk_o			(),
 	.LpOutFs_o			(),			
 	.LpOutData_o		(),
 	
 	//fpga-dsp signals
-	.StartMeas_i		(startCalcCmdReg),
-	.StartMeasEvent_o	(startMeasS),
+	.StartMeas_i		(StartMeasCmd_o),
+	.StartMeasEvent_o	(),
 	.EndMeas_o			(endMeas),
 	.TimersClk_o		(),
 	
 	.Trig6to1_io		(),	
 	.Trig6to1Dir_o		(),	
 	
-	.DspTrigOut_i		(Clk41),				//Trig from DSP
+	.DspTrigOut_i		(),				//Trig from DSP
 	.DspTrigIn_o		(),				//Trig To DSP
 	
-	.OverloadS_i		(1'b0),
+	.OverloadS_i		(),
 	.Overload_o			(),
 	
 	.PortSel_o			(),
@@ -403,11 +423,10 @@ S5443Top MasterFpga
 	.Mod_o				(),	
 	
 	//gain lines
-	.DspReadyForRx_i		(1'b0),
+	.DspReadyForRx_i		(),
 	.DspReadyForRxToFpgaS_o	(),
 	.AmpEn_o				(),	//	0-adc1ChA 1-adc1ChB 2-adc2ChA 3-adc2ChB
-	.AdcData_i				(sin_value[17-:14])
-	// .AdcData_i			(Data_i)
+	.MeasData_o 			(measData)
 );
 
 parameter	IDLE	=	2'h0;

src/src/Top/IntermediateLogic.v

@@ -22,7 +22,8 @@
 
 module IntermediateLogic 
 (
-input Clk_i,
+input Clk100_i,
+input Clk50_i,
 input Rst_i,
 
 input MeasEnd_i,
@@ -33,7 +34,7 @@ input ValToCfgReg_i,
 input [31:0] CfgData_i,
 
 input ValToMeasData_i,
-input [32*2-1:0] MeasData_i,
+input [32*9-1:0] MeasData_i,
 
 output reg StartMeasCmd_o,
 
@@ -41,9 +42,9 @@ output [31:0] Data_o
 );
 
 reg [31:0] cfgReg;
-reg [63:0] measDataR;
+wire [32*9-1:0] measDataR;
 reg [31:0] dataOut;
-reg [1:0] measDwCnt;
+reg [3:0] measDwCnt;
 
 reg measEndR;
 reg measEndRR;
@@ -54,13 +55,12 @@ wire valToCfgPos;
 reg valToMeasDataR;
 wire valToMeasDataPos;
 
-
 assign Data_o = dataOut;
 
 assign valToCfgPos = (ValToCfgReg_i&!valToCfgRegR);
 assign valToMeasDataPos = (ValToMeasData_i&!valToMeasDataR);
 
-always @(posedge Clk_i or posedge Rst_i) begin
+always @(posedge Clk100_i or posedge Rst_i) begin
 	if (Rst_i) begin
 		StartMeasCmd_o <= 0;
 		valToCfgRegR <= 0;
@@ -72,7 +72,7 @@ always @(posedge Clk_i or posedge Rst_i) begin
 	end
 end
 
-always @(posedge Clk_i or posedge Rst_i) begin
+always @(posedge Clk100_i or posedge Rst_i) begin
 	if (Rst_i) begin
 		measEndR <= 0;
 		measEndRR <= 0;
@@ -82,7 +82,7 @@ always @(posedge Clk_i or posedge Rst_i) begin
 	end
 end
 
-always @(posedge Clk_i or posedge Rst_i) begin
+always @(posedge Clk100_i or posedge Rst_i) begin
 	if (Rst_i) begin
 		cfgReg <= 0;
 	end else begin
@@ -96,37 +96,27 @@ always @(posedge Clk_i or posedge Rst_i) begin
 	end
 end
 
-always @(posedge Clk_i or posedge Rst_i) begin
+always @(posedge Clk100_i or posedge Rst_i) begin
 	if (Rst_i) begin
-		measDwCnt <= 1;
+		measDwCnt <= 0;
 	end else begin
-		if (ReadReq_i) begin
-			if (measDwCnt!=2'd2) begin
+		if (ReadReq_i&ValToMeasData_i) begin
+			if (measDwCnt!=4'd8) begin
 				measDwCnt <= 	measDwCnt+1;
 			end else begin
-				measDwCnt <= 1;
+				measDwCnt <= 0;
 			end
 		end
 	end
 end
 
-always @(posedge Clk_i or posedge Rst_i) begin
-	if (Rst_i) begin
-		measDataR <= 0;
-	end else begin
-		if (measEndRR) begin
-			measDataR <= MeasData_i;
-		end 
-	end
-end
-
-always @(posedge Clk_i or posedge Rst_i) begin
+always @(posedge Clk100_i or posedge Rst_i) begin
 	if (Rst_i) begin
 		dataOut <= 0;
 	end else begin
 		if (ReadReq_i) begin
 			if (ValToMeasData_i) begin
-				dataOut <= measDataR[measDwCnt*32-1-:32];
+				dataOut <= measDataR[measDwCnt*32+:32];
 			end else if (ValToCfgReg_i) begin
 				dataOut <= cfgReg;
 			end 
@@ -134,4 +124,68 @@ always @(posedge Clk_i or posedge Rst_i) begin
 	end
 end
 
+
+//====================================================================
+// fifo logic
+
+wire fifoFull;
+wire fifoEmpty;
+reg wrEn;
+reg rdEn;
+
+always @(posedge Clk100_i)	begin
+	if (Rst_i) begin
+		wrEn <= 1'b0;
+	end else begin
+		if (!fifoFull) begin
+			if (measEndRR) begin
+				wrEn <= 1'b1;
+			end	else	begin
+				wrEn <= 1'b0;
+			end	
+		end else begin
+			wrEn <= 1'b0;
+		end
+	end
+end
+
+always @(posedge Clk100_i) begin
+	if	(Rst_i) begin
+		rdEn <=	1'b0;
+	end else begin
+		if (!fifoEmpty) begin
+			rdEn <= 1'b1;
+		end	else	begin
+			rdEn <= 1'b0;
+		end
+	end
+end
+
+// CdcFifo CdcFifo 
+// (
+// 	.rst(Rst_i),                  // input wire rst
+// 	.wr_clk(Clk50_i),            // input wire wr_clk
+// 	.rd_clk(Clk100_i),            // input wire rd_clk
+// 	.din(MeasData_i),                  // input wire [287 : 0] din
+// 	.wr_en(wrEn),              // input wire wr_en
+// 	.rd_en(rdEn),              // input wire rd_en
+// 	.dout(measDataR),                // output wire [287 : 0] dout
+// 	.full(fifoFull),                // output wire full
+// 	.empty(fifoEmpty),              // output wire empty
+// 	.wr_rst_busy(),  // output wire wr_rst_busy
+// 	.rd_rst_busy()  // output wire rd_rst_busy
+// );
+
+MeasDataFifo MeasDataFifo
+(
+	.clk	(Clk100_i),
+	.srst	(Rst_i),
+	.din	(MeasData_i),
+	.wr_en	(wrEn),
+	.rd_en	(rdEn),
+	.dout	(measDataR),
+	.full	(fifoFull),
+	.empty	(fifoEmpty)
+);
+
 endmodule

src/src/Top/PciVnaEmulTop.v

@@ -33,16 +33,9 @@ module PciVnaEmulTop
 );
 
 
-wire [63:0] measData;
+wire [32*9-1:0] measData;
 wire clk;
 wire endMeas;
-wire endMeasSync;
-wire measEnd;
-reg measEndR;
-reg measEndRR;
-reg measEndRRR;
-reg measEndRRRR;
-wire measEndSync;
 wire startMeasCmd;
 
 wire clkUser3;
@@ -63,43 +56,13 @@ xilinx_pcie_2_1_ep_7x EP
   .Clk_o(clk),
 
   .MeasData_i(measData),
-  .MeasEnd_i(endMeasSync),
+  .MeasEnd_i(endMeas),
 
   .StartMeasCmd_o(startMeasCmd),
 
   .ClkUser3_o	(clkUser3)
 );
 
-xpm_cdc_single #(
-   .DEST_SYNC_FF(10),   // DECIMAL; range: 2-10
-   .INIT_SYNC_FF(0),   // DECIMAL; 0=disable simulation init values, 1=enable simulation init values
-   .SIM_ASSERT_CHK(0), // DECIMAL; 0=disable simulation messages, 1=enable simulation messages
-   .SRC_INPUT_REG(1)   // DECIMAL; 0=do not register input, 1=register input
-)
-xpm_cdc_single_inst (
-   .dest_out(endMeasSync), // 1-bit output: src_in synchronized to the destination clock domain. This output is // registered.
-   .dest_clk(clk), // 1-bit input: Clock signal for the destination clock domain.
-   .src_clk(clkUser3),   // 1-bit input: optional; required when SRC_INPUT_REG = 1
-   .src_in(measEndRRRR)      // 1-bit input: Input signal to be synchronized to dest_clk domain.
-);
-
-always @(posedge clkUser3 ) begin
-    measEndR <= endMeas;
-end
-
-always @(posedge clkUser3) begin 
-    measEndRR <= measEndR;
-end
-
-always @(posedge clkUser3) begin 
-    measEndRRR <= measEndRR;
-end
-
-
-always @(posedge clkUser3) begin 
-  measEndRRRR <= measEndRRR;
-end
-   
 S5443Top FPGA_M 
 (
 	.Clk_i				(clkUser3), 
@@ -148,7 +111,6 @@ S5443Top FPGA_M
 	.StartMeas_i		(startMeasCmd),
 	.StartMeasEvent_o	(),
 	.EndMeas_o			(endMeas),
-  .MeasEnd_o      (measEnd),
 	.TimersClk_o		(),
 	
 	.Trig6to1_io		(),	

src/src/Top/S5443Top.v

@@ -115,7 +115,6 @@ module	S5443Top
 	input	StartMeas_i,		//"high"- start meas, "low"-stop meas
 	output	StartMeasEvent_o,
 	output	EndMeas_o,
-	output  MeasEnd_o,
 	
 	output	TimersClk_o,
 	
@@ -145,7 +144,7 @@ module	S5443Top
 	output	StartMeasDsp_o,
 	output	[ChNum-1:0]	AmpEn_o,	//	0-adc1ChA 1-adc1ChB 2-adc2ChA 3-adc2ChB
 	
-	output  [ResultWidth*2-1:0] MeasData_o
+	output  [ResultWidth*9-1:0] MeasData_o
 );
 //================================================================================
 //  reg/wire
@@ -403,6 +402,15 @@ module	S5443Top
 	reg		dspReadyForRxRegRR;
 	
 	wire	sampleStrobeGenRst;
+
+	wire	[7:0]	ampEnT1	=	{{7{1'b0}},ampEnNewStates[0]};
+	wire	[7:0]	ampEnR1	=	{{7{1'b0}},ampEnNewStates[1]};
+	wire	[7:0]	ampEnR2	=	{{7{1'b0}},ampEnNewStates[2]};
+	wire	[7:0]	ampEnT2	=	{{7{1'b0}},ampEnNewStates[3]};
+
+	wire	[31:0]	serviceData	=	{ampEnR2,ampEnT2,ampEnR1,ampEnT1};
+	wire	[ResultWidth*(ChNum*2+1)-1:0]	measDataBus;
+
 //================================================================================
 //  assignments
 //================================================================================	
@@ -502,15 +510,10 @@ module	S5443Top
 	assign	pgP3WidthArray[PGenNum-6]	=	{pG2P123Width[23:16],pG2P3Width};
 	assign	pgP3WidthArray[PGenNum-7]	=	{pG1P123Width[23:16],pG1P3Width};
 
-	assign	adcDataBus	[ChNum-4]	=	IsSim? 0:ncoSin;
-	assign	adcDataBus	[ChNum-3]	=	IsSim? 0:ncoSin;
-	assign	adcDataBus	[ChNum-2]	=	IsSim? 0:ncoSin;
-	assign	adcDataBus	[ChNum-1]	=	IsSim? 0:ncoSin;
-	
-	/*assign	adcDataBus	[ChNum-4]	=	adc1ChT1Data;
+	assign	adcDataBus	[ChNum-4]	=	adc1ChT1Data;
 	assign	adcDataBus	[ChNum-3]	=	adc1ChR1Data;
 	assign	adcDataBus	[ChNum-2]	=	adc2ChR2Data;
-	assign	adcDataBus	[ChNum-1]	=	adc2ChT2Data;*/
+	assign	adcDataBus	[ChNum-1]	=	adc2ChT2Data;
 
 	assign	gainManual	[ChNum-4]	=	gainCtrl[5];
 	assign	gainManual	[ChNum-3]	=	gainCtrl[4];
@@ -532,7 +535,8 @@ module	S5443Top
 	
 	assign	StartMeasEvent_o	=	startMeasEvent;
 	
-	assign	EndMeas_o	=	stopMeas|stopMeasR; //stretching pulse for 1 more clk period
+	assign	EndMeas_o	=	measDataRdy; //stretching pulse for 1 more clk period
+	// assign	EndMeas_o	=	stopMeas|stopMeasR; //stretching pulse for 1 more clk period
 	
 	assign	gainLowThresholdBus		[ChNum-4]	=	gainLowThreshT1;
 	assign	gainLowThresholdBus		[ChNum-3]	=	gainLowThreshR1;
@@ -569,13 +573,25 @@ module	S5443Top
 	assign	Trig6to1_io	[3]	=	(measCtrl[19])	?	1'bz:extPortsMuxedOut[3];	//1 - in, 0 - out
 	assign	Trig6to1_io	[4]	=	(measCtrl[20])	?	1'bz:extPortsMuxedOut[4];	//1 - in, 0 - out
 	assign	Trig6to1_io	[5]	=	(measCtrl[21])	?	1'bz:extPortsMuxedOut[5];	//1 - in, 0 - out
+
+	assign	measDataBus	[(ResultWidth-1)-:ResultWidth]		=	adc1ImT1;
+	assign	measDataBus	[(ResultWidth*2)-1-:ResultWidth]	=	adc1ReT1;
+	assign	measDataBus	[(ResultWidth*3)-1-:ResultWidth]	=	adc1ImR1;
+	assign	measDataBus	[(ResultWidth*4)-1-:ResultWidth]	=	adc1ReR1;
+	assign	measDataBus	[(ResultWidth*5)-1-:ResultWidth]	=	adc2ImT2;
+	assign	measDataBus	[(ResultWidth*6)-1-:ResultWidth]	=	adc2ReT2;
+	assign	measDataBus	[(ResultWidth*7)-1-:ResultWidth]	=	adc2ImR2;
+	assign	measDataBus	[(ResultWidth*8)-1-:ResultWidth]	=	adc2ReR2;
+	assign	measDataBus	[(ResultWidth*9)-1-:ResultWidth]	=	serviceData;
 	
 	assign	DspReadyForRxToFpgaS_o	=	dspReadyForRxRegR;
 	assign	StartMeasDsp_o	=	startMeasSyncR;
 
 	assign TimersClk_o = 0;
 
-	assign MeasData_o = {adc1ImT1,adc1ReT1};
+	assign MeasData_o = measDataBus;
+
+
 //================================================================================
 //  CODING
 //================================================================================
@@ -819,7 +835,7 @@ InternalDsp
 	.MeasDataRdy_o			(measDataRdy),
 	.EndMeas_o				(stopMeas),
 	.MeasWind_o				(measWind),
-	.MeasEnd_o				(MeasEnd_o),
+	.MeasEnd_o				(measEnd),
 	.SampleStrobeGenRst_o	(sampleStrobeGenRst)
 );