VNA_PCIE/script/recreateIp.tcl

##################################################################
# CHECK VIVADO VERSION
##################################################################

set scripts_vivado_version 2024.1
set current_vivado_version [version -short]

if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
  catch {common::send_msg_id "IPS_TCL-100" "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_ip_tcl to create an updated script."}
  return 1
}

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# START
##################################################################

# To test this script, run the following commands from Vivado Tcl console:
# source recreateIp.tcl
# If there is no project opened, this script will create a
# project, but make sure you do not have an existing project
# in the current working folder.

set list_projs [get_projects -quiet]
if { $list_projs eq "" } {
  create_project VNA_PCIE_PROJ VNA_PCIE_PROJ -part xc7a100tfgg484-2
  set_property target_language Verilog [current_project]
  set_property simulator_language Verilog [current_project]
}

##################################################################
# CHECK IPs
##################################################################

set bCheckIPs 1
set bCheckIPsPassed 1
if { $bCheckIPs == 1 } {
  set list_check_ips { xilinx.com:ip:clk_wiz:6.0 xilinx.com:ip:pcie_7x:3.3 }
  set list_ips_missing ""
  common::send_msg_id "IPS_TCL-1001" "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ."

  foreach ip_vlnv $list_check_ips {
  set ip_obj [get_ipdefs -all $ip_vlnv]
  if { $ip_obj eq "" } {
    lappend list_ips_missing $ip_vlnv
    }
  }

  if { $list_ips_missing ne "" } {
    catch {common::send_msg_id "IPS_TCL-105" "ERROR" "The following IPs are not found in the IP Catalog:\n  $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." }
    set bCheckIPsPassed 0
  }
}

if { $bCheckIPsPassed != 1 } {
  common::send_msg_id "IPS_TCL-102" "WARNING" "Will not continue with creation of design due to the error(s) above."
  return 1
}

##################################################################
# CREATE IP ClkPllSysTo125
##################################################################

set ClkPllSysTo125 [create_ip -name clk_wiz -vendor xilinx.com -library ip -version 6.0 -module_name ClkPllSysTo125]

# User Parameters
set_property -dict [list \
  CONFIG.CLKOUT1_DRIVES {BUFG} \
  CONFIG.CLKOUT1_JITTER {203.457} \
  CONFIG.CLKOUT1_PHASE_ERROR {155.540} \
  CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {50.000} \
  CONFIG.CLKOUT2_DRIVES {BUFG} \
  CONFIG.CLKOUT3_DRIVES {BUFG} \
  CONFIG.CLKOUT4_DRIVES {BUFG} \
  CONFIG.CLKOUT5_DRIVES {BUFG} \
  CONFIG.CLKOUT6_DRIVES {BUFG} \
  CONFIG.CLKOUT7_DRIVES {BUFG} \
  CONFIG.MMCM_BANDWIDTH {OPTIMIZED} \
  CONFIG.MMCM_CLKFBOUT_MULT_F {17} \
  CONFIG.MMCM_CLKOUT0_DIVIDE_F {17} \
  CONFIG.MMCM_COMPENSATION {ZHOLD} \
  CONFIG.MMCM_DIVCLK_DIVIDE {2} \
  CONFIG.PRIMITIVE {PLL} \
  CONFIG.PRIM_SOURCE {Single_ended_clock_capable_pin} \
  CONFIG.SECONDARY_SOURCE {Single_ended_clock_capable_pin} \
  CONFIG.USE_LOCKED {false} \
  CONFIG.USE_PHASE_ALIGNMENT {false} \
  CONFIG.USE_RESET {false} \
] [get_ips ClkPllSysTo125]

# Runtime Parameters
set_property -dict { 
  GENERATE_SYNTH_CHECKPOINT {1}
} $ClkPllSysTo125

##################################################################

##################################################################
# CREATE IP pcie1234
##################################################################

set pcie1234 [create_ip -name pcie_7x -vendor xilinx.com -library ip -version 3.3 -module_name pcie1234]

# User Parameters
set_property -dict [list \
  CONFIG.Device_ID {7012} \
  CONFIG.Interface_Width {64_bit} \
  CONFIG.Link_Speed {2.5_GT/s} \
  CONFIG.Max_Payload_Size {512_bytes} \
  CONFIG.Maximum_Link_Width {X2} \
  CONFIG.PCIe_Blk_Locn {X0Y0} \
  CONFIG.Trans_Buf_Pipeline {None} \
  CONFIG.User_Clk_Freq {125} \
  CONFIG.en_ext_pipe_interface {false} \
  CONFIG.pipe_mode_sim {Enable_Pipe_Simulation} \
  CONFIG.pipe_sim {true} \
] [get_ips pcie1234]

# Runtime Parameters
set_property -dict { 
  GENERATE_SYNTH_CHECKPOINT {1}
} $pcie1234

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