VNA_PCIE/script/recreate.tcl

#*****************************************************************************************
# Vivado (TM) v2024.1 (64-bit)
#
# recreate.tcl: Tcl script for re-creating project 'VNA_PCIE_PROJ'
#
# Generated by Vivado on Thu Oct 10 17:06:21 +0700 2024
# IP Build 5075265 on Wed May 22 21:45:21 MDT 2024
#
# This file contains the Vivado Tcl commands for re-creating the project to the state*
# when this script was generated. In order to re-create the project, please source this
# file in the Vivado Tcl Shell.
#
# * Note that the runs in the created project will be configured the same way as the
#   original project, however they will not be launched automatically. To regenerate the
#   run results please launch the synthesis/implementation runs as needed.
#
#*****************************************************************************************
# NOTE: In order to use this script for source control purposes, please make sure that the
#       following files are added to the source control system:-
#
# 1. This project restoration tcl script (recreate.tcl) that was generated.
#
# 2. The following source(s) files that were local or imported into the original project.
#    (Please see the '$orig_proj_dir' and '$origin_dir' variable setting below at the start of the script)
#
#    "C:/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PulseMeas/ActivePortSelector.v"
#    "C:/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/InternalDsp/AdcCalibration.v"
#    "C:/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/InternalDsp/ComplPrng.v"
#    "C:/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/InternalDsp/CordicNco.v"
#    "C:/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/InternalDsp/CordicRotation.v"
#    "C:/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/DitherGen/DitherGenv2.v"
#    "C:/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/InternalDsp/DspPipeline.v"
#    "C:/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PCIeImports/EP_MEM.v"
#    "C:/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/Math/FpCustomMultiplier.v"
#    "C:/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/GainOverloadControl/GainControl.v"
#    "C:/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/GainOverloadControl/GainControlWrapper.v"
#    "C:/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/InitRst/InitRst.v"
#    "C:/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/Top/IntermediateLogic.v"
#    "C:/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/InternalDsp/InternalDsp.v"
#    "C:/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/InternalDsp/MeasCtrlModule.v"
#    "C:/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PulseMeas/MeasStartEventGen.v"
#    "C:/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/Math/MultModule.v"
#    "C:/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PulseMeas/Mux.v"
#    "C:/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/Math/MyIntToFp.v"
#    "C:/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/InternalDsp/NcoRstGen.v"
#    "C:/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/GainOverloadControl/OverloadDetect.v"
#    "C:/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PulseMeas/PGenRstGenerator.v"
#    "C:/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PCIeImports/PIO.v"
#    "C:/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PCIeImports/PIO_EP.v"
#    "C:/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PCIeImports/PIO_EP_MEM_ACCESS.v"
#    "C:/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PCIeImports/PIO_RX_ENGINE.v"
#    "C:/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PCIeImports/PIO_TO_CTRL.v"
#    "C:/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PCIeImports/PIO_TX_ENGINE.v"
#    "C:/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PulseMeas/PulseGen.v"
#    "C:/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/RegMap/RegMap.v"
#    "C:/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/Top/S5443Top.v"
#    "C:/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PulseMeas/SampleStrobeGenRstDemux.v"
#    "C:/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/Math/SimpleMult.v"
#    "C:/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PulseMeas/StartAfterGainSel.v"
#    "C:/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/Math/SumAcc.v"
#    "C:/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PulseMeas/TrigInt2Mux.v"
#    "C:/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/InternalDsp/WinParameters.v"
#    "C:/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/InternalDsp/Win_calc.v"
#    "C:/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PCIeImports/pcie1234_pipe_clock.v"
#    "C:/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PCIeImports/pcie1234_support.v"
#    "C:/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PCIeImports/pcie_app_7x.v"
#    "C:/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PCIeImports/xilinx_pcie_2_1_ep_7x.v"
#    "C:/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/Top/PciVnaEmulTop.v"
#    "C:/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/AdcDataRx/AdcSync.v"
#    "C:/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/AdcDataRx/delay_controller_wrap.v"
#    "C:/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/AdcDataRx/n_x_serdes_1_to_7_mmcm_idelay_sdr.v"
#    "C:/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/AdcDataRx/serdes_1_to_7_mmcm_idelay_sdr.v"
#    "C:/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/AdcDataRx/serdes_1_to_7_slave_idelay_sdr.v"
#    "C:/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/AdcDataRx/top5x2_7to1_sdr_rx.v"
#    "C:/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/AdcDataRx/AdcDataInterface.v"
#    "C:/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/ClkGen/Clk200Gen.v"
#    "C:/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/ExtDspInterface/DspInterface.v"
#    "C:/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/ExtDspInterface/DspPpiOut.v"
#    "C:/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/MeasDataFifo/FifoController.v"
#    "C:/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/Top/IntermediateLogicTb.v"
#    "C:/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/MeasDataFifo/MeasDataFifoWrapper.v"
#    "C:/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PulseMeas/PulseGenNew.v"
#    "C:/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/Sim/S5443TopPulseProfileTb.v"
#    "C:/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/Sim/S5443TopSimpleMeasTb.v"
#    "C:/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/ExtDspInterface/SlaveSpi.v"
#    "C:/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PCIeImports/board_common.vh"
#    "C:/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PCIeImports/pipe_interconnect.vh"
#    "C:/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PCIeImports/board.v"
#    "C:/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PCIeImports/pci_exp_usrapp_cfg.v"
#    "C:/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PCIeImports/pci_exp_expect_tasks.vh"
#    "C:/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PCIeImports/pci_exp_usrapp_com.v"
#    "C:/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PCIeImports/pci_exp_usrapp_pl.v"
#    "C:/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PCIeImports/pci_exp_usrapp_rx.v"
#    "C:/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PCIeImports/tests.vh"
#    "C:/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PCIeImports/sample_tests1.vh"
#    "C:/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PCIeImports/pci_exp_usrapp_tx.v"
#    "C:/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PCIeImports/pcie1234_gt_top_pipe_mode.v"
#    "C:/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PCIeImports/pcie_2_1_rport_7x.v"
#    "C:/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PCIeImports/pcie_axi_trn_bridge.v"
#    "C:/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PCIeImports/sys_clk_gen.v"
#    "C:/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PCIeImports/sys_clk_gen_ds.v"
#    "C:/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PCIeImports/xil_sig2pipe.v"
#    "C:/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PCIeImports/xilinx_pcie_2_1_rport_7x.v"
#
# 3. The following remote source files that were added to the original project:-
#
#    "C:/VNA_PCIE_REPO/src/src/PulseMeas/ActivePortSelector.v"
#    "C:/VNA_PCIE_REPO/src/src/InternalDsp/AdcCalibration.v"
#    "C:/VNA_PCIE_REPO/src/src/InternalDsp/ComplPrng.v"
#    "C:/VNA_PCIE_REPO/src/src/InternalDsp/CordicNco.v"
#    "C:/VNA_PCIE_REPO/src/src/InternalDsp/CordicRotation.v"
#    "C:/VNA_PCIE_REPO/src/src/DitherGen/DitherGenv2.v"
#    "C:/VNA_PCIE_REPO/src/src/InternalDsp/DspPipeline.v"
#    "C:/VNA_PCIE_REPO/src/src/PCIeImports/EP_MEM.v"
#    "C:/VNA_PCIE_REPO/src/src/Math/FpCustomMultiplier.v"
#    "C:/VNA_PCIE_REPO/src/src/GainOverloadControl/GainControl.v"
#    "C:/VNA_PCIE_REPO/src/src/GainOverloadControl/GainControlWrapper.v"
#    "C:/VNA_PCIE_REPO/src/src/InitRst/InitRst.v"
#    "C:/VNA_PCIE_REPO/src/src/Top/IntermediateLogic.v"
#    "C:/VNA_PCIE_REPO/src/src/InternalDsp/InternalDsp.v"
#    "C:/VNA_PCIE_REPO/src/src/InternalDsp/MeasCtrlModule.v"
#    "C:/VNA_PCIE_REPO/src/src/PulseMeas/MeasStartEventGen.v"
#    "C:/VNA_PCIE_REPO/src/src/Math/MultModule.v"
#    "C:/VNA_PCIE_REPO/src/src/PulseMeas/Mux.v"
#    "C:/VNA_PCIE_REPO/src/src/Math/MyIntToFp.v"
#    "C:/VNA_PCIE_REPO/src/src/InternalDsp/NcoRstGen.v"
#    "C:/VNA_PCIE_REPO/src/src/GainOverloadControl/OverloadDetect.v"
#    "C:/VNA_PCIE_REPO/src/src/PulseMeas/PGenRstGenerator.v"
#    "C:/VNA_PCIE_REPO/src/src/PCIeImports/PIO.v"
#    "C:/VNA_PCIE_REPO/src/src/PCIeImports/PIO_EP.v"
#    "C:/VNA_PCIE_REPO/src/src/PCIeImports/PIO_EP_MEM_ACCESS.v"
#    "C:/VNA_PCIE_REPO/src/src/PCIeImports/PIO_RX_ENGINE.v"
#    "C:/VNA_PCIE_REPO/src/src/PCIeImports/PIO_TO_CTRL.v"
#    "C:/VNA_PCIE_REPO/src/src/PCIeImports/PIO_TX_ENGINE.v"
#    "C:/VNA_PCIE_REPO/src/src/PulseMeas/PulseGen.v"
#    "C:/VNA_PCIE_REPO/src/src/RegMap/RegMap.v"
#    "C:/VNA_PCIE_REPO/src/src/Top/S5443Top.v"
#    "C:/VNA_PCIE_REPO/src/src/PulseMeas/SampleStrobeGenRstDemux.v"
#    "C:/VNA_PCIE_REPO/src/src/Math/SimpleMult.v"
#    "C:/VNA_PCIE_REPO/src/src/PulseMeas/StartAfterGainSel.v"
#    "C:/VNA_PCIE_REPO/src/src/Math/SumAcc.v"
#    "C:/VNA_PCIE_REPO/src/src/PulseMeas/TrigInt2Mux.v"
#    "C:/VNA_PCIE_REPO/src/src/InternalDsp/WinParameters.v"
#    "C:/VNA_PCIE_REPO/src/src/InternalDsp/Win_calc.v"
#    "C:/VNA_PCIE_REPO/src/src/PCIeImports/pcie1234_pipe_clock.v"
#    "C:/VNA_PCIE_REPO/src/src/PCIeImports/pcie1234_support.v"
#    "C:/VNA_PCIE_REPO/src/src/PCIeImports/pcie_app_7x.v"
#    "C:/VNA_PCIE_REPO/src/src/PCIeImports/xilinx_pcie_2_1_ep_7x.v"
#    "C:/VNA_PCIE_REPO/src/src/Top/PciVnaEmulTop.v"
#    "C:/VNA_PCIE_REPO/src/src/AdcDataRx/AdcSync.v"
#    "C:/VNA_PCIE_REPO/src/src/AdcDataRx/delay_controller_wrap.v"
#    "C:/VNA_PCIE_REPO/src/src/AdcDataRx/n_x_serdes_1_to_7_mmcm_idelay_sdr.v"
#    "C:/VNA_PCIE_REPO/src/src/AdcDataRx/serdes_1_to_7_mmcm_idelay_sdr.v"
#    "C:/VNA_PCIE_REPO/src/src/AdcDataRx/serdes_1_to_7_slave_idelay_sdr.v"
#    "C:/VNA_PCIE_REPO/src/src/AdcDataRx/top5x2_7to1_sdr_rx.v"
#    "C:/VNA_PCIE_REPO/src/src/AdcDataRx/AdcDataInterface.v"
#    "C:/VNA_PCIE_REPO/src/src/ClkGen/Clk200Gen.v"
#    "C:/VNA_PCIE_REPO/src/src/ExtDspInterface/DspInterface.v"
#    "C:/VNA_PCIE_REPO/src/src/ExtDspInterface/DspPpiOut.v"
#    "C:/VNA_PCIE_REPO/src/src/MeasDataFifo/FifoController.v"
#    "C:/VNA_PCIE_REPO/src/src/Top/IntermediateLogicTb.v"
#    "C:/VNA_PCIE_REPO/src/src/MeasDataFifo/MeasDataFifoWrapper.v"
#    "C:/VNA_PCIE_REPO/src/src/PulseMeas/PulseGenNew.v"
#    "C:/VNA_PCIE_REPO/src/src/Sim/S5443TopPulseProfileTb.v"
#    "C:/VNA_PCIE_REPO/src/src/Sim/S5443TopSimpleMeasTb.v"
#    "C:/VNA_PCIE_REPO/src/src/ExtDspInterface/SlaveSpi.v"
#    "C:/VNA_PCIE_REPO/src/src/PCIeImports/board_common.vh"
#    "C:/VNA_PCIE_REPO/src/src/PCIeImports/pipe_interconnect.vh"
#    "C:/VNA_PCIE_REPO/src/src/PCIeImports/board.v"
#    "C:/VNA_PCIE_REPO/src/src/PCIeImports/pci_exp_usrapp_cfg.v"
#    "C:/VNA_PCIE_REPO/src/src/PCIeImports/pci_exp_expect_tasks.vh"
#    "C:/VNA_PCIE_REPO/src/src/PCIeImports/pci_exp_usrapp_com.v"
#    "C:/VNA_PCIE_REPO/src/src/PCIeImports/pci_exp_usrapp_pl.v"
#    "C:/VNA_PCIE_REPO/src/src/PCIeImports/pci_exp_usrapp_rx.v"
#    "C:/VNA_PCIE_REPO/src/src/PCIeImports/tests.vh"
#    "C:/VNA_PCIE_REPO/src/src/PCIeImports/sample_tests1.vh"
#    "C:/VNA_PCIE_REPO/src/src/PCIeImports/pci_exp_usrapp_tx.v"
#    "C:/VNA_PCIE_REPO/src/src/PCIeImports/pcie1234_gt_top_pipe_mode.v"
#    "C:/VNA_PCIE_REPO/src/src/PCIeImports/pcie_2_1_rport_7x.v"
#    "C:/VNA_PCIE_REPO/src/src/PCIeImports/pcie_axi_trn_bridge.v"
#    "C:/VNA_PCIE_REPO/src/src/PCIeImports/sys_clk_gen.v"
#    "C:/VNA_PCIE_REPO/src/src/PCIeImports/sys_clk_gen_ds.v"
#    "C:/VNA_PCIE_REPO/src/src/PCIeImports/xil_sig2pipe.v"
#    "C:/VNA_PCIE_REPO/src/src/PCIeImports/xilinx_pcie_2_1_rport_7x.v"
#    "C:/VNA_PCIE_REPO/src/consrtrs/xilinx_pcie_7x_ep_x1g1.xdc"
#
#*****************************************************************************************

# Check file required for this script exists
proc checkRequiredFiles { origin_dir} {
  set status true
  set files [list \
 "[file normalize "$origin_dir/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PulseMeas/ActivePortSelector.v"]"\
 "[file normalize "$origin_dir/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/InternalDsp/AdcCalibration.v"]"\
 "[file normalize "$origin_dir/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/InternalDsp/ComplPrng.v"]"\
 "[file normalize "$origin_dir/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/InternalDsp/CordicNco.v"]"\
 "[file normalize "$origin_dir/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/InternalDsp/CordicRotation.v"]"\
 "[file normalize "$origin_dir/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/DitherGen/DitherGenv2.v"]"\
 "[file normalize "$origin_dir/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/InternalDsp/DspPipeline.v"]"\
 "[file normalize "$origin_dir/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PCIeImports/EP_MEM.v"]"\
 "[file normalize "$origin_dir/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/Math/FpCustomMultiplier.v"]"\
 "[file normalize "$origin_dir/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/GainOverloadControl/GainControl.v"]"\
 "[file normalize "$origin_dir/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/GainOverloadControl/GainControlWrapper.v"]"\
 "[file normalize "$origin_dir/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/InitRst/InitRst.v"]"\
 "[file normalize "$origin_dir/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/Top/IntermediateLogic.v"]"\
 "[file normalize "$origin_dir/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/InternalDsp/InternalDsp.v"]"\
 "[file normalize "$origin_dir/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/InternalDsp/MeasCtrlModule.v"]"\
 "[file normalize "$origin_dir/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PulseMeas/MeasStartEventGen.v"]"\
 "[file normalize "$origin_dir/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/Math/MultModule.v"]"\
 "[file normalize "$origin_dir/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PulseMeas/Mux.v"]"\
 "[file normalize "$origin_dir/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/Math/MyIntToFp.v"]"\
 "[file normalize "$origin_dir/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/InternalDsp/NcoRstGen.v"]"\
 "[file normalize "$origin_dir/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/GainOverloadControl/OverloadDetect.v"]"\
 "[file normalize "$origin_dir/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PulseMeas/PGenRstGenerator.v"]"\
 "[file normalize "$origin_dir/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PCIeImports/PIO.v"]"\
 "[file normalize "$origin_dir/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PCIeImports/PIO_EP.v"]"\
 "[file normalize "$origin_dir/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PCIeImports/PIO_EP_MEM_ACCESS.v"]"\
 "[file normalize "$origin_dir/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PCIeImports/PIO_RX_ENGINE.v"]"\
 "[file normalize "$origin_dir/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PCIeImports/PIO_TO_CTRL.v"]"\
 "[file normalize "$origin_dir/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PCIeImports/PIO_TX_ENGINE.v"]"\
 "[file normalize "$origin_dir/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PulseMeas/PulseGen.v"]"\
 "[file normalize "$origin_dir/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/RegMap/RegMap.v"]"\
 "[file normalize "$origin_dir/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/Top/S5443Top.v"]"\
 "[file normalize "$origin_dir/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PulseMeas/SampleStrobeGenRstDemux.v"]"\
 "[file normalize "$origin_dir/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/Math/SimpleMult.v"]"\
 "[file normalize "$origin_dir/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PulseMeas/StartAfterGainSel.v"]"\
 "[file normalize "$origin_dir/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/Math/SumAcc.v"]"\
 "[file normalize "$origin_dir/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PulseMeas/TrigInt2Mux.v"]"\
 "[file normalize "$origin_dir/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/InternalDsp/WinParameters.v"]"\
 "[file normalize "$origin_dir/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/InternalDsp/Win_calc.v"]"\
 "[file normalize "$origin_dir/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PCIeImports/pcie1234_pipe_clock.v"]"\
 "[file normalize "$origin_dir/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PCIeImports/pcie1234_support.v"]"\
 "[file normalize "$origin_dir/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PCIeImports/pcie_app_7x.v"]"\
 "[file normalize "$origin_dir/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PCIeImports/xilinx_pcie_2_1_ep_7x.v"]"\
 "[file normalize "$origin_dir/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/Top/PciVnaEmulTop.v"]"\
 "[file normalize "$origin_dir/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/AdcDataRx/AdcSync.v"]"\
 "[file normalize "$origin_dir/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/AdcDataRx/delay_controller_wrap.v"]"\
 "[file normalize "$origin_dir/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/AdcDataRx/n_x_serdes_1_to_7_mmcm_idelay_sdr.v"]"\
 "[file normalize "$origin_dir/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/AdcDataRx/serdes_1_to_7_mmcm_idelay_sdr.v"]"\
 "[file normalize "$origin_dir/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/AdcDataRx/serdes_1_to_7_slave_idelay_sdr.v"]"\
 "[file normalize "$origin_dir/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/AdcDataRx/top5x2_7to1_sdr_rx.v"]"\
 "[file normalize "$origin_dir/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/AdcDataRx/AdcDataInterface.v"]"\
 "[file normalize "$origin_dir/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/ClkGen/Clk200Gen.v"]"\
 "[file normalize "$origin_dir/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/ExtDspInterface/DspInterface.v"]"\
 "[file normalize "$origin_dir/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/ExtDspInterface/DspPpiOut.v"]"\
 "[file normalize "$origin_dir/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/MeasDataFifo/FifoController.v"]"\
 "[file normalize "$origin_dir/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/Top/IntermediateLogicTb.v"]"\
 "[file normalize "$origin_dir/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/MeasDataFifo/MeasDataFifoWrapper.v"]"\
 "[file normalize "$origin_dir/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PulseMeas/PulseGenNew.v"]"\
 "[file normalize "$origin_dir/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/Sim/S5443TopPulseProfileTb.v"]"\
 "[file normalize "$origin_dir/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/Sim/S5443TopSimpleMeasTb.v"]"\
 "[file normalize "$origin_dir/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/ExtDspInterface/SlaveSpi.v"]"\
 "[file normalize "$origin_dir/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PCIeImports/board_common.vh"]"\
 "[file normalize "$origin_dir/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PCIeImports/pipe_interconnect.vh"]"\
 "[file normalize "$origin_dir/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PCIeImports/board.v"]"\
 "[file normalize "$origin_dir/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PCIeImports/pci_exp_usrapp_cfg.v"]"\
 "[file normalize "$origin_dir/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PCIeImports/pci_exp_expect_tasks.vh"]"\
 "[file normalize "$origin_dir/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PCIeImports/pci_exp_usrapp_com.v"]"\
 "[file normalize "$origin_dir/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PCIeImports/pci_exp_usrapp_pl.v"]"\
 "[file normalize "$origin_dir/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PCIeImports/pci_exp_usrapp_rx.v"]"\
 "[file normalize "$origin_dir/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PCIeImports/tests.vh"]"\
 "[file normalize "$origin_dir/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PCIeImports/sample_tests1.vh"]"\
 "[file normalize "$origin_dir/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PCIeImports/pci_exp_usrapp_tx.v"]"\
 "[file normalize "$origin_dir/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PCIeImports/pcie1234_gt_top_pipe_mode.v"]"\
 "[file normalize "$origin_dir/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PCIeImports/pcie_2_1_rport_7x.v"]"\
 "[file normalize "$origin_dir/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PCIeImports/pcie_axi_trn_bridge.v"]"\
 "[file normalize "$origin_dir/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PCIeImports/sys_clk_gen.v"]"\
 "[file normalize "$origin_dir/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PCIeImports/sys_clk_gen_ds.v"]"\
 "[file normalize "$origin_dir/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PCIeImports/xil_sig2pipe.v"]"\
 "[file normalize "$origin_dir/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PCIeImports/xilinx_pcie_2_1_rport_7x.v"]"\
  ]
  foreach ifile $files {
    if { ![file isfile $ifile] } {
      puts " Could not find local file $ifile "
      set status false
    }
  }

  set files [list \
 "[file normalize "$origin_dir/VNA_PCIE_REPO/src/src/PulseMeas/ActivePortSelector.v"]"\
 "[file normalize "$origin_dir/VNA_PCIE_REPO/src/src/InternalDsp/AdcCalibration.v"]"\
 "[file normalize "$origin_dir/VNA_PCIE_REPO/src/src/InternalDsp/ComplPrng.v"]"\
 "[file normalize "$origin_dir/VNA_PCIE_REPO/src/src/InternalDsp/CordicNco.v"]"\
 "[file normalize "$origin_dir/VNA_PCIE_REPO/src/src/InternalDsp/CordicRotation.v"]"\
 "[file normalize "$origin_dir/VNA_PCIE_REPO/src/src/DitherGen/DitherGenv2.v"]"\
 "[file normalize "$origin_dir/VNA_PCIE_REPO/src/src/InternalDsp/DspPipeline.v"]"\
 "[file normalize "$origin_dir/VNA_PCIE_REPO/src/src/PCIeImports/EP_MEM.v"]"\
 "[file normalize "$origin_dir/VNA_PCIE_REPO/src/src/Math/FpCustomMultiplier.v"]"\
 "[file normalize "$origin_dir/VNA_PCIE_REPO/src/src/GainOverloadControl/GainControl.v"]"\
 "[file normalize "$origin_dir/VNA_PCIE_REPO/src/src/GainOverloadControl/GainControlWrapper.v"]"\
 "[file normalize "$origin_dir/VNA_PCIE_REPO/src/src/InitRst/InitRst.v"]"\
 "[file normalize "$origin_dir/VNA_PCIE_REPO/src/src/Top/IntermediateLogic.v"]"\
 "[file normalize "$origin_dir/VNA_PCIE_REPO/src/src/InternalDsp/InternalDsp.v"]"\
 "[file normalize "$origin_dir/VNA_PCIE_REPO/src/src/InternalDsp/MeasCtrlModule.v"]"\
 "[file normalize "$origin_dir/VNA_PCIE_REPO/src/src/PulseMeas/MeasStartEventGen.v"]"\
 "[file normalize "$origin_dir/VNA_PCIE_REPO/src/src/Math/MultModule.v"]"\
 "[file normalize "$origin_dir/VNA_PCIE_REPO/src/src/PulseMeas/Mux.v"]"\
 "[file normalize "$origin_dir/VNA_PCIE_REPO/src/src/Math/MyIntToFp.v"]"\
 "[file normalize "$origin_dir/VNA_PCIE_REPO/src/src/InternalDsp/NcoRstGen.v"]"\
 "[file normalize "$origin_dir/VNA_PCIE_REPO/src/src/GainOverloadControl/OverloadDetect.v"]"\
 "[file normalize "$origin_dir/VNA_PCIE_REPO/src/src/PulseMeas/PGenRstGenerator.v"]"\
 "[file normalize "$origin_dir/VNA_PCIE_REPO/src/src/PCIeImports/PIO.v"]"\
 "[file normalize "$origin_dir/VNA_PCIE_REPO/src/src/PCIeImports/PIO_EP.v"]"\
 "[file normalize "$origin_dir/VNA_PCIE_REPO/src/src/PCIeImports/PIO_EP_MEM_ACCESS.v"]"\
 "[file normalize "$origin_dir/VNA_PCIE_REPO/src/src/PCIeImports/PIO_RX_ENGINE.v"]"\
 "[file normalize "$origin_dir/VNA_PCIE_REPO/src/src/PCIeImports/PIO_TO_CTRL.v"]"\
 "[file normalize "$origin_dir/VNA_PCIE_REPO/src/src/PCIeImports/PIO_TX_ENGINE.v"]"\
 "[file normalize "$origin_dir/VNA_PCIE_REPO/src/src/PulseMeas/PulseGen.v"]"\
 "[file normalize "$origin_dir/VNA_PCIE_REPO/src/src/RegMap/RegMap.v"]"\
 "[file normalize "$origin_dir/VNA_PCIE_REPO/src/src/Top/S5443Top.v"]"\
 "[file normalize "$origin_dir/VNA_PCIE_REPO/src/src/PulseMeas/SampleStrobeGenRstDemux.v"]"\
 "[file normalize "$origin_dir/VNA_PCIE_REPO/src/src/Math/SimpleMult.v"]"\
 "[file normalize "$origin_dir/VNA_PCIE_REPO/src/src/PulseMeas/StartAfterGainSel.v"]"\
 "[file normalize "$origin_dir/VNA_PCIE_REPO/src/src/Math/SumAcc.v"]"\
 "[file normalize "$origin_dir/VNA_PCIE_REPO/src/src/PulseMeas/TrigInt2Mux.v"]"\
 "[file normalize "$origin_dir/VNA_PCIE_REPO/src/src/InternalDsp/WinParameters.v"]"\
 "[file normalize "$origin_dir/VNA_PCIE_REPO/src/src/InternalDsp/Win_calc.v"]"\
 "[file normalize "$origin_dir/VNA_PCIE_REPO/src/src/PCIeImports/pcie1234_pipe_clock.v"]"\
 "[file normalize "$origin_dir/VNA_PCIE_REPO/src/src/PCIeImports/pcie1234_support.v"]"\
 "[file normalize "$origin_dir/VNA_PCIE_REPO/src/src/PCIeImports/pcie_app_7x.v"]"\
 "[file normalize "$origin_dir/VNA_PCIE_REPO/src/src/PCIeImports/xilinx_pcie_2_1_ep_7x.v"]"\
 "[file normalize "$origin_dir/VNA_PCIE_REPO/src/src/Top/PciVnaEmulTop.v"]"\
 "[file normalize "$origin_dir/VNA_PCIE_REPO/src/src/AdcDataRx/AdcSync.v"]"\
 "[file normalize "$origin_dir/VNA_PCIE_REPO/src/src/AdcDataRx/delay_controller_wrap.v"]"\
 "[file normalize "$origin_dir/VNA_PCIE_REPO/src/src/AdcDataRx/n_x_serdes_1_to_7_mmcm_idelay_sdr.v"]"\
 "[file normalize "$origin_dir/VNA_PCIE_REPO/src/src/AdcDataRx/serdes_1_to_7_mmcm_idelay_sdr.v"]"\
 "[file normalize "$origin_dir/VNA_PCIE_REPO/src/src/AdcDataRx/serdes_1_to_7_slave_idelay_sdr.v"]"\
 "[file normalize "$origin_dir/VNA_PCIE_REPO/src/src/AdcDataRx/top5x2_7to1_sdr_rx.v"]"\
 "[file normalize "$origin_dir/VNA_PCIE_REPO/src/src/AdcDataRx/AdcDataInterface.v"]"\
 "[file normalize "$origin_dir/VNA_PCIE_REPO/src/src/ClkGen/Clk200Gen.v"]"\
 "[file normalize "$origin_dir/VNA_PCIE_REPO/src/src/ExtDspInterface/DspInterface.v"]"\
 "[file normalize "$origin_dir/VNA_PCIE_REPO/src/src/ExtDspInterface/DspPpiOut.v"]"\
 "[file normalize "$origin_dir/VNA_PCIE_REPO/src/src/MeasDataFifo/FifoController.v"]"\
 "[file normalize "$origin_dir/VNA_PCIE_REPO/src/src/Top/IntermediateLogicTb.v"]"\
 "[file normalize "$origin_dir/VNA_PCIE_REPO/src/src/MeasDataFifo/MeasDataFifoWrapper.v"]"\
 "[file normalize "$origin_dir/VNA_PCIE_REPO/src/src/PulseMeas/PulseGenNew.v"]"\
 "[file normalize "$origin_dir/VNA_PCIE_REPO/src/src/Sim/S5443TopPulseProfileTb.v"]"\
 "[file normalize "$origin_dir/VNA_PCIE_REPO/src/src/Sim/S5443TopSimpleMeasTb.v"]"\
 "[file normalize "$origin_dir/VNA_PCIE_REPO/src/src/ExtDspInterface/SlaveSpi.v"]"\
 "[file normalize "$origin_dir/VNA_PCIE_REPO/src/src/PCIeImports/board_common.vh"]"\
 "[file normalize "$origin_dir/VNA_PCIE_REPO/src/src/PCIeImports/pipe_interconnect.vh"]"\
 "[file normalize "$origin_dir/VNA_PCIE_REPO/src/src/PCIeImports/board.v"]"\
 "[file normalize "$origin_dir/VNA_PCIE_REPO/src/src/PCIeImports/pci_exp_usrapp_cfg.v"]"\
 "[file normalize "$origin_dir/VNA_PCIE_REPO/src/src/PCIeImports/pci_exp_expect_tasks.vh"]"\
 "[file normalize "$origin_dir/VNA_PCIE_REPO/src/src/PCIeImports/pci_exp_usrapp_com.v"]"\
 "[file normalize "$origin_dir/VNA_PCIE_REPO/src/src/PCIeImports/pci_exp_usrapp_pl.v"]"\
 "[file normalize "$origin_dir/VNA_PCIE_REPO/src/src/PCIeImports/pci_exp_usrapp_rx.v"]"\
 "[file normalize "$origin_dir/VNA_PCIE_REPO/src/src/PCIeImports/tests.vh"]"\
 "[file normalize "$origin_dir/VNA_PCIE_REPO/src/src/PCIeImports/sample_tests1.vh"]"\
 "[file normalize "$origin_dir/VNA_PCIE_REPO/src/src/PCIeImports/pci_exp_usrapp_tx.v"]"\
 "[file normalize "$origin_dir/VNA_PCIE_REPO/src/src/PCIeImports/pcie1234_gt_top_pipe_mode.v"]"\
 "[file normalize "$origin_dir/VNA_PCIE_REPO/src/src/PCIeImports/pcie_2_1_rport_7x.v"]"\
 "[file normalize "$origin_dir/VNA_PCIE_REPO/src/src/PCIeImports/pcie_axi_trn_bridge.v"]"\
 "[file normalize "$origin_dir/VNA_PCIE_REPO/src/src/PCIeImports/sys_clk_gen.v"]"\
 "[file normalize "$origin_dir/VNA_PCIE_REPO/src/src/PCIeImports/sys_clk_gen_ds.v"]"\
 "[file normalize "$origin_dir/VNA_PCIE_REPO/src/src/PCIeImports/xil_sig2pipe.v"]"\
 "[file normalize "$origin_dir/VNA_PCIE_REPO/src/src/PCIeImports/xilinx_pcie_2_1_rport_7x.v"]"\
 "[file normalize "$origin_dir/VNA_PCIE_REPO/src/consrtrs/xilinx_pcie_7x_ep_x1g1.xdc"]"\
  ]
  foreach ifile $files {
    if { ![file isfile $ifile] } {
      puts " Could not find remote file $ifile "
      set status false
    }
  }

  return $status
}
# Set the reference directory for source file relative paths (by default the value is script directory path)
set origin_dir "C:/"

# Use origin directory path location variable, if specified in the tcl shell
if { [info exists ::origin_dir_loc] } {
  set origin_dir $::origin_dir_loc
}

# Set the project name
set _xil_proj_name_ "VNA_PCIE_PROJ"

# Use project name variable, if specified in the tcl shell
if { [info exists ::user_project_name] } {
  set _xil_proj_name_ $::user_project_name
}

variable script_file
set script_file "recreate.tcl"

# Help information for this script
proc print_help {} {
  variable script_file
  puts "\nDescription:"
  puts "Recreate a Vivado project from this script. The created project will be"
  puts "functionally equivalent to the original project for which this script was"
  puts "generated. The script contains commands for creating a project, filesets,"
  puts "runs, adding/importing sources and setting properties on various objects.\n"
  puts "Syntax:"
  puts "$script_file"
  puts "$script_file -tclargs \[--origin_dir <path>\]"
  puts "$script_file -tclargs \[--project_name <name>\]"
  puts "$script_file -tclargs \[--help\]\n"
  puts "Usage:"
  puts "Name                   Description"
  puts "-------------------------------------------------------------------------"
  puts "\[--origin_dir <path>\]  Determine source file paths wrt this path. Default"
  puts "                       origin_dir path value is \".\", otherwise, the value"
  puts "                       that was set with the \"-paths_relative_to\" switch"
  puts "                       when this script was generated.\n"
  puts "\[--project_name <name>\] Create project with the specified name. Default"
  puts "                       name is the name of the project from where this"
  puts "                       script was generated.\n"
  puts "\[--help\]               Print help information for this script"
  puts "-------------------------------------------------------------------------\n"
  exit 0
}

if { $::argc > 0 } {
  for {set i 0} {$i < $::argc} {incr i} {
    set option [string trim [lindex $::argv $i]]
    switch -regexp -- $option {
      "--origin_dir"   { incr i; set origin_dir [lindex $::argv $i] }
      "--project_name" { incr i; set _xil_proj_name_ [lindex $::argv $i] }
      "--help"         { print_help }
      default {
        if { [regexp {^-} $option] } {
          puts "ERROR: Unknown option '$option' specified, please type '$script_file -tclargs --help' for usage info.\n"
          return 1
        }
      }
    }
  }
}

# Set the directory path for the original project from where this script was exported
set orig_proj_dir "[file normalize "$origin_dir/VNA_PCIE_PROJ"]"

# Check for paths and files needed for project creation
set validate_required 0
if { $validate_required } {
  if { [checkRequiredFiles $origin_dir] } {
    puts "Tcl file $script_file is valid. All files required for project creation is accesable. "
  } else {
    puts "Tcl file $script_file is not valid. Not all files required for project creation is accesable. "
    return
  }
}

# Create project
create_project ${_xil_proj_name_} ./${_xil_proj_name_} -part xc7a100tfgg484-2

# Set the directory path for the new project
set proj_dir [get_property directory [current_project]]

# Reconstruct message rules
# None

# Set project properties
set obj [current_project]
set_property -name "default_lib" -value "xil_defaultlib" -objects $obj
set_property -name "enable_resource_estimation" -value "0" -objects $obj
set_property -name "enable_vhdl_2008" -value "1" -objects $obj
set_property -name "ip_cache_permissions" -value "read write" -objects $obj
set_property -name "ip_output_repo" -value "$proj_dir/${_xil_proj_name_}.cache/ip" -objects $obj
set_property -name "mem.enable_memory_map_generation" -value "1" -objects $obj
set_property -name "part" -value "xc7a100tfgg484-2" -objects $obj
set_property -name "revised_directory_structure" -value "1" -objects $obj
set_property -name "sim.central_dir" -value "$proj_dir/${_xil_proj_name_}.ip_user_files" -objects $obj
set_property -name "sim.ip.auto_export_scripts" -value "1" -objects $obj
set_property -name "simulator_language" -value "Mixed" -objects $obj
set_property -name "sim_compile_state" -value "1" -objects $obj
set_property -name "webtalk.activehdl_export_sim" -value "1" -objects $obj
set_property -name "webtalk.modelsim_export_sim" -value "1" -objects $obj
set_property -name "webtalk.questa_export_sim" -value "1" -objects $obj
set_property -name "webtalk.riviera_export_sim" -value "1" -objects $obj
set_property -name "webtalk.vcs_export_sim" -value "1" -objects $obj
set_property -name "webtalk.xcelium_export_sim" -value "1" -objects $obj
set_property -name "webtalk.xsim_export_sim" -value "1" -objects $obj
set_property -name "xpm_libraries" -value "XPM_CDC XPM_MEMORY" -objects $obj

# Create 'sources_1' fileset (if not found)
if {[string equal [get_filesets -quiet sources_1] ""]} {
  create_fileset -srcset sources_1
}

# Set 'sources_1' fileset object
set obj [get_filesets sources_1]
set files [list \
 [file normalize "${origin_dir}/VNA_PCIE_REPO/src/src/PulseMeas/ActivePortSelector.v"] \
 [file normalize "${origin_dir}/VNA_PCIE_REPO/src/src/InternalDsp/AdcCalibration.v"] \
 [file normalize "${origin_dir}/VNA_PCIE_REPO/src/src/InternalDsp/ComplPrng.v"] \
 [file normalize "${origin_dir}/VNA_PCIE_REPO/src/src/InternalDsp/CordicNco.v"] \
 [file normalize "${origin_dir}/VNA_PCIE_REPO/src/src/InternalDsp/CordicRotation.v"] \
 [file normalize "${origin_dir}/VNA_PCIE_REPO/src/src/DitherGen/DitherGenv2.v"] \
 [file normalize "${origin_dir}/VNA_PCIE_REPO/src/src/InternalDsp/DspPipeline.v"] \
 [file normalize "${origin_dir}/VNA_PCIE_REPO/src/src/PCIeImports/EP_MEM.v"] \
 [file normalize "${origin_dir}/VNA_PCIE_REPO/src/src/Math/FpCustomMultiplier.v"] \
 [file normalize "${origin_dir}/VNA_PCIE_REPO/src/src/GainOverloadControl/GainControl.v"] \
 [file normalize "${origin_dir}/VNA_PCIE_REPO/src/src/GainOverloadControl/GainControlWrapper.v"] \
 [file normalize "${origin_dir}/VNA_PCIE_REPO/src/src/InitRst/InitRst.v"] \
 [file normalize "${origin_dir}/VNA_PCIE_REPO/src/src/Top/IntermediateLogic.v"] \
 [file normalize "${origin_dir}/VNA_PCIE_REPO/src/src/InternalDsp/InternalDsp.v"] \
 [file normalize "${origin_dir}/VNA_PCIE_REPO/src/src/InternalDsp/MeasCtrlModule.v"] \
 [file normalize "${origin_dir}/VNA_PCIE_REPO/src/src/PulseMeas/MeasStartEventGen.v"] \
 [file normalize "${origin_dir}/VNA_PCIE_REPO/src/src/Math/MultModule.v"] \
 [file normalize "${origin_dir}/VNA_PCIE_REPO/src/src/PulseMeas/Mux.v"] \
 [file normalize "${origin_dir}/VNA_PCIE_REPO/src/src/Math/MyIntToFp.v"] \
 [file normalize "${origin_dir}/VNA_PCIE_REPO/src/src/InternalDsp/NcoRstGen.v"] \
 [file normalize "${origin_dir}/VNA_PCIE_REPO/src/src/GainOverloadControl/OverloadDetect.v"] \
 [file normalize "${origin_dir}/VNA_PCIE_REPO/src/src/PulseMeas/PGenRstGenerator.v"] \
 [file normalize "${origin_dir}/VNA_PCIE_REPO/src/src/PCIeImports/PIO.v"] \
 [file normalize "${origin_dir}/VNA_PCIE_REPO/src/src/PCIeImports/PIO_EP.v"] \
 [file normalize "${origin_dir}/VNA_PCIE_REPO/src/src/PCIeImports/PIO_EP_MEM_ACCESS.v"] \
 [file normalize "${origin_dir}/VNA_PCIE_REPO/src/src/PCIeImports/PIO_RX_ENGINE.v"] \
 [file normalize "${origin_dir}/VNA_PCIE_REPO/src/src/PCIeImports/PIO_TO_CTRL.v"] \
 [file normalize "${origin_dir}/VNA_PCIE_REPO/src/src/PCIeImports/PIO_TX_ENGINE.v"] \
 [file normalize "${origin_dir}/VNA_PCIE_REPO/src/src/PulseMeas/PulseGen.v"] \
 [file normalize "${origin_dir}/VNA_PCIE_REPO/src/src/RegMap/RegMap.v"] \
 [file normalize "${origin_dir}/VNA_PCIE_REPO/src/src/Top/S5443Top.v"] \
 [file normalize "${origin_dir}/VNA_PCIE_REPO/src/src/PulseMeas/SampleStrobeGenRstDemux.v"] \
 [file normalize "${origin_dir}/VNA_PCIE_REPO/src/src/Math/SimpleMult.v"] \
 [file normalize "${origin_dir}/VNA_PCIE_REPO/src/src/PulseMeas/StartAfterGainSel.v"] \
 [file normalize "${origin_dir}/VNA_PCIE_REPO/src/src/Math/SumAcc.v"] \
 [file normalize "${origin_dir}/VNA_PCIE_REPO/src/src/PulseMeas/TrigInt2Mux.v"] \
 [file normalize "${origin_dir}/VNA_PCIE_REPO/src/src/InternalDsp/WinParameters.v"] \
 [file normalize "${origin_dir}/VNA_PCIE_REPO/src/src/InternalDsp/Win_calc.v"] \
 [file normalize "${origin_dir}/VNA_PCIE_REPO/src/src/PCIeImports/pcie1234_pipe_clock.v"] \
 [file normalize "${origin_dir}/VNA_PCIE_REPO/src/src/PCIeImports/pcie1234_support.v"] \
 [file normalize "${origin_dir}/VNA_PCIE_REPO/src/src/PCIeImports/pcie_app_7x.v"] \
 [file normalize "${origin_dir}/VNA_PCIE_REPO/src/src/PCIeImports/xilinx_pcie_2_1_ep_7x.v"] \
 [file normalize "${origin_dir}/VNA_PCIE_REPO/src/src/Top/PciVnaEmulTop.v"] \
 [file normalize "${origin_dir}/VNA_PCIE_REPO/src/src/AdcDataRx/AdcSync.v"] \
 [file normalize "${origin_dir}/VNA_PCIE_REPO/src/src/AdcDataRx/delay_controller_wrap.v"] \
 [file normalize "${origin_dir}/VNA_PCIE_REPO/src/src/AdcDataRx/n_x_serdes_1_to_7_mmcm_idelay_sdr.v"] \
 [file normalize "${origin_dir}/VNA_PCIE_REPO/src/src/AdcDataRx/serdes_1_to_7_mmcm_idelay_sdr.v"] \
 [file normalize "${origin_dir}/VNA_PCIE_REPO/src/src/AdcDataRx/serdes_1_to_7_slave_idelay_sdr.v"] \
 [file normalize "${origin_dir}/VNA_PCIE_REPO/src/src/AdcDataRx/top5x2_7to1_sdr_rx.v"] \
 [file normalize "${origin_dir}/VNA_PCIE_REPO/src/src/AdcDataRx/AdcDataInterface.v"] \
 [file normalize "${origin_dir}/VNA_PCIE_REPO/src/src/ClkGen/Clk200Gen.v"] \
 [file normalize "${origin_dir}/VNA_PCIE_REPO/src/src/ExtDspInterface/DspInterface.v"] \
 [file normalize "${origin_dir}/VNA_PCIE_REPO/src/src/ExtDspInterface/DspPpiOut.v"] \
 [file normalize "${origin_dir}/VNA_PCIE_REPO/src/src/MeasDataFifo/FifoController.v"] \
 [file normalize "${origin_dir}/VNA_PCIE_REPO/src/src/Top/IntermediateLogicTb.v"] \
 [file normalize "${origin_dir}/VNA_PCIE_REPO/src/src/MeasDataFifo/MeasDataFifoWrapper.v"] \
 [file normalize "${origin_dir}/VNA_PCIE_REPO/src/src/PulseMeas/PulseGenNew.v"] \
 [file normalize "${origin_dir}/VNA_PCIE_REPO/src/src/Sim/S5443TopPulseProfileTb.v"] \
 [file normalize "${origin_dir}/VNA_PCIE_REPO/src/src/Sim/S5443TopSimpleMeasTb.v"] \
 [file normalize "${origin_dir}/VNA_PCIE_REPO/src/src/ExtDspInterface/SlaveSpi.v"] \
 [file normalize "${origin_dir}/VNA_PCIE_REPO/src/src/PCIeImports/board_common.vh"] \
 [file normalize "${origin_dir}/VNA_PCIE_REPO/src/src/PCIeImports/pipe_interconnect.vh"] \
 [file normalize "${origin_dir}/VNA_PCIE_REPO/src/src/PCIeImports/board.v"] \
 [file normalize "${origin_dir}/VNA_PCIE_REPO/src/src/PCIeImports/pci_exp_usrapp_cfg.v"] \
 [file normalize "${origin_dir}/VNA_PCIE_REPO/src/src/PCIeImports/pci_exp_expect_tasks.vh"] \
 [file normalize "${origin_dir}/VNA_PCIE_REPO/src/src/PCIeImports/pci_exp_usrapp_com.v"] \
 [file normalize "${origin_dir}/VNA_PCIE_REPO/src/src/PCIeImports/pci_exp_usrapp_pl.v"] \
 [file normalize "${origin_dir}/VNA_PCIE_REPO/src/src/PCIeImports/pci_exp_usrapp_rx.v"] \
 [file normalize "${origin_dir}/VNA_PCIE_REPO/src/src/PCIeImports/tests.vh"] \
 [file normalize "${origin_dir}/VNA_PCIE_REPO/src/src/PCIeImports/sample_tests1.vh"] \
 [file normalize "${origin_dir}/VNA_PCIE_REPO/src/src/PCIeImports/pci_exp_usrapp_tx.v"] \
 [file normalize "${origin_dir}/VNA_PCIE_REPO/src/src/PCIeImports/pcie1234_gt_top_pipe_mode.v"] \
 [file normalize "${origin_dir}/VNA_PCIE_REPO/src/src/PCIeImports/pcie_2_1_rport_7x.v"] \
 [file normalize "${origin_dir}/VNA_PCIE_REPO/src/src/PCIeImports/pcie_axi_trn_bridge.v"] \
 [file normalize "${origin_dir}/VNA_PCIE_REPO/src/src/PCIeImports/sys_clk_gen.v"] \
 [file normalize "${origin_dir}/VNA_PCIE_REPO/src/src/PCIeImports/sys_clk_gen_ds.v"] \
 [file normalize "${origin_dir}/VNA_PCIE_REPO/src/src/PCIeImports/xil_sig2pipe.v"] \
 [file normalize "${origin_dir}/VNA_PCIE_REPO/src/src/PCIeImports/xilinx_pcie_2_1_rport_7x.v"] \
]
add_files -norecurse -fileset $obj $files

# Set 'sources_1' fileset file properties for remote files
set file "$origin_dir/VNA_PCIE_REPO/src/src/PCIeImports/board_common.vh"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "Verilog Header" -objects $file_obj

set file "$origin_dir/VNA_PCIE_REPO/src/src/PCIeImports/pipe_interconnect.vh"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "Verilog Header" -objects $file_obj

set file "$origin_dir/VNA_PCIE_REPO/src/src/PCIeImports/pci_exp_expect_tasks.vh"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "Verilog Header" -objects $file_obj

set file "$origin_dir/VNA_PCIE_REPO/src/src/PCIeImports/tests.vh"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "Verilog Header" -objects $file_obj

set file "$origin_dir/VNA_PCIE_REPO/src/src/PCIeImports/sample_tests1.vh"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "Verilog Header" -objects $file_obj

# Create 'constrs_1' fileset (if not found)
if {[string equal [get_filesets -quiet constrs_1] ""]} {
  create_fileset -constrset constrs_1
}

# Set 'constrs_1' fileset object
set obj [get_filesets constrs_1]

# Add/Import constrs file and set constrs file properties
set file "[file normalize "$origin_dir/VNA_PCIE_REPO/src/consrtrs/xilinx_pcie_7x_ep_x1g1.xdc"]"
set file_added [add_files -norecurse -fileset $obj [list $file]]
set file "$origin_dir/VNA_PCIE_REPO/src/consrtrs/xilinx_pcie_7x_ep_x1g1.xdc"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets constrs_1] [list "*$file"]]
set_property -name "file_type" -value "XDC" -objects $file_obj

# Set 'constrs_1' fileset properties
set obj [get_filesets constrs_1]
set_property -name "target_constrs_file" -value "[file normalize "$origin_dir/VNA_PCIE_REPO/src/consrtrs/xilinx_pcie_7x_ep_x1g1.xdc"]" -objects $obj
set_property -name "target_part" -value "xc7a100tfgg484-2" -objects $obj
set_property -name "target_ucf" -value "[file normalize "$origin_dir/VNA_PCIE_REPO/src/consrtrs/xilinx_pcie_7x_ep_x1g1.xdc"]" -objects $obj

# Create 'sim_1' fileset (if not found)
if {[string equal [get_filesets -quiet sim_1] ""]} {
  create_fileset -simset sim_1
}

# Set 'sim_1' fileset object
set obj [get_filesets sim_1]
# Empty (no sources present)

# Set 'sim_1' fileset properties
set obj [get_filesets sim_1]
set_property -name "top" -value "AdcDataInterface" -objects $obj
set_property -name "top_auto_set" -value "0" -objects $obj
set_property -name "top_lib" -value "xil_defaultlib" -objects $obj

# Set 'utils_1' fileset object
set obj [get_filesets utils_1]
# Import local files from the original project
set files [list \
 [file normalize "${origin_dir}/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PulseMeas/ActivePortSelector.v"]\
 [file normalize "${origin_dir}/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/InternalDsp/AdcCalibration.v"]\
 [file normalize "${origin_dir}/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/InternalDsp/ComplPrng.v"]\
 [file normalize "${origin_dir}/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/InternalDsp/CordicNco.v"]\
 [file normalize "${origin_dir}/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/InternalDsp/CordicRotation.v"]\
 [file normalize "${origin_dir}/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/DitherGen/DitherGenv2.v"]\
 [file normalize "${origin_dir}/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/InternalDsp/DspPipeline.v"]\
 [file normalize "${origin_dir}/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PCIeImports/EP_MEM.v"]\
 [file normalize "${origin_dir}/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/Math/FpCustomMultiplier.v"]\
 [file normalize "${origin_dir}/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/GainOverloadControl/GainControl.v"]\
 [file normalize "${origin_dir}/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/GainOverloadControl/GainControlWrapper.v"]\
 [file normalize "${origin_dir}/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/InitRst/InitRst.v"]\
 [file normalize "${origin_dir}/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/Top/IntermediateLogic.v"]\
 [file normalize "${origin_dir}/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/InternalDsp/InternalDsp.v"]\
 [file normalize "${origin_dir}/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/InternalDsp/MeasCtrlModule.v"]\
 [file normalize "${origin_dir}/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PulseMeas/MeasStartEventGen.v"]\
 [file normalize "${origin_dir}/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/Math/MultModule.v"]\
 [file normalize "${origin_dir}/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PulseMeas/Mux.v"]\
 [file normalize "${origin_dir}/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/Math/MyIntToFp.v"]\
 [file normalize "${origin_dir}/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/InternalDsp/NcoRstGen.v"]\
 [file normalize "${origin_dir}/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/GainOverloadControl/OverloadDetect.v"]\
 [file normalize "${origin_dir}/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PulseMeas/PGenRstGenerator.v"]\
 [file normalize "${origin_dir}/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PCIeImports/PIO.v"]\
 [file normalize "${origin_dir}/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PCIeImports/PIO_EP.v"]\
 [file normalize "${origin_dir}/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PCIeImports/PIO_EP_MEM_ACCESS.v"]\
 [file normalize "${origin_dir}/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PCIeImports/PIO_RX_ENGINE.v"]\
 [file normalize "${origin_dir}/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PCIeImports/PIO_TO_CTRL.v"]\
 [file normalize "${origin_dir}/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PCIeImports/PIO_TX_ENGINE.v"]\
 [file normalize "${origin_dir}/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PulseMeas/PulseGen.v"]\
 [file normalize "${origin_dir}/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/RegMap/RegMap.v"]\
 [file normalize "${origin_dir}/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/Top/S5443Top.v"]\
 [file normalize "${origin_dir}/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PulseMeas/SampleStrobeGenRstDemux.v"]\
 [file normalize "${origin_dir}/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/Math/SimpleMult.v"]\
 [file normalize "${origin_dir}/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PulseMeas/StartAfterGainSel.v"]\
 [file normalize "${origin_dir}/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/Math/SumAcc.v"]\
 [file normalize "${origin_dir}/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PulseMeas/TrigInt2Mux.v"]\
 [file normalize "${origin_dir}/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/InternalDsp/WinParameters.v"]\
 [file normalize "${origin_dir}/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/InternalDsp/Win_calc.v"]\
 [file normalize "${origin_dir}/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PCIeImports/pcie1234_pipe_clock.v"]\
 [file normalize "${origin_dir}/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PCIeImports/pcie1234_support.v"]\
 [file normalize "${origin_dir}/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PCIeImports/pcie_app_7x.v"]\
 [file normalize "${origin_dir}/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PCIeImports/xilinx_pcie_2_1_ep_7x.v"]\
 [file normalize "${origin_dir}/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/Top/PciVnaEmulTop.v"]\
 [file normalize "${origin_dir}/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/AdcDataRx/AdcSync.v"]\
 [file normalize "${origin_dir}/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/AdcDataRx/delay_controller_wrap.v"]\
 [file normalize "${origin_dir}/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/AdcDataRx/n_x_serdes_1_to_7_mmcm_idelay_sdr.v"]\
 [file normalize "${origin_dir}/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/AdcDataRx/serdes_1_to_7_mmcm_idelay_sdr.v"]\
 [file normalize "${origin_dir}/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/AdcDataRx/serdes_1_to_7_slave_idelay_sdr.v"]\
 [file normalize "${origin_dir}/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/AdcDataRx/top5x2_7to1_sdr_rx.v"]\
 [file normalize "${origin_dir}/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/AdcDataRx/AdcDataInterface.v"]\
 [file normalize "${origin_dir}/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/ClkGen/Clk200Gen.v"]\
 [file normalize "${origin_dir}/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/ExtDspInterface/DspInterface.v"]\
 [file normalize "${origin_dir}/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/ExtDspInterface/DspPpiOut.v"]\
 [file normalize "${origin_dir}/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/MeasDataFifo/FifoController.v"]\
 [file normalize "${origin_dir}/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/Top/IntermediateLogicTb.v"]\
 [file normalize "${origin_dir}/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/MeasDataFifo/MeasDataFifoWrapper.v"]\
 [file normalize "${origin_dir}/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PulseMeas/PulseGenNew.v"]\
 [file normalize "${origin_dir}/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/Sim/S5443TopPulseProfileTb.v"]\
 [file normalize "${origin_dir}/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/Sim/S5443TopSimpleMeasTb.v"]\
 [file normalize "${origin_dir}/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/ExtDspInterface/SlaveSpi.v"]\
 [file normalize "${origin_dir}/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PCIeImports/board_common.vh"]\
 [file normalize "${origin_dir}/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PCIeImports/pipe_interconnect.vh"]\
 [file normalize "${origin_dir}/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PCIeImports/board.v"]\
 [file normalize "${origin_dir}/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PCIeImports/pci_exp_usrapp_cfg.v"]\
 [file normalize "${origin_dir}/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PCIeImports/pci_exp_expect_tasks.vh"]\
 [file normalize "${origin_dir}/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PCIeImports/pci_exp_usrapp_com.v"]\
 [file normalize "${origin_dir}/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PCIeImports/pci_exp_usrapp_pl.v"]\
 [file normalize "${origin_dir}/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PCIeImports/pci_exp_usrapp_rx.v"]\
 [file normalize "${origin_dir}/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PCIeImports/tests.vh"]\
 [file normalize "${origin_dir}/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PCIeImports/sample_tests1.vh"]\
 [file normalize "${origin_dir}/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PCIeImports/pci_exp_usrapp_tx.v"]\
 [file normalize "${origin_dir}/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PCIeImports/pcie1234_gt_top_pipe_mode.v"]\
 [file normalize "${origin_dir}/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PCIeImports/pcie_2_1_rport_7x.v"]\
 [file normalize "${origin_dir}/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PCIeImports/pcie_axi_trn_bridge.v"]\
 [file normalize "${origin_dir}/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PCIeImports/sys_clk_gen.v"]\
 [file normalize "${origin_dir}/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PCIeImports/sys_clk_gen_ds.v"]\
 [file normalize "${origin_dir}/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PCIeImports/xil_sig2pipe.v"]\
 [file normalize "${origin_dir}/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/PCIeImports/xilinx_pcie_2_1_rport_7x.v"]\
]
set imported_files ""
foreach f $files {
  lappend imported_files [import_files -fileset utils_1 $f]
}

# Set 'utils_1' fileset file properties for remote files
# None

# Set 'utils_1' fileset file properties for local files
set file "PCIeImports/board_common.vh"
set file_obj [get_files -of_objects [get_filesets utils_1] [list "*$file"]]
set_property -name "file_type" -value "Verilog Header" -objects $file_obj

set file "PCIeImports/pipe_interconnect.vh"
set file_obj [get_files -of_objects [get_filesets utils_1] [list "*$file"]]
set_property -name "file_type" -value "Verilog Header" -objects $file_obj

set file "PCIeImports/pci_exp_expect_tasks.vh"
set file_obj [get_files -of_objects [get_filesets utils_1] [list "*$file"]]
set_property -name "file_type" -value "Verilog Header" -objects $file_obj

set file "PCIeImports/tests.vh"
set file_obj [get_files -of_objects [get_filesets utils_1] [list "*$file"]]
set_property -name "file_type" -value "Verilog Header" -objects $file_obj

set file "PCIeImports/sample_tests1.vh"
set file_obj [get_files -of_objects [get_filesets utils_1] [list "*$file"]]
set_property -name "file_type" -value "Verilog Header" -objects $file_obj


# Set 'utils_1' fileset properties
set obj [get_filesets utils_1]

set idrFlowPropertiesConstraints ""
catch {
 set idrFlowPropertiesConstraints [get_param runs.disableIDRFlowPropertyConstraints]
 set_param runs.disableIDRFlowPropertyConstraints 1
}

# Create 'synth_1' run (if not found)
if {[string equal [get_runs -quiet synth_1] ""]} {
    create_run -name synth_1 -part xc7a100tfgg484-2 -flow {Vivado Synthesis 2024} -strategy "Vivado Synthesis Defaults" -report_strategy {No Reports} -constrset constrs_1
} else {
  set_property strategy "Vivado Synthesis Defaults" [get_runs synth_1]
  set_property flow "Vivado Synthesis 2024" [get_runs synth_1]
}
set obj [get_runs synth_1]
set_property set_report_strategy_name 1 $obj
set_property report_strategy {Vivado Synthesis Default Reports} $obj
set_property set_report_strategy_name 0 $obj
# Create 'synth_1_synth_report_utilization_0' report (if not found)
if { [ string equal [get_report_configs -of_objects [get_runs synth_1] synth_1_synth_report_utilization_0] "" ] } {
  create_report_config -report_name synth_1_synth_report_utilization_0 -report_type report_utilization:1.0 -steps synth_design -runs synth_1
}
set obj [get_report_configs -of_objects [get_runs synth_1] synth_1_synth_report_utilization_0]
if { $obj != "" } {

}
set obj [get_runs synth_1]
set_property -name "part" -value "xc7a100tfgg484-2" -objects $obj
set_property -name "auto_incremental_checkpoint" -value "1" -objects $obj
set_property -name "strategy" -value "Vivado Synthesis Defaults" -objects $obj
set_property -name "steps.synth_design.args.flatten_hierarchy" -value "none" -objects $obj
set_property -name "steps.synth_design.args.gated_clock_conversion" -value "auto" -objects $obj

# set the current synth run
current_run -synthesis [get_runs synth_1]

# Create 'impl_1' run (if not found)
if {[string equal [get_runs -quiet impl_1] ""]} {
    create_run -name impl_1 -part xc7a100tfgg484-2 -flow {Vivado Implementation 2024} -strategy "Vivado Implementation Defaults" -report_strategy {No Reports} -constrset constrs_1 -parent_run synth_1
} else {
  set_property strategy "Vivado Implementation Defaults" [get_runs impl_1]
  set_property flow "Vivado Implementation 2024" [get_runs impl_1]
}
set obj [get_runs impl_1]
set_property set_report_strategy_name 1 $obj
set_property report_strategy {Vivado Implementation Default Reports} $obj
set_property set_report_strategy_name 0 $obj
# Create 'impl_1_init_report_timing_summary_0' report (if not found)
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_init_report_timing_summary_0] "" ] } {
  create_report_config -report_name impl_1_init_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps init_design -runs impl_1
}
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_init_report_timing_summary_0]
if { $obj != "" } {
set_property -name "is_enabled" -value "0" -objects $obj
set_property -name "options.max_paths" -value "10" -objects $obj
set_property -name "options.report_unconstrained" -value "1" -objects $obj

}
# Create 'impl_1_opt_report_drc_0' report (if not found)
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_drc_0] "" ] } {
  create_report_config -report_name impl_1_opt_report_drc_0 -report_type report_drc:1.0 -steps opt_design -runs impl_1
}
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_drc_0]
if { $obj != "" } {

}
# Create 'impl_1_opt_report_timing_summary_0' report (if not found)
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_timing_summary_0] "" ] } {
  create_report_config -report_name impl_1_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps opt_design -runs impl_1
}
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_timing_summary_0]
if { $obj != "" } {
set_property -name "is_enabled" -value "0" -objects $obj
set_property -name "options.max_paths" -value "10" -objects $obj
set_property -name "options.report_unconstrained" -value "1" -objects $obj

}
# Create 'impl_1_power_opt_report_timing_summary_0' report (if not found)
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_power_opt_report_timing_summary_0] "" ] } {
  create_report_config -report_name impl_1_power_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps power_opt_design -runs impl_1
}
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_power_opt_report_timing_summary_0]
if { $obj != "" } {
set_property -name "is_enabled" -value "0" -objects $obj
set_property -name "options.max_paths" -value "10" -objects $obj
set_property -name "options.report_unconstrained" -value "1" -objects $obj

}
# Create 'impl_1_place_report_io_0' report (if not found)
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_io_0] "" ] } {
  create_report_config -report_name impl_1_place_report_io_0 -report_type report_io:1.0 -steps place_design -runs impl_1
}
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_io_0]
if { $obj != "" } {

}
# Create 'impl_1_place_report_utilization_0' report (if not found)
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_utilization_0] "" ] } {
  create_report_config -report_name impl_1_place_report_utilization_0 -report_type report_utilization:1.0 -steps place_design -runs impl_1
}
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_utilization_0]
if { $obj != "" } {

}
# Create 'impl_1_place_report_control_sets_0' report (if not found)
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_control_sets_0] "" ] } {
  create_report_config -report_name impl_1_place_report_control_sets_0 -report_type report_control_sets:1.0 -steps place_design -runs impl_1
}
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_control_sets_0]
if { $obj != "" } {
set_property -name "options.verbose" -value "1" -objects $obj

}
# Create 'impl_1_place_report_incremental_reuse_0' report (if not found)
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_0] "" ] } {
  create_report_config -report_name impl_1_place_report_incremental_reuse_0 -report_type report_incremental_reuse:1.0 -steps place_design -runs impl_1
}
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_0]
if { $obj != "" } {
set_property -name "is_enabled" -value "0" -objects $obj

}
# Create 'impl_1_place_report_incremental_reuse_1' report (if not found)
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_1] "" ] } {
  create_report_config -report_name impl_1_place_report_incremental_reuse_1 -report_type report_incremental_reuse:1.0 -steps place_design -runs impl_1
}
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_1]
if { $obj != "" } {
set_property -name "is_enabled" -value "0" -objects $obj

}
# Create 'impl_1_place_report_timing_summary_0' report (if not found)
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_timing_summary_0] "" ] } {
  create_report_config -report_name impl_1_place_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps place_design -runs impl_1
}
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_timing_summary_0]
if { $obj != "" } {
set_property -name "is_enabled" -value "0" -objects $obj
set_property -name "options.max_paths" -value "10" -objects $obj
set_property -name "options.report_unconstrained" -value "1" -objects $obj

}
# Create 'impl_1_post_place_power_opt_report_timing_summary_0' report (if not found)
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_post_place_power_opt_report_timing_summary_0] "" ] } {
  create_report_config -report_name impl_1_post_place_power_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps post_place_power_opt_design -runs impl_1
}
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_post_place_power_opt_report_timing_summary_0]
if { $obj != "" } {
set_property -name "is_enabled" -value "0" -objects $obj
set_property -name "options.max_paths" -value "10" -objects $obj
set_property -name "options.report_unconstrained" -value "1" -objects $obj

}
# Create 'impl_1_phys_opt_report_timing_summary_0' report (if not found)
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_phys_opt_report_timing_summary_0] "" ] } {
  create_report_config -report_name impl_1_phys_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps phys_opt_design -runs impl_1
}
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_phys_opt_report_timing_summary_0]
if { $obj != "" } {
set_property -name "is_enabled" -value "0" -objects $obj
set_property -name "options.max_paths" -value "10" -objects $obj
set_property -name "options.report_unconstrained" -value "1" -objects $obj

}
# Create 'impl_1_route_report_drc_0' report (if not found)
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_drc_0] "" ] } {
  create_report_config -report_name impl_1_route_report_drc_0 -report_type report_drc:1.0 -steps route_design -runs impl_1
}
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_drc_0]
if { $obj != "" } {

}
# Create 'impl_1_route_report_methodology_0' report (if not found)
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_methodology_0] "" ] } {
  create_report_config -report_name impl_1_route_report_methodology_0 -report_type report_methodology:1.0 -steps route_design -runs impl_1
}
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_methodology_0]
if { $obj != "" } {

}
# Create 'impl_1_route_report_power_0' report (if not found)
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_power_0] "" ] } {
  create_report_config -report_name impl_1_route_report_power_0 -report_type report_power:1.0 -steps route_design -runs impl_1
}
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_power_0]
if { $obj != "" } {

}
# Create 'impl_1_route_report_route_status_0' report (if not found)
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_route_status_0] "" ] } {
  create_report_config -report_name impl_1_route_report_route_status_0 -report_type report_route_status:1.0 -steps route_design -runs impl_1
}
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_route_status_0]
if { $obj != "" } {

}
# Create 'impl_1_route_report_timing_summary_0' report (if not found)
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_timing_summary_0] "" ] } {
  create_report_config -report_name impl_1_route_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps route_design -runs impl_1
}
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_timing_summary_0]
if { $obj != "" } {
set_property -name "options.max_paths" -value "10" -objects $obj
set_property -name "options.report_unconstrained" -value "1" -objects $obj

}
# Create 'impl_1_route_report_incremental_reuse_0' report (if not found)
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_incremental_reuse_0] "" ] } {
  create_report_config -report_name impl_1_route_report_incremental_reuse_0 -report_type report_incremental_reuse:1.0 -steps route_design -runs impl_1
}
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_incremental_reuse_0]
if { $obj != "" } {

}
# Create 'impl_1_route_report_clock_utilization_0' report (if not found)
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_clock_utilization_0] "" ] } {
  create_report_config -report_name impl_1_route_report_clock_utilization_0 -report_type report_clock_utilization:1.0 -steps route_design -runs impl_1
}
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_clock_utilization_0]
if { $obj != "" } {

}
# Create 'impl_1_route_report_bus_skew_0' report (if not found)
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_bus_skew_0] "" ] } {
  create_report_config -report_name impl_1_route_report_bus_skew_0 -report_type report_bus_skew:1.1 -steps route_design -runs impl_1
}
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_bus_skew_0]
if { $obj != "" } {
set_property -name "options.warn_on_violation" -value "1" -objects $obj

}
# Create 'impl_1_post_route_phys_opt_report_timing_summary_0' report (if not found)
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_timing_summary_0] "" ] } {
  create_report_config -report_name impl_1_post_route_phys_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps post_route_phys_opt_design -runs impl_1
}
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_timing_summary_0]
if { $obj != "" } {
set_property -name "options.max_paths" -value "10" -objects $obj
set_property -name "options.report_unconstrained" -value "1" -objects $obj
set_property -name "options.warn_on_violation" -value "1" -objects $obj

}
# Create 'impl_1_post_route_phys_opt_report_bus_skew_0' report (if not found)
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_bus_skew_0] "" ] } {
  create_report_config -report_name impl_1_post_route_phys_opt_report_bus_skew_0 -report_type report_bus_skew:1.1 -steps post_route_phys_opt_design -runs impl_1
}
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_bus_skew_0]
if { $obj != "" } {
set_property -name "options.warn_on_violation" -value "1" -objects $obj

}
set obj [get_runs impl_1]
set_property -name "part" -value "xc7a100tfgg484-2" -objects $obj
set_property -name "strategy" -value "Vivado Implementation Defaults" -objects $obj
set_property -name "steps.write_bitstream.args.readback_file" -value "0" -objects $obj
set_property -name "steps.write_bitstream.args.verbose" -value "0" -objects $obj

# set the current impl run
current_run -implementation [get_runs impl_1]
catch {
 if { $idrFlowPropertiesConstraints != {} } {
   set_param runs.disableIDRFlowPropertyConstraints $idrFlowPropertiesConstraints
 }
}

puts "INFO: Project created:${_xil_proj_name_}"
# Create 'drc_1' gadget (if not found)
if {[string equal [get_dashboard_gadgets  [ list "drc_1" ] ] ""]} {
create_dashboard_gadget -name {drc_1} -type drc
}
set obj [get_dashboard_gadgets [ list "drc_1" ] ]
set_property -name "reports" -value "impl_1#impl_1_route_report_drc_0" -objects $obj

# Create 'methodology_1' gadget (if not found)
if {[string equal [get_dashboard_gadgets  [ list "methodology_1" ] ] ""]} {
create_dashboard_gadget -name {methodology_1} -type methodology
}
set obj [get_dashboard_gadgets [ list "methodology_1" ] ]
set_property -name "reports" -value "impl_1#impl_1_route_report_methodology_0" -objects $obj

# Create 'power_1' gadget (if not found)
if {[string equal [get_dashboard_gadgets  [ list "power_1" ] ] ""]} {
create_dashboard_gadget -name {power_1} -type power
}
set obj [get_dashboard_gadgets [ list "power_1" ] ]
set_property -name "reports" -value "impl_1#impl_1_route_report_power_0" -objects $obj

# Create 'timing_1' gadget (if not found)
if {[string equal [get_dashboard_gadgets  [ list "timing_1" ] ] ""]} {
create_dashboard_gadget -name {timing_1} -type timing
}
set obj [get_dashboard_gadgets [ list "timing_1" ] ]
set_property -name "reports" -value "impl_1#impl_1_route_report_timing_summary_0" -objects $obj

# Create 'utilization_1' gadget (if not found)
if {[string equal [get_dashboard_gadgets  [ list "utilization_1" ] ] ""]} {
create_dashboard_gadget -name {utilization_1} -type utilization
}
set obj [get_dashboard_gadgets [ list "utilization_1" ] ]
set_property -name "reports" -value "synth_1#synth_1_synth_report_utilization_0" -objects $obj
set_property -name "run.step" -value "synth_design" -objects $obj
set_property -name "run.type" -value "synthesis" -objects $obj

# Create 'utilization_2' gadget (if not found)
if {[string equal [get_dashboard_gadgets  [ list "utilization_2" ] ] ""]} {
create_dashboard_gadget -name {utilization_2} -type utilization
}
set obj [get_dashboard_gadgets [ list "utilization_2" ] ]
set_property -name "reports" -value "impl_1#impl_1_place_report_utilization_0" -objects $obj

move_dashboard_gadget -name {utilization_1} -row 0 -col 0
move_dashboard_gadget -name {power_1} -row 1 -col 0
move_dashboard_gadget -name {drc_1} -row 2 -col 0
move_dashboard_gadget -name {timing_1} -row 0 -col 1
move_dashboard_gadget -name {utilization_2} -row 1 -col 1
move_dashboard_gadget -name {methodology_1} -row 2 -col 1


##################################################################
# CHECK VIVADO VERSION
##################################################################

set scripts_vivado_version 2024.1
set current_vivado_version [version -short]

if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
  catch {common::send_msg_id "IPS_TCL-100" "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_ip_tcl to create an updated script."}
  return 1
}

##################################################################
# START
##################################################################

# To test this script, run the following commands from Vivado Tcl console:
# source recreateIp.tcl
# If there is no project opened, this script will create a
# project, but make sure you do not have an existing project
# in the current working folder.

set list_projs [get_projects -quiet]
if { $list_projs eq "" } {
  create_project VNA_PCIE_PROJ VNA_PCIE_PROJ -part xc7a100tfgg484-2
  set_property target_language Verilog [current_project]
  set_property simulator_language Mixed [current_project]
}

##################################################################
# CHECK IPs
##################################################################

set bCheckIPs 1
set bCheckIPsPassed 1
if { $bCheckIPs == 1 } {
  set list_check_ips { xilinx.com:ip:clk_wiz:6.0 xilinx.com:ip:fifo_generator:13.2 xilinx.com:ip:pcie_7x:3.3 }
  set list_ips_missing ""
  common::send_msg_id "IPS_TCL-1001" "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ."

  foreach ip_vlnv $list_check_ips {
  set ip_obj [get_ipdefs -all $ip_vlnv]
  if { $ip_obj eq "" } {
    lappend list_ips_missing $ip_vlnv
    }
  }

  if { $list_ips_missing ne "" } {
    catch {common::send_msg_id "IPS_TCL-105" "ERROR" "The following IPs are not found in the IP Catalog:\n  $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." }
    set bCheckIPsPassed 0
  }
}

if { $bCheckIPsPassed != 1 } {
  common::send_msg_id "IPS_TCL-102" "WARNING" "Will not continue with creation of design due to the error(s) above."
  return 1
}

##################################################################
# CREATE IP ClkPllSysTo125
##################################################################

set ClkPllSysTo125 [create_ip -name clk_wiz -vendor xilinx.com -library ip -version 6.0 -module_name ClkPllSysTo125]

# User Parameters
set_property -dict [list \
  CONFIG.CLKOUT1_DRIVES {BUFG} \
  CONFIG.CLKOUT1_JITTER {203.457} \
  CONFIG.CLKOUT1_PHASE_ERROR {155.540} \
  CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {50.000} \
  CONFIG.CLKOUT2_DRIVES {BUFG} \
  CONFIG.CLKOUT3_DRIVES {BUFG} \
  CONFIG.CLKOUT4_DRIVES {BUFG} \
  CONFIG.CLKOUT5_DRIVES {BUFG} \
  CONFIG.CLKOUT6_DRIVES {BUFG} \
  CONFIG.CLKOUT7_DRIVES {BUFG} \
  CONFIG.MMCM_BANDWIDTH {OPTIMIZED} \
  CONFIG.MMCM_CLKFBOUT_MULT_F {17} \
  CONFIG.MMCM_CLKOUT0_DIVIDE_F {17} \
  CONFIG.MMCM_COMPENSATION {ZHOLD} \
  CONFIG.MMCM_DIVCLK_DIVIDE {2} \
  CONFIG.PRIMITIVE {PLL} \
  CONFIG.PRIM_SOURCE {Single_ended_clock_capable_pin} \
  CONFIG.SECONDARY_SOURCE {Single_ended_clock_capable_pin} \
  CONFIG.USE_LOCKED {false} \
  CONFIG.USE_PHASE_ALIGNMENT {false} \
  CONFIG.USE_RESET {false} \
] [get_ips ClkPllSysTo125]

# Runtime Parameters
set_property -dict { 
  GENERATE_SYNTH_CHECKPOINT {1}
} $ClkPllSysTo125

##################################################################

##################################################################
# CREATE IP MeasDataFifo
##################################################################

set MeasDataFifo [create_ip -name fifo_generator -vendor xilinx.com -library ip -version 13.2 -module_name MeasDataFifo]

# User Parameters
set_property CONFIG.Input_Data_Width {288} [get_ips MeasDataFifo]

# Runtime Parameters
set_property -dict { 
  GENERATE_SYNTH_CHECKPOINT {1}
} $MeasDataFifo

##################################################################

##################################################################
# CREATE IP pcie1234
##################################################################

set pcie1234 [create_ip -name pcie_7x -vendor xilinx.com -library ip -version 3.3 -module_name pcie1234]

# User Parameters
set_property -dict [list \
  CONFIG.Device_ID {7012} \
  CONFIG.Interface_Width {64_bit} \
  CONFIG.Link_Speed {2.5_GT/s} \
  CONFIG.Max_Payload_Size {512_bytes} \
  CONFIG.Maximum_Link_Width {X2} \
  CONFIG.PCIe_Blk_Locn {X0Y0} \
  CONFIG.Trans_Buf_Pipeline {None} \
  CONFIG.User_Clk_Freq {125} \
  CONFIG.en_ext_pipe_interface {false} \
  CONFIG.pipe_mode_sim {Enable_Pipe_Simulation} \
  CONFIG.pipe_sim {true} \
] [get_ips pcie1234]

# Runtime Parameters
set_property -dict { 
  GENERATE_SYNTH_CHECKPOINT {1}
} $pcie1234

##################################################################