VNA_PCIE/src/src/AdcDataRx/top5x2_7to1_sdr_rx.v

//////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2012-2015 Xilinx, Inc.
// This design is confidential and proprietary of Xilinx, All Rights Reserved.
//////////////////////////////////////////////////////////////////////////////
//   ____  ____
//  /   /\/   /
// /___/  \  /   Vendor: Xilinx
// \   \   \/    Version: 1.2
//  \   \        Filename: top5x2_7to1_sdr_rx.v
//  /   /        Date Last Modified:  21JAN2015
// /___/   /\    Date Created: 2SEP2011
// \   \  /  \
//  \___\/\___\
// 
//Device: 	7-Series
//Purpose:  	SDR top level receiver example - 2 channels of 5-bits each
//
//Reference:	XAPP585.pdf
//    
//Revision History:
//    Rev 1.0 - First created (nicks)
//    Rev 1.1 - BUFG added to IDELAY reference clock
//    Rev 1.2 - Updated format (brandond)
//
//////////////////////////////////////////////////////////////////////////////
//
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//////////////////////////////////////////////////////////////////////////////

`timescale 1ps/1ps

module top5x2_7to1_sdr_rx 
#(
	parameter	integer	D	=	4,		// Set the number of outputs per channel to be 5 in this example
	parameter	integer	N	=	1,       // Set the number of channels to be 2 in this example
	parameter	DataWidth	=	14
)
(
	input	reset,					// reset (active high)
	input	refclkin,				// Reference clock for input delay control
	input	Locked_i,				// Reference clock for input delay control
	input	clkin1_p,	
	input	clkin1_n,			// lvds channel 1 clock input
	input	[D-1:0]	datain1_p,
	input	[D-1:0]	datain1_n,			// lvds channel 1 data inputs
	input	clkin2_p,	
	input	clkin2_n,			// lvds channel 2 clock input
	input	[D-1:0]	datain2_p,	
	input	[D-1:0]	datain2_n,			// lvds channel 2 data inputs
	output	reg	dummy,
	output	[27:0]	dout,
	output	DivClk_o
	// output	[DataWidth-1:0]	dout
);// Dummy output for test
			
		
wire	refclkint; 		
wire	rx_mmcm_lckdps;		
wire	[1:0]	rx_mmcm_lckdpsbs;	
wire	rxclk_div;		
wire	clkin_p;			
wire	clkin_n;			
wire	[D*N-1:0]	datain_p;		
wire	[D*N-1:0]	datain_n;		
// wire	[N*DataWidth-1:0]	rxdall;			
wire	[27:0]	rxdall;			
wire	delay_ready;		
wire	rx_mmcm_lckd;	

IDELAYCTRL	icontrol 
(              			// Instantiate input delay control block
	.REFCLK	(refclkin),
	.RST	(~Locked_i),
	.RDY	(delay_ready)
);

// Input clock and data for 2 channels
assign	clkin_p		=	clkin1_p;
assign	clkin_n		=	clkin1_n;
assign	datain_p	=	datain1_p;
assign	datain_n	=	datain1_n;

assign	dout		=	rxdall;
assign	DivClk_o	=	rxclk_div;

n_x_serdes_1_to_7_mmcm_idelay_sdr 
#(
	.N	(N),
	.SAMPL_CLOCK	("BUF_G"),
	.PIXEL_CLOCK	("BUF_G"),
	.USE_PLL		("TRUE"),
	.HIGH_PERFORMANCE_MODE	("FALSE"),
	.D	(D),				// Number of data lines
	.CLKIN_PERIOD	(40.000),			// Set input clock period
	.MMCM_MODE		(4),				// Parameter to set multiplier for MMCM to get VCO in correct operating range. 1 multiplies input clock by 7, 2 multiplies clock by 14, etc
	.DIFF_TERM		("TRUE"),
	// .DATA_FORMAT	("PER_CLOCK")
	.DATA_FORMAT	("PER_CHANL")
) 			// PER_CLOCK or PER_CHANL data formatting
ReceiverModule	
(                          
	.clkin_p	(clkin_p),
	.clkin_n	(clkin_n),
	.datain_p	(datain_p),
	.datain_n	(datain_n),
	.enable_phase_detector	(1'b0),
	.rxclk		(),
	.idelay_rdy	(delay_ready),
	.rxclk_div	(rxclk_div),
	.reset		(reset),
	.rx_mmcm_lckd		(rx_mmcm_lckd),
	.rx_mmcm_lckdps		(rx_mmcm_lckdps),
	.rx_mmcm_lckdpsbs	(rx_mmcm_lckdpsbs),
	.clk_data	(),
	.rx_data	(rxdall),
	.bit_rate_value		(16'h0350),			// required bit rate value
	.bit_time_value		(),
	.status		(),
	.debug		()
);
      	
endmodule