VNA_PCIE/src/src/Math/SumAcc.v

module SumAcc 
#(	
	parameter	IDataWidth	=	14,
	parameter	ODataWidth	=	48
)
(
    input	Clk_i,
    input	Rst_i,
    input	Val_i,
    input	AccZeroing_i,
	input	[IDataWidth-1:0]	Data_i,
	
	output	[ODataWidth-1:0]	Result_o,
	output	ResultVal_o
);

//================================================================================
//  LOCALPARAMS

//================================================================================
//  REG/WIRE
	reg		[ODataWidth-1:0]	dataAcc;
	reg		resultVal;
	wire	[ODataWidth-1:0]	extData	=	{{(ODataWidth - IDataWidth){Data_i[IDataWidth-1]}}, Data_i};	//sign extension
	
	reg		accZeroing;
	reg		accZeroingR;
	reg		accZeroingRR;
//================================================================================
//  ASSIGNMENTS
	assign	Result_o	=	dataAcc;
	assign	ResultVal_o	=	resultVal;
//================================================================================
//  CODING

	always	@(posedge	Clk_i)	begin
		if	(Rst_i)	begin
			accZeroing		<=	0;
			accZeroingR		<=	0;
			accZeroingRR		<=	0;
		end	else	begin
			accZeroing		<=	AccZeroing_i;
			accZeroingR		<=	accZeroing;
			accZeroingRR	<=	accZeroingR;
		end
	end
	
	always	@(posedge	Clk_i)	begin
		if	(Rst_i)	begin
			dataAcc		<=	{ODataWidth{1'b0}};
		end	else	if	(Val_i)	begin
			if	(!accZeroingRR)	begin
				dataAcc		<=	dataAcc+extData;
			end	else	begin
				dataAcc		<=	0+extData;
			end
		resultVal	<=	accZeroingR;
		end	else	begin
			dataAcc		<=	0;
			resultVal	<=	0;
		end
	end

endmodule