Init

CMakeLists.txt

@@ -0,0 +1,11 @@
+cmake_minimum_required(VERSION 3.25.1)
+project(UserProgramme)
+
+set(CMAKE_CXX_STANDARD 14)
+
+add_executable(UserProgramme
+        main.cpp
+        RegMap.h
+        RegMap.h
+        vna.h
+        vna.h)

RegMap.h

@@ -0,0 +1,383 @@
+
+#ifndef USERPROGRAMME_REGMAP_H
+#define USERPROGRAMME_REGMAP_H
+
+#define SENS_CTRL_ADDR                          0x00
+#define SENS_LOW_THRES_T1_ADDR                  0x01
+#define SENS_HIGH_THRES_T1_ADDR                 0x02
+#define SENS_LOW_THRES_R1_ADDR                  0x03
+#define SENS_HIGH_THRES_R1_ADDR                 0x04
+#define SENS_LOW_THRES_T2_ADDR                  0x05
+#define SENS_HIGH_THRES_T2_ADDR                 0x06
+#define SENS_LOW_THRES_R2_ADDR                  0x07
+#define SENS_HIGH_THRES_R2_ADDR                 0x08
+#define OVERLOAD_STS_ADDR                       0x09
+#define OVERLOAD_THRESHOLD_ADDR                 0xa
+#define PGMODE0_ADDR                            0xb
+#define NCO_FTW2_H                              0xc
+#define NCO_FTW2_L                              0xd
+#define DITHER_CTRL_ADDR                        0xe
+#define MEAS_CTRL_ADDR                          0x11
+#define ADC_CTRL_ADDR                           0x12
+#define ADC0_SPI_ADDR                           0x13
+#define ADC1_SPI_ADDR                           0x14
+#define NCO_FTW1_H_ADDR                         0x15
+#define NCO_FTW1_L_ADDR                         0x16
+#define CORR_COEF_H_ADDR                        0x17
+#define CORR_COEF_L_ADDR                        0x18
+
+/*PG7 Settings*/
+#define PGMODE1_ADDR                            0x1b
+#define MUX_CTRL1_ADDR                          0x1c
+#define MUX_CTRL2_ADDR                          0x1d
+#define MUX_CTRL3_ADDR                          0x1e
+#define MUX_CTRL4_ADDR                          0x1f
+#define PG7P1DEL_ADDR                           0x20
+#define PG7P2DEL_ADDR                           0x21
+#define PG7P3DEL_ADDR                           0x22
+#define PG7P123DEL_ADDR                         0x23
+#define PG7P1W_ADDR                             0x24
+#define PG7P2W_ADDR                             0x25
+#define PG7P3W_ADDR                             0x26
+#define PG7P123W_ADDR                           0x27
+
+/*PG1 Settings*/
+#define PG1P1DEL_ADDR                           0x28
+#define PG1P2DEL_ADDR                           0x29
+#define PG1P3DEL_ADDR                           0x2a
+#define PG1P123DEL_ADDR                         0x2b
+#define PG1P1W_ADDR                             0x2c
+#define PG1P2W_ADDR                             0x2d
+#define PG1P3W_ADDR                             0x2e
+#define PG1P123W_ADDR                           0x2f
+
+/*PG2 Settings*/
+#define PG2P1DEL_ADDR                           0x30
+#define PG2P2DEL_ADDR                           0x31
+#define PG2P3DEL_ADDR                           0x32
+#define PG2P123DEL_ADDR                         0x33
+#define PG2P1W_ADDR                             0x34
+#define PG2P2W_ADDR                             0x35
+#define PG2P3W_ADDR                             0x36
+#define PG2P123W_ADDR                           0x37
+
+/*PG3 Settings*/
+#define PG3P1DEL_ADDR                           0x38
+#define PG3P2DEL_ADDR                           0x39
+#define PG3P3DEL_ADDR                           0x3a
+#define PG3P123DEL_ADDR                         0x3b
+#define PG3P1W_ADDR                             0x3c
+#define PG3P2W_ADDR                             0x3d
+#define PG3P3W_ADDR                             0x3e
+#define PG3P123W_ADDR                           0x3f
+
+/*PG4 Settings*/
+#define PG4P1DEL_ADDR                           0x40
+#define PG4P2DEL_ADDR                           0x41
+#define PG4P3DEL_ADDR                           0x42
+#define PG4P123DEL_ADDR                         0x43
+#define PG4P1W_ADDR                             0x44
+#define PG4P2W_ADDR                             0x45
+#define PG4P3W_ADDR                             0x46
+#define PG4P123W_ADDR                           0x47
+
+/*PG5 Settings*/
+#define PG5P1DEL_ADDR                           0x48
+#define PG5P2DEL_ADDR                           0x49
+#define PG5P3DEL_ADDR                           0x4a
+#define PG5P123DEL_ADDR                         0x4b
+#define PG5P1W_ADDR                             0x4c
+#define PG5P2W_ADDR                             0x4d
+#define PG5P3W_ADDR                             0x4e
+#define PG5P123W_ADDR                           0x4f
+
+/*PG6 Settings*/
+#define PG6P1DEL_ADDR                           0x50
+#define PG6P2DEL_ADDR                           0x51
+#define PG6P3DEL_ADDR                           0x52
+#define PG6P123DEL_ADDR                         0x53
+#define PG6P1W_ADDR                             0x54
+#define PG6P2W_ADDR                             0x55
+#define PG6P3W_ADDR                             0x56
+#define PG6P123W_ADDR                           0x57
+
+/*Meas Ctrl */
+#define MEASNUM_23_0_ADDR                       0x58
+#define MEASNUM_31_24_ADDR                      0x59
+#define CFGREG_ADDR                             0x80
+#define MEASDATA_FIFO_ADDR                      0x96
+
+/**********************************************************************************
+ * 										PGMODE0_REG
+ *********************************************************************************/
+
+/*Gen1 Modes*/
+#define BITP_PG1MODE                             0
+#define ENUM_PG1MODE_OFF                         (0 << BITP_PG1MODE)
+#define ENUM_PG1MODE_1P                          (1 << BITP_PG1MODE)
+#define ENUM_PG1MODE_2P                          (2 << BITP_PG1MODE)
+#define ENUM_PG1MODE_3P                          (3 << BITP_PG1MODE)
+#define ENUM_PG1MODE_NP                          (4 << BITP_PG1MODE)
+#define ENUM_PG1MODE_CONT                        (5 << BITP_PG1MODE)
+/*Gen2 Modes*/
+#define BITP_PG2MODE                             3
+#define ENUM_PG2MODE_OFF                         (0 << BITP_PG2MODE)
+#define ENUM_PG2MODE_1P                          (1 << BITP_PG2MODE)
+#define ENUM_PG2MODE_2P                          (2 << BITP_PG2MODE)
+#define ENUM_PG2MODE_3P                          (3 << BITP_PG2MODE)
+#define ENUM_PG2MODE_NP                          (4 << BITP_PG2MODE)
+#define ENUM_PG2MODE_CONT                        (5 << BITP_PG2MODE)
+/*Gen3 Modes*/
+#define BITP_PG3MODE                             6
+#define ENUM_PG3MODE_OFF                         (0 << BITP_PG3MODE)
+#define ENUM_PG3MODE_1P                          (1 << BITP_PG3MODE)
+#define ENUM_PG3MODE_2P                          (2 << BITP_PG3MODE)
+#define ENUM_PG3MODE_3P                          (3 << BITP_PG3MODE)
+#define ENUM_PG3MODE_NP                          (4 << BITP_PG3MODE)
+#define ENUM_PG3MODE_CONT                        (5 << BITP_PG3MODE)
+/*Gen4 Modes*/
+#define BITP_PG4MODE                             9
+#define ENUM_PG4MODE_OFF                         (0 << BITP_PG4MODE)
+#define ENUM_PG4MODE_1P                          (1 << BITP_PG4MODE)
+#define ENUM_PG4MODE_2P                          (2 << BITP_PG4MODE)
+#define ENUM_PG4MODE_3P                          (3 << BITP_PG4MODE)
+#define ENUM_PG4MODE_NP                          (4 << BITP_PG4MODE)
+#define ENUM_PG4MODE_CONT                        (5 << BITP_PG4MODE)
+/*Gen5 Modes*/
+#define BITP_PG5MODE                            12
+#define ENUM_PG5MODE_OFF                         (0 << BITP_PG5MODE)
+#define ENUM_PG5MODE_1P                          (1 << BITP_PG5MODE)
+#define ENUM_PG5MODE_2P                          (2 << BITP_PG5MODE)
+#define ENUM_PG5MODE_3P                          (3 << BITP_PG5MODE)
+#define ENUM_PG5MODE_NP                          (4 << BITP_PG5MODE)
+#define ENUM_PG5MODE_CONT                        (5 << BITP_PG5MODE)
+/*Gen6 Modes*/
+#define BITP_PG6MODE                            15
+#define ENUM_PG6MODE_OFF                         (0 << BITP_PG6MODE)
+#define ENUM_PG6MODE_1P                          (1 << BITP_PG6MODE)
+#define ENUM_PG6MODE_2P                          (2 << BITP_PG6MODE)
+#define ENUM_PG6MODE_3P                          (3 << BITP_PG6MODE)
+#define ENUM_PG6MODE_NP                          (4 << BITP_PG6MODE)
+#define ENUM_PG6MODE_CONT                        (5 << BITP_PG6MODE)
+/*Gen7 Modes*/
+#define BITP_PG7MODE                            18
+#define BITM_PG7MODE                            (0x07 << BITP_PG7MODE)
+#define ENUM_PG7MODE_OFF                         (0 << BITP_PG7MODE)
+#define ENUM_PG7MODE_1P                          (1 << BITP_PG7MODE)
+#define ENUM_PG7MODE_2P                          (2 << BITP_PG7MODE)
+#define ENUM_PG7MODE_3P                          (3 << BITP_PG7MODE)
+#define ENUM_PG7MODE_NP                          (4 << BITP_PG7MODE)
+#define ENUM_PG7MODE_CONT                        (5 << BITP_PG7MODE)
+
+/**********************************************************************************
+ * 										MEAS_CTRL_REG
+ *********************************************************************************/
+#define BITP_MEAS_CTRL_T                            0
+#define BITP_MEAS_CTRL_R                            2
+#define BITP_MEAS_CTRL_SW                           6
+#define BITP_MEAS_CTRL_M                            10
+#define BITP_MEAS_CTRL_P                            14
+#define BITP_MEAS_CTRL_P1D                          18
+#define BITP_MEAS_CTRL_P2D                          19
+#define BITP_MEAS_CTRL_P3D                          20
+#define BITP_MEAS_CTRL_P4D                          21
+#define BITP_MEAS_CTRL_P5D                          22
+#define BITP_MEAS_CTRL_P6D                          23
+
+#define BITM_MEAS_CTRL_T                                    (0x03 << BITP_MEAS_CTRL_T)
+#define BITM_MEAS_CTRL_R                                    (0xF << BITP_MEAS_CTRL_R)
+#define BITM_MEAS_CTRL_SW                                   (0xF << BITP_MEAS_CTRL_SW)
+#define BITM_MEAS_CTRL_M                                    (0xF << BITP_MEAS_CTRL_M)
+#define BITM_MEAS_CTRL_P                                    (0xF << BITP_MEAS_CTRL_P)
+#define BITM_MEAS_CTRL_P1D                                  (0x01 << BITP_MEAS_CTRL_P1D)
+#define BITM_MEAS_CTRL_P2D                                  (0x01 << BITP_MEAS_CTRL_P2D)
+#define BITM_MEAS_CTRL_P3D                                  (0x01 << BITP_MEAS_CTRL_P3D)
+#define BITM_MEAS_CTRL_P4D                                  (0x01 << BITP_MEAS_CTRL_P4D)
+#define BITM_MEAS_CTRL_P5D                                  (0x01 << BITP_MEAS_CTRL_P5D)
+#define BITM_MEAS_CTRL_P6D                                  (0x01 << BITP_MEAS_CTRL_P6D)
+
+#define ENUM_MEAS_CTRL_P1D_IN                               (0x01 << BITP_MEAS_CTRL_P1D)
+#define ENUM_MEAS_CTRL_P2D_IN                               (0x01 << BITP_MEAS_CTRL_P2D)
+#define ENUM_MEAS_CTRL_P3D_IN                               (0x01 << BITP_MEAS_CTRL_P3D)
+#define ENUM_MEAS_CTRL_P4D_IN                               (0x01 << BITP_MEAS_CTRL_P4D)
+#define ENUM_MEAS_CTRL_P5D_IN                               (0x01 << BITP_MEAS_CTRL_P5D)
+#define ENUM_MEAS_CTRL_P6D_IN                               (0x01 << BITP_MEAS_CTRL_P6D)
+
+#define ENUM_MEAS_CTRL_P1D_OUT                              (0x00 << BITP_MEAS_CTRL_P1D)
+#define ENUM_MEAS_CTRL_P2D_OUT                              (0x00 << BITP_MEAS_CTRL_P2D)
+#define ENUM_MEAS_CTRL_P3D_OUT                              (0x00 << BITP_MEAS_CTRL_P3D)
+#define ENUM_MEAS_CTRL_P4D_OUT                              (0x00 << BITP_MEAS_CTRL_P4D)
+#define ENUM_MEAS_CTRL_P5D_OUT                              (0x00 << BITP_MEAS_CTRL_P5D)
+#define ENUM_MEAS_CTRL_P6D_OUT                              (0x00 << BITP_MEAS_CTRL_P6D)
+
+
+/**********************************************************************************
+ * 										CORR_COEF_H_REG
+ *********************************************************************************/
+#define BITP_CORR_COEF_H_CO                                 0
+#define BITM_CORR_COEF_H_CO                                 (0xFF << BITP_CORR_COEF_H_CO)
+/**********************************************************************************
+ * 										CORR_COEF_L_REG
+ *********************************************************************************/
+#define BITP_CORR_COEF_L_CO                                 0
+#define BITM_CORR_COEF_L_CO                                (0xFFFFFF << BITP_CORR_COEF_L_CO)
+
+/**********************************************************************************
+ * 										PGMODE1_REG
+ *********************************************************************************/
+#define BITP_PG1MODE1_RSTP_1                                0
+#define BITP_PG1MODE1_RST_P2                                1
+#define BITP_PG1MODE1_RST_P3                                2
+#define BITP_PG1MODE1_RST_P4                                3
+#define BITP_PG1MODE1_RST5_P5                               4
+#define BITP_PG1MODE1_RST6_P6                               5
+#define BITP_PG1MODE1_RST7_P7                               6
+
+#define BITM_PG1MODE1_RSTP_1                                (0x01 << BITP_PG1MODE1_RSTP_1)
+#define BITM_PG1MODE1_RST_P2                                (0x01 << BITP_PG1MODE1_RST_P2)
+#define BITM_PG1MODE1_RST_P3                                (0x01 << BITP_PG1MODE1_RST_P3)
+#define BITM_PG1MODE1_RST_P4                                (0x01 << BITP_PG1MODE1_RST_P4)
+#define BITM_PG1MODE1_RST5_P5                               (0x01 << BITP_PG1MODE1_RST5_P5)
+#define BITM_PG1MODE1_RST6_P6                               (0x01 << BITP_PG1MODE1_RST6_P6)
+#define BITM_PG1MODE1_RST7_P7                               (0x01 << BITP_PG1MODE1_RST7_P7)
+
+#define ENUM_PG1MODE1_RSTP_1_ON                             (0x01 << BITP_PG1MODE1_RSTP_1)
+#define ENUM_PG1MODE1_RST_P2_ON                             (0x01 << BITP_PG1MODE1_RST_P2)
+#define ENUM_PG1MODE1_RST_P3_ON                             (0x01 << BITP_PG1MODE1_RST_P3)
+#define ENUM_PG1MODE1_RST_P4_ON                             (0x01 << BITP_PG1MODE1_RST_P4)
+#define ENUM_PG1MODE1_RST5_P5_ON                            (0x01 << BITP_PG1MODE1_RST5_P5)
+#define ENUM_PG1MODE1_RST6_P6_ON                            (0x01 << BITP_PG1MODE1_RST6_P6)
+#define ENUM_PG1MODE1_RST7_P7_ON                            (0x01 << BITP_PG1MODE1_RST7_P7)
+
+#define ENUM_PG1MODE1_RSTP_1_OFF                            (0x00 << BITP_PG1MODE1_RSTP_1)
+#define ENUM_PG1MODE1_RST_P2_OFF                            (0x00 << BITP_PG1MODE1_RST_P2)
+#define ENUM_PG1MODE1_RST_P3_OFF                            (0x00 << BITP_PG1MODE1_RST_P3)
+#define ENUM_PG1MODE1_RST_P4_OFF                            (0x00 << BITP_PG1MODE1_RST_P4)
+#define ENUM_PG1MODE1_RST5_P5_OFF                           (0x00 << BITP_PG1MODE1_RST5_P5)
+#define ENUM_PG1MODE1_RST6_P6_OFF                           (0x00 << BITP_PG1MODE1_RST6_P6)
+#define ENUM_PG1MODE1_RST7_P7_OFF                           (0x00 << BITP_PG1MODE1_RST7_P7)
+
+#define BITP_PGMODE1_POL_P1                                 10
+#define BITP_PGMODE1_POL_P2                                 11
+#define BITP_PGMODE1_POL_P3                                 12
+#define BITP_PGMODE1_POL_P4                                 13
+#define BITP_PGMODE1_POL_P5                                 14
+#define BITP_PGMODE1_POL_P6                                 15
+#define BITP_PGMODE1_POL_P7                                 16
+
+#define BITM_PGMODE1_POL_P1                                 (0x01 << BITP_PGMODE1_POL_P1)
+#define BITM_PGMODE1_POL_P2                                 (0x01 << BITP_PGMODE1_POL_P2)
+#define BITM_PGMODE1_POL_P3                                 (0x01 << BITP_PGMODE1_POL_P3)
+#define BITM_PGMODE1_POL_P4                                 (0x01 << BITP_PGMODE1_POL_P4)
+#define BITM_PGMODE1_POL_P5                                 (0x01 << BITP_PGMODE1_POL_P5)
+#define BITM_PGMODE1_POL_P6                                 (0x01 << BITP_PGMODE1_POL_P6)
+#define BITM_PGMODE1_POL_P7                                 (0x01 << BITP_PGMODE1_POL_P7)
+
+#define BITP_PGMODE1_FRONT_P1                               17
+#define BITP_PGMODE1_FRONT_P2                               18
+#define BITP_PGMODE1_FRONT_P3                               19
+#define BITP_PGMODE1_FRONT_P4                               20
+#define BITP_PGMODE1_FRONT_P5                               21
+#define BITP_PGMODE1_FRONT_P6                               22
+#define BITP_PGMODE1_FRONT_P7                               23
+
+#define BITM_PGMODE1_FRONT_P1                               (0x01 << BITP_PGMODE1_FRONT_P1)
+#define BITM_PGMODE1_FRONT_P2                               (0x01 << BITP_PGMODE1_FRONT_P2)
+#define BITM_PGMODE1_FRONT_P3                               (0x01 << BITP_PGMODE1_FRONT_P3)
+#define BITM_PGMODE1_FRONT_P4                               (0x01 << BITP_PGMODE1_FRONT_P4)
+#define BITM_PGMODE1_FRONT_P5                               (0x01 << BITP_PGMODE1_FRONT_P5)
+#define BITM_PGMODE1_FRONT_P6                               (0x01 << BITP_PGMODE1_FRONT_P6)
+#define BITM_PGMODE1_FRONT_P7                               (0x01 << BITP_PGMODE1_FRONT_P7)
+
+/**********************************************************************************
+ * 										MUXCTRL2_REG
+ *********************************************************************************/
+#define BITP_MUXCTRL2_SSM                                   0
+#define BITM_MUXCTRL2_SSM                                   (0x1F << BITP_MUXCTRL2_SSM)
+
+#define BITP_MUXCTRL2_G1                                    5
+#define BITM_MUXCTRL2_G1                                    (0x1F << BITP_MUXCTRL2_G1)
+
+#define BITP_MUXCTRL2_G2                                    10
+#define BITM_MUXCTRL2_G2                                    (0x1F << BITP_MUXCTRL2_G2)
+
+#define BITP_MUXCTRL2_G3                                    15
+#define BITM_MUXCTRL2_G3                                    (0x1F << BITP_MUXCTRL2_G3)
+
+/**********************************************************************************
+ * 										MUXCTRL3_REG
+ *********************************************************************************/
+#define BITP_MUXCTRL3_ET1                                    0
+#define BITM_MUXCTRL3_ET1                                    (0x1F << BITP_MUXCTRL3_ET1)
+
+#define BITP_MUXCTRL3_ET2                                    5
+#define BITM_MUXCTRL3_ET2                                    (0x1F << BITP_MUXCTRL3_ET2)
+
+#define BITP_MUXCTRL3_ET                                     10
+#define BITM_MUXCTRL3_ET                                     (0x1F << BITP_MUXCTRL3_ET)
+
+#define BITP_MUXCTRL3_GM                                     15
+#define BITM_MUXCTRL3_GM                                     (0x1F << BITP_MUXCTRL3_GM)
+
+#define BITP_MUXCTRL3_IT2                                    20
+#define BITM_MUXCTRL3_IT2                                    (0xF << BITP_MUXCTRL3_IT2)
+
+/**********************************************************************************
+ * 										MUXCTRL4_REG
+ *********************************************************************************/
+#define BITP_MUXCTRL4_ET3                                    0
+#define BITM_MUXCTRL4_ET3                                    (0x1F << BITP_MUXCTRL4_ET3)
+
+#define BITP_MUXCTRL4_ET4                                    5
+#define BITM_MUXCTRL4_ET4                                    (0x1F << BITP_MUXCTRL4_ET4)
+
+#define BITP_MUXCTRL4_ET5                                    10
+#define BITM_MUXCTRL4_ET5                                    (0x1F << BITP_MUXCTRL4_ET5)
+
+#define BITP_MUXCTRL4_ET6                                    15
+#define BITM_MUXCTRL4_ET6                                    (0x1F << BITP_MUXCTRL4_ET6)
+
+/**********************************************************************************
+ * 										PG7P1W_REG
+ *********************************************************************************/
+#define BITP_PG7P1W_DELAY                                     0
+#define BITM_PG7P1W_DELAY                                     (0xFFFFFF << BITP_PG7P1W_DELAY)
+
+/**********************************************************************************
+ * 										PG7P1W_REG
+ *********************************************************************************/
+#define BITP_PG7P1W_DELAY                                     0
+#define BITM_PG7P1W_DELAY                                     (0xFFFFFF << BITP_PG7P1W_DELAY)
+
+/**********************************************************************************
+ * 										PG7P2W_REG
+ *********************************************************************************/
+#define BITP_PG7P2W_DELAY                                     0
+#define BITM_PG7P2W_DELAY                                     (0xFFFFFF << BITP_PG7P2W_DELAY)
+
+/**********************************************************************************
+ * 										PG7P3W_REG
+ *********************************************************************************/
+#define BITP_PG7P3W_DELAY                                     0
+#define BITM_PG7P3W_DELAY                                     (0xFFFFFF << BITP_PG7P3W_DELAY)
+
+/**********************************************************************************
+ * 										MEASNUM_REG
+ *********************************************************************************/
+#define BITP_MEASNUM_23_0                                     0
+#define BITM_MEASNUM_23_0                                     (0xFFFFFF << BITP_MEASNUM_23_0)
+
+/**********************************************************************************
+ * 										CFGREG_REG
+ *********************************************************************************/
+#define BITP_CFGREG_MEASSTART                                   0
+#define BITM_CFGREG_MEASSTART                                   (0x01 << BITP_CFGREG_MEASSTART)
+
+#define BITP_CFGREG_MEASSTOP                                    1
+#define BITM_CFGREG_MEASSTOP                                    (0x01 << BITP_CFGREG_MEASSTOP)
+
+#define ENUM_CFGREG_MEASSTART_START                             (0x01 << BITP_CFGREG_MEASSTART)
+#define ENUM_CFGREG_MEASSTOP_STOP                               (0x01 << BITP_CFGREG_MEASSTOP)
+
+
+#endif //USERPROGRAMME_REGMAP_H

main.cpp

@@ -0,0 +1,154 @@
+#include "RegMap.h"
+#include "vna.h"
+#include <cmath>
+#include <fcntl.h>
+#include <iostream>
+#include <sys/mman.h>
+
+
+#define BITM_0_7 0x000000FF
+#define BITM_8_15 0x0000FF00
+#define BITM_16_23 0x00FF0000
+#define BITM_24_31 0xFF000000
+
+#define BITP_MANTISSA 0
+#define BITP_EXPONENT 23
+#define BITP_SIGN 31
+
+#define BITM_MANTISSA ((1 << 23) - 1) << BITP_MANTISSA
+#define BITM_EXPONENT ((1 << 8) - 1) << BITP_EXPONENT
+#define BITM_SIGN (1 << BITP_SIGN)
+
+void *bar0;
+
+void vna::cfgRegWrite() {
+    // Write to the configuration register
+    uint32_t *ptr = (uint32_t *) (bar0) + CFGREG_ADDR;
+    *ptr = ENUM_CFGREG_MEASSTART_START;
+}
+
+void vna::cfgRegRead() {
+    // Read the configuration register
+    uint32_t *readValue;
+    uint32_t reg = 0;
+    while (!(reg & ENUM_CFGREG_MEASSTOP_STOP)) {
+        readValue = (uint32_t *) (bar0) + CFGREG_ADDR;
+        reg = lsbToMsb(*readValue);
+        if (reg & ENUM_CFGREG_MEASSTOP_STOP) {
+            std::cout << "End measurement bit is set" << std::endl;
+        } else {
+            std::cout << "End measurement bit is not set" << std::endl;
+        }
+    }
+}
+
+void vna::adcDataRead() {
+    // Read the adc data
+    for (int i = 0; i < 8; i++) {
+        uint32_t *data = (uint32_t *) (bar0) + 0x02;
+        adcData[i] = lsbToMsb(*data);
+        (void) printf("adcData[%d] = %0x\n", i, adcData[i]);
+    }
+    // Convert the read adc data to fp32 1.8.23 form
+    for (int i = 0; i < 8; i++) {
+        int sign = (adcData[i] & BITM_SIGN) ? -1 : 1;
+        int exponent = ((adcData[i] & BITM_EXPONENT) >> 23);
+        float mantissa = (adcData[i] & BITM_MANTISSA) / (float) pow(2, 23);
+        float adcFloat = sign * (mantissa + 1) * pow(2, (exponent - 127));
+        (void) printf("adcDataFloat[%d] = %.12f\n", i, adcFloat);
+    }
+}
+
+uint32_t vna::lsbToMsb(uint32_t reg) {
+    auto result = static_cast<uint32_t>((reg & BITM_24_31) >> 24);
+    result |= static_cast<uint32_t>((reg & BITM_16_23) >> 8);
+    result |= static_cast<uint32_t>((reg & BITM_8_15) << 8);
+    result |= static_cast<uint32_t>((reg & BITM_0_7) << 24);
+    return result;
+}
+
+void vna::sendSettings() {
+    /*Send the PGMODE reg*/
+    uint32_t *data = (uint32_t *) (bar0) + PGMODE0_ADDR;
+    *data = 0x49209U;
+    /*Send the MEASCTRL reg*/
+    data = (uint32_t *) (bar0) + MEAS_CTRL_ADDR;
+    *data = 0x3f6000U;
+    /*Send the ADCCTRL reg*/
+    data = (uint32_t *) (bar0) + ADC_CTRL_ADDR;
+    *data = 0x2U;
+    /*Send the CORR_COEF_H reg*/
+    data = (uint32_t *) (bar0) + CORR_COEF_H_ADDR;
+    *data = 0x3fU;
+    /*Send the PGMODE1 reg*/
+    data = (uint32_t *) (bar0) + PGMODE1_ADDR;
+    *data = 0x1000U;
+    /*Send the MUXCTRL2 reg*/
+    data = (uint32_t *) (bar0) + MUX_CTRL2_ADDR;
+    *data = 0x1a3U;
+    /*Send the MUXCTRL3 reg*/
+    data = (uint32_t *) (bar0) + MUX_CTRL3_ADDR;
+    *data = 0x13c2eU;
+    /*Send the MUXCTRL4 reg*/
+    data = (uint32_t *) (bar0) + MUX_CTRL4_ADDR;
+    *data = 0x8421U;
+    /*Send the PG7P1W reg*/
+    data = (uint32_t *) (bar0) + PG7P1W_ADDR;
+    *data = 0x1U;
+    /*Send the PG1P1W reg*/
+    data = (uint32_t *) (bar0) + PG1P1W_ADDR;
+    *data = 0x1U;
+    /*Send the PG2P1W reg*/
+    data = (uint32_t *) (bar0) + PG2P1W_ADDR;
+    *data = 0x1U;
+    /*Send the PG3P1W reg*/
+    data = (uint32_t *) (bar0) + PG3P1W_ADDR;
+    *data = 0x1U;
+    /*Send the PG4P1W reg*/
+    data = (uint32_t *) (bar0) + PG4P1W_ADDR;
+    *data = 0x1U;
+    /*Send the PG5P1W reg*/
+    data = (uint32_t *) (bar0) + PG5P1W_ADDR;
+    *data = 0x1U;
+    /*Send the PG6P1W reg*/
+    data = (uint32_t *) (bar0) + PG6P1W_ADDR;
+    *data = 0x1U;
+    /*Send the MEASNUM reg*/
+    data = (uint32_t *) (bar0) + MEASNUM_23_0_ADDR;
+    *data = 0x1U;
+}
+
+int main() {
+
+    const char *filename = "/dev/MyDmaModule";
+    int pciFd;// File descriptor
+
+    // Open the device file
+    pciFd = open(filename, O_RDWR | O_SYNC);
+    if (pciFd < 0) {
+        std::cout << "Error: Cannot open device file" << std::endl;
+        return -1;
+    }
+    bar0 = mmap(nullptr, 0x1000U, PROT_READ | PROT_WRITE, MAP_SHARED, pciFd, 0);
+
+    if (bar0 == MAP_FAILED) {
+        std::cout << "Error: Cannot map the device file" << std::endl;
+        (void) close(pciFd);
+        return -1;
+    }
+    // Create an object of the vna class
+    vna tmsg;
+    /* Send the settings */
+    tmsg.sendSettings();
+    // Call the cfgRegWrite method
+    tmsg.cfgRegWrite();
+    // Call the cfgRegRead method
+    vna::cfgRegRead();
+    // Call the adcDataRead method
+    tmsg.adcDataRead();
+    // Close the device file
+    (void) close(pciFd);
+    // Unmap the device file
+    (void) munmap(bar0, 0x1000U);
+    return 0;
+}

vna.h

@@ -0,0 +1,33 @@
+#ifndef USERPROGRAMME_VNA_H
+#define USERPROGRAMME_VNA_H
+
+#include "unistd.h"
+#include <cstdint>
+#include <vector>
+
+class vna {
+public :
+    // Constructor
+    vna() = default;
+
+    // Destructor
+    ~vna() = default;
+
+private:
+    //Array of the 32-bit adc data
+    std::vector<int> adcData = std::vector<int>(8);
+public:
+    // Public methods
+    void adcDataRead();
+
+    static void cfgRegRead();
+
+    void cfgRegWrite();
+
+    void sendSettings();
+
+    static uint32_t lsbToMsb(uint32_t reg);
+
+};
+
+#endif //USERPROGRAMME_VNA_H