Рефакторинг кода. Изменение левой части структурной схемы.

src/scr/InitRst/InitRst.v

@@ -0,0 +1,104 @@
+module InitRst (
+    clk_i,
+    signal_o
+);
+
+//================================================================================
+//
+//  FUNCTIONS
+//
+//================================================================================
+
+    function integer bit_num;
+        input integer value;
+        begin
+            bit_num = 0;
+            while (value > 0) begin
+                value   = value >> 1;
+                bit_num = bit_num + 1;
+            end
+        end
+    endfunction
+
+//================================================================================
+//
+//  PARAMETER/LOCALPARAM
+//
+//================================================================================
+
+    parameter   DELAY_VALUE     = 20;
+    localparam  DELAY_CNT_W     = bit_num(DELAY_VALUE);
+
+//================================================================================
+//
+//  PORTS
+//
+//================================================================================
+
+    input           clk_i;
+    output  reg     signal_o;
+
+//================================================================================
+//
+//  STATE MACHINE STATES
+//
+//================================================================================
+
+    localparam      SM_RST_S    = 1'b0;
+    localparam      SM_DONE_S   = 1'b1;
+
+//================================================================================
+//
+//  REG/WIRE
+//
+//================================================================================
+
+    reg                         curr_state  = SM_RST_S;
+    reg     [DELAY_CNT_W-1:0]   delay_cnt   = {DELAY_CNT_W{1'b0}};
+    reg                         delay_flag  = 1'b0;
+
+    reg                         next_state;
+    reg     [DELAY_CNT_W-1:0]   delay_cnt_next	=	{DELAY_CNT_W{1'b0}};
+    reg                         signal_next;
+
+//================================================================================
+//
+//  CODING
+//
+//================================================================================
+
+initial begin
+    curr_state  = SM_RST_S;
+    delay_cnt   = {DELAY_CNT_W{1'b0}};
+    signal_o    = 1'b1;
+    delay_flag  = 1'b0;
+end
+
+always @(posedge clk_i) begin
+    curr_state  <= next_state;
+    delay_cnt   <= delay_cnt_next;
+    signal_o    <= signal_next;
+    delay_flag  <= delay_cnt > (DELAY_VALUE - 1);
+end
+
+always @(*) begin
+    next_state      = SM_RST_S;
+    delay_cnt_next  = delay_cnt;
+    signal_next     = 1'b1;
+    case(curr_state)
+        SM_RST_S    : begin
+            if (delay_flag) begin
+                next_state      = SM_DONE_S;
+            end else begin
+                next_state      = SM_RST_S;
+                delay_cnt_next  = delay_cnt + {{(DELAY_CNT_W-1){1'b0}}, 1'b1};
+            end
+        end
+        SM_DONE_S   : begin
+            signal_next = 1'b0;
+            next_state  = SM_DONE_S;
+        end
+    endcase
+end
+
+endmodule

src/scr/RegMap/RegMap.v

@@ -0,0 +1,897 @@
+
+module RegMap #(
+	parameter CMD_REG_WIDTH = 32,
+	parameter ADDR_REG_WIDTH = 12
+)
+(
+	input Clk_i,
+	input Rst_i,
+	input [1:0] SmcBe_i,
+
+	input [CMD_REG_WIDTH/2-1:0] Data_i,
+	input [ADDR_REG_WIDTH-1:0] Addr_i,
+	input Val_i,
+
+	input [CMD_REG_WIDTH-1:0] TxFifoCtrlReg0_i,
+	input [CMD_REG_WIDTH-1:0] RxFifoCtrlReg0_i,
+	input [CMD_REG_WIDTH-1:0] TxFifoCtrlReg1_i,
+	input [CMD_REG_WIDTH-1:0] RxFifoCtrlReg1_i,
+	input [CMD_REG_WIDTH-1:0] TxFifoCtrlReg2_i,
+	input [CMD_REG_WIDTH-1:0] RxFifoCtrlReg2_i,
+	input [CMD_REG_WIDTH-1:0] TxFifoCtrlReg3_i,
+	input [CMD_REG_WIDTH-1:0] RxFifoCtrlReg3_i,
+	input [CMD_REG_WIDTH-1:0] TxFifoCtrlReg4_i,
+	input [CMD_REG_WIDTH-1:0] RxFifoCtrlReg4_i,
+	input [CMD_REG_WIDTH-1:0] TxFifoCtrlReg5_i,
+	input [CMD_REG_WIDTH-1:0] RxFifoCtrlReg5_i,
+	input [CMD_REG_WIDTH-1:0] TxFifoCtrlReg6_i,
+	input [CMD_REG_WIDTH-1:0] RxFifoCtrlReg6_i,
+
+	input [6:0] LdReg_i,
+
+	output reg [CMD_REG_WIDTH/2-1:0] Spi0CtrlReg_o,
+	output reg [CMD_REG_WIDTH/2-1:0] Spi0ClkReg_o,
+	output reg [CMD_REG_WIDTH/2-1:0] Spi0CsDelayReg_o,
+	output reg [CMD_REG_WIDTH/2-1:0] Spi0CsCtrlReg_o,
+	output reg [CMD_REG_WIDTH/2-1:0] Spi0TxFifoCtrlReg_o,
+	output reg [CMD_REG_WIDTH/2-1:0] Spi0RxFifoCtrlReg_o,
+	output reg [CMD_REG_WIDTH/2-1:0] Spi0TxFifoReg_o,
+	output reg [CMD_REG_WIDTH/2-1:0] Spi0RxFifoReg_o,
+
+	output reg [CMD_REG_WIDTH/2-1:0] Spi1CtrlReg_o,
+	output reg [CMD_REG_WIDTH/2-1:0] Spi1ClkReg_o,
+	output reg [CMD_REG_WIDTH/2-1:0] Spi1CsDelayReg_o,
+	output reg [CMD_REG_WIDTH/2-1:0] Spi1CsCtrlReg_o,
+	output reg [CMD_REG_WIDTH/2-1:0] Spi1TxFifoCtrlReg_o,
+	output reg [CMD_REG_WIDTH/2-1:0] Spi1RxFifoCtrlReg_o,
+	output reg [CMD_REG_WIDTH/2-1:0] Spi1TxFifoReg_o,
+	output reg [CMD_REG_WIDTH/2-1:0] Spi1RxFifoReg_o,
+
+	output reg [CMD_REG_WIDTH/2-1:0] Spi2CtrlReg_o,
+	output reg [CMD_REG_WIDTH/2-1:0] Spi2ClkReg_o,
+	output reg [CMD_REG_WIDTH/2-1:0] Spi2CsDelayReg_o,
+	output reg [CMD_REG_WIDTH/2-1:0] Spi2CsCtrlReg_o,
+	output reg [CMD_REG_WIDTH/2-1:0] Spi2TxFifoCtrlReg_o,
+	output reg [CMD_REG_WIDTH/2-1:0] Spi2RxFifoCtrlReg_o,
+	output reg [CMD_REG_WIDTH/2-1:0] Spi2TxFifoReg_o,
+	output reg [CMD_REG_WIDTH/2-1:0] Spi2RxFifoReg_o,
+	
+	output reg [CMD_REG_WIDTH/2-1:0] Spi3CtrlReg_o,
+	output reg [CMD_REG_WIDTH/2-1:0] Spi3ClkReg_o,
+	output reg [CMD_REG_WIDTH/2-1:0] Spi3CsDelayReg_o,
+	output reg [CMD_REG_WIDTH/2-1:0] Spi3CsCtrlReg_o,
+	output reg [CMD_REG_WIDTH/2-1:0] Spi3TxFifoCtrlReg_o,
+	output reg [CMD_REG_WIDTH/2-1:0] Spi3RxFifoCtrlReg_o,
+	output reg [CMD_REG_WIDTH/2-1:0] Spi3TxFifoReg_o,
+	output reg [CMD_REG_WIDTH/2-1:0] Spi3RxFifoReg_o,
+
+	output reg [CMD_REG_WIDTH/2-1:0] Spi4CtrlReg_o,
+	output reg [CMD_REG_WIDTH/2-1:0] Spi4ClkReg_o,
+	output reg [CMD_REG_WIDTH/2-1:0] Spi4CsDelayReg_o,
+	output reg [CMD_REG_WIDTH/2-1:0] Spi4CsCtrlReg_o,
+	output reg [CMD_REG_WIDTH/2-1:0] Spi4TxFifoCtrlReg_o,
+	output reg [CMD_REG_WIDTH/2-1:0] Spi4RxFifoCtrlReg_o,
+	output reg [CMD_REG_WIDTH/2-1:0] Spi4TxFifoReg_o,
+	output reg [CMD_REG_WIDTH/2-1:0] Spi4RxFifoReg_o,
+	
+	output reg [CMD_REG_WIDTH/2-1:0] Spi5CtrlReg_o,
+	output reg [CMD_REG_WIDTH/2-1:0] Spi5ClkReg_o,
+	output reg [CMD_REG_WIDTH/2-1:0] Spi5CsDelayReg_o,
+	output reg [CMD_REG_WIDTH/2-1:0] Spi5CsCtrlReg_o,
+	output reg [CMD_REG_WIDTH/2-1:0] Spi5TxFifoCtrlReg_o,
+	output reg [CMD_REG_WIDTH/2-1:0] Spi5RxFifoCtrlReg_o,
+	output reg [CMD_REG_WIDTH/2-1:0] Spi5TxFifoReg_o,
+	output reg [CMD_REG_WIDTH/2-1:0] Spi5RxFifoReg_o,
+
+	output reg [CMD_REG_WIDTH/2-1:0] Spi6CtrlReg_o,
+	output reg [CMD_REG_WIDTH/2-1:0] Spi6ClkReg_o,
+	output reg [CMD_REG_WIDTH/2-1:0] Spi6CsDelayReg_o,
+	output reg [CMD_REG_WIDTH/2-1:0] Spi6CsCtrlReg_o,
+	output reg [CMD_REG_WIDTH/2-1:0] Spi6TxFifoCtrlReg_o,
+	output reg [CMD_REG_WIDTH/2-1:0] Spi6RxFifoCtrlReg_o,
+	output reg [CMD_REG_WIDTH/2-1:0] Spi6TxFifoReg_o,
+	output reg [CMD_REG_WIDTH/2-1:0] Spi6RxFifoReg_o,
+
+	output [CMD_REG_WIDTH/2-1:0] SpiTxRxEnReg_o,
+	output [CMD_REG_WIDTH-1:0] GPIOAReg_o,
+
+	output [CMD_REG_WIDTH/2-1:0] AnsDataReg_o,
+	
+	output Led_o
+);
+
+//================================================================================
+//	REG/WIRE
+//================================================================================
+	(* dont_touch = "yes" *)reg [CMD_REG_WIDTH/2-1:0] spiTxRxEnReg;
+	reg [CMD_REG_WIDTH/2-1:0] GPIOAReg;
+	reg [CMD_REG_WIDTH/2-1:0] GPIOARegS;
+	
+	(* dont_touch = "yes" *)reg [CMD_REG_WIDTH/2-1:0] ansReg;
+	(* dont_touch = "yes" *)reg [CMD_REG_WIDTH/2-1:0] ledReg;
+	
+	reg	[1:0]	beReg;
+
+//================================================================================
+//	ASSIGNMENTS
+//================================================================================
+	assign SpiTxRxEnReg_o = spiTxRxEnReg;
+	assign GPIOAReg_o = {GPIOARegS, GPIOAReg};
+	
+	assign AnsDataReg_o = ansReg;
+	assign Led_o = ledReg[0];
+
+//================================================================================
+//	LOCALPARAMS
+//================================================================================
+	localparam SPI_0_CTRL_ADDR 				= 12'h00;
+	localparam SPI_0_CLK_ADDR  				= 12'h04;
+	localparam SPI_0_CS_DELAY_ADDR 			= 12'h08;
+	localparam SPI_0_CS_CTRL_ADDR 			= 12'h0c;
+	localparam SPI_0_TX_FIFO_CTRL_ADDR_LSB 	= 12'h10;
+	localparam SPI_0_TX_FIFO_CTRL_ADDR_MSB 	= 12'h12;
+	localparam SPI_0_RX_FIFO_CTRL_ADDR_LSB 	= 12'h14;
+	localparam SPI_0_RX_FIFO_CTRL_ADDR_MSB 	= 12'h16;
+	localparam SPI_0_TX_FIFO 				= 12'h18;
+	localparam SPI_0_RX_FIFO 				= 12'h1c;
+	
+	localparam SPI_1_CTRL_ADDR 				= 12'h50;
+	localparam SPI_1_CLK_ADDR  				= 12'h54;
+	localparam SPI_1_CS_DELAY_ADDR 			= 12'h58;
+	localparam SPI_1_CS_CTRL_ADDR 			= 12'h5c;
+	localparam SPI_1_TX_FIFO_CTRL_ADDR_LSB 	= 12'h60;
+	localparam SPI_1_TX_FIFO_CTRL_ADDR_MSB 	= 12'h62;
+	localparam SPI_1_RX_FIFO_CTRL_ADDR_LSB 	= 12'h64;
+	localparam SPI_1_RX_FIFO_CTRL_ADDR_MSB 	= 12'h66;
+	localparam SPI_1_TX_FIFO 				= 12'h68;
+	localparam SPI_1_RX_FIFO 				= 12'h6c;
+	
+	localparam SPI_2_CTRL_ADDR 				= 12'hF0;
+	localparam SPI_2_CLK_ADDR  				= 12'hF4;
+	localparam SPI_2_CS_DELAY_ADDR 			= 12'hF8;
+	localparam SPI_2_CS_CTRL_ADDR 			= 12'hFc;
+	localparam SPI_2_TX_FIFO_CTRL_ADDR_LSB 	= 12'h100;
+	localparam SPI_2_TX_FIFO_CTRL_ADDR_MSB 	= 12'h102;
+	localparam SPI_2_RX_FIFO_CTRL_ADDR_LSB 	= 12'h104;
+	localparam SPI_2_RX_FIFO_CTRL_ADDR_MSB 	= 12'h106;
+	localparam SPI_2_TX_FIFO 				= 12'h108;
+	localparam SPI_2_RX_FIFO 				= 12'h10c;
+	
+	localparam SPI_3_CTRL_ADDR 				= 12'h140;
+	localparam SPI_3_CLK_ADDR  				= 12'h144;
+	localparam SPI_3_CS_DELAY_ADDR 			= 12'h148;
+	localparam SPI_3_CS_CTRL_ADDR 			= 12'h14c;
+	localparam SPI_3_TX_FIFO_CTRL_ADDR_LSB 	= 12'h150;
+	localparam SPI_3_TX_FIFO_CTRL_ADDR_MSB 	= 12'h152;
+	localparam SPI_3_RX_FIFO_CTRL_ADDR_LSB 	= 12'h154;
+	localparam SPI_3_RX_FIFO_CTRL_ADDR_MSB 	= 12'h156;
+	localparam SPI_3_TX_FIFO 				= 12'h158;
+	localparam SPI_3_RX_FIFO 				= 12'h15c;
+	
+	localparam SPI_4_CTRL_ADDR 				= 12'h190;
+	localparam SPI_4_CLK_ADDR  				= 12'h194;
+	localparam SPI_4_CS_DELAY_ADDR 			= 12'h198;
+	localparam SPI_4_CS_CTRL_ADDR 			= 12'h19c;
+	localparam SPI_4_TX_FIFO_CTRL_ADDR_LSB 	= 12'h1a0;
+	localparam SPI_4_TX_FIFO_CTRL_ADDR_MSB 	= 12'h1a2;
+	localparam SPI_4_RX_FIFO_CTRL_ADDR_LSB 	= 12'h1a4;
+	localparam SPI_4_RX_FIFO_CTRL_ADDR_MSB 	= 12'h1a6;
+	localparam SPI_4_TX_FIFO 				= 12'h1a8;
+	localparam SPI_4_RX_FIFO 				= 12'h1ac;
+	
+	localparam SPI_5_CTRL_ADDR 				= 12'h1e0;
+	localparam SPI_5_CLK_ADDR  				= 12'h1e4;
+	localparam SPI_5_CS_DELAY_ADDR 			= 12'h1e8;
+	localparam SPI_5_CS_CTRL_ADDR 			= 12'h1ec;
+	localparam SPI_5_TX_FIFO_CTRL_ADDR_LSB 	= 12'h1f0;
+	localparam SPI_5_TX_FIFO_CTRL_ADDR_MSB 	= 12'h1f2;
+	localparam SPI_5_RX_FIFO_CTRL_ADDR_LSB 	= 12'h1f4;
+	localparam SPI_5_RX_FIFO_CTRL_ADDR_MSB 	= 12'h1f6;
+	localparam SPI_5_TX_FIFO 				= 12'h1f8;
+	localparam SPI_5_RX_FIFO 				= 12'h1fc;
+	
+	localparam SPI_6_CTRL_ADDR 				= 12'h230;
+	localparam SPI_6_CLK_ADDR  				= 12'h234;
+	localparam SPI_6_CS_DELAY_ADDR 			= 12'h238;
+	localparam SPI_6_CS_CTRL_ADDR 			= 12'h23c;
+	localparam SPI_6_TX_FIFO_CTRL_ADDR_LSB 	= 12'h240;
+	localparam SPI_6_TX_FIFO_CTRL_ADDR_MSB 	= 12'h242;
+	localparam SPI_6_RX_FIFO_CTRL_ADDR_LSB 	= 12'h244;
+	localparam SPI_6_RX_FIFO_CTRL_ADDR_MSB 	= 12'h246;
+	localparam SPI_6_TX_FIFO 				= 12'h248;
+	localparam SPI_6_RX_FIFO 				= 12'h24c;
+	
+	localparam SPI_TX_RX_EN 	= 12'hF00;
+	localparam GPIO_CTRL_ADDR 	= 12'hFF0;
+	localparam GPIO_CTRL_ADDR_S = 12'hFF2;
+	
+	localparam DEBUG_0_ADDR = 12'hFF8;
+	localparam DEBUG_1_ADDR = 12'hFFC;
+
+//================================================================================
+//  CODING
+//================================================================================
+	always	@(posedge	Clk_i)	begin
+		if	(!Rst_i)	begin
+			beReg	<=	2'b0;
+		end	else	begin
+			beReg	<=	SmcBe_i;
+		end
+	end
+	
+	always @(posedge Clk_i) begin 
+		if (Rst_i) begin 
+			Spi0ClkReg_o 		<= 0;
+			Spi0CtrlReg_o 		<= 0;
+			Spi0CsDelayReg_o 	<= 0;
+			Spi0CsCtrlReg_o 	<= 0;
+			Spi0TxFifoCtrlReg_o <= 0;
+			Spi0RxFifoCtrlReg_o <= 0;
+			Spi1ClkReg_o 		<= 0;
+			Spi1CtrlReg_o 		<= 0;
+			Spi1CsDelayReg_o 	<= 0;
+			Spi1CsCtrlReg_o 	<= 0;
+			Spi1TxFifoCtrlReg_o <= 0;
+			Spi1RxFifoCtrlReg_o <= 0;
+			Spi2ClkReg_o 		<= 0;
+			Spi2CtrlReg_o 		<= 0;
+			Spi2CsDelayReg_o 	<= 0;
+			Spi2CsCtrlReg_o 	<= 0;
+			Spi2TxFifoCtrlReg_o <= 0;
+			Spi2RxFifoCtrlReg_o <= 0;
+			Spi3ClkReg_o 		<= 0;
+			Spi3CtrlReg_o 		<= 0;
+			Spi3CsDelayReg_o 	<= 0;
+			Spi3CsCtrlReg_o 	<= 0;
+			Spi3TxFifoCtrlReg_o <= 0;
+			Spi3RxFifoCtrlReg_o <= 0;
+			Spi4ClkReg_o 		<= 0;
+			Spi4CtrlReg_o 		<= 0;
+			Spi4CsDelayReg_o 	<= 0;
+			Spi4CsCtrlReg_o 	<= 0;
+			Spi4TxFifoCtrlReg_o <= 0;
+			Spi4RxFifoCtrlReg_o <= 0;
+			Spi5ClkReg_o 		<= 0;
+			Spi5CtrlReg_o 		<= 0;
+			Spi5CsDelayReg_o 	<= 0;
+			Spi5CsCtrlReg_o 	<= 0;
+			Spi5TxFifoCtrlReg_o <= 0;
+			Spi5RxFifoCtrlReg_o <= 0;
+			Spi6ClkReg_o 		<= 0;
+			Spi6CtrlReg_o 		<= 0;
+			Spi6CsDelayReg_o 	<= 0;
+			Spi6CsCtrlReg_o 	<= 0;
+			Spi6TxFifoCtrlReg_o <= 0;
+			Spi6RxFifoCtrlReg_o <= 0;
+			spiTxRxEnReg 		<= 0;
+			GPIOAReg 			<= 0;
+			GPIOARegS 			<= 0;
+			ledReg 				<= 0;
+		end
+		else begin 
+			if (Val_i) begin 
+				case (beReg)  
+					0 : begin 
+						case (Addr_i) 
+							SPI_0_CTRL_ADDR : begin 
+								Spi0CtrlReg_o <= Data_i;
+							end
+							SPI_0_CLK_ADDR : begin 
+								Spi0ClkReg_o <= Data_i;
+							end
+							SPI_0_CS_DELAY_ADDR : begin 
+								Spi0CsDelayReg_o <= Data_i;
+							end
+							SPI_0_CS_CTRL_ADDR : begin 
+								Spi0CsCtrlReg_o <= Data_i;
+							end
+							SPI_0_TX_FIFO_CTRL_ADDR_LSB : begin 
+								Spi0TxFifoCtrlReg_o <= Data_i;
+							end
+							SPI_0_RX_FIFO_CTRL_ADDR_LSB : begin 
+								Spi0RxFifoCtrlReg_o <= Data_i;
+							end
+							SPI_1_CTRL_ADDR : begin 
+								Spi1CtrlReg_o <= Data_i;
+							end
+							SPI_1_CLK_ADDR : begin 
+								Spi1ClkReg_o <= Data_i;
+							end
+							SPI_1_CS_DELAY_ADDR : begin 
+								Spi1CsDelayReg_o <= Data_i;
+							end
+							SPI_1_CS_CTRL_ADDR : begin 
+								Spi1CsCtrlReg_o <= Data_i;
+							end
+							SPI_1_TX_FIFO_CTRL_ADDR_LSB : begin 
+								Spi1TxFifoCtrlReg_o <= Data_i;
+							end
+							SPI_1_RX_FIFO_CTRL_ADDR_LSB : begin 
+								Spi1RxFifoCtrlReg_o <= Data_i;
+							end
+							SPI_2_CTRL_ADDR : begin 
+								Spi2CtrlReg_o <= Data_i;
+							end
+							SPI_2_CLK_ADDR : begin 
+								Spi2ClkReg_o <= Data_i;
+							end
+							SPI_2_CS_DELAY_ADDR : begin 
+								Spi2CsDelayReg_o <= Data_i;
+							end
+							SPI_2_CS_CTRL_ADDR : begin 
+								Spi2CsCtrlReg_o <= Data_i;
+							end
+							SPI_2_TX_FIFO_CTRL_ADDR_LSB : begin 
+								Spi2TxFifoCtrlReg_o <= Data_i;
+							end
+							SPI_2_RX_FIFO_CTRL_ADDR_LSB : begin 
+								Spi2RxFifoCtrlReg_o <= Data_i;
+							end
+							SPI_3_CTRL_ADDR : begin 
+								Spi3CtrlReg_o <= Data_i;
+							end
+							SPI_3_CLK_ADDR : begin 
+								Spi3ClkReg_o <= Data_i;
+							end
+							SPI_3_CS_DELAY_ADDR : begin 
+								Spi3CsDelayReg_o <= Data_i;
+							end
+							SPI_3_CS_CTRL_ADDR : begin 
+								Spi3CsCtrlReg_o <= Data_i;
+							end
+							SPI_3_TX_FIFO_CTRL_ADDR_LSB : begin 
+								Spi3TxFifoCtrlReg_o <= Data_i;
+							end
+							SPI_3_RX_FIFO_CTRL_ADDR_LSB : begin 
+								Spi3RxFifoCtrlReg_o <= Data_i;
+							end
+							SPI_4_CTRL_ADDR : begin 
+								Spi4CtrlReg_o <= Data_i;
+							end
+							SPI_4_CLK_ADDR : begin 
+								Spi4ClkReg_o <= Data_i;
+							end
+							SPI_4_CS_DELAY_ADDR : begin 
+								Spi4CsDelayReg_o <= Data_i;
+							end
+							SPI_4_CS_CTRL_ADDR : begin 
+								Spi4CsCtrlReg_o <= Data_i;
+							end
+							SPI_4_TX_FIFO_CTRL_ADDR_LSB : begin 
+								Spi4TxFifoCtrlReg_o <= Data_i;
+							end
+							SPI_4_RX_FIFO_CTRL_ADDR_LSB : begin 
+								Spi4RxFifoCtrlReg_o <= Data_i;
+							end
+							SPI_5_CTRL_ADDR : begin 
+								Spi5CtrlReg_o <= Data_i;
+							end
+							SPI_5_CLK_ADDR : begin 
+								Spi5ClkReg_o <= Data_i;
+							end
+							SPI_5_CS_DELAY_ADDR : begin 
+								Spi5CsDelayReg_o <= Data_i;
+							end
+							SPI_5_CS_CTRL_ADDR : begin 
+								Spi5CsCtrlReg_o <= Data_i;
+							end
+							SPI_5_TX_FIFO_CTRL_ADDR_LSB : begin 
+								Spi5TxFifoCtrlReg_o <= Data_i;
+							end
+							SPI_5_RX_FIFO_CTRL_ADDR_LSB : begin 
+								Spi5RxFifoCtrlReg_o <= Data_i;
+							end
+							SPI_6_CTRL_ADDR : begin 
+								Spi6CtrlReg_o <= Data_i;
+							end
+							SPI_6_CLK_ADDR : begin 
+								Spi6ClkReg_o <= Data_i;
+							end
+							SPI_6_CS_DELAY_ADDR : begin 
+								Spi6CsDelayReg_o <= Data_i;
+							end
+							SPI_6_CS_CTRL_ADDR : begin 
+								Spi6CsCtrlReg_o <= Data_i;
+							end
+							SPI_6_TX_FIFO_CTRL_ADDR_LSB : begin 
+								Spi6TxFifoCtrlReg_o <= Data_i;
+							end
+							SPI_6_RX_FIFO_CTRL_ADDR_LSB : begin 
+								Spi6RxFifoCtrlReg_o <= Data_i;
+							end
+							SPI_TX_RX_EN : begin 
+								spiTxRxEnReg <= Data_i;
+							end
+							GPIO_CTRL_ADDR : begin 
+								GPIOAReg <= Data_i;
+							end
+							GPIO_CTRL_ADDR_S : begin 
+								GPIOARegS <= Data_i;
+							end
+							DEBUG_0_ADDR : begin 
+								ledReg <= Data_i;
+							end
+						endcase
+					end
+					1 : begin 
+						case (Addr_i)
+							SPI_0_CTRL_ADDR : begin
+								Spi0CtrlReg_o[15:8] <= Data_i[15:8];
+							end
+							SPI_0_CLK_ADDR : begin 
+								Spi0ClkReg_o[15:8] <= Data_i[15:8];
+							end
+							SPI_0_CS_DELAY_ADDR : begin 
+								Spi0CsDelayReg_o[15:8] <= Data_i[15:8];
+							end
+							SPI_0_CS_CTRL_ADDR : begin 
+								Spi0CsCtrlReg_o[15:8] <= Data_i[15:8];
+							end
+							SPI_0_TX_FIFO_CTRL_ADDR_LSB : begin 
+								Spi0TxFifoCtrlReg_o[15:8] <= Data_i[15:8];
+							end
+							SPI_0_RX_FIFO_CTRL_ADDR_LSB : begin 
+								Spi0RxFifoCtrlReg_o[15:8] <= Data_i[15:8];
+							end
+							SPI_1_CTRL_ADDR : begin 
+								Spi1CtrlReg_o[15:8] <= Data_i[15:8];
+							end
+							SPI_1_CLK_ADDR : begin 
+								Spi1ClkReg_o[15:8] <= Data_i[15:8];
+							end
+							SPI_1_CS_DELAY_ADDR : begin 
+								Spi1CsDelayReg_o[15:8] <= Data_i[15:8];
+							end
+							SPI_1_CS_CTRL_ADDR : begin 
+								Spi1CsCtrlReg_o[15:8] <= Data_i[15:8];
+							end
+							SPI_1_TX_FIFO_CTRL_ADDR_LSB : begin 
+								Spi1TxFifoCtrlReg_o[15:8] <= Data_i[15:8];
+							end
+							SPI_1_RX_FIFO_CTRL_ADDR_LSB : begin 
+								Spi1RxFifoCtrlReg_o[15:8] <= Data_i[15:8];
+							end
+							SPI_2_CTRL_ADDR : begin 
+								Spi2CtrlReg_o[15:8] <= Data_i[15:8];
+							end
+							SPI_2_CLK_ADDR : begin 
+								Spi2ClkReg_o[15:8] <= Data_i[15:8];
+							end
+							SPI_2_CS_DELAY_ADDR : begin 
+								Spi2CsDelayReg_o[15:8] <= Data_i[15:8];
+							end
+							SPI_2_CS_CTRL_ADDR : begin 
+								Spi2CsCtrlReg_o[15:8] <= Data_i[15:8];
+							end
+							SPI_2_TX_FIFO_CTRL_ADDR_LSB : begin 
+								Spi2TxFifoCtrlReg_o[15:8] <= Data_i[15:8];
+							end
+							SPI_2_RX_FIFO_CTRL_ADDR_LSB : begin 
+								Spi2RxFifoCtrlReg_o[15:8] <= Data_i[15:8];
+							end
+							SPI_3_CTRL_ADDR : begin 
+								Spi3CtrlReg_o[15:8] <= Data_i[15:8];
+							end
+							SPI_3_CLK_ADDR : begin 
+								Spi3ClkReg_o[15:8] <= Data_i[15:8];
+							end
+							SPI_3_CS_DELAY_ADDR : begin 
+								Spi3CsDelayReg_o[15:8] <= Data_i[15:8];
+							end
+							SPI_3_CS_CTRL_ADDR : begin 
+								Spi3CsCtrlReg_o[15:8] <= Data_i[15:8];
+							end
+							SPI_3_TX_FIFO_CTRL_ADDR_LSB : begin 
+								Spi3TxFifoCtrlReg_o[15:8] <= Data_i[15:8];
+							end
+							SPI_3_RX_FIFO_CTRL_ADDR_LSB : begin 
+								Spi3RxFifoCtrlReg_o[15:8] <= Data_i[15:8];
+							end
+							SPI_4_CTRL_ADDR : begin 
+								Spi4CtrlReg_o[15:8] <= Data_i[15:8];
+							end
+							SPI_4_CLK_ADDR : begin 
+								Spi4ClkReg_o[15:8] <= Data_i[15:8];
+							end
+							SPI_4_CS_DELAY_ADDR : begin 
+								Spi4CsDelayReg_o[15:8] <= Data_i[15:8];
+							end
+							SPI_4_CS_CTRL_ADDR : begin 
+								Spi4CsCtrlReg_o[15:8] <= Data_i[15:8];
+							end
+							SPI_4_TX_FIFO_CTRL_ADDR_LSB : begin 
+								Spi4TxFifoCtrlReg_o[15:8] <= Data_i[15:8];
+							end
+							SPI_4_RX_FIFO_CTRL_ADDR_LSB : begin 
+								Spi4RxFifoCtrlReg_o[15:8] <= Data_i[15:8];
+							end
+							SPI_5_CTRL_ADDR : begin 
+								Spi5CtrlReg_o[15:8] <= Data_i[15:8];
+							end
+							SPI_5_CLK_ADDR : begin 
+								Spi5ClkReg_o[15:8] <= Data_i[15:8];
+							end
+							SPI_5_CS_DELAY_ADDR : begin 
+								Spi5CsDelayReg_o[15:8] <= Data_i[15:8];
+							end
+							SPI_5_CS_CTRL_ADDR : begin 
+								Spi5CsCtrlReg_o[15:8] <= Data_i[15:8];
+							end
+							SPI_5_TX_FIFO_CTRL_ADDR_LSB : begin 
+								Spi5TxFifoCtrlReg_o[15:8] <= Data_i[15:8];
+							end
+							SPI_5_RX_FIFO_CTRL_ADDR_LSB : begin 
+								Spi5RxFifoCtrlReg_o[15:8] <= Data_i[15:8];
+							end
+							SPI_6_CTRL_ADDR : begin 
+								Spi6CtrlReg_o[15:8] <= Data_i[15:8];
+							end
+							SPI_6_CLK_ADDR : begin 
+								Spi6ClkReg_o[15:8] <= Data_i[15:8];
+							end
+							SPI_6_CS_DELAY_ADDR : begin 
+								Spi6CsDelayReg_o[15:8] <= Data_i[15:8];
+							end
+							SPI_6_CS_CTRL_ADDR : begin 
+								Spi6CsCtrlReg_o[15:8] <= Data_i[15:8];
+							end
+							SPI_6_TX_FIFO_CTRL_ADDR_LSB : begin 
+								Spi6TxFifoCtrlReg_o[15:8] <= Data_i[15:8];
+							end
+							SPI_6_RX_FIFO_CTRL_ADDR_LSB : begin 
+								Spi6RxFifoCtrlReg_o[15:8] <= Data_i[15:8];
+							end
+							SPI_TX_RX_EN : begin 
+								spiTxRxEnReg[15:8] <= Data_i[15:8];
+							end
+							GPIO_CTRL_ADDR : begin 
+								GPIOAReg[15:8] <= Data_i[15:8];
+							end
+							GPIO_CTRL_ADDR_S : begin 
+								GPIOARegS[15:8] <= Data_i[15:8];
+							end
+							DEBUG_0_ADDR : begin 
+								ledReg[15:8] <= Data_i[15:8];
+							end
+						endcase 
+					end
+					2 : begin 
+						case (Addr_i) 
+							SPI_0_CTRL_ADDR : begin 
+								Spi0CtrlReg_o[7:0] <= Data_i[7:0];
+							end
+							SPI_0_CLK_ADDR : begin 
+								Spi0ClkReg_o[7:0] <= Data_i[7:0];
+							end
+							SPI_0_CS_DELAY_ADDR : begin 
+								Spi0CsDelayReg_o[7:0] <= Data_i[7:0];
+							end
+							SPI_0_CS_CTRL_ADDR : begin 
+								Spi0CsCtrlReg_o[7:0] <= Data_i[7:0];
+							end
+							SPI_0_TX_FIFO_CTRL_ADDR_LSB : begin 
+								Spi0TxFifoCtrlReg_o[7:0] <= Data_i[7:0];
+							end
+							SPI_0_RX_FIFO_CTRL_ADDR_LSB : begin 
+								Spi0RxFifoCtrlReg_o[7:0] <= Data_i[7:0];
+							end
+							SPI_1_CTRL_ADDR : begin 
+								Spi1CtrlReg_o[7:0] <= Data_i[7:0];
+							end
+							SPI_1_CLK_ADDR : begin 
+								Spi1ClkReg_o[7:0] <= Data_i[7:0];
+							end
+							SPI_1_CS_DELAY_ADDR : begin 
+								Spi1CsDelayReg_o[7:0] <= Data_i[7:0];
+							end
+							SPI_1_CS_CTRL_ADDR : begin 
+								Spi1CsCtrlReg_o[7:0] <= Data_i[7:0];
+							end
+							SPI_1_TX_FIFO_CTRL_ADDR_LSB : begin 
+								Spi1TxFifoCtrlReg_o[7:0] <= Data_i[7:0];
+							end
+							SPI_1_RX_FIFO_CTRL_ADDR_LSB : begin 
+								Spi1RxFifoCtrlReg_o[7:0] <= Data_i[7:0];
+							end
+							SPI_2_CTRL_ADDR : begin 
+								Spi2CtrlReg_o[7:0] <= Data_i[7:0];
+							end
+							SPI_2_CLK_ADDR : begin 
+								Spi2ClkReg_o[7:0] <= Data_i[7:0];
+							end
+							SPI_2_CS_DELAY_ADDR : begin 
+								Spi2CsDelayReg_o[7:0] <= Data_i[7:0];
+							end
+							SPI_2_CS_CTRL_ADDR : begin 
+								Spi2CsCtrlReg_o[7:0] <= Data_i[7:0];
+							end
+							SPI_2_TX_FIFO_CTRL_ADDR_LSB : begin 
+								Spi2TxFifoCtrlReg_o[7:0] <= Data_i[7:0];
+							end
+							SPI_2_RX_FIFO_CTRL_ADDR_LSB : begin 
+								Spi2RxFifoCtrlReg_o[7:0] <= Data_i[7:0];
+							end
+							SPI_3_CTRL_ADDR : begin 
+								Spi3CtrlReg_o[7:0] <= Data_i[7:0];
+							end
+							SPI_3_CLK_ADDR : begin 
+								Spi3ClkReg_o[7:0] <= Data_i[7:0];
+							end
+							SPI_3_CS_DELAY_ADDR : begin 
+								Spi3CsDelayReg_o[7:0] <= Data_i[7:0];
+							end
+							SPI_3_CS_CTRL_ADDR : begin 
+								Spi3CsCtrlReg_o[7:0] <= Data_i[7:0];
+							end
+							SPI_3_TX_FIFO_CTRL_ADDR_LSB : begin 
+								Spi3TxFifoCtrlReg_o[7:0] <= Data_i[7:0];
+							end
+							SPI_3_RX_FIFO_CTRL_ADDR_LSB : begin 
+								Spi3RxFifoCtrlReg_o[7:0] <= Data_i[7:0];
+							end
+							SPI_4_CTRL_ADDR : begin 
+								Spi4CtrlReg_o[7:0] <= Data_i[7:0];
+							end
+							SPI_4_CLK_ADDR : begin 
+								Spi4ClkReg_o[7:0] <= Data_i[7:0];
+							end
+							SPI_4_CS_DELAY_ADDR : begin 
+								Spi4CsDelayReg_o[7:0] <= Data_i[7:0];
+							end
+							SPI_4_CS_CTRL_ADDR : begin 
+								Spi4CsCtrlReg_o[7:0] <= Data_i[7:0];
+							end
+							SPI_4_TX_FIFO_CTRL_ADDR_LSB : begin 
+								Spi4TxFifoCtrlReg_o[7:0] <= Data_i[7:0];
+							end
+							SPI_4_RX_FIFO_CTRL_ADDR_LSB : begin 
+								Spi4RxFifoCtrlReg_o[7:0] <= Data_i[7:0];
+							end
+							SPI_5_CTRL_ADDR : begin 
+								Spi5CtrlReg_o[7:0] <= Data_i[7:0];
+							end
+							SPI_5_CLK_ADDR : begin 
+								Spi5ClkReg_o[7:0] <= Data_i[7:0];
+							end
+							SPI_5_CS_DELAY_ADDR : begin 
+								Spi5CsDelayReg_o[7:0] <= Data_i[7:0];
+							end
+							SPI_5_CS_CTRL_ADDR : begin 
+								Spi5CsCtrlReg_o[7:0] <= Data_i[7:0];
+							end
+							SPI_5_TX_FIFO_CTRL_ADDR_LSB : begin 
+								Spi5TxFifoCtrlReg_o[7:0] <= Data_i[7:0];
+							end
+							SPI_5_RX_FIFO_CTRL_ADDR_LSB : begin 
+								Spi5RxFifoCtrlReg_o[7:0] <= Data_i[7:0];
+							end
+							SPI_6_CTRL_ADDR : begin 
+								Spi6CtrlReg_o[7:0] <= Data_i[7:0];
+							end
+							SPI_6_CLK_ADDR : begin 
+								Spi6ClkReg_o[7:0] <= Data_i[7:0];
+							end
+							SPI_6_CS_DELAY_ADDR : begin 
+								Spi6CsDelayReg_o[7:0] <= Data_i[7:0];
+							end
+							SPI_6_CS_CTRL_ADDR : begin 
+								Spi6CsCtrlReg_o[7:0] <= Data_i[7:0];
+							end
+							SPI_6_TX_FIFO_CTRL_ADDR_LSB : begin 
+								Spi6TxFifoCtrlReg_o[7:0] <= Data_i[7:0];
+							end
+							SPI_6_RX_FIFO_CTRL_ADDR_LSB : begin 
+								Spi6RxFifoCtrlReg_o[7:0] <= Data_i[7:0];
+							end
+							SPI_TX_RX_EN : begin 
+								spiTxRxEnReg[7:0] <= Data_i[7:0];
+							end
+							GPIO_CTRL_ADDR : begin 
+								GPIOAReg[7:0] <= Data_i[7:0];
+							end
+							GPIO_CTRL_ADDR_S : begin 
+								GPIOARegS[7:0] <= Data_i[7:0];
+							end
+							DEBUG_0_ADDR : begin 
+								ledReg[7:0] <= Data_i[7:0];
+							end
+						endcase
+					end
+				endcase
+			end
+		end
+	end
+	
+	always @(*) begin 
+		if (Rst_i) begin 
+			ansReg = 0;
+		end	else begin
+			case (Addr_i)
+				SPI_0_CTRL_ADDR : begin 
+					ansReg = Spi0CtrlReg_o;
+				end
+				SPI_0_CLK_ADDR : begin 
+					ansReg = Spi0ClkReg_o;
+				end
+				SPI_0_CS_DELAY_ADDR : begin 
+					ansReg = Spi0CsDelayReg_o;
+				end
+				SPI_0_CS_CTRL_ADDR : begin 
+					ansReg = Spi0CsCtrlReg_o;
+				end
+				SPI_0_TX_FIFO_CTRL_ADDR_LSB : begin 
+					ansReg = TxFifoCtrlReg0_i[15:0];
+				end
+				SPI_0_TX_FIFO_CTRL_ADDR_MSB : begin 
+					ansReg = TxFifoCtrlReg0_i[31:16];
+				end
+				SPI_0_RX_FIFO_CTRL_ADDR_LSB : begin 
+					ansReg = RxFifoCtrlReg0_i[15:0];
+				end
+				SPI_0_RX_FIFO_CTRL_ADDR_MSB : begin 
+					ansReg = RxFifoCtrlReg0_i[31:16];
+				end
+				SPI_1_CTRL_ADDR : begin 
+					ansReg = Spi1CtrlReg_o;
+				end
+				SPI_1_CLK_ADDR : begin 
+					ansReg = Spi1ClkReg_o;
+				end
+				SPI_1_CS_DELAY_ADDR : begin 
+					ansReg = Spi1CsDelayReg_o;
+				end
+				SPI_1_CS_CTRL_ADDR : begin 
+					ansReg = Spi1CsCtrlReg_o;
+				end
+				SPI_1_TX_FIFO_CTRL_ADDR_LSB : begin 
+					ansReg = TxFifoCtrlReg1_i[15:0];
+				end
+				SPI_1_TX_FIFO_CTRL_ADDR_MSB : begin 
+					ansReg = TxFifoCtrlReg1_i[31:16];
+				end
+				SPI_1_RX_FIFO_CTRL_ADDR_LSB : begin 
+					ansReg = RxFifoCtrlReg1_i[15:0];
+				end
+				SPI_1_RX_FIFO_CTRL_ADDR_MSB : begin 
+					ansReg = RxFifoCtrlReg1_i[31:16];
+				end
+				SPI_2_CTRL_ADDR : begin 
+					ansReg = Spi2CtrlReg_o;
+				end
+				SPI_2_CLK_ADDR : begin 
+					ansReg = Spi2ClkReg_o;
+				end
+				SPI_2_CS_DELAY_ADDR : begin 
+					ansReg = Spi2CsDelayReg_o;
+				end
+				SPI_2_CS_CTRL_ADDR : begin 
+					ansReg = Spi2CsCtrlReg_o;
+				end
+				SPI_2_TX_FIFO_CTRL_ADDR_LSB : begin 
+					ansReg = TxFifoCtrlReg2_i[15:0];
+				end
+				SPI_2_TX_FIFO_CTRL_ADDR_MSB : begin 
+					ansReg = TxFifoCtrlReg2_i[31:16];
+				end
+				SPI_2_RX_FIFO_CTRL_ADDR_LSB : begin 
+					ansReg = RxFifoCtrlReg2_i[15:0];
+				end
+				SPI_2_RX_FIFO_CTRL_ADDR_MSB : begin 
+					ansReg = RxFifoCtrlReg2_i[31:16];
+				end
+				SPI_3_CTRL_ADDR : begin 
+					ansReg = Spi3CtrlReg_o;
+				end
+				SPI_3_CLK_ADDR : begin 
+					ansReg = Spi3ClkReg_o;
+				end
+				SPI_3_CS_DELAY_ADDR : begin 
+					ansReg = Spi3CsDelayReg_o;
+				end
+				SPI_3_CS_CTRL_ADDR : begin 
+					ansReg = Spi3CsCtrlReg_o;
+				end
+				SPI_3_TX_FIFO_CTRL_ADDR_LSB : begin 
+					ansReg = TxFifoCtrlReg3_i[15:0];
+				end
+				SPI_3_TX_FIFO_CTRL_ADDR_MSB : begin 
+					ansReg = TxFifoCtrlReg3_i[31:16];
+				end
+				SPI_3_RX_FIFO_CTRL_ADDR_LSB : begin 
+					ansReg = RxFifoCtrlReg3_i[15:0];
+				end
+				SPI_3_RX_FIFO_CTRL_ADDR_MSB : begin 
+					ansReg = RxFifoCtrlReg3_i[31:16];
+				end
+				SPI_4_CTRL_ADDR : begin 
+					ansReg = Spi4CtrlReg_o;
+				end
+				SPI_4_CLK_ADDR : begin 
+					ansReg = Spi4ClkReg_o;
+				end
+				SPI_4_CS_DELAY_ADDR : begin 
+					ansReg = Spi4CsDelayReg_o;
+				end
+				SPI_4_CS_CTRL_ADDR : begin 
+					ansReg = Spi4CsCtrlReg_o;
+				end
+				SPI_4_TX_FIFO_CTRL_ADDR_LSB : begin 
+					ansReg = TxFifoCtrlReg4_i[15:0];
+				end
+				SPI_4_TX_FIFO_CTRL_ADDR_MSB : begin 
+					ansReg = TxFifoCtrlReg4_i[31:16];
+				end
+				SPI_4_RX_FIFO_CTRL_ADDR_LSB : begin 
+					ansReg = RxFifoCtrlReg4_i[15:0];
+				end
+				SPI_4_RX_FIFO_CTRL_ADDR_MSB : begin 
+					ansReg = RxFifoCtrlReg4_i[31:16];
+				end
+				SPI_5_CTRL_ADDR : begin 
+					ansReg = Spi5CtrlReg_o;
+				end
+				SPI_5_CLK_ADDR : begin 
+					ansReg = Spi5ClkReg_o;
+				end
+				SPI_5_CS_DELAY_ADDR : begin 
+					ansReg = Spi5CsDelayReg_o;
+				end
+				SPI_5_CS_CTRL_ADDR : begin 
+					ansReg = Spi5CsCtrlReg_o;
+				end
+				SPI_5_TX_FIFO_CTRL_ADDR_LSB : begin 
+					ansReg = TxFifoCtrlReg5_i[15:0];
+				end
+				SPI_5_TX_FIFO_CTRL_ADDR_MSB : begin 
+					ansReg = TxFifoCtrlReg5_i[31:16];
+				end
+				SPI_5_RX_FIFO_CTRL_ADDR_LSB : begin 
+					ansReg = RxFifoCtrlReg5_i[15:0];
+				end
+				SPI_5_RX_FIFO_CTRL_ADDR_MSB : begin 
+					ansReg = RxFifoCtrlReg5_i[31:16];
+				end
+				SPI_6_CTRL_ADDR : begin 
+					ansReg = Spi6CtrlReg_o;
+				end
+				SPI_6_CLK_ADDR : begin 
+					ansReg = Spi6ClkReg_o;
+				end
+				SPI_6_CS_DELAY_ADDR : begin 
+					ansReg = Spi6CsDelayReg_o;
+				end
+				SPI_6_CS_CTRL_ADDR : begin 
+					ansReg = Spi6CsCtrlReg_o;
+				end
+				SPI_6_TX_FIFO_CTRL_ADDR_LSB : begin 
+					ansReg = TxFifoCtrlReg6_i[15:0];
+				end
+				SPI_6_TX_FIFO_CTRL_ADDR_MSB : begin 
+					ansReg = TxFifoCtrlReg6_i[31:16];
+				end
+				SPI_6_RX_FIFO_CTRL_ADDR_LSB : begin 
+					ansReg = RxFifoCtrlReg6_i[15:0];
+				end
+				SPI_6_RX_FIFO_CTRL_ADDR_MSB : begin 
+					ansReg = RxFifoCtrlReg6_i[31:16];
+				end
+				SPI_TX_RX_EN : begin 
+					ansReg = spiTxRxEnReg;
+				end
+				GPIO_CTRL_ADDR : begin 
+					ansReg = GPIOAReg;
+				end
+				GPIO_CTRL_ADDR_S : begin 
+					ansReg = {9'd0,LdReg_i};
+				end
+				DEBUG_0_ADDR : begin 
+					ansReg = ledReg;
+				end
+				default : begin 
+					ansReg = 0;
+				end
+			endcase
+		end
+	end
+
+endmodule

src/scr/SmcInDataMux/SmcInDataMux.v

@@ -0,0 +1,166 @@
+module SmcInDataMux 
+#(
+	parameter	CMD_REG_WIDTH	=	16,
+	parameter	ADDR_REG_WIDTH	=	12,
+	
+	parameter	FIFO_NUM	=	7,
+	
+	parameter	FIFO_0_WRITE_LSB_ADDR	=	12'h0+12'd24,
+	parameter	FIFO_0_WRITE_MSB_ADDR	=	12'h0+12'd26,
+	parameter	FIFO_1_WRITE_LSB_ADDR	=	12'h50+12'd24,
+	parameter	FIFO_1_WRITE_MSB_ADDR	=	12'h50+12'd26,
+	parameter	FIFO_2_WRITE_LSB_ADDR	=	12'hf0+12'd24,
+	parameter	FIFO_2_WRITE_MSB_ADDR	=	12'hf0+12'd26,
+	parameter	FIFO_3_WRITE_LSB_ADDR	=	12'h140+12'd24,
+	parameter	FIFO_3_WRITE_MSB_ADDR	=	12'h140+12'd26,
+	parameter	FIFO_4_WRITE_LSB_ADDR	=	12'h190+12'd24,
+	parameter	FIFO_4_WRITE_MSB_ADDR	=	12'h190+12'd26,
+	parameter	FIFO_5_WRITE_LSB_ADDR	=	12'h1e0+12'd24,
+	parameter	FIFO_5_WRITE_MSB_ADDR	=	12'h1e0+12'd26,
+	parameter	FIFO_6_WRITE_LSB_ADDR	=	12'h230+12'd24,
+	parameter	FIFO_6_WRITE_MSB_ADDR	=	12'h230+12'd26,
+
+	parameter	FIFO_0_READ_LSB_ADDR	=	12'h0+12'd28,
+	parameter	FIFO_0_READ_MSB_ADDR	=	12'h0+12'd30,
+	parameter	FIFO_1_READ_LSB_ADDR	=	12'h50+12'd28,
+	parameter	FIFO_1_READ_MSB_ADDR	=	12'h50+12'd30,
+	parameter	FIFO_2_READ_LSB_ADDR	=	12'hf0+12'd28,
+	parameter	FIFO_2_READ_MSB_ADDR	=	12'hf0+12'd30,
+	parameter	FIFO_3_READ_LSB_ADDR	=	12'h140+12'd28,
+	parameter	FIFO_3_READ_MSB_ADDR	=	12'h140+12'd30,
+	parameter	FIFO_4_READ_LSB_ADDR	=	12'h190+12'd28,
+	parameter	FIFO_4_READ_MSB_ADDR	=	12'h190+12'd30,
+	parameter	FIFO_5_READ_LSB_ADDR	=	12'h1e0+12'd28,
+	parameter	FIFO_5_READ_MSB_ADDR	=	12'h1e0+12'd30,
+	parameter	FIFO_6_READ_LSB_ADDR	=	12'h230+12'd28,
+	parameter	FIFO_6_READ_MSB_ADDR	=	12'h230+12'd30
+)
+(
+	input	Clk_i,
+	input	Rst_i,
+
+	input	SmcVal_i,
+	input	[CMD_REG_WIDTH-1:0]		SmcData_i,
+	input	[ADDR_REG_WIDTH-1:0]	SmcAddr_i,
+
+	output	RequestToFifo_o,
+
+	output	reg	ToRegMapVal_o,
+	output	reg	[CMD_REG_WIDTH-1:0]		ToRegMapData_o,
+	output	reg	[ADDR_REG_WIDTH-1:0]	ToRegMapAddr_o,
+	
+	output	reg	[FIFO_NUM-1:0]	ToFifoVal_o,
+	output	reg	[CMD_REG_WIDTH*2*FIFO_NUM-1:0]	ToFifoData_o
+);
+
+//================================================================================
+//	REG/WIRE
+//================================================================================
+	wire	requestToFifo0	=((SmcAddr_i==FIFO_0_WRITE_LSB_ADDR||SmcAddr_i==FIFO_0_WRITE_MSB_ADDR)|| (SmcAddr_i==FIFO_0_READ_LSB_ADDR||SmcAddr_i==FIFO_0_READ_MSB_ADDR));
+	wire	requestToFifo1	=((SmcAddr_i==FIFO_1_WRITE_LSB_ADDR||SmcAddr_i==FIFO_1_WRITE_MSB_ADDR)|| (SmcAddr_i==FIFO_1_READ_LSB_ADDR||SmcAddr_i==FIFO_1_READ_MSB_ADDR));
+	wire	requestToFifo2	=((SmcAddr_i==FIFO_2_WRITE_LSB_ADDR||SmcAddr_i==FIFO_2_WRITE_MSB_ADDR)|| (SmcAddr_i==FIFO_2_READ_LSB_ADDR||SmcAddr_i==FIFO_2_READ_MSB_ADDR));
+	wire	requestToFifo3	=((SmcAddr_i==FIFO_3_WRITE_LSB_ADDR||SmcAddr_i==FIFO_3_WRITE_MSB_ADDR)|| (SmcAddr_i==FIFO_3_READ_LSB_ADDR||SmcAddr_i==FIFO_3_READ_MSB_ADDR));
+	wire	requestToFifo4	=((SmcAddr_i==FIFO_4_WRITE_LSB_ADDR||SmcAddr_i==FIFO_4_WRITE_MSB_ADDR)|| (SmcAddr_i==FIFO_4_READ_LSB_ADDR||SmcAddr_i==FIFO_4_READ_MSB_ADDR));
+	wire	requestToFifo5	=((SmcAddr_i==FIFO_5_WRITE_LSB_ADDR||SmcAddr_i==FIFO_5_WRITE_MSB_ADDR)|| (SmcAddr_i==FIFO_5_READ_LSB_ADDR||SmcAddr_i==FIFO_5_READ_MSB_ADDR));
+	wire	requestToFifo6	=((SmcAddr_i==FIFO_6_WRITE_LSB_ADDR||SmcAddr_i==FIFO_6_WRITE_MSB_ADDR)|| (SmcAddr_i==FIFO_6_READ_LSB_ADDR||SmcAddr_i==FIFO_6_READ_MSB_ADDR));
+	
+	wire	requestToFifo	=	(requestToFifo0|requestToFifo1|requestToFifo2|requestToFifo3|requestToFifo4|requestToFifo5|requestToFifo6);
+
+//================================================================================
+//	ASSIGNMENTS
+//================================================================================
+	assign	RequestToFifo_o	=	requestToFifo;
+
+//================================================================================
+//	LOCALPARAMS
+//================================================================================
+
+//================================================================================
+//	CODING
+//================================================================================
+	always	@(posedge	Clk_i	or	posedge	Rst_i)	begin
+		if	(Rst_i)	begin
+			ToRegMapVal_o	<=	1'b0;
+			ToRegMapData_o	<=	16'h0;
+			ToRegMapAddr_o	<=	12'h0;
+			
+			ToFifoVal_o		<=	7'h0;
+			ToFifoData_o	<=	0;
+		end	else	begin
+			if	(requestToFifo)	begin	
+				case(SmcAddr_i)	
+					FIFO_0_WRITE_LSB_ADDR:	begin
+										ToFifoVal_o[0]	<=	1'b0;
+										ToFifoData_o[CMD_REG_WIDTH*0+:CMD_REG_WIDTH]	<=	SmcData_i;
+									end
+					FIFO_0_WRITE_MSB_ADDR:	begin
+										ToFifoVal_o[0]	<=	SmcVal_i;
+										ToFifoData_o[CMD_REG_WIDTH*1+:CMD_REG_WIDTH]	<=	SmcData_i;
+									end
+									
+					FIFO_1_WRITE_LSB_ADDR:	begin
+										ToFifoVal_o[1]	<=	1'b0;
+										ToFifoData_o[CMD_REG_WIDTH*2+:CMD_REG_WIDTH]	<=	SmcData_i;
+									end
+					FIFO_1_WRITE_MSB_ADDR:	begin
+										ToFifoVal_o[1]	<=	SmcVal_i;
+										ToFifoData_o[CMD_REG_WIDTH*3+:CMD_REG_WIDTH]	<=	SmcData_i;
+									end
+									
+					FIFO_2_WRITE_LSB_ADDR:	begin
+										ToFifoVal_o[2]	<=	1'b0;
+										ToFifoData_o[CMD_REG_WIDTH*4+:CMD_REG_WIDTH]	<=	SmcData_i;
+									end
+					FIFO_2_WRITE_MSB_ADDR:	begin
+										ToFifoVal_o[2]	<=	SmcVal_i;
+										ToFifoData_o[CMD_REG_WIDTH*5+:CMD_REG_WIDTH]	<=	SmcData_i;
+									end
+									
+					FIFO_3_WRITE_LSB_ADDR:	begin
+										ToFifoVal_o[3]	<=	1'b0;
+										ToFifoData_o[CMD_REG_WIDTH*6+:CMD_REG_WIDTH]	<=	SmcData_i;
+									end
+					FIFO_3_WRITE_MSB_ADDR:	begin
+										ToFifoVal_o[3]	<=	SmcVal_i;
+										ToFifoData_o[CMD_REG_WIDTH*7+:CMD_REG_WIDTH]	<=	SmcData_i;
+									end
+									
+					FIFO_4_WRITE_LSB_ADDR:	begin
+										ToFifoVal_o[4]	<=	1'b0;
+										ToFifoData_o[CMD_REG_WIDTH*8+:CMD_REG_WIDTH]	<=	SmcData_i;
+									end
+					FIFO_4_WRITE_MSB_ADDR:	begin
+										ToFifoVal_o[4]	<=	SmcVal_i;
+										ToFifoData_o[CMD_REG_WIDTH*9+:CMD_REG_WIDTH]	<=	SmcData_i;
+									end
+									
+					FIFO_5_WRITE_LSB_ADDR:	begin
+										ToFifoVal_o[5]	<=	1'b0;
+										ToFifoData_o[CMD_REG_WIDTH*10+:CMD_REG_WIDTH]	<=	SmcData_i;
+									end
+					FIFO_5_WRITE_MSB_ADDR:	begin
+										ToFifoVal_o[5]	<=	SmcVal_i;
+										ToFifoData_o[CMD_REG_WIDTH*11+:CMD_REG_WIDTH]	<=	SmcData_i;
+									end
+									
+					FIFO_6_WRITE_LSB_ADDR:	begin
+										ToFifoVal_o[6]	<=	1'b0;
+										ToFifoData_o[CMD_REG_WIDTH*12+:CMD_REG_WIDTH]	<=	SmcData_i;
+									end
+					FIFO_6_WRITE_MSB_ADDR:	begin
+										ToFifoVal_o[6]	<=	SmcVal_i;
+										ToFifoData_o[CMD_REG_WIDTH*13+:CMD_REG_WIDTH]	<=	SmcData_i;
+									end
+				endcase
+				ToRegMapAddr_o	<=	0;
+				ToRegMapVal_o	<=	0;
+			end	else	begin
+				ToRegMapVal_o	<=	SmcVal_i;
+				ToFifoVal_o		<=	7'h0;
+				ToRegMapData_o	<=	SmcData_i;
+				ToRegMapAddr_o	<=	SmcAddr_i;
+				ToFifoData_o	<=	0;
+			end
+		end
+	end
+endmodule

src/scr/Top/S5443_3Top.v

@@ -0,0 +1,182 @@
+module S5443_3Top
+#(
+	parameter CMD_REG_WIDTH = 32,
+	parameter ADDR_REG_WIDTH = 12,
+	parameter STAGES = 3,
+	parameter SPI_NUM = 7
+)
+(
+	input Clk123_i,
+	input [ADDR_REG_WIDTH-2:0] SmcAddr_i,
+	inout [CMD_REG_WIDTH/2-1:0] SmcData_io,
+	
+	input SmcAwe_i,
+	input SmcAmsN_i,
+	
+	input SmcAre_i,
+	input [1:0] SmcBe_i,
+	input SmcAoe_i,
+	input [SPI_NUM-1:0] Ld_i,
+
+	output  Led_o,
+   
+	output  [SPI_NUM-1:0] Mosi0_o, 
+	inout   [SPI_NUM-1:0] Mosi1_io, //inout: when RSPI mode, input; when QSPI mode output; 
+	output  [SPI_NUM-1:0] Mosi2_o,
+	output  [SPI_NUM-1:0] Mosi3_o,
+	output  [SPI_NUM-1:0] Ss_o,
+	output  [SPI_NUM-1:0] SsFlash_o,
+	output  [SPI_NUM-1:0] Sck_o,
+	output  [SPI_NUM-1:0] SpiRst_o,
+	output  [SPI_NUM-1:0] SpiDir_o,
+	output  LD_o
+);
+
+//================================================================================
+//  REG/WIRE
+//================================================================================
+wire gclk;
+wire initRst;
+
+wire [ADDR_REG_WIDTH-1:0] addrExt;
+
+wire smcValComb;
+wire requestToFifo;
+
+wire toRegMapVal;
+wire [CMD_REG_WIDTH/2-1:0]	toRegMapData;
+wire [ADDR_REG_WIDTH-1:0]	toRegMapAddr;
+wire [SPI_NUM-1:0]	toFifoVal;
+wire [CMD_REG_WIDTH*SPI_NUM-1:0]	toFifoData;
+
+wire [CMD_REG_WIDTH-1:0] spi0Ctrl;
+
+//================================================================================
+//  ASSIGNMENTS
+//================================================================================
+assign addrExt = {SmcAddr_i, 1'b0};
+assign smcValComb = (!SmcAmsN_i && !SmcAwe_i) ? 1'b1 : 1'b0;
+
+assign Led_o = |spi0Ctrl;
+
+//================================================================================
+//  CODING
+//================================================================================	
+	BUFG BUFG_inst (
+		.O	(gclk),		// 1-bit output: Clock output
+		.I	(Clk123_i)	// 1-bit input: Clock input
+	);
+
+	SmcInDataMux SmcInDataMux
+	(
+		.Clk_i				(gclk),
+		.Rst_i				(initRst),
+	
+		.SmcVal_i			(smcValComb),
+		.SmcData_i			(SmcData_io),
+		.SmcAddr_i			(addrExt),
+
+		.RequestToFifo_o	(requestToFifo),
+		.ToRegMapVal_o		(toRegMapVal),
+		.ToRegMapData_o		(toRegMapData),
+		.ToRegMapAddr_o		(toRegMapAddr),
+	
+		.ToFifoVal_o		(toFifoVal),
+		.ToFifoData_o		(toFifoData)
+	);
+
+	RegMap 
+	#(
+		.CMD_REG_WIDTH(32),
+		.ADDR_REG_WIDTH(12)
+	)
+	RegMap_inst 
+	(
+		.Clk_i				(gclk),
+		.Rst_i				(initRst),
+		.Data_i				(toRegMapData),
+		.Addr_i				(toRegMapAddr),
+		.Val_i				(toRegMapVal),
+		.SmcBe_i			(SmcBe_i),
+
+		.TxFifoCtrlReg0_i		(spi0TxFifoCtrlReg),
+		.TxFifoCtrlReg1_i		(spi1TxFifoCtrlReg),
+		.TxFifoCtrlReg2_i		(spi2TxFifoCtrlReg),
+		.TxFifoCtrlReg3_i		(spi3TxFifoCtrlReg),
+		.TxFifoCtrlReg4_i		(spi4TxFifoCtrlReg),
+		.TxFifoCtrlReg5_i		(spi5TxFifoCtrlReg),
+		.TxFifoCtrlReg6_i		(spi6TxFifoCtrlReg),
+		.RxFifoCtrlReg0_i		(spi0RxFifoCtrlReg),
+		.RxFifoCtrlReg1_i		(spi1RxFifoCtrlReg),
+		.RxFifoCtrlReg2_i		(spi2RxFifoCtrlReg),
+		.RxFifoCtrlReg3_i		(spi3RxFifoCtrlReg),
+		.RxFifoCtrlReg4_i		(spi4RxFifoCtrlReg),
+		.RxFifoCtrlReg5_i		(spi5RxFifoCtrlReg),
+		.RxFifoCtrlReg6_i		(spi6RxFifoCtrlReg),
+
+		.LdReg_i				(ldReg),
+
+		//Spi0
+		.Spi0CtrlReg_o			(spi0Ctrl),
+		.Spi0ClkReg_o			(spi0Clk),
+		.Spi0CsDelayReg_o		(spi0CsDelay),
+		.Spi0CsCtrlReg_o		(spi0CsCtrl),
+		.Spi0TxFifoCtrlReg_o	(spi0TxFifoCtrl),
+		.Spi0RxFifoCtrlReg_o	(spi0RxFifoCtrl),
+		//Spi1
+		.Spi1CtrlReg_o			(spi1Ctrl),
+		.Spi1ClkReg_o			(spi1Clk),
+		.Spi1CsDelayReg_o		(spi1CsDelay),
+		.Spi1CsCtrlReg_o		(spi1CsCtrl),
+		.Spi1TxFifoCtrlReg_o	(spi1TxFifoCtrl),
+		.Spi1RxFifoCtrlReg_o	(spi1RxFifoCtrl),
+		//Spi2
+		.Spi2CtrlReg_o			(spi2Ctrl),
+		.Spi2ClkReg_o			(spi2Clk),
+		.Spi2CsDelayReg_o		(spi2CsDelay),
+		.Spi2CsCtrlReg_o		(spi2CsCtrl),
+		.Spi2TxFifoCtrlReg_o	(spi2TxFifoCtrl),
+		.Spi2RxFifoCtrlReg_o	(spi2RxFifoCtrl),
+		//Spi3
+		.Spi3CtrlReg_o			(spi3Ctrl),
+		.Spi3ClkReg_o			(spi3Clk),
+		.Spi3CsDelayReg_o		(spi3CsDelay),
+		.Spi3CsCtrlReg_o		(spi3CsCtrl),
+		.Spi3TxFifoCtrlReg_o	(spi3TxFifoCtrl),
+		.Spi3RxFifoCtrlReg_o	(spi3RxFifoCtrl),
+		//Spi4
+		.Spi4CtrlReg_o			(spi4Ctrl),
+		.Spi4ClkReg_o			(spi4Clk),
+		.Spi4CsDelayReg_o		(spi4CsDelay),
+		.Spi4CsCtrlReg_o		(spi4CsCtrl),
+		.Spi4TxFifoCtrlReg_o	(spi4TxFifoCtrl),
+		.Spi4RxFifoCtrlReg_o	(spi4RxFifoCtrl),
+		//Spi5
+		.Spi5CtrlReg_o			(spi5Ctrl),
+		.Spi5ClkReg_o			(spi5Clk),
+		.Spi5CsDelayReg_o		(spi5CsDelay),
+		.Spi5CsCtrlReg_o		(spi5CsCtrl),
+		.Spi5TxFifoCtrlReg_o	(spi5TxFifoCtrl),
+		.Spi5RxFifoCtrlReg_o	(spi5RxFifoCtrl),
+		//Spi6
+		.Spi6CtrlReg_o			(spi6Ctrl),
+		.Spi6ClkReg_o			(spi6Clk),
+		.Spi6CsDelayReg_o		(spi6CsDelay),
+		.Spi6CsCtrlReg_o		(spi6CsCtrl),
+		.Spi6TxFifoCtrlReg_o	(spi6TxFifoCtrl),
+		.Spi6RxFifoCtrlReg_o	(spi6RxFifoCtrl),
+		.SpiTxRxEnReg_o			(spiTxRxEn),
+		.GPIOAReg_o				(GPIOA),
+
+		.Led_o					(Led_o),
+		.AnsDataReg_o			(ansData)
+
+	);
+
+	InitRst InitRst_inst
+	(
+		.clk_i		(gclk),
+		.signal_o	(initRst)
+	);
+
+endmodule

src/scr/Top/S5443_3_tb.v

@@ -0,0 +1,373 @@
+`timescale 1ns / 1ps
+module S5443_3_tb;
+
+parameter CLK_PERIOD = 8.13; // Clock period in ns
+
+
+
+
+reg Clk_i;
+reg Rst_i;
+reg [10:0] SmcAddr_i;
+reg [15:0]SmcData_i;
+reg SmcAre_i;
+reg SmcAwe_i;
+wire SmcAmsN_i;
+wire [1:0] SmcBe_i;
+reg SmcAoe_i;
+
+reg [31:0] tb_cnt;
+wire [15:0] smcData;
+reg mosi1reg;
+//***********************************************
+//	           SPI0 Adresses
+//***********************************************
+
+// Address map for SPI0
+localparam [10:0] BaseAddr0 = 11'h0;
+localparam [10:0] Spi0CtrlAddr = BaseAddr0;
+localparam [10:0] Spi0ClkAddr = (BaseAddr0 + 4)>>1;
+localparam [10:0] Spi0CsDelayAddr = (BaseAddr0 + 8)>>1;
+localparam [10:0] Spi0CsCtrlAddr = (BaseAddr0 + 12)>>1;
+localparam [10:0] Spi0TxFifoCtrlAddr = (BaseAddr0 + 16)>>1;
+localparam [10:0] Spi0RxFifoCtrlAddr = (BaseAddr0 + 20)>>1;
+localparam [10:0] Spi0TxFifoAddrL = (BaseAddr0 + 24)>>1;
+localparam [10:0] Spi0TxFifoAddrM = (BaseAddr0 + 26)>>1;
+localparam [10:0] Spi0RxFifoAddrL = (BaseAddr0 + 28)>>1;
+localparam [10:0] Spi0RxFifoAddrM = (BaseAddr0 + 30)>>1;
+
+// Data for SPI0CtrlReg 
+
+
+//***********************************************
+//	           SPI0 Ctrl Reg Data
+//***********************************************
+localparam SpiEn0 = 1'b1;//1 for enable, 0 for disable
+localparam ClockPhase0 = 1'b0;//
+localparam ClockPolarity0 = 1'b0;//0 for active high, 1 for active low
+localparam Assel0 = 1'b1;//0 for software control, 1 for hardware control
+localparam SelSt0 = 1'b1; //1 - assert slave select(low), 0 - deassert slave select(high)
+localparam Size0 = 2'd2; //0 - 8 bits, 1 - 16 bits, 2 - 24 bits, 3 - 32 bits
+localparam Mode0 = 1'b0; // 1 - 4 Mosi, 0 - 1 Mosi
+localparam LSBF0 = 1'b0; // 1 - LSB first, 0 - MSB first
+
+localparam [15:0] Spi0CtrlRegData = {8'h0,LSBF0, Mode0, Size0, SelSt0, Assel0, ClockPolarity0, ClockPhase0, SpiEn0};
+
+
+//***********************************************
+//	           SPI0 Clk Reg Data
+//***********************************************
+
+localparam Div = 4'd1; // Custom divider value(input clock frequency = 80 MHz)
+localparam Mux0 = 1'b1; // 0 - input clock, 1 - MMCM output clock
+localparam Mux1 = 3'd0; // MMCM output clock number
+
+localparam Spi0ClkRegData = {8'h0, Mux1, Mux0, Div};
+
+
+//***********************************************
+//	           SPI0 Cs Delay Reg Data
+//***********************************************
+localparam Lag0 = 1'b0; //Extended SPI clock lag control, 0 - Disable, 1 - Enable
+localparam Lead0 = 1'b0; //Extended SPI clock lead control, 0 - Disable, 1 - Enable
+localparam Stop0 = 6'd0; //Number of clock cycles to wait after CS is deasserted
+
+localparam [15:0] Spi0CsDelayRegData = {8'h0, Stop0, Lead0, Lag0};
+
+//***********************************************
+//	           SPI0 Cs Ctrl Reg Data
+//***********************************************
+localparam CS0 = 1'b1; // 1 - device selected, 0 - device deselected
+localparam CS1 = 1'b1; // 1 - device selected, 0 - device deselected
+
+localparam [15:0] Spi0CsCtrlRegData = {14'h0, CS1, CS0};
+
+//***********************************************
+//	           SPI0 Tx Fifo Ctrl Reg Data
+//***********************************************
+localparam RstTxFifo0 = 1'b1; // 1 - Reset Tx FIFO, 0 - Normal operation
+// at least 5 clock cycles of a slow clock
+
+localparam [15:0] Spi0TxFifoCtrlRegDataRstOn = {15'h0, RstTxFifo0};
+localparam [15:0] Spi0TxFifoCtrlRegDataRstOff = {15'h0, 1'b0};
+
+//***********************************************
+//	           SPI0 Rx Fifo Ctrl Reg Data
+//***********************************************
+localparam RstRxFifo0 = 1'b1; // 1 - Reset Rx FIFO, 0 - Normal operation
+
+localparam [15:0] Spi0RxFifoCtrlRegDataRstOn = {15'h0, RstRxFifo0};
+localparam [15:0] Spi0RxFifoCtrlRegDataRstOff = {15'h0, 1'b0};
+
+//***********************************************
+//	           SPITXRX Enable Register
+//***********************************************
+localparam SpiTxRxEn0 = 1'b1;
+localparam SpiTxRxEn1 = 1'b0;
+localparam SpiTxRxEn2 = 1'b0;
+localparam SpiTxRxEn3 = 1'b0;
+localparam SpiTxRxEn4 = 1'b0;
+localparam SpiTxRxEn5 = 1'b0;
+localparam SpiTxRxEn6 = 1'b0;
+
+localparam [15:0] SpiTxRxEnRegData = {8'h0, SpiTxRxEn6, SpiTxRxEn5, SpiTxRxEn4, SpiTxRxEn3, SpiTxRxEn2, SpiTxRxEn1, SpiTxRxEn0};
+
+
+
+//***********************************************
+//	           GPIO Reg Data
+//***********************************************
+localparam RstForSbTmsg = 1'b1; // 1 - Reset for SB TMSG, 0 - Normal operation
+
+
+localparam [15:0] GPIORegDataRstOn = {15'h0, RstForSbTmsg};
+localparam [15:0] GPIORegDataRstOff = {15'h0, 1'b0};
+
+
+//***********************************************
+//	           SPI1HEADERS
+//***********************************************
+localparam [10:0] BaseAddr1 = 11'h50;
+localparam [10:0] Spi1CtrlAddr = BaseAddr1;
+localparam [10:0] Spi1ClkAddr = BaseAddr1 + 4;
+localparam [10:0] Spi1CsDelayAddr = BaseAddr1 + 8;
+localparam [10:0] Spi1CsCtrlAddr = BaseAddr1 + 12;
+localparam [10:0] Spi1TxFifoCtrlAddr = BaseAddr1 + 16;
+localparam [10:0] Spi1RxFifoCtrlAddr = BaseAddr1 + 20;
+localparam [10:0] Spi1TxFifoAddr = BaseAddr1 + 24;
+localparam [10:0] Spi1RxFifoAddr = BaseAddr1 + 28;
+
+//***********************************************
+//	           SPI2HEADERS
+//***********************************************
+localparam [10:0] BaseAddr2 = 11'hF0;
+localparam [10:0] Spi2CtrlAddr = BaseAddr2;
+localparam [10:0] Spi2ClkAddr = BaseAddr2 + 4;
+localparam [10:0] Spi2CsDelayAddr = BaseAddr2 + 8;
+localparam [10:0] Spi2CsCtrlAddr = BaseAddr2 + 12;
+localparam [10:0] Spi2TxFifoCtrlAddr = BaseAddr2 + 16;
+localparam [10:0] Spi2RxFifoCtrlAddr = BaseAddr2 + 20;
+localparam [10:0] Spi2TxFifoAddr = BaseAddr2 + 24;
+localparam [10:0] Spi2RxFifoAddr = BaseAddr2 + 28;
+
+//***********************************************
+//	           SPI3HEADERS
+//***********************************************
+localparam [10:0] BaseAddr3 = 11'h140;
+localparam [10:0] Spi3CtrlAddr = BaseAddr3;
+localparam [10:0] Spi3ClkAddr = BaseAddr3 + 4;
+localparam [10:0] Spi3CsDelayAddr = BaseAddr3 + 8;
+localparam [10:0] Spi3CsCtrlAddr = BaseAddr3 + 12;
+localparam [10:0] Spi3TxFifoCtrlAddr = BaseAddr3 + 16;
+localparam [10:0] Spi3RxFifoCtrlAddr = BaseAddr3 + 20;
+localparam [10:0] Spi3TxFifoAddr = BaseAddr3 + 24;
+localparam [10:0] Spi3RxFifoAddr = BaseAddr3 + 28;
+
+//***********************************************
+//	           SPI4HEADERS
+//***********************************************
+localparam [10:0] BaseAddr4 = 11'h190;
+localparam [10:0] Spi4CtrlAddr = BaseAddr4;
+localparam [10:0] Spi4ClkAddr = BaseAddr4 + 4;
+localparam [10:0] Spi4CsDelayAddr = BaseAddr4 + 8;
+localparam [10:0] Spi4CsCtrlAddr = BaseAddr4 + 12;
+localparam [10:0] Spi4TxFifoCtrlAddr = BaseAddr4 + 16;
+localparam [10:0] Spi4RxFifoCtrlAddr = BaseAddr4 + 20;
+localparam [10:0] Spi4TxFifoAddr = BaseAddr4 + 24;
+localparam [10:0] Spi4RxFifoAddr = BaseAddr4 + 28;
+
+//***********************************************
+//	           SPI5HEADERS
+//***********************************************
+localparam [10:0] BaseAddr5 = 11'h1E0;
+localparam [10:0] Spi5CtrlAddr = BaseAddr5;
+localparam [10:0] Spi5ClkAddr = BaseAddr5 + 4;
+localparam [10:0] Spi5CsDelayAddr = BaseAddr5 + 8;
+localparam [10:0] Spi5CsCtrlAddr = BaseAddr5 + 12;
+localparam [10:0] Spi5TxFifoCtrlAddr = BaseAddr5 + 16;
+localparam [10:0] Spi5RxFifoCtrlAddr = BaseAddr5 + 20;
+localparam [10:0] Spi5TxFifoAddr = BaseAddr5 + 24;
+localparam [10:0] Spi5RxFifoAddr = BaseAddr5 + 28;
+
+
+//***********************************************
+//	           SPI5HEADERS
+//***********************************************
+localparam [10:0] BaseAddr6 = 11'h230;
+localparam [10:0] Spi6CtrlAddr = BaseAddr6;
+localparam [10:0] Spi6ClkAddr = BaseAddr6 + 4;
+localparam [10:0] Spi6CsDelayAddr = BaseAddr6 + 8;
+localparam [10:0] Spi6CsCtrlAddr = BaseAddr6 + 12;
+localparam [10:0] Spi6TxFifoCtrlAddr = BaseAddr6 + 16;
+localparam [10:0] Spi6RxFifoCtrlAddr = BaseAddr6 + 20;
+localparam [10:0] Spi6TxFifoAddr = BaseAddr6 + 24;
+localparam [10:0] Spi6RxFifoAddr = BaseAddr6 + 28;
+
+
+//***********************************************
+//	           SPITXRX Enable Reg Adress
+//***********************************************
+localparam SpiTxRxEnAddr = 11'h780;
+
+//***********************************************
+//	           GPIO Reg Adress
+//***********************************************
+localparam GPIOAddr = 11'hFF0;
+
+//***********************************************
+//	           ASSIGNS
+//***********************************************
+assign SmcBe_i = (tb_cnt >0 && tb_cnt <=44) ? 2'b00 : 2'b11;
+assign SmcAmsN_i = (tb_cnt > 0 && tb_cnt <= 44) ? 1'b0 : 1'b1;
+assign smcData = SmcData_i;
+assign mosi1_io = (!Mode0) ? mosi0_o : 1'bz;
+
+//***********************************************
+//	           CLOCK GENERATION
+//***********************************************
+always #(CLK_PERIOD/2) Clk_i = ~Clk_i;
+
+	S5443_3Top uut (
+		.Clk123_i(Clk_i), 
+		.SmcAddr_i(SmcAddr_i), 
+		.SmcData_io(smcData), 
+		.SmcAwe_i(SmcAwe_i), 
+		.SmcAmsN_i(SmcAmsN_i), 
+		.SmcAre_i(SmcAre_i), 
+		.SmcBe_i(SmcBe_i), 
+		.SmcAoe_i(SmcAoe_i), 
+		.Led_o(), 
+		.Mosi0_o(mosi0_o), 
+		.Mosi1_io(mosi1_io), 
+		.Mosi2_o(), 
+		.Mosi3_o(), 
+		.Ss_o(), 
+		.SsFlash_o(), 
+		.Sck_o(), 
+		.SpiRst_o(), 
+		.LD_o()
+	);
+
+always @(posedge Clk_i) begin 
+	if (Rst_i) begin
+		SmcAwe_i <= 1'b1;
+	end
+	else begin 
+		if (tb_cnt > 0 && tb_cnt <= 44) begin 
+			if (tb_cnt % 2 != 0) begin 
+				SmcAwe_i <= 1'b1;
+			end
+			else begin 
+				SmcAwe_i <= 1'b0;
+			end
+		end
+	end
+end
+
+always @(posedge Clk_i) begin 
+	if (Rst_i) begin 
+		SmcAddr_i <= 0;
+	end
+	else begin
+		if (tb_cnt < 27) begin
+		case (tb_cnt)
+		0: begin 
+			SmcAddr_i <= BaseAddr0;
+		end
+		3: begin 
+			SmcAddr_i <= Spi0ClkAddr;
+		end
+		5: begin 
+			SmcAddr_i <= Spi0CsDelayAddr;
+		end
+		7: begin 
+			SmcAddr_i <= Spi0CsCtrlAddr;
+		end
+		9: begin 
+			SmcAddr_i <= Spi0TxFifoCtrlAddr;
+		end
+		11: begin 
+			SmcAddr_i <= Spi0RxFifoCtrlAddr;
+		end
+		19: begin 
+			SmcAddr_i <= Spi0TxFifoCtrlAddr;
+		end
+		21: begin 
+			SmcAddr_i <= Spi0RxFifoCtrlAddr;
+		end
+		23: begin 
+			SmcAddr_i <= SpiTxRxEnAddr;
+		end
+		endcase
+		end
+		else begin 
+			if (tb_cnt % 2 != 0) begin 
+				SmcAddr_i <= Spi0TxFifoAddrL;
+			end
+			else begin 
+				SmcAddr_i <= Spi0TxFifoAddrM;
+			end
+		end
+	end
+end
+
+always @(posedge Clk_i) begin 
+	if (Rst_i) begin 
+		SmcData_i <= 16'h0;
+	end
+	else begin
+		if (tb_cnt < 27 ) begin  
+			case (tb_cnt)
+			0 : begin 
+				SmcData_i <= Spi0CtrlRegData;
+			end
+			3 : begin 
+				SmcData_i <= Spi0ClkRegData;
+			end
+			5 : begin 
+				SmcData_i <= Spi0CsDelayRegData;
+			end
+			7 : begin 
+				SmcData_i <= Spi0CsCtrlRegData;
+			end
+			9 : begin 
+				SmcData_i <= Spi0TxFifoCtrlRegDataRstOn;
+			end
+			11 : begin 
+				SmcData_i <= Spi0RxFifoCtrlRegDataRstOn;
+			end
+			19 : begin 
+				SmcData_i <= Spi0TxFifoCtrlRegDataRstOff;
+			end
+			21 : begin 
+				SmcData_i <= Spi0RxFifoCtrlRegDataRstOff;
+			end
+			23 : begin 
+				SmcData_i <= SpiTxRxEnRegData;
+			end
+			endcase
+		end
+		else begin 
+				SmcData_i <= $urandom_range(0, 8'hFF);
+			end
+	end
+end
+
+always @(posedge Clk_i) begin 
+	if (Rst_i) begin 
+		tb_cnt <= 0;
+	end
+	else begin 
+		tb_cnt <= tb_cnt + 1;
+	end
+end
+
+initial begin 
+	Clk_i = 1'b0;
+	Rst_i = 1'b1;
+	SmcAre_i = 1'b1;
+	SmcAoe_i = 1'b1;
+	#(CLK_PERIOD*300) Rst_i = 1'b0;
+end
+
+endmodule