`timescale 1ns / 1ps

//////////////////////////////////////////////////////////////////////////////////
// Company: Tair
// Engineer: Churbanov S.
// 
// Create Date:     
// Design Name: 
// Module Name:    TopSbtmsg
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//		Clk_i - is 24MHz.
//
//////////////////////////////////////////////////////////////////////////////////

module TopSbTmsg 
#(
    parameter DEVNUM = 8,
    parameter WORDWIDTH = 24,
    parameter SSPIWORDWIDTH = 24
) 
(
	input Clk_i,
	input Rst_i,
	
	input Sck_i,
	input Ss_i,
	
	input Mosi0_i,
	inout Mosi1_io,
	input Mosi2_i,
	input Mosi3_i,
	
	input Miso1_i,
	input Miso2_i,
	input MisoMax2870_i,
	
	output I2CSck_o,
	inout I2CSda_io,
	
	output [DEVNUM-1:0] Ss_o,
	output [DEVNUM-1:0] Sck_o,
	output [DEVNUM-1:0] Mosi_o,
	
	output [21:0] Gpio_o
);

//================================================================================
//  LOCALPARAM


//================================================================================
//  REG/WIRE
	wire gclk;
	wire clk100;
	wire clk5;
	wire clk20;
	wire clk50;
	wire clk26dot25;
	wire clk60;

	//FifoLMX
	wire [23:0] dataFromLmxFifo;
	wire [23:0] dataFromLmxFifoCtrl;
	wire readEnLmx;
	wire writeEnLmx;
	wire lmxFifoEmpty;
	wire lmxFifoFull;
	wire valRdDataLMX;

	//FifoDDS
	wire [63:0] dataFromDdsFifo;
	wire [63:0] dataFromDdsFifoCtrl;
	wire readEnDds;
	wire writeEnDds;
	wire ddsFifoEmpty;
	wire ddsFifoFull;
	wire valRdDataDDS;

	//FifoPot
	wire [15:0] dataFromPotFifo;
	wire [15:0] dataFromPotFifoCtrl;
	wire readEnPot;
	wire writeEnPot;
	wire potFifoEmpty;
	wire potFifoFull;
	wire valRdDataPOT;

	//FifoDAC
	wire [15:0] dataFromDacFifo;
	wire [15:0] dataFromDacFifoCtrl;
	wire readEnDac;
	wire writeEnDac;
	wire dacFifoEmpty;
	wire dacFifoFull;

	//FifoAtt
	wire [15:0] dataFromAttFifo;
	wire [15:0] dataFromAttFifoCtrl;
	wire readEnAtt;
	wire writeEnAtt;
	wire attFifoEmpty;
	wire attFifoFull;
	wire valRdDataATT;

	//FifoShReg
	wire [7:0] dataFromShRegFifo;
	wire [7:0] dataFromShRegFifoCtrl;
	wire readEnShReg;
	wire writeEnShReg;
	wire shRegFifoEmpty;
	wire shRegFifoFull;
	wire valRdDataShReg;

	//FifoMax
	wire [31:0] dataFromMaxFifo;
	wire [31:0] dataFromMaxFifoCtrl;
	wire readEnMax;
	wire writeEnMax;
	wire maxFifoEmpty;
	wire maxFifoFull;
	wire valRdDataMAX;

	wire spiDataVal;
	wire [WORDWIDTH-1:0] spiData;
	
	wire busyMosi1;
	wire busyMosi4;
	
	wire valLmxDataToFifo;		
	wire valDdsDataToFifo;		
	wire valPotDataToFifo;		
	wire valDacDataToFifo;		
	wire valAttDataToFifo;		
	wire valShRegDataToFifo;	
	wire valMaxDataToFifo;		
	wire valGpioDataToFifo;	
	
	wire flagDirectLmx;	
	wire flagDirectDds;	
	wire flagDirectPot;	
	wire flagDirectDac;	
	wire flagDirectAtt;	
	wire flagDirectShReg;	
	wire flagDirectMax;	
	wire flagDirectGpio;	
	wire flagDirectTemp;	
	
	
//================================================================================
//  ASSIGNMENTS





//================================================================================
//  CODING
ClkGen ClkGen_inst (
	.Clk24Mhz_i			(Clk_i),
	.Clk24Mhz_o			(gclk),
	.Clk100Mhz_o		(clk100),
	.Clk5Mhz_o			(clk5),
	.Clk20Mhz_o			(clk20),
	.Clk50Mhz_o			(clk50),
	.Clk26dot25Mhz_o 	(clk26dot25),
	.Clk60Mhz_o			(clk60)
);

InterfaceArbiter 
#(	
	.OUTWORDWIDTH	(WORDWIDTH),
	.SSPIWORDWIDTH	(SSPIWORDWIDTH)
)
SpiSlaveArbiter
(
	.Rst_i			(Rst_i),
	.Clk_i			(clk100),
		
	.Sck_i			(Sck_i),
	.Ss_i			(Ss_i),
		
	.Mosi0_i		(Mosi0_i),
	.Mosi1_i		(Mosi1_io),
	.Mosi2_i		(Mosi2_i),
	.Mosi3_i		(Mosi3_i),
		
		
	.DataVal_o		(spiDataVal),
	.Data_o			(spiData)
);

PacketAnalyzer4Mosi PacketAnalyzer4Mosi
(
	.Clk_i					(clk100),
	.Rst_i					(Rst_i),

	.DataFromSpi_i			(spiData),
	.ValDataFromSpi_i		(spiDataVal),

	.BusyMosi1_i			(busyMosi1),

	.ValLmxDataToFifo_o		(valLmxDataToFifo),
	.ValDdsDataToFifo_o		(valDdsDataToFifo),
	.ValPotDataToFifo_o		(valPotDataToFifo),
	.ValDacDataToFifo_o		(valDacDataToFifo),
	.ValAttDataToFifo_o		(valAttDataToFifo),
	.ValShRegDataToFifo_o	(valShRegDataToFifo),
	.ValMaxDataToFifo_o		(valMaxDataToFifo),
	.ValGpioDataToFifo_o	(valGpioDataToFifo),

	.Busy_o					(busyMosi4)
);

PacketAnalyzer1Mosi PacketAnalyzer1Mosi
(
	.Clk_i				(clk100),
	.Rst_i				(Rst_i),

	.DataFromSpi_i		(spiData),
	.ValDataFromSpi_i	(spiDataVal),

	.BusyMosi4_i		(busyMosi4),

	.FlagDirectLmx_o	(flagDirectLmx),
	.FlagDirectDds_o	(flagDirectDds),
	.FlagDirectPot_o	(flagDirectPot),
	.FlagDirectDac_o	(flagDirectDac),
	.FlagDirectAtt_o	(flagDirectAtt),
	.FlagDirectShReg_o	(flagDirectShReg),
	.FlagDirectMax_o	(flagDirectMax),
	.FlagDirectGpio_o	(flagDirectGpio),
	.FlagDirectTemp_o	(flagDirectTemp),

	.Busy_o				(busyMosi1)
);

//***********************************************
//	           LMX2594
//***********************************************
FifoCtrl #(
	.IN_WIDTH		(24),
	.WR_NUM			(1),
	.OUT_WIDTH		(24)
) FifoCtrlLmx
(
	.WrClk_i		(clk100),
	.RdClk_i		(clk60),
	.Rst_i			(Rst_i),
	.Data_i			(spiData),
	.Val_i			(valLmxDataToFifo),
	.BusySpiM_i		(busySpiMLmx),
	.FifoFull_i		(lmxFifoFull),
	.FifoEmpty_i	(lmxFifoEmpty),
	.Data_o			(dataFromLmxFifoCtrl),
	.ReadEn_o		(readEnLmx),
	.WriteEn_o		(writeEnLmx),
	.ValRdData_o	(valRdDataLMX)
);

FifoLMX FifoLMX_inst (
	.Data	(dataFromLmxFifoCtrl),
	.WrClk	(clk100),
	.RdClk	(clk60),
	.Reset	(Rst_i),
	.WrEn	(writeEnLmx),
	.RdEn	(readEnLmx),
	.Full	(lmxFifoFull),
	.Empty	(lmxFifoEmpty),
	.Q		(dataFromLmxFifo)
);

SpiM #(
	.DATA_WIDTH	(24)
)SpiMLmx(
	.Clk_i		(clk60),
	.Rst_i		(Rst_i),
	.Val_i		(valRdDataLMX),
	.SpiData_i	(dataFromLmxFifo),
	.Busy_o	    (busySpiMLmx),
	.Ss_o		(),
	.Mosi_o		(),
	.Sck_o		()
);

//***********************************************
//	           		DDS
//***********************************************
FifoCtrl #(
	.IN_WIDTH		(24),
	.WR_NUM			(3),
	.OUT_WIDTH		(64)
) FifoCtrlDDS
(
	.WrClk_i		(clk100),
	.RdClk_i		(clk50),
	.Rst_i			(Rst_i),
	.Data_i			(spiData),
	.Val_i			(valDdsDataToFifo),
	.BusySpiM_i		(busySpiMDds),
	.FifoFull_i		(ddsFifoFull),
	.FifoEmpty_i	(ddsFifoEmpty),
	.Data_o			(dataFromDdsFifoCtrl),
	.ReadEn_o		(readEnDds),
	.WriteEn_o		(writeEnDds),
	.ValRdData_o	(valRdDataDDS)
);

FifoDDS FifoDDS_inst (
	.Data	(dataFromDdsFifoCtrl),
	.WrClk	(clk100),
	.RdClk	(clk50),
	.Reset	(Rst_i),
	.WrEn	(writeEnDds),
	.RdEn	(readEnDds),
	.Full	(ddsFifoFull),
	.Empty	(ddsFifoEmpty),
	.Q		(dataFromDdsFifo)
);

SpiM #(
	.DATA_WIDTH	(64)
)SpiMDDS(
	.Clk_i		(clk50),
	.Rst_i		(Rst_i),
	.Val_i		(valRdDataDDS),
	.SpiData_i	(dataFromDdsFifo),
	.Busy_o	    (busySpiMDds),
	.Ss_o		(),
	.Mosi_o		(),
	.Sck_o		()
);

//***********************************************
//	           		POT
//***********************************************
FifoCtrl #(
	.IN_WIDTH		(24),
	.WR_NUM			(1),
	.OUT_WIDTH		(16)
) FifoCtrlPot
(
	.WrClk_i		(clk100),
	.RdClk_i		(clk5),
	.Rst_i			(Rst_i),
	.Data_i			(spiData),
	.Val_i			(valPotDataToFifo),
	.BusySpiM_i		(busySpiMPot),
	.FifoFull_i		(potFifoFull),
	.FifoEmpty_i	(potFifoEmpty),
	.Data_o			(dataFromPotFifoCtrl),
	.ReadEn_o		(readEnPot),
	.WriteEn_o		(writeEnPot),
	.ValRdData_o	(valRdDataPOT)
);

Fifo16x3 FifoPot_inst (
	.Data	(dataFromPotFifoCtrl),
	.WrClk	(clk100),
	.RdClk	(clk5),
	.Reset	(Rst_i),
	.WrEn	(writeEnPot),
	.RdEn	(readEnPot),
	.Full	(potFifoFull),
	.Empty	(potFifoEmpty),
	.Q		(dataFromPotFifo)
);

SpiM #(
	.DATA_WIDTH	(16)
)SpiMPot(
	.Clk_i		(clk5),
	.Rst_i		(Rst_i),
	.Val_i		(valRdDataPOT),
	.SpiData_i	(dataFromPotFifo),
	.Busy_o	    (busySpiMPot),
	.Ss_o		(),
	.Mosi_o		(),
	.Sck_o		()
);

//***********************************************
//	           		DAC
//***********************************************
FifoCtrl #(
	.IN_WIDTH		(24),
	.WR_NUM			(1),
	.OUT_WIDTH		(16)
) FifoCtrlDac
(
	.WrClk_i		(clk100),
	.RdClk_i		(clk5),
	.Rst_i			(Rst_i),
	.Data_i			(spiData),
	.Val_i			(valDacDataToFifo),
	.BusySpiM_i		(busySpiMDac),
	.FifoFull_i		(dacFifoFull),
	.FifoEmpty_i	(dacFifoEmpty),
	.Data_o			(dataFromDacFifoCtrl),
	.ReadEn_o		(readEnDac),
	.WriteEn_o		(writeEnDac),
	.ValRdData_o	(valRdDataDAC)
);

Fifo16x3 FifoDAC_inst (
	.Data	(dataFromDacFifoCtrl),
	.WrClk	(clk100),
	.RdClk	(clk50),
	.Reset	(Rst_i),
	.WrEn	(writeEnDac),
	.RdEn	(readEnDac),
	.Full	(dacFifoFull),
	.Empty	(dacFifoEmpty),
	.Q		(dataFromDacFifo)
);

SpiM #(
	.DATA_WIDTH	(16)
)SpiMDac(
	.Clk_i		(clk50),
	.Rst_i		(Rst_i),
	.Val_i		(valRdDataDAC),
	.SpiData_i	(dataFromDacFifo),
	.Busy_o	    (busySpiMDac),
	.Ss_o		(),
	.Mosi_o		(),
	.Sck_o		()
);

//***********************************************
//	           		ATT
//***********************************************
FifoCtrl #(
	.IN_WIDTH		(24),
	.WR_NUM			(1),
	.OUT_WIDTH		(16)
) FifoCtrlAtt
(
	.WrClk_i		(clk100),
	.RdClk_i		(clk50),
	.Rst_i			(Rst_i),
	.Data_i			(spiData),
	.Val_i			(valAttDataToFifo),
	.BusySpiM_i		(busySpiMAtt),
	.FifoFull_i		(attFifoFull),
	.FifoEmpty_i	(attFifoEmpty),
	.Data_o			(dataFromAttFifoCtrl),
	.ReadEn_o		(readEnAtt),
	.WriteEn_o		(writeEnAtt),
	.ValRdData_o	(valRdDataATT)
);

Fifo16x3 FifoAtt_inst (
	.Data	(dataFromAttFifoCtrl),
	.WrClk	(clk100),
	.RdClk	(clk50),
	.Reset	(Rst_i),
	.WrEn	(writeEnAtt),
	.RdEn	(readEnAtt),
	.Full	(attFifoFull),
	.Empty	(attFifoEmpty),
	.Q		(dataFromAttFifo)
);

SpiM #(
	.DATA_WIDTH	(16)
)SpiMAtt(
	.Clk_i		(clk50),
	.Rst_i		(Rst_i),
	.Val_i		(valRdDataATT),
	.SpiData_i	(dataFromAttFifo),
	.Busy_o	    (busySpiMAtt),
	.Ss_o		(),
	.Mosi_o		(),
	.Sck_o		()
);

//***********************************************
//	           		ShiftRegister
//***********************************************
FifoCtrl #(
	.IN_WIDTH		(24),
	.WR_NUM			(1),
	.OUT_WIDTH		(8)
) FifoCtrlShReg
(
	.WrClk_i		(clk100),
	.RdClk_i		(clk26dot25),
	.Rst_i			(Rst_i),
	.Data_i			(spiData),
	.Val_i			(valShRegDataToFifo),
	.BusySpiM_i		(busySpiMShReg),
	.FifoFull_i		(shRegFifoFull),
	.FifoEmpty_i	(shRegFifoEmpty),
	.Data_o			(dataFromShRegFifoCtrl),
	.ReadEn_o		(readEnShReg),
	.WriteEn_o		(writeEnShReg),
	.ValRdData_o	(valRdDataShReg)
);

FifoShiftReg FifoShReg_inst (
	.Data	(dataFromShRegFifoCtrl),
	.WrClk	(clk100),
	.RdClk	(clk26dot25),
	.Reset	(Rst_i),
	.WrEn	(writeEnShReg),
	.RdEn	(readEnShReg),
	.Full	(shRegFifoFull),
	.Empty	(shRegFifoEmpty),
	.Q		(dataFromShRegFifo)
);

SpiM #(
	.DATA_WIDTH	(8)
)SpiMShReg(
	.Clk_i		(clk26dot25),
	.Rst_i		(Rst_i),
	.Val_i		(valRdDataShReg),
	.SpiData_i	(dataFromShRegFifo),
	.Busy_o	    (busySpiMShReg),
	.Ss_o		(),
	.Mosi_o		(),
	.Sck_o		()
);

//***********************************************
//	           		MAX2870
//***********************************************
FifoCtrl #(
	.IN_WIDTH		(24),
	.WR_NUM			(2),
	.OUT_WIDTH		(32)
) FifoCtrlMax
(
	.WrClk_i		(clk100),
	.RdClk_i		(clk50),
	.Rst_i			(Rst_i),
	.Data_i			(spiData),
	.Val_i			(valMaxDataToFifo),
	.BusySpiM_i		(busySpiMMax),
	.FifoFull_i		(maxFifoFull),
	.FifoEmpty_i	(maxFifoEmpty),
	.Data_o			(dataFromMaxFifoCtrl),
	.ReadEn_o		(readEnMax),
	.WriteEn_o		(writeEnMax),
	.ValRdData_o	(valRdDataMAX)
);

FifoMax2870 FifoMax2870_inst (
	.Data	(dataFromMaxFifoCtrl),
	.WrClk	(clk100),
	.RdClk	(clk50),
	.Reset	(Rst_i),
	.WrEn	(writeEnMax),
	.RdEn	(readEnMax),
	.Full	(maxFifoFull),
	.Empty	(maxFifoEmpty),
	.Q		(dataFromMaxFifo)
);

SpiM #(
	.DATA_WIDTH	(32)
)SpiMMax(
	.Clk_i		(clk50),
	.Rst_i		(Rst_i),
	.Val_i		(valRdDataMAX),
	.SpiData_i	(dataFromMaxFifo),
	.Busy_o	    (busySpiMMax),
	.Ss_o		(),
	.Mosi_o		(),
	.Sck_o		()
);

endmodule
