- Synthesis Messages
- Synthesis Details
- Resource
  - Resource Usage Summary
  - Resource Utilization Summary
- Timing
  - Clock Summary
  - Max Frequency Summary
  - Detail Timing Paths Informations

# Synthesis Messages

Report Title | GowinSynthesis Report
Design File | C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v
GowinSynthesis Constraints File | ---
Tool Version | V1.9.9.02
Part Number | GW1N-LV9PG256C6/I5
Device | GW1N-
Created Time | Wed Apr 24 12:23:21 2024
Legal Announcement | Copyright (C)2014-2024 Gowin Semiconductor Corporation. ALL rights reserved.

# Synthesis Details

Top Level Module | FifoLMX

Synthesis Process

Running parser:
CPU time = 0h 0m 0.468s, Elapsed time = 0h 0m 0.488s, Peak memory usage = 74.570MB
Running netlist conversion:
CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 74.570MB
Running device independent optimization:
Optimizing Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 74.570MB
Optimizing Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 74.570MB
Optimizing Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 74.570MB
Running inference:
Inferring Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 74.570MB
Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 74.570MB
Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 74.570MB
Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 74.570MB
Running technical mapping:
Tech-Mapping Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 74.570MB
Tech-Mapping Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 74.570MB
Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 74.570MB
Tech-Mapping Phase 3: CPU time = 0h 0m 0.203s, Elapsed time = 0h 0m 0.217s, Peak memory usage = 95.809MB
Tech-Mapping Phase 4: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.021s, Peak memory usage = 95.809MB
Generate output files:
CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.014s, Peak memory usage = 95.809MB

Total Time and Memory Usage | CPU time = 0h 0m 0.732s, Elapsed time = 0h 0m 0.748s, Peak memory usage = 95.809MB

# Resource

## Resource Usage Summary

Resource | Usage
I/O Port | 55
I/O Buf | 55
IBUF | 29
OBUF | 26
Register | 28
DFFP | 8
DFFC | 20
LUT | 37
LUT2 | 7
LUT3 | 12
LUT4 | 18
ALU | 4
ALU | 4
INV | 2
INV | 2
BSRAM | 1
SDPB | 1

## Resource Utilization Summary

Resource | Usage | Utilization
Logic | 43(39 LUT, 4 ALU) / 8640 | <1%
Register | 28 / 7104 | <1%
--Register as Latch | 0 / 7104 | 0%
--Register as FF | 28 / 7104 | <1%
BSRAM | 1 / 26 | 4%

# Timing

## Clock Summary:

Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object
--- | --- | --- | --- | --- | --- | --- | --- | ---
RdClk | Base | 20.000 | 50.0 | 0.000 | 10.000 |  |  | RdClk_ibuf/I
WrClk | Base | 20.000 | 50.0 | 0.000 | 10.000 |  |  | WrClk_ibuf/I

## Max Frequency Summary:

No. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity
--- | --- | --- | --- | --- | ---
1 | RdClk | 50.000(MHz) | 172.344(MHz) | 3 | TOP
2 | WrClk | 50.000(MHz) | 50.621(MHz) | 5 | TOP

## Detail Timing Paths Information

### Path 1

Path Summary:

Slack | 0.123
Data Arrival Time | 20.203
Data Required Time | 20.326
From | fifo_inst/reset_w_1_s0
To | fifo_inst/Equal.wbin_0_s0
Launch Clk | WrClk[R]
Latch Clk | WrClk[F]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | NODE
--- | --- | --- | --- | --- | ---
10.000 | 0.000 |  |  |  | WrClk
10.000 | 0.000 | tCL | FF | 1 | WrClk_ibuf/I
10.000 | 0.000 | tINS | FF | 16 | WrClk_ibuf/O
10.960 | 0.960 | tNET | FF | 1 | fifo_inst/reset_w_1_s0/CLK
11.418 | 0.458 | tC2Q | FF | 14 | fifo_inst/reset_w_1_s0/Q
12.378 | 0.960 | tNET | FF | 1 | fifo_inst/n372_s2/I0
13.410 | 1.032 | tINS | FF | 3 | fifo_inst/n372_s2/F
14.370 | 0.960 | tNET | FF | 1 | fifo_inst/Full_s8/I1
15.469 | 1.099 | tINS | FF | 3 | fifo_inst/Full_s8/F
16.429 | 0.960 | tNET | FF | 1 | fifo_inst/n23_s1/I2
17.251 | 0.822 | tINS | FF | 3 | fifo_inst/n23_s1/F
18.211 | 0.960 | tNET | FF | 1 | fifo_inst/Equal.wbinnext_0_s3/I0
19.243 | 1.032 | tINS | FF | 1 | fifo_inst/Equal.wbinnext_0_s3/F
20.203 | 0.960 | tNET | FF | 1 | fifo_inst/Equal.wbin_0_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | NODE
--- | --- | --- | --- | --- | ---
20.000 | 0.000 |  |  |  | WrClk
20.000 | 0.000 | tCL | RR | 1 | WrClk_ibuf/I
20.000 | 0.000 | tINS | RR | 16 | WrClk_ibuf/O
20.726 | 0.726 | tNET | RR | 1 | fifo_inst/Equal.wbin_0_s0/CLK
20.326 | -0.400 | tSu |  | 1 | fifo_inst/Equal.wbin_0_s0

Path Statistics:

Clock Skew: | -0.234
Setup Relationship: | 10.000
Logic Level: | 5
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.960, 100.000%
Arrival Data Path Delay: | cell: 3.985, 43.112%; route: 4.800, 51.929%; tC2Q: 0.458, 4.959%
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.960, 100.000%

### Path 2

Path Summary:

Slack | 0.123
Data Arrival Time | 20.203
Data Required Time | 20.326
From | fifo_inst/reset_w_1_s0
To | fifo_inst/Equal.wbin_1_s0
Launch Clk | WrClk[R]
Latch Clk | WrClk[F]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | NODE
--- | --- | --- | --- | --- | ---
10.000 | 0.000 |  |  |  | WrClk
10.000 | 0.000 | tCL | FF | 1 | WrClk_ibuf/I
10.000 | 0.000 | tINS | FF | 16 | WrClk_ibuf/O
10.960 | 0.960 | tNET | FF | 1 | fifo_inst/reset_w_1_s0/CLK
11.418 | 0.458 | tC2Q | FF | 14 | fifo_inst/reset_w_1_s0/Q
12.378 | 0.960 | tNET | FF | 1 | fifo_inst/n372_s2/I0
13.410 | 1.032 | tINS | FF | 3 | fifo_inst/n372_s2/F
14.370 | 0.960 | tNET | FF | 1 | fifo_inst/Full_s8/I1
15.469 | 1.099 | tINS | FF | 3 | fifo_inst/Full_s8/F
16.429 | 0.960 | tNET | FF | 1 | fifo_inst/Full_d_s/I2
17.251 | 0.822 | tINS | FF | 8 | fifo_inst/Full_d_s/F
18.211 | 0.960 | tNET | FF | 1 | fifo_inst/Equal.wbinnext_1_s4/I0
19.243 | 1.032 | tINS | FF | 1 | fifo_inst/Equal.wbinnext_1_s4/F
20.203 | 0.960 | tNET | FF | 1 | fifo_inst/Equal.wbin_1_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | NODE
--- | --- | --- | --- | --- | ---
20.000 | 0.000 |  |  |  | WrClk
20.000 | 0.000 | tCL | RR | 1 | WrClk_ibuf/I
20.000 | 0.000 | tINS | RR | 16 | WrClk_ibuf/O
20.726 | 0.726 | tNET | RR | 1 | fifo_inst/Equal.wbin_1_s0/CLK
20.326 | -0.400 | tSu |  | 1 | fifo_inst/Equal.wbin_1_s0

Path Statistics:

Clock Skew: | -0.234
Setup Relationship: | 10.000
Logic Level: | 5
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.960, 100.000%
Arrival Data Path Delay: | cell: 3.985, 43.112%; route: 4.800, 51.929%; tC2Q: 0.458, 4.959%
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.960, 100.000%

### Path 3

Path Summary:

Slack | 0.123
Data Arrival Time | 20.203
Data Required Time | 20.326
From | fifo_inst/reset_w_1_s0
To | fifo_inst/Equal.wbin_2_s0
Launch Clk | WrClk[R]
Latch Clk | WrClk[F]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | NODE
--- | --- | --- | --- | --- | ---
10.000 | 0.000 |  |  |  | WrClk
10.000 | 0.000 | tCL | FF | 1 | WrClk_ibuf/I
10.000 | 0.000 | tINS | FF | 16 | WrClk_ibuf/O
10.960 | 0.960 | tNET | FF | 1 | fifo_inst/reset_w_1_s0/CLK
11.418 | 0.458 | tC2Q | FF | 14 | fifo_inst/reset_w_1_s0/Q
12.378 | 0.960 | tNET | FF | 1 | fifo_inst/n372_s2/I0
13.410 | 1.032 | tINS | FF | 3 | fifo_inst/n372_s2/F
14.370 | 0.960 | tNET | FF | 1 | fifo_inst/Full_s8/I1
15.469 | 1.099 | tINS | FF | 3 | fifo_inst/Full_s8/F
16.429 | 0.960 | tNET | FF | 1 | fifo_inst/Full_d_s/I2
17.251 | 0.822 | tINS | FF | 8 | fifo_inst/Full_d_s/F
18.211 | 0.960 | tNET | FF | 1 | fifo_inst/Equal.wbinnext_2_s3/I0
19.243 | 1.032 | tINS | FF | 1 | fifo_inst/Equal.wbinnext_2_s3/F
20.203 | 0.960 | tNET | FF | 1 | fifo_inst/Equal.wbin_2_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | NODE
--- | --- | --- | --- | --- | ---
20.000 | 0.000 |  |  |  | WrClk
20.000 | 0.000 | tCL | RR | 1 | WrClk_ibuf/I
20.000 | 0.000 | tINS | RR | 16 | WrClk_ibuf/O
20.726 | 0.726 | tNET | RR | 1 | fifo_inst/Equal.wbin_2_s0/CLK
20.326 | -0.400 | tSu |  | 1 | fifo_inst/Equal.wbin_2_s0

Path Statistics:

Clock Skew: | -0.234
Setup Relationship: | 10.000
Logic Level: | 5
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.960, 100.000%
Arrival Data Path Delay: | cell: 3.985, 43.112%; route: 4.800, 51.929%; tC2Q: 0.458, 4.959%
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.960, 100.000%

### Path 4

Path Summary:

Slack | 0.123
Data Arrival Time | 20.203
Data Required Time | 20.326
From | fifo_inst/reset_w_1_s0
To | fifo_inst/Equal.wbin_3_s0
Launch Clk | WrClk[R]
Latch Clk | WrClk[F]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | NODE
--- | --- | --- | --- | --- | ---
10.000 | 0.000 |  |  |  | WrClk
10.000 | 0.000 | tCL | FF | 1 | WrClk_ibuf/I
10.000 | 0.000 | tINS | FF | 16 | WrClk_ibuf/O
10.960 | 0.960 | tNET | FF | 1 | fifo_inst/reset_w_1_s0/CLK
11.418 | 0.458 | tC2Q | FF | 14 | fifo_inst/reset_w_1_s0/Q
12.378 | 0.960 | tNET | FF | 1 | fifo_inst/n372_s2/I0
13.410 | 1.032 | tINS | FF | 3 | fifo_inst/n372_s2/F
14.370 | 0.960 | tNET | FF | 1 | fifo_inst/Full_s8/I1
15.469 | 1.099 | tINS | FF | 3 | fifo_inst/Full_s8/F
16.429 | 0.960 | tNET | FF | 1 | fifo_inst/Full_d_s/I2
17.251 | 0.822 | tINS | FF | 8 | fifo_inst/Full_d_s/F
18.211 | 0.960 | tNET | FF | 1 | fifo_inst/Equal.wbinnext_3_s3/I0
19.243 | 1.032 | tINS | FF | 1 | fifo_inst/Equal.wbinnext_3_s3/F
20.203 | 0.960 | tNET | FF | 1 | fifo_inst/Equal.wbin_3_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | NODE
--- | --- | --- | --- | --- | ---
20.000 | 0.000 |  |  |  | WrClk
20.000 | 0.000 | tCL | RR | 1 | WrClk_ibuf/I
20.000 | 0.000 | tINS | RR | 16 | WrClk_ibuf/O
20.726 | 0.726 | tNET | RR | 1 | fifo_inst/Equal.wbin_3_s0/CLK
20.326 | -0.400 | tSu |  | 1 | fifo_inst/Equal.wbin_3_s0

Path Statistics:

Clock Skew: | -0.234
Setup Relationship: | 10.000
Logic Level: | 5
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.960, 100.000%
Arrival Data Path Delay: | cell: 3.985, 43.112%; route: 4.800, 51.929%; tC2Q: 0.458, 4.959%
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.960, 100.000%

### Path 5

Path Summary:

Slack | 0.123
Data Arrival Time | 20.203
Data Required Time | 20.326
From | fifo_inst/reset_w_1_s0
To | fifo_inst/wptr_0_s0
Launch Clk | WrClk[R]
Latch Clk | WrClk[F]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | NODE
--- | --- | --- | --- | --- | ---
10.000 | 0.000 |  |  |  | WrClk
10.000 | 0.000 | tCL | FF | 1 | WrClk_ibuf/I
10.000 | 0.000 | tINS | FF | 16 | WrClk_ibuf/O
10.960 | 0.960 | tNET | FF | 1 | fifo_inst/reset_w_1_s0/CLK
11.418 | 0.458 | tC2Q | FF | 14 | fifo_inst/reset_w_1_s0/Q
12.378 | 0.960 | tNET | FF | 1 | fifo_inst/n372_s2/I0
13.410 | 1.032 | tINS | FF | 3 | fifo_inst/n372_s2/F
14.370 | 0.960 | tNET | FF | 1 | fifo_inst/Full_s8/I1
15.469 | 1.099 | tINS | FF | 3 | fifo_inst/Full_s8/F
16.429 | 0.960 | tNET | FF | 1 | fifo_inst/n23_s1/I2
17.251 | 0.822 | tINS | FF | 3 | fifo_inst/n23_s1/F
18.211 | 0.960 | tNET | FF | 1 | fifo_inst/Equal.wgraynext_0_s0/I0
19.243 | 1.032 | tINS | FF | 1 | fifo_inst/Equal.wgraynext_0_s0/F
20.203 | 0.960 | tNET | FF | 1 | fifo_inst/wptr_0_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | NODE
--- | --- | --- | --- | --- | ---
20.000 | 0.000 |  |  |  | WrClk
20.000 | 0.000 | tCL | RR | 1 | WrClk_ibuf/I
20.000 | 0.000 | tINS | RR | 16 | WrClk_ibuf/O
20.726 | 0.726 | tNET | RR | 1 | fifo_inst/wptr_0_s0/CLK
20.326 | -0.400 | tSu |  | 1 | fifo_inst/wptr_0_s0

Path Statistics:

Clock Skew: | -0.234
Setup Relationship: | 10.000
Logic Level: | 5
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.960, 100.000%
Arrival Data Path Delay: | cell: 3.985, 43.112%; route: 4.800, 51.929%; tC2Q: 0.458, 4.959%
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.960, 100.000%