`timescale 1ns / 1ns

module GpioCtrlTb();

reg Clk;
reg Rst;
reg [4:0] cnt;
reg [4:0] state;

reg [23:0] DataGpio;
reg ValData;

always #5 Clk = ~Clk;

initial begin
	Clk	=	1'b1;
	Rst = 	1'b1;
	#100
	Rst = 	1'b0;
end

always @(posedge Clk) begin
	if(Rst) begin
		DataGpio <= 0;
		cnt <= 0;
		state <= 0;
		ValData <= 0;
	end 
	else begin
		case (state)
			0: begin
				DataGpio <= 23'h3FFFFF;

				if (cnt == 6) begin
					cnt <= 0;
					ValData <= 1;
					state <= state + 1;
				end
				else begin
					ValData = 0;
					cnt <= cnt + 1;
					state <= state;
				end
			end
			1: begin
				DataGpio <= 23'h311111;

				if (cnt == 6) begin
					cnt <= 0;
					ValData <= 1;
					state <= state + 1;
				end
				else begin
					ValData = 0;
					cnt <= cnt + 1;
					state <= state;
				end
			end
			2: begin
				DataGpio <= 23'h3AAAAA;

				if (cnt == 6) begin
					cnt <= 0;
					ValData <= 1;
					state <= state + 1;
				end
				else begin
					ValData = 0;
					cnt <= cnt + 1;
					state <= state;
				end
			end
			3: begin
				ValData = 0;
			end
		endcase
	end
end

GpioCtrl DUT(
	.Clk_i					(Clk),
	.Rst_i					(Rst),

	.ValGpioDataToFifo_i	(ValData),
	.Data_i					(DataGpio),

	.GpioReg_o				()
);

endmodule