// Company:         TAIR
// Engineer:        Chigrinskiy A.  
// 
// Create Date:     18/04/2024 
// Design Name: 
// Module Name:     AttenuatorWrapper
// Project Name:    SB_TMSG44V1_FPGA
// Target Devices:  Board: SB_TMSG44v1. FPGA: GW1N-LV9PG256C6/I5
// Tool versions:
// Description:    This module is a wrapper for the Fifo, Fifo Controller and SPI Master modules.
//
// Dependencies:  
// Revision: 
// Revision 1.0 - File Created
// Additional Comments: 
//
////////////////////////////////////////////////////////////////////////////////////////////
module AttenuatorWrapper #(
    parameter IN_WIDTH = 24,
    parameter WR_NUM = 1,
    parameter OUT_WIDTH = 16,
    parameter DATA_WIDTH = 16
)(
    input WrClk_i,
    input RdClk_i,
    input Rst_i,
    input [IN_WIDTH-1:0] Data_i,
    input Val_i,

    output Ss_o,
    output Sck_o,
    output Mosi_o

);
//================================================================================
//	                                REG/WIRE
//================================================================================    
wire [OUT_WIDTH-1:0] dataFromAttFifoCtrl;
wire [OUT_WIDTH-1:0] dataFromAttFifo;
wire readEnAtt;
wire writeEnAtt;
wire valRdDataATT;
wire busySpiMAtt;
wire attFifoFull;
wire attFifoEmpty;

//==========================================================================//
//									CODING									//
//==========================================================================//
FifoCtrl #(
	.IN_WIDTH		(24),
	.WR_NUM			(1),
	.OUT_WIDTH		(16)
) FifoCtrlAtt
(
	.WrClk_i		(WrClk_i),
	.RdClk_i		(RdClk_i),
	.Rst_i			(Rst_i),
	.Data_i			(Data_i),
	.Val_i			(Val_i),
	.BusySpiM_i		(busySpiMAtt),
	.FifoFull_i		(attFifoFull),
	.FifoEmpty_i	(attFifoEmpty),
	.Data_o			(dataFromAttFifoCtrl),
	.ReadEn_o		(readEnAtt),
	.WriteEn_o		(writeEnAtt),
	.ValRdData_o	(valRdDataATT)
);

Fifo16x3 FifoAtt_inst (
	.Data	(dataFromAttFifoCtrl),
	.WrClk	(WrClk_i),
	.RdClk	(RdClk_i),
	.Reset	(Rst_i),
	.WrEn	(writeEnAtt),
	.RdEn	(readEnAtt),
	.Full	(attFifoFull),
	.Empty	(attFifoEmpty),
	.Q		(dataFromAttFifo)
);

SpiM #(
	.DATA_WIDTH	(16)
)SpiMAtt(
	.Clk_i		(RdClk_i),
	.Rst_i		(Rst_i),
	.Val_i		(valRdDataATT),
	.SpiData_i	(dataFromAttFifo),
	.Busy_o	    (busySpiMAtt),
	.Ss_o		(Ss_o),
	.Mosi_o		(Mosi_o),
	.Sck_o		(Sck_o)
);

endmodule