`timescale 1ns / 1ps

//////////////////////////////////////////////////////////////////////////////////
// Company: Tair
// Engineer: Churbanov S.
// 
// Create Date:     
// Design Name: 
// Module Name:    TopSbtmsg
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//		Clk_i - is 24MHz.
//
//////////////////////////////////////////////////////////////////////////////////

module TopSbTmsg 
#(
    parameter DEVNUM = 8,
    parameter WORDWIDTH = 24,
    parameter SSPIWORDWIDTH = 24
) 
(
	input Clk_i,
	input Rst_i,
	
	input Sck_i,
	input Ss_i,
	
	input Mosi0_i,
	inout Mosi1_io,
	input Mosi2_i,
	input Mosi3_i,
	
	input Miso1_i,
	input Miso2_i,
	input MisoMax2870_i,
	
	output I2CSck_o,
	inout I2CSda_io,
	
	output [DEVNUM-1:0] Ss_o,
	output [DEVNUM-1:0] Sck_o,
	output [DEVNUM-1:0] Mosi_o,
	
	output [21:0] Gpio_o
);

//================================================================================
//  LOCALPARAM


//================================================================================
//  REG/WIRE

	wire clk24;
	wire gclk100;
	wire clk5;
	wire clk20;
	wire clk50;
	wire clk26dot25;
	wire clk60;

	wire spiDataVal;
	wire [WORDWIDTH-1:0] spiData;
	
	wire busyMosi1;
	wire busyMosi4;
	
	wire valLmxDataToFifo;		
	wire valDdsDataToFifo;		
	wire valPotDataToFifo;		
	wire valDacDataToFifo;		
	wire valAttDataToFifo;		
	wire valShRegDataToFifo;	
	wire valMaxDataToFifo;		
	wire valGpioDataToFifo;	
	
	wire flagDirectLmx;	
	wire flagDirectDds;	
	wire flagDirectPot;	
	wire flagDirectDac;	
	wire flagDirectAtt;	
	wire flagDirectShReg;	
	wire flagDirectMax;	
	wire flagDirectGpio;	
	wire flagDirectTemp;	
	
//================================================================================
//  ASSIGNMENTS





//================================================================================
//  CODING

ClkGen ClkGen
(
	.Clk24Mhz_i			(Clk_i),
	
	.Clk24Mhz_o			(clk24),
	.Clk100Mhz_o		(gclk100),
	.Clk5Mhz_o			(clk5),
	.Clk20Mhz_o			(clk20),
	.Clk50Mhz_o			(clk50),
	.Clk26dot25Mhz_o	(clk26dot25),
	.Clk60Mhz_o			(clk60)
);

InterfaceArbiter 
#(	
	.OUTWORDWIDTH	(WORDWIDTH),
	.SSPIWORDWIDTH	(SSPIWORDWIDTH)
)
SpiSlaveArbiter
(
	.Rst_i		(Rst_i),
	.Clk_i		(gclk100),
	
	.Sck_i		(Sck_i),
	.Ss_i		(Ss_i),
	
	.Mosi0_i	(Mosi0_i),
	.Mosi1_i	(Mosi1_io),
	.Mosi2_i	(Mosi2_i),
	.Mosi3_i	(Mosi3_i),
	
	
	.DataVal_o	(spiDataVal),
	.Data_o		(spiData)
);

PacketAnalyzer4Mosi PacketAnalyzer4Mosi
(
	.Clk_i					(gclk100),
	.Rst_i					(Rst_i),

	.DataFromSpi_i			(spiData),
	.ValDataFromSpi_i		(spiDataVal),

	.BusyMosi1_i			(busyMosi1),

	.ValLmxDataToFifo_o		(valLmxDataToFifo),
	.ValDdsDataToFifo_o		(valDdsDataToFifo),
	.ValPotDataToFifo_o		(valPotDataToFifo),
	.ValDacDataToFifo_o		(valDacDataToFifo),
	.ValAttDataToFifo_o		(valAttDataToFifo),
	.ValShRegDataToFifo_o	(valShRegDataToFifo),
	.ValMaxDataToFifo_o		(valMaxDataToFifo),
	.ValGpioDataToFifo_o	(valGpioDataToFifo),

	.Busy_o					(busyMosi4)
);

PacketAnalyzer1Mosi	PacketAnalyzer1Mosi
(
	.Clk_i					(gclk100),
	.Rst_i					(Rst_i),
	
	.DataFromSpi_i			(spiData),
	.ValDataFromSpi_i		(spiDataVal),
	
	.BusyMosi4_i			(busyMosi4),
	
	.FlagDirectLmx_o		(flagDirectLmx),
	.FlagDirectDds_o		(flagDirectDds),
	.FlagDirectPot_o		(flagDirectPot),
	.FlagDirectDac_o		(flagDirectDac),
	.FlagDirectAtt_o		(flagDirectAtt),
	.FlagDirectShReg_o		(flagDirectShReg),
	.FlagDirectMax_o		(flagDirectMax),
	.FlagDirectGpio_o		(flagDirectGpio),
	.FlagDirectTemp_o		(flagDirectTemp),
	
	.Busy_o					(busyMosi1)
);

LmxWrapper #(
	.IN_WIDTH		(24),
	.WR_NUM			(1),
	.OUT_WIDTH		(24),
	.DATA_WIDTH		(24)
) LmxWrapper_inst(
	.WrClk_i		(gclk100),
	.RdClk_i		(clk60),
	.Rst_i			(Rst_i),
	.Data_i			(spiData),
	.Val_i			(valLmxDataToFifo),
	.Ss_o			(),
	.Sck_o			(),
	.Mosi_o			()
);

DDSWrapper #(
	.IN_WIDTH		(24),
	.WR_NUM			(3),
	.OUT_WIDTH		(64),
	.DATA_WIDTH		(64)
) DDSWrapper_inst(
	.WrClk_i		(gclk100),
	.RdClk_i		(clk50),
	.Rst_i			(Rst_i),
	.Data_i			(spiData),
	.Val_i			(valDdsDataToFifo),
	.Ss_o			(),
	.Sck_o			(),
	.Mosi_o			()
);

PotWrapper #(
	.IN_WIDTH		(24),
	.WR_NUM			(1),
	.OUT_WIDTH		(16),
	.DATA_WIDTH		(16)
) PotWrapper_inst(
	.WrClk_i		(gclk100),
	.RdClk_i		(clk5),
	.Rst_i			(Rst_i),
	.Data_i			(spiData),
	.Val_i			(valPotDataToFifo),
	.Ss_o			(),
	.Sck_o			(),
	.Mosi_o			()
);

DacWrapper #(
	.IN_WIDTH		(24),
	.WR_NUM			(1),
	.OUT_WIDTH		(16),
	.DATA_WIDTH		(16)
) DacWrapper_inst(
	.WrClk_i		(gclk100),
	.RdClk_i		(clk50),
	.Rst_i			(Rst_i),
	.Data_i			(spiData),
	.Val_i			(valDacDataToFifo),
	.Ss_o			(),
	.Sck_o			(),
	.Mosi_o			()
);

AttenuatorWrapper #(
	.IN_WIDTH		(24),
	.WR_NUM			(1),
	.OUT_WIDTH		(16),
	.DATA_WIDTH		(16)
) AttenuatorWrapper_inst(
	.WrClk_i		(gclk100),
	.RdClk_i		(clk50),
	.Rst_i			(Rst_i),
	.Data_i			(spiData),
	.Val_i			(valAttDataToFifo),
	.Ss_o			(),
	.Sck_o			(),
	.Mosi_o			()
);

ShiftRegWrapper #(
	.IN_WIDTH		(24),
	.WR_NUM			(1),
	.OUT_WIDTH		(8),
	.DATA_WIDTH		(8)
) ShRegWrapper_inst(
	.WrClk_i		(gclk100),
	.RdClk_i		(clk26dot25),
	.Rst_i			(Rst_i),
	.Data_i			(spiData),
	.Val_i			(valShRegDataToFifo),
	.Ss_o			(),
	.Sck_o			(),
	.Mosi_o			()
);

Max2870Wrapper #(
	.IN_WIDTH		(24),
	.WR_NUM			(2),
	.OUT_WIDTH		(32),
	.DATA_WIDTH		(32)
) Max2870Wrapper_inst(
	.WrClk_i		(gclk100),
	.RdClk_i		(clk20),
	.Rst_i			(Rst_i),
	.Data_i			(spiData),
	.Val_i			(valMaxDataToFifo),
	.Ss_o			(),
	.Sck_o			(),
	.Mosi_o			()
);

GpioCtrl GpioCtrl
(
	.Clk_i					(gclk100),
	.Rst_i					(Rst_i),
	
	.ValGpioDataToFifo_i	(valGpioDataToFifo),
	.Data_i					(spiData),

	.GpioReg_o				(Gpio_o)
);


endmodule
