//Copyright (C)2014-2025 GOWIN Semiconductor Corporation.
//All rights reserved.
//File Title: Timing Constraints file
//Tool Version: V1.9.11 (64-bit) 
//Created Time: 2025-06-04 14:02:12
create_clock -name clk5 -period 200 -waveform {0 100} [get_nets {clk5}]
create_clock -name clk60 -period 16.667 -waveform {0 8.334} [get_nets {clk60}]
create_clock -name Clk_i -period 41.667 -waveform {0 20.834} [get_ports {Clk_i}]
create_clock -name Sck_i -period 10 -waveform {0 5} [get_ports {Sck_i}]
create_clock -name clk50 -period 20 -waveform {0 10} [get_nets {clk50}]
set_clock_groups -asynchronous -group [get_clocks {Clk_i}] -group [get_clocks {Sck_i}]
set_false_path -from [get_clocks {Sck_i}] -to [get_clocks {Clk_i}] 
set_false_path -from [get_clocks {Sck_i}] -to [get_clocks {Sck_i}] 
set_false_path -from [get_clocks {Sck_i}] -to [get_clocks {clk60}] 
set_false_path -from [get_clocks {clk60}] -to [get_clocks {Sck_i}] 
set_false_path -from [get_regs {InitRst/signal_o_s1}] 
report_timing -setup -from_clock [get_clocks {clk50}] -to_clock [get_clocks {clk50}]
report_timing -setup -from_clock [get_clocks {clk60}] -to_clock [get_clocks {clk60}]
