// Company:         TAIR
// Engineer:        Chigrinskiy A.  
// 
// Create Date:     18/04/2024 
// Design Name: 
// Module Name:     ShiftRegWrapper
// Project Name:    SB_TMSG44V1_FPGA
// Target Devices:  Board: SB_TMSG44v1. FPGA: GW1N-LV9PG256C6/I5
// Tool versions:
// Description:    This module is a wrapper for the Fifo, Fifo Controller and SPI Master modules.
//
// Dependencies:  
// Revision: 
// Revision 1.0 - File Created
// Additional Comments: 
//
////////////////////////////////////////////////////////////////////////////////////////////
module ShiftRegWrapper #(
    parameter IN_WIDTH = 24,
    parameter WR_NUM = 1,
    parameter OUT_WIDTH = 8,
    parameter DATA_WIDTH = 8
)(
    input WrClk_i,
    input RdClk_i,
    input Rst_i,
    input [IN_WIDTH-1:0] Data_i,
    input Val_i,

    output Ss_o,
    output Sck_o,
    output Mosi_o
);
//================================================================================
//	                                REG/WIRE
//================================================================================    
wire [OUT_WIDTH-1:0] dataFromShRegFifoCtrl;
wire [OUT_WIDTH-1:0] dataFromShRegFifo;
wire readEnShReg;
wire writeEnShReg;
wire valRdDataShReg;
wire busySpiMShReg;
wire shRegFifoFull;
wire shRegFifoEmpty;

//==========================================================================//
//									CODING									//
//==========================================================================//
FifoCtrl #(
	.IN_WIDTH		(IN_WIDTH),
	.WR_NUM			(WR_NUM),
	.OUT_WIDTH		(OUT_WIDTH)
) FifoCtrlShReg
(
	.WrClk_i		(WrClk_i),
	.RdClk_i		(RdClk_i),
	.Rst_i			(Rst_i),
	.Data_i			(Data_i),
	.Val_i			(Val_i),
	.BusySpiM_i		(busySpiMShReg),
	.FifoFull_i		(shRegFifoFull),
	.FifoEmpty_i	(shRegFifoEmpty),
	.Data_o			(dataFromShRegFifoCtrl),
	.ReadEn_o		(readEnShReg),
	.WriteEn_o		(writeEnShReg),
	.ValRdData_o	(valRdDataShReg)
);

FifoShiftReg FifoShReg_inst (
	.Data	(dataFromShRegFifoCtrl),
	.WrClk	(WrClk_i),
	.RdClk	(RdClk_i),
	.Reset	(Rst_i),
	.WrEn	(writeEnShReg),
	.RdEn	(readEnShReg),
	.Full	(shRegFifoFull),
	.Empty	(shRegFifoEmpty),
	.Q		(dataFromShRegFifo)
);

SpiM #(
	.DATA_WIDTH	(DATA_WIDTH)
)SpiMShReg(
	.Clk_i		(RdClk_i),
	.Rst_i		(Rst_i),
	.Val_i		(valRdDataShReg),
	.SpiData_i	(dataFromShRegFifo),
	.Busy_o	    (busySpiMShReg),
	.Ss_o		(Ss_o),
	.Mosi_o		(Mosi_o),
	.Sck_o		(Sck_o)
);

endmodule